1a10e763bSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 29a0bf528SMauro Carvalho Chehab /* 39a0bf528SMauro Carvalho Chehab * dib3000mb_priv.h 49a0bf528SMauro Carvalho Chehab * 599e44da7SPatrick Boettcher * Copyright (C) 2004 Patrick Boettcher (patrick.boettcher@posteo.de) 69a0bf528SMauro Carvalho Chehab * 79a0bf528SMauro Carvalho Chehab * for more information see dib3000mb.c . 89a0bf528SMauro Carvalho Chehab */ 99a0bf528SMauro Carvalho Chehab 109a0bf528SMauro Carvalho Chehab #ifndef __DIB3000MB_PRIV_H_INCLUDED__ 119a0bf528SMauro Carvalho Chehab #define __DIB3000MB_PRIV_H_INCLUDED__ 129a0bf528SMauro Carvalho Chehab 139a0bf528SMauro Carvalho Chehab /* handy shortcuts */ 149a0bf528SMauro Carvalho Chehab #define rd(reg) dib3000_read_reg(state,reg) 159a0bf528SMauro Carvalho Chehab 169a0bf528SMauro Carvalho Chehab #define wr(reg,val) if (dib3000_write_reg(state,reg,val)) \ 17585e3227SMauro Carvalho Chehab { pr_err("while sending 0x%04x to 0x%04x.", val, reg); return -EREMOTEIO; } 189a0bf528SMauro Carvalho Chehab 199a0bf528SMauro Carvalho Chehab #define wr_foreach(a,v) { int i; \ 209a0bf528SMauro Carvalho Chehab if (sizeof(a) != sizeof(v)) \ 21585e3227SMauro Carvalho Chehab pr_err("sizeof: %zu %zu is different", sizeof(a), sizeof(v));\ 229a0bf528SMauro Carvalho Chehab for (i=0; i < sizeof(a)/sizeof(u16); i++) \ 239a0bf528SMauro Carvalho Chehab wr(a[i],v[i]); \ 249a0bf528SMauro Carvalho Chehab } 259a0bf528SMauro Carvalho Chehab 269a0bf528SMauro Carvalho Chehab #define set_or(reg,val) wr(reg,rd(reg) | val) 279a0bf528SMauro Carvalho Chehab 289a0bf528SMauro Carvalho Chehab #define set_and(reg,val) wr(reg,rd(reg) & val) 299a0bf528SMauro Carvalho Chehab 309a0bf528SMauro Carvalho Chehab /* debug */ 319a0bf528SMauro Carvalho Chehab 32585e3227SMauro Carvalho Chehab #define dprintk(level, fmt, arg...) do { \ 33585e3227SMauro Carvalho Chehab if (debug & level) \ 34585e3227SMauro Carvalho Chehab printk(KERN_DEBUG pr_fmt("%s: " fmt), \ 35585e3227SMauro Carvalho Chehab __func__, ##arg); \ 36585e3227SMauro Carvalho Chehab } while (0) 379a0bf528SMauro Carvalho Chehab 389a0bf528SMauro Carvalho Chehab /* mask for enabling a specific pid for the pid_filter */ 399a0bf528SMauro Carvalho Chehab #define DIB3000_ACTIVATE_PID_FILTERING (0x2000) 409a0bf528SMauro Carvalho Chehab 419a0bf528SMauro Carvalho Chehab /* common values for tuning */ 429a0bf528SMauro Carvalho Chehab #define DIB3000_ALPHA_0 ( 0) 439a0bf528SMauro Carvalho Chehab #define DIB3000_ALPHA_1 ( 1) 449a0bf528SMauro Carvalho Chehab #define DIB3000_ALPHA_2 ( 2) 459a0bf528SMauro Carvalho Chehab #define DIB3000_ALPHA_4 ( 4) 469a0bf528SMauro Carvalho Chehab 479a0bf528SMauro Carvalho Chehab #define DIB3000_CONSTELLATION_QPSK ( 0) 489a0bf528SMauro Carvalho Chehab #define DIB3000_CONSTELLATION_16QAM ( 1) 499a0bf528SMauro Carvalho Chehab #define DIB3000_CONSTELLATION_64QAM ( 2) 509a0bf528SMauro Carvalho Chehab 519a0bf528SMauro Carvalho Chehab #define DIB3000_GUARD_TIME_1_32 ( 0) 529a0bf528SMauro Carvalho Chehab #define DIB3000_GUARD_TIME_1_16 ( 1) 539a0bf528SMauro Carvalho Chehab #define DIB3000_GUARD_TIME_1_8 ( 2) 549a0bf528SMauro Carvalho Chehab #define DIB3000_GUARD_TIME_1_4 ( 3) 559a0bf528SMauro Carvalho Chehab 569a0bf528SMauro Carvalho Chehab #define DIB3000_TRANSMISSION_MODE_2K ( 0) 579a0bf528SMauro Carvalho Chehab #define DIB3000_TRANSMISSION_MODE_8K ( 1) 589a0bf528SMauro Carvalho Chehab 599a0bf528SMauro Carvalho Chehab #define DIB3000_SELECT_LP ( 0) 609a0bf528SMauro Carvalho Chehab #define DIB3000_SELECT_HP ( 1) 619a0bf528SMauro Carvalho Chehab 629a0bf528SMauro Carvalho Chehab #define DIB3000_FEC_1_2 ( 1) 639a0bf528SMauro Carvalho Chehab #define DIB3000_FEC_2_3 ( 2) 649a0bf528SMauro Carvalho Chehab #define DIB3000_FEC_3_4 ( 3) 659a0bf528SMauro Carvalho Chehab #define DIB3000_FEC_5_6 ( 5) 669a0bf528SMauro Carvalho Chehab #define DIB3000_FEC_7_8 ( 7) 679a0bf528SMauro Carvalho Chehab 689a0bf528SMauro Carvalho Chehab #define DIB3000_HRCH_OFF ( 0) 699a0bf528SMauro Carvalho Chehab #define DIB3000_HRCH_ON ( 1) 709a0bf528SMauro Carvalho Chehab 719a0bf528SMauro Carvalho Chehab #define DIB3000_DDS_INVERSION_OFF ( 0) 729a0bf528SMauro Carvalho Chehab #define DIB3000_DDS_INVERSION_ON ( 1) 739a0bf528SMauro Carvalho Chehab 749a0bf528SMauro Carvalho Chehab #define DIB3000_TUNER_WRITE_ENABLE(a) (0xffff & (a << 8)) 759a0bf528SMauro Carvalho Chehab #define DIB3000_TUNER_WRITE_DISABLE(a) (0xffff & ((a << 8) | (1 << 7))) 769a0bf528SMauro Carvalho Chehab 779a0bf528SMauro Carvalho Chehab #define DIB3000_REG_MANUFACTOR_ID ( 1025) 789a0bf528SMauro Carvalho Chehab #define DIB3000_I2C_ID_DIBCOM (0x01b3) 799a0bf528SMauro Carvalho Chehab 809a0bf528SMauro Carvalho Chehab #define DIB3000_REG_DEVICE_ID ( 1026) 819a0bf528SMauro Carvalho Chehab #define DIB3000MB_DEVICE_ID (0x3000) 829a0bf528SMauro Carvalho Chehab #define DIB3000MC_DEVICE_ID (0x3001) 839a0bf528SMauro Carvalho Chehab #define DIB3000P_DEVICE_ID (0x3002) 849a0bf528SMauro Carvalho Chehab 859a0bf528SMauro Carvalho Chehab /* frontend state */ 869a0bf528SMauro Carvalho Chehab struct dib3000_state { 879a0bf528SMauro Carvalho Chehab struct i2c_adapter* i2c; 889a0bf528SMauro Carvalho Chehab 899a0bf528SMauro Carvalho Chehab /* configuration settings */ 909a0bf528SMauro Carvalho Chehab struct dib3000_config config; 919a0bf528SMauro Carvalho Chehab 929a0bf528SMauro Carvalho Chehab struct dvb_frontend frontend; 939a0bf528SMauro Carvalho Chehab int timing_offset; 949a0bf528SMauro Carvalho Chehab int timing_offset_comp_done; 959a0bf528SMauro Carvalho Chehab 969a0bf528SMauro Carvalho Chehab u32 last_tuned_bw; 979a0bf528SMauro Carvalho Chehab u32 last_tuned_freq; 989a0bf528SMauro Carvalho Chehab }; 999a0bf528SMauro Carvalho Chehab 1009a0bf528SMauro Carvalho Chehab /* register addresses and some of their default values */ 1019a0bf528SMauro Carvalho Chehab 1029a0bf528SMauro Carvalho Chehab /* restart subsystems */ 1039a0bf528SMauro Carvalho Chehab #define DIB3000MB_REG_RESTART ( 0) 1049a0bf528SMauro Carvalho Chehab 1059a0bf528SMauro Carvalho Chehab #define DIB3000MB_RESTART_OFF ( 0) 1069a0bf528SMauro Carvalho Chehab #define DIB3000MB_RESTART_AUTO_SEARCH (1 << 1) 1079a0bf528SMauro Carvalho Chehab #define DIB3000MB_RESTART_CTRL (1 << 2) 1089a0bf528SMauro Carvalho Chehab #define DIB3000MB_RESTART_AGC (1 << 3) 1099a0bf528SMauro Carvalho Chehab 1109a0bf528SMauro Carvalho Chehab /* FFT size */ 1119a0bf528SMauro Carvalho Chehab #define DIB3000MB_REG_FFT ( 1) 1129a0bf528SMauro Carvalho Chehab 1139a0bf528SMauro Carvalho Chehab /* Guard time */ 1149a0bf528SMauro Carvalho Chehab #define DIB3000MB_REG_GUARD_TIME ( 2) 1159a0bf528SMauro Carvalho Chehab 1169a0bf528SMauro Carvalho Chehab /* QAM */ 1179a0bf528SMauro Carvalho Chehab #define DIB3000MB_REG_QAM ( 3) 1189a0bf528SMauro Carvalho Chehab 1199a0bf528SMauro Carvalho Chehab /* Alpha coefficient high priority Viterbi algorithm */ 1209a0bf528SMauro Carvalho Chehab #define DIB3000MB_REG_VIT_ALPHA ( 4) 1219a0bf528SMauro Carvalho Chehab 1229a0bf528SMauro Carvalho Chehab /* spectrum inversion */ 1239a0bf528SMauro Carvalho Chehab #define DIB3000MB_REG_DDS_INV ( 5) 1249a0bf528SMauro Carvalho Chehab 1259a0bf528SMauro Carvalho Chehab /* DDS frequency value (IF position) ad ? values don't match reg_3000mb.txt */ 1269a0bf528SMauro Carvalho Chehab #define DIB3000MB_REG_DDS_FREQ_MSB ( 6) 1279a0bf528SMauro Carvalho Chehab #define DIB3000MB_REG_DDS_FREQ_LSB ( 7) 1289a0bf528SMauro Carvalho Chehab #define DIB3000MB_DDS_FREQ_MSB ( 178) 1299a0bf528SMauro Carvalho Chehab #define DIB3000MB_DDS_FREQ_LSB ( 8990) 1309a0bf528SMauro Carvalho Chehab 1319a0bf528SMauro Carvalho Chehab /* timing frequency (carrier spacing) */ 1329a0bf528SMauro Carvalho Chehab static u16 dib3000mb_reg_timing_freq[] = { 8,9 }; 1339a0bf528SMauro Carvalho Chehab static u16 dib3000mb_timing_freq[][2] = { 1349a0bf528SMauro Carvalho Chehab { 126 , 48873 }, /* 6 MHz */ 1359a0bf528SMauro Carvalho Chehab { 147 , 57019 }, /* 7 MHz */ 1369a0bf528SMauro Carvalho Chehab { 168 , 65164 }, /* 8 MHz */ 1379a0bf528SMauro Carvalho Chehab }; 1389a0bf528SMauro Carvalho Chehab 1399a0bf528SMauro Carvalho Chehab /* impulse noise parameter */ 1409a0bf528SMauro Carvalho Chehab /* 36 ??? */ 1419a0bf528SMauro Carvalho Chehab 1429a0bf528SMauro Carvalho Chehab static u16 dib3000mb_reg_impulse_noise[] = { 10,11,12,15,36 }; 1439a0bf528SMauro Carvalho Chehab 1449a0bf528SMauro Carvalho Chehab enum dib3000mb_impulse_noise_type { 1459a0bf528SMauro Carvalho Chehab DIB3000MB_IMPNOISE_OFF, 1469a0bf528SMauro Carvalho Chehab DIB3000MB_IMPNOISE_MOBILE, 1479a0bf528SMauro Carvalho Chehab DIB3000MB_IMPNOISE_FIXED, 1489a0bf528SMauro Carvalho Chehab DIB3000MB_IMPNOISE_DEFAULT 1499a0bf528SMauro Carvalho Chehab }; 1509a0bf528SMauro Carvalho Chehab 1519a0bf528SMauro Carvalho Chehab static u16 dib3000mb_impulse_noise_values[][5] = { 1529a0bf528SMauro Carvalho Chehab { 0x0000, 0x0004, 0x0014, 0x01ff, 0x0399 }, /* off */ 1539a0bf528SMauro Carvalho Chehab { 0x0001, 0x0004, 0x0014, 0x01ff, 0x037b }, /* mobile */ 1549a0bf528SMauro Carvalho Chehab { 0x0001, 0x0004, 0x0020, 0x01bd, 0x0399 }, /* fixed */ 1559a0bf528SMauro Carvalho Chehab { 0x0000, 0x0002, 0x000a, 0x01ff, 0x0399 }, /* default */ 1569a0bf528SMauro Carvalho Chehab }; 1579a0bf528SMauro Carvalho Chehab 1589a0bf528SMauro Carvalho Chehab /* 1599a0bf528SMauro Carvalho Chehab * Dual Automatic-Gain-Control 1609a0bf528SMauro Carvalho Chehab * - gains RF in tuner (AGC1) 1619a0bf528SMauro Carvalho Chehab * - gains IF after filtering (AGC2) 1629a0bf528SMauro Carvalho Chehab */ 1639a0bf528SMauro Carvalho Chehab 1649a0bf528SMauro Carvalho Chehab /* also from 16 to 18 */ 1659a0bf528SMauro Carvalho Chehab static u16 dib3000mb_reg_agc_gain[] = { 1669a0bf528SMauro Carvalho Chehab 19,20,21,22,23,24,25,26,27,28,29,30,31,32 1679a0bf528SMauro Carvalho Chehab }; 1689a0bf528SMauro Carvalho Chehab 1699a0bf528SMauro Carvalho Chehab static u16 dib3000mb_default_agc_gain[] = 1709a0bf528SMauro Carvalho Chehab { 0x0001, 52429, 623, 128, 166, 195, 61, /* RF ??? */ 1719a0bf528SMauro Carvalho Chehab 0x0001, 53766, 38011, 0, 90, 33, 23 }; /* IF ??? */ 1729a0bf528SMauro Carvalho Chehab 1739a0bf528SMauro Carvalho Chehab /* phase noise */ 1749a0bf528SMauro Carvalho Chehab /* 36 is set when setting the impulse noise */ 1759a0bf528SMauro Carvalho Chehab static u16 dib3000mb_reg_phase_noise[] = { 33,34,35,37,38 }; 1769a0bf528SMauro Carvalho Chehab 1779a0bf528SMauro Carvalho Chehab static u16 dib3000mb_default_noise_phase[] = { 2, 544, 0, 5, 4 }; 1789a0bf528SMauro Carvalho Chehab 1799a0bf528SMauro Carvalho Chehab /* lock duration */ 1809a0bf528SMauro Carvalho Chehab static u16 dib3000mb_reg_lock_duration[] = { 39,40 }; 1819a0bf528SMauro Carvalho Chehab static u16 dib3000mb_default_lock_duration[] = { 135, 135 }; 1829a0bf528SMauro Carvalho Chehab 1839a0bf528SMauro Carvalho Chehab /* AGC loop bandwidth */ 1849a0bf528SMauro Carvalho Chehab static u16 dib3000mb_reg_agc_bandwidth[] = { 43,44,45,46,47,48,49,50 }; 1859a0bf528SMauro Carvalho Chehab 1869a0bf528SMauro Carvalho Chehab static u16 dib3000mb_agc_bandwidth_low[] = 1879a0bf528SMauro Carvalho Chehab { 2088, 10, 2088, 10, 3448, 5, 3448, 5 }; 1889a0bf528SMauro Carvalho Chehab static u16 dib3000mb_agc_bandwidth_high[] = 1899a0bf528SMauro Carvalho Chehab { 2349, 5, 2349, 5, 2586, 2, 2586, 2 }; 1909a0bf528SMauro Carvalho Chehab 1919a0bf528SMauro Carvalho Chehab /* 1929a0bf528SMauro Carvalho Chehab * lock0 definition (coff_lock) 1939a0bf528SMauro Carvalho Chehab */ 1949a0bf528SMauro Carvalho Chehab #define DIB3000MB_REG_LOCK0_MASK ( 51) 1959a0bf528SMauro Carvalho Chehab #define DIB3000MB_LOCK0_DEFAULT ( 4) 1969a0bf528SMauro Carvalho Chehab 1979a0bf528SMauro Carvalho Chehab /* 1989a0bf528SMauro Carvalho Chehab * lock1 definition (cpil_lock) 1999a0bf528SMauro Carvalho Chehab * for auto search 2009a0bf528SMauro Carvalho Chehab * which values hide behind the lock masks 2019a0bf528SMauro Carvalho Chehab */ 2029a0bf528SMauro Carvalho Chehab #define DIB3000MB_REG_LOCK1_MASK ( 52) 2039a0bf528SMauro Carvalho Chehab #define DIB3000MB_LOCK1_SEARCH_4 (0x0004) 2049a0bf528SMauro Carvalho Chehab #define DIB3000MB_LOCK1_SEARCH_2048 (0x0800) 2059a0bf528SMauro Carvalho Chehab #define DIB3000MB_LOCK1_DEFAULT (0x0001) 2069a0bf528SMauro Carvalho Chehab 2079a0bf528SMauro Carvalho Chehab /* 2089a0bf528SMauro Carvalho Chehab * lock2 definition (fec_lock) */ 2099a0bf528SMauro Carvalho Chehab #define DIB3000MB_REG_LOCK2_MASK ( 53) 2109a0bf528SMauro Carvalho Chehab #define DIB3000MB_LOCK2_DEFAULT (0x0080) 2119a0bf528SMauro Carvalho Chehab 2129a0bf528SMauro Carvalho Chehab /* 2139a0bf528SMauro Carvalho Chehab * SEQ ? what was that again ... :) 2149a0bf528SMauro Carvalho Chehab * changes when, inversion, guard time and fft is 2159a0bf528SMauro Carvalho Chehab * either automatically detected or not 2169a0bf528SMauro Carvalho Chehab */ 2179a0bf528SMauro Carvalho Chehab #define DIB3000MB_REG_SEQ ( 54) 2189a0bf528SMauro Carvalho Chehab 2199a0bf528SMauro Carvalho Chehab /* bandwidth */ 2209a0bf528SMauro Carvalho Chehab static u16 dib3000mb_reg_bandwidth[] = { 55,56,57,58,59,60,61,62,63,64,65,66,67 }; 2219a0bf528SMauro Carvalho Chehab static u16 dib3000mb_bandwidth_6mhz[] = 2229a0bf528SMauro Carvalho Chehab { 0, 33, 53312, 112, 46635, 563, 36565, 0, 1000, 0, 1010, 1, 45264 }; 2239a0bf528SMauro Carvalho Chehab 2249a0bf528SMauro Carvalho Chehab static u16 dib3000mb_bandwidth_7mhz[] = 2259a0bf528SMauro Carvalho Chehab { 0, 28, 64421, 96, 39973, 483, 3255, 0, 1000, 0, 1010, 1, 45264 }; 2269a0bf528SMauro Carvalho Chehab 2279a0bf528SMauro Carvalho Chehab static u16 dib3000mb_bandwidth_8mhz[] = 2289a0bf528SMauro Carvalho Chehab { 0, 25, 23600, 84, 34976, 422, 43808, 0, 1000, 0, 1010, 1, 45264 }; 2299a0bf528SMauro Carvalho Chehab 2309a0bf528SMauro Carvalho Chehab #define DIB3000MB_REG_UNK_68 ( 68) 2319a0bf528SMauro Carvalho Chehab #define DIB3000MB_UNK_68 ( 0) 2329a0bf528SMauro Carvalho Chehab 2339a0bf528SMauro Carvalho Chehab #define DIB3000MB_REG_UNK_69 ( 69) 2349a0bf528SMauro Carvalho Chehab #define DIB3000MB_UNK_69 ( 0) 2359a0bf528SMauro Carvalho Chehab 2369a0bf528SMauro Carvalho Chehab #define DIB3000MB_REG_UNK_71 ( 71) 2379a0bf528SMauro Carvalho Chehab #define DIB3000MB_UNK_71 ( 0) 2389a0bf528SMauro Carvalho Chehab 2399a0bf528SMauro Carvalho Chehab #define DIB3000MB_REG_UNK_77 ( 77) 2409a0bf528SMauro Carvalho Chehab #define DIB3000MB_UNK_77 ( 6) 2419a0bf528SMauro Carvalho Chehab 2429a0bf528SMauro Carvalho Chehab #define DIB3000MB_REG_UNK_78 ( 78) 2439a0bf528SMauro Carvalho Chehab #define DIB3000MB_UNK_78 (0x0080) 2449a0bf528SMauro Carvalho Chehab 2459a0bf528SMauro Carvalho Chehab /* isi */ 2469a0bf528SMauro Carvalho Chehab #define DIB3000MB_REG_ISI ( 79) 2479a0bf528SMauro Carvalho Chehab #define DIB3000MB_ISI_ACTIVATE ( 0) 2489a0bf528SMauro Carvalho Chehab #define DIB3000MB_ISI_INHIBIT ( 1) 2499a0bf528SMauro Carvalho Chehab 2509a0bf528SMauro Carvalho Chehab /* sync impovement */ 2519a0bf528SMauro Carvalho Chehab #define DIB3000MB_REG_SYNC_IMPROVEMENT ( 84) 2529a0bf528SMauro Carvalho Chehab #define DIB3000MB_SYNC_IMPROVE_2K_1_8 ( 3) 2539a0bf528SMauro Carvalho Chehab #define DIB3000MB_SYNC_IMPROVE_DEFAULT ( 0) 2549a0bf528SMauro Carvalho Chehab 2559a0bf528SMauro Carvalho Chehab /* phase noise compensation inhibition */ 2569a0bf528SMauro Carvalho Chehab #define DIB3000MB_REG_PHASE_NOISE ( 87) 2579a0bf528SMauro Carvalho Chehab #define DIB3000MB_PHASE_NOISE_DEFAULT ( 0) 2589a0bf528SMauro Carvalho Chehab 2599a0bf528SMauro Carvalho Chehab #define DIB3000MB_REG_UNK_92 ( 92) 2609a0bf528SMauro Carvalho Chehab #define DIB3000MB_UNK_92 (0x0080) 2619a0bf528SMauro Carvalho Chehab 2629a0bf528SMauro Carvalho Chehab #define DIB3000MB_REG_UNK_96 ( 96) 2639a0bf528SMauro Carvalho Chehab #define DIB3000MB_UNK_96 (0x0010) 2649a0bf528SMauro Carvalho Chehab 2659a0bf528SMauro Carvalho Chehab #define DIB3000MB_REG_UNK_97 ( 97) 2669a0bf528SMauro Carvalho Chehab #define DIB3000MB_UNK_97 (0x0009) 2679a0bf528SMauro Carvalho Chehab 2689a0bf528SMauro Carvalho Chehab /* mobile mode ??? */ 2699a0bf528SMauro Carvalho Chehab #define DIB3000MB_REG_MOBILE_MODE ( 101) 2709a0bf528SMauro Carvalho Chehab #define DIB3000MB_MOBILE_MODE_ON ( 1) 2719a0bf528SMauro Carvalho Chehab #define DIB3000MB_MOBILE_MODE_OFF ( 0) 2729a0bf528SMauro Carvalho Chehab 2739a0bf528SMauro Carvalho Chehab #define DIB3000MB_REG_UNK_106 ( 106) 2749a0bf528SMauro Carvalho Chehab #define DIB3000MB_UNK_106 (0x0080) 2759a0bf528SMauro Carvalho Chehab 2769a0bf528SMauro Carvalho Chehab #define DIB3000MB_REG_UNK_107 ( 107) 2779a0bf528SMauro Carvalho Chehab #define DIB3000MB_UNK_107 (0x0080) 2789a0bf528SMauro Carvalho Chehab 2799a0bf528SMauro Carvalho Chehab #define DIB3000MB_REG_UNK_108 ( 108) 2809a0bf528SMauro Carvalho Chehab #define DIB3000MB_UNK_108 (0x0080) 2819a0bf528SMauro Carvalho Chehab 2829a0bf528SMauro Carvalho Chehab /* fft */ 2839a0bf528SMauro Carvalho Chehab #define DIB3000MB_REG_UNK_121 ( 121) 2849a0bf528SMauro Carvalho Chehab #define DIB3000MB_UNK_121_2K ( 7) 2859a0bf528SMauro Carvalho Chehab #define DIB3000MB_UNK_121_DEFAULT ( 5) 2869a0bf528SMauro Carvalho Chehab 2879a0bf528SMauro Carvalho Chehab #define DIB3000MB_REG_UNK_122 ( 122) 2889a0bf528SMauro Carvalho Chehab #define DIB3000MB_UNK_122 ( 2867) 2899a0bf528SMauro Carvalho Chehab 2909a0bf528SMauro Carvalho Chehab /* QAM for mobile mode */ 2919a0bf528SMauro Carvalho Chehab #define DIB3000MB_REG_MOBILE_MODE_QAM ( 126) 2929a0bf528SMauro Carvalho Chehab #define DIB3000MB_MOBILE_MODE_QAM_64 ( 3) 2939a0bf528SMauro Carvalho Chehab #define DIB3000MB_MOBILE_MODE_QAM_QPSK_16 ( 1) 2949a0bf528SMauro Carvalho Chehab #define DIB3000MB_MOBILE_MODE_QAM_OFF ( 0) 2959a0bf528SMauro Carvalho Chehab 2969a0bf528SMauro Carvalho Chehab /* 2979a0bf528SMauro Carvalho Chehab * data diversity when having more than one chip on-board 2989a0bf528SMauro Carvalho Chehab * see also DIB3000MB_OUTPUT_MODE_DATA_DIVERSITY 2999a0bf528SMauro Carvalho Chehab */ 3009a0bf528SMauro Carvalho Chehab #define DIB3000MB_REG_DATA_IN_DIVERSITY ( 127) 3019a0bf528SMauro Carvalho Chehab #define DIB3000MB_DATA_DIVERSITY_IN_OFF ( 0) 3029a0bf528SMauro Carvalho Chehab #define DIB3000MB_DATA_DIVERSITY_IN_ON ( 2) 3039a0bf528SMauro Carvalho Chehab 3049a0bf528SMauro Carvalho Chehab /* vit hrch */ 3059a0bf528SMauro Carvalho Chehab #define DIB3000MB_REG_VIT_HRCH ( 128) 3069a0bf528SMauro Carvalho Chehab 3079a0bf528SMauro Carvalho Chehab /* vit code rate */ 3089a0bf528SMauro Carvalho Chehab #define DIB3000MB_REG_VIT_CODE_RATE ( 129) 3099a0bf528SMauro Carvalho Chehab 3109a0bf528SMauro Carvalho Chehab /* vit select hp */ 3119a0bf528SMauro Carvalho Chehab #define DIB3000MB_REG_VIT_HP ( 130) 3129a0bf528SMauro Carvalho Chehab 3139a0bf528SMauro Carvalho Chehab /* time frame for Bit-Error-Rate calculation */ 3149a0bf528SMauro Carvalho Chehab #define DIB3000MB_REG_BERLEN ( 135) 3159a0bf528SMauro Carvalho Chehab #define DIB3000MB_BERLEN_LONG ( 0) 3169a0bf528SMauro Carvalho Chehab #define DIB3000MB_BERLEN_DEFAULT ( 1) 3179a0bf528SMauro Carvalho Chehab #define DIB3000MB_BERLEN_MEDIUM ( 2) 3189a0bf528SMauro Carvalho Chehab #define DIB3000MB_BERLEN_SHORT ( 3) 3199a0bf528SMauro Carvalho Chehab 3209a0bf528SMauro Carvalho Chehab /* 142 - 152 FIFO parameters 3219a0bf528SMauro Carvalho Chehab * which is what ? 3229a0bf528SMauro Carvalho Chehab */ 3239a0bf528SMauro Carvalho Chehab 3249a0bf528SMauro Carvalho Chehab #define DIB3000MB_REG_FIFO_142 ( 142) 3259a0bf528SMauro Carvalho Chehab #define DIB3000MB_FIFO_142 ( 0) 3269a0bf528SMauro Carvalho Chehab 3279a0bf528SMauro Carvalho Chehab /* MPEG2 TS output mode */ 3289a0bf528SMauro Carvalho Chehab #define DIB3000MB_REG_MPEG2_OUT_MODE ( 143) 3299a0bf528SMauro Carvalho Chehab #define DIB3000MB_MPEG2_OUT_MODE_204 ( 0) 3309a0bf528SMauro Carvalho Chehab #define DIB3000MB_MPEG2_OUT_MODE_188 ( 1) 3319a0bf528SMauro Carvalho Chehab 3329a0bf528SMauro Carvalho Chehab #define DIB3000MB_REG_PID_PARSE ( 144) 3339a0bf528SMauro Carvalho Chehab #define DIB3000MB_PID_PARSE_INHIBIT ( 0) 3349a0bf528SMauro Carvalho Chehab #define DIB3000MB_PID_PARSE_ACTIVATE ( 1) 3359a0bf528SMauro Carvalho Chehab 3369a0bf528SMauro Carvalho Chehab #define DIB3000MB_REG_FIFO ( 145) 3379a0bf528SMauro Carvalho Chehab #define DIB3000MB_FIFO_INHIBIT ( 1) 3389a0bf528SMauro Carvalho Chehab #define DIB3000MB_FIFO_ACTIVATE ( 0) 3399a0bf528SMauro Carvalho Chehab 3409a0bf528SMauro Carvalho Chehab #define DIB3000MB_REG_FIFO_146 ( 146) 3419a0bf528SMauro Carvalho Chehab #define DIB3000MB_FIFO_146 ( 3) 3429a0bf528SMauro Carvalho Chehab 3439a0bf528SMauro Carvalho Chehab #define DIB3000MB_REG_FIFO_147 ( 147) 3449a0bf528SMauro Carvalho Chehab #define DIB3000MB_FIFO_147 (0x0100) 3459a0bf528SMauro Carvalho Chehab 3469a0bf528SMauro Carvalho Chehab /* 3479a0bf528SMauro Carvalho Chehab * pidfilter 3489a0bf528SMauro Carvalho Chehab * it is not a hardware pidfilter but a filter which drops all pids 3499a0bf528SMauro Carvalho Chehab * except the ones set. Necessary because of the limited USB1.1 bandwidth. 3509a0bf528SMauro Carvalho Chehab * regs 153-168 3519a0bf528SMauro Carvalho Chehab */ 3529a0bf528SMauro Carvalho Chehab 3539a0bf528SMauro Carvalho Chehab #define DIB3000MB_REG_FIRST_PID ( 153) 3549a0bf528SMauro Carvalho Chehab #define DIB3000MB_NUM_PIDS ( 16) 3559a0bf528SMauro Carvalho Chehab 3569a0bf528SMauro Carvalho Chehab /* 3579a0bf528SMauro Carvalho Chehab * output mode 3589a0bf528SMauro Carvalho Chehab * USB devices have to use 'slave'-mode 3599a0bf528SMauro Carvalho Chehab * see also DIB3000MB_REG_ELECT_OUT_MODE 3609a0bf528SMauro Carvalho Chehab */ 3619a0bf528SMauro Carvalho Chehab #define DIB3000MB_REG_OUTPUT_MODE ( 169) 3629a0bf528SMauro Carvalho Chehab #define DIB3000MB_OUTPUT_MODE_GATED_CLK ( 0) 3639a0bf528SMauro Carvalho Chehab #define DIB3000MB_OUTPUT_MODE_CONT_CLK ( 1) 3649a0bf528SMauro Carvalho Chehab #define DIB3000MB_OUTPUT_MODE_SERIAL ( 2) 3659a0bf528SMauro Carvalho Chehab #define DIB3000MB_OUTPUT_MODE_DATA_DIVERSITY ( 5) 3669a0bf528SMauro Carvalho Chehab #define DIB3000MB_OUTPUT_MODE_SLAVE ( 6) 3679a0bf528SMauro Carvalho Chehab 3689a0bf528SMauro Carvalho Chehab /* irq event mask */ 3699a0bf528SMauro Carvalho Chehab #define DIB3000MB_REG_IRQ_EVENT_MASK ( 170) 3709a0bf528SMauro Carvalho Chehab #define DIB3000MB_IRQ_EVENT_MASK ( 0) 3719a0bf528SMauro Carvalho Chehab 3729a0bf528SMauro Carvalho Chehab /* filter coefficients */ 3739a0bf528SMauro Carvalho Chehab static u16 dib3000mb_reg_filter_coeffs[] = { 3749a0bf528SMauro Carvalho Chehab 171, 172, 173, 174, 175, 176, 177, 178, 3759a0bf528SMauro Carvalho Chehab 179, 180, 181, 182, 183, 184, 185, 186, 3769a0bf528SMauro Carvalho Chehab 188, 189, 190, 191, 192, 194 3779a0bf528SMauro Carvalho Chehab }; 3789a0bf528SMauro Carvalho Chehab 3799a0bf528SMauro Carvalho Chehab static u16 dib3000mb_filter_coeffs[] = { 3809a0bf528SMauro Carvalho Chehab 226, 160, 29, 3819a0bf528SMauro Carvalho Chehab 979, 998, 19, 3829a0bf528SMauro Carvalho Chehab 22, 1019, 1006, 3839a0bf528SMauro Carvalho Chehab 1022, 12, 6, 3849a0bf528SMauro Carvalho Chehab 1017, 1017, 3, 3859a0bf528SMauro Carvalho Chehab 6, 1019, 3869a0bf528SMauro Carvalho Chehab 1021, 2, 3, 3879a0bf528SMauro Carvalho Chehab 1, 0, 3889a0bf528SMauro Carvalho Chehab }; 3899a0bf528SMauro Carvalho Chehab 3909a0bf528SMauro Carvalho Chehab /* 3919a0bf528SMauro Carvalho Chehab * mobile algorithm (when you are moving with your device) 3929a0bf528SMauro Carvalho Chehab * but not faster than 90 km/h 3939a0bf528SMauro Carvalho Chehab */ 3949a0bf528SMauro Carvalho Chehab #define DIB3000MB_REG_MOBILE_ALGO ( 195) 3959a0bf528SMauro Carvalho Chehab #define DIB3000MB_MOBILE_ALGO_ON ( 0) 3969a0bf528SMauro Carvalho Chehab #define DIB3000MB_MOBILE_ALGO_OFF ( 1) 3979a0bf528SMauro Carvalho Chehab 3989a0bf528SMauro Carvalho Chehab /* multiple demodulators algorithm */ 3999a0bf528SMauro Carvalho Chehab #define DIB3000MB_REG_MULTI_DEMOD_MSB ( 206) 4009a0bf528SMauro Carvalho Chehab #define DIB3000MB_REG_MULTI_DEMOD_LSB ( 207) 4019a0bf528SMauro Carvalho Chehab 4029a0bf528SMauro Carvalho Chehab /* terminator, no more demods */ 4039a0bf528SMauro Carvalho Chehab #define DIB3000MB_MULTI_DEMOD_MSB ( 32767) 4049a0bf528SMauro Carvalho Chehab #define DIB3000MB_MULTI_DEMOD_LSB ( 4095) 4059a0bf528SMauro Carvalho Chehab 4069a0bf528SMauro Carvalho Chehab /* bring the device into a known */ 4079a0bf528SMauro Carvalho Chehab #define DIB3000MB_REG_RESET_DEVICE ( 1024) 4089a0bf528SMauro Carvalho Chehab #define DIB3000MB_RESET_DEVICE (0x812c) 4099a0bf528SMauro Carvalho Chehab #define DIB3000MB_RESET_DEVICE_RST ( 0) 4109a0bf528SMauro Carvalho Chehab 4119a0bf528SMauro Carvalho Chehab /* hardware clock configuration */ 4129a0bf528SMauro Carvalho Chehab #define DIB3000MB_REG_CLOCK ( 1027) 4139a0bf528SMauro Carvalho Chehab #define DIB3000MB_CLOCK_DEFAULT (0x9000) 4149a0bf528SMauro Carvalho Chehab #define DIB3000MB_CLOCK_DIVERSITY (0x92b0) 4159a0bf528SMauro Carvalho Chehab 4169a0bf528SMauro Carvalho Chehab /* power down config */ 4179a0bf528SMauro Carvalho Chehab #define DIB3000MB_REG_POWER_CONTROL ( 1028) 4189a0bf528SMauro Carvalho Chehab #define DIB3000MB_POWER_DOWN ( 1) 4199a0bf528SMauro Carvalho Chehab #define DIB3000MB_POWER_UP ( 0) 4209a0bf528SMauro Carvalho Chehab 4219a0bf528SMauro Carvalho Chehab /* electrical output mode */ 4229a0bf528SMauro Carvalho Chehab #define DIB3000MB_REG_ELECT_OUT_MODE ( 1029) 4239a0bf528SMauro Carvalho Chehab #define DIB3000MB_ELECT_OUT_MODE_OFF ( 0) 4249a0bf528SMauro Carvalho Chehab #define DIB3000MB_ELECT_OUT_MODE_ON ( 1) 4259a0bf528SMauro Carvalho Chehab 4269a0bf528SMauro Carvalho Chehab /* set the tuner i2c address */ 4279a0bf528SMauro Carvalho Chehab #define DIB3000MB_REG_TUNER ( 1089) 4289a0bf528SMauro Carvalho Chehab 4299a0bf528SMauro Carvalho Chehab /* monitoring registers (read only) */ 4309a0bf528SMauro Carvalho Chehab 4319a0bf528SMauro Carvalho Chehab /* agc loop locked (size: 1) */ 4329a0bf528SMauro Carvalho Chehab #define DIB3000MB_REG_AGC_LOCK ( 324) 4339a0bf528SMauro Carvalho Chehab 4349a0bf528SMauro Carvalho Chehab /* agc power (size: 16) */ 4359a0bf528SMauro Carvalho Chehab #define DIB3000MB_REG_AGC_POWER ( 325) 4369a0bf528SMauro Carvalho Chehab 4379a0bf528SMauro Carvalho Chehab /* agc1 value (16) */ 4389a0bf528SMauro Carvalho Chehab #define DIB3000MB_REG_AGC1_VALUE ( 326) 4399a0bf528SMauro Carvalho Chehab 4409a0bf528SMauro Carvalho Chehab /* agc2 value (16) */ 4419a0bf528SMauro Carvalho Chehab #define DIB3000MB_REG_AGC2_VALUE ( 327) 4429a0bf528SMauro Carvalho Chehab 4439a0bf528SMauro Carvalho Chehab /* total RF power (16), can be used for signal strength */ 4449a0bf528SMauro Carvalho Chehab #define DIB3000MB_REG_RF_POWER ( 328) 4459a0bf528SMauro Carvalho Chehab 4469a0bf528SMauro Carvalho Chehab /* dds_frequency with offset (24) */ 4479a0bf528SMauro Carvalho Chehab #define DIB3000MB_REG_DDS_VALUE_MSB ( 339) 4489a0bf528SMauro Carvalho Chehab #define DIB3000MB_REG_DDS_VALUE_LSB ( 340) 4499a0bf528SMauro Carvalho Chehab 4509a0bf528SMauro Carvalho Chehab /* timing offset signed (24) */ 4519a0bf528SMauro Carvalho Chehab #define DIB3000MB_REG_TIMING_OFFSET_MSB ( 341) 4529a0bf528SMauro Carvalho Chehab #define DIB3000MB_REG_TIMING_OFFSET_LSB ( 342) 4539a0bf528SMauro Carvalho Chehab 4549a0bf528SMauro Carvalho Chehab /* fft start position (13) */ 4559a0bf528SMauro Carvalho Chehab #define DIB3000MB_REG_FFT_WINDOW_POS ( 353) 4569a0bf528SMauro Carvalho Chehab 4579a0bf528SMauro Carvalho Chehab /* carriers locked (1) */ 4589a0bf528SMauro Carvalho Chehab #define DIB3000MB_REG_CARRIER_LOCK ( 355) 4599a0bf528SMauro Carvalho Chehab 4609a0bf528SMauro Carvalho Chehab /* noise power (24) */ 4619a0bf528SMauro Carvalho Chehab #define DIB3000MB_REG_NOISE_POWER_MSB ( 372) 4629a0bf528SMauro Carvalho Chehab #define DIB3000MB_REG_NOISE_POWER_LSB ( 373) 4639a0bf528SMauro Carvalho Chehab 4649a0bf528SMauro Carvalho Chehab #define DIB3000MB_REG_MOBILE_NOISE_MSB ( 374) 4659a0bf528SMauro Carvalho Chehab #define DIB3000MB_REG_MOBILE_NOISE_LSB ( 375) 4669a0bf528SMauro Carvalho Chehab 4679a0bf528SMauro Carvalho Chehab /* 4689a0bf528SMauro Carvalho Chehab * signal power (16), this and the above can be 4699a0bf528SMauro Carvalho Chehab * used to calculate the signal/noise - ratio 4709a0bf528SMauro Carvalho Chehab */ 4719a0bf528SMauro Carvalho Chehab #define DIB3000MB_REG_SIGNAL_POWER ( 380) 4729a0bf528SMauro Carvalho Chehab 4739a0bf528SMauro Carvalho Chehab /* mer (24) */ 4749a0bf528SMauro Carvalho Chehab #define DIB3000MB_REG_MER_MSB ( 381) 4759a0bf528SMauro Carvalho Chehab #define DIB3000MB_REG_MER_LSB ( 382) 4769a0bf528SMauro Carvalho Chehab 4779a0bf528SMauro Carvalho Chehab /* 4789a0bf528SMauro Carvalho Chehab * Transmission Parameter Signalling (TPS) 4799a0bf528SMauro Carvalho Chehab * the following registers can be used to get TPS-information. 4809a0bf528SMauro Carvalho Chehab * The values are according to the DVB-T standard. 4819a0bf528SMauro Carvalho Chehab */ 4829a0bf528SMauro Carvalho Chehab 4839a0bf528SMauro Carvalho Chehab /* TPS locked (1) */ 4849a0bf528SMauro Carvalho Chehab #define DIB3000MB_REG_TPS_LOCK ( 394) 4859a0bf528SMauro Carvalho Chehab 4869a0bf528SMauro Carvalho Chehab /* QAM from TPS (2) (values according to DIB3000MB_REG_QAM) */ 4879a0bf528SMauro Carvalho Chehab #define DIB3000MB_REG_TPS_QAM ( 398) 4889a0bf528SMauro Carvalho Chehab 4899a0bf528SMauro Carvalho Chehab /* hierarchy from TPS (1) */ 4909a0bf528SMauro Carvalho Chehab #define DIB3000MB_REG_TPS_HRCH ( 399) 4919a0bf528SMauro Carvalho Chehab 4929a0bf528SMauro Carvalho Chehab /* alpha from TPS (3) (values according to DIB3000MB_REG_VIT_ALPHA) */ 4939a0bf528SMauro Carvalho Chehab #define DIB3000MB_REG_TPS_VIT_ALPHA ( 400) 4949a0bf528SMauro Carvalho Chehab 4959a0bf528SMauro Carvalho Chehab /* code rate high priority from TPS (3) (values according to DIB3000MB_FEC_*) */ 4969a0bf528SMauro Carvalho Chehab #define DIB3000MB_REG_TPS_CODE_RATE_HP ( 401) 4979a0bf528SMauro Carvalho Chehab 4989a0bf528SMauro Carvalho Chehab /* code rate low priority from TPS (3) if DIB3000MB_REG_TPS_VIT_ALPHA */ 4999a0bf528SMauro Carvalho Chehab #define DIB3000MB_REG_TPS_CODE_RATE_LP ( 402) 5009a0bf528SMauro Carvalho Chehab 5019a0bf528SMauro Carvalho Chehab /* guard time from TPS (2) (values according to DIB3000MB_REG_GUARD_TIME */ 5029a0bf528SMauro Carvalho Chehab #define DIB3000MB_REG_TPS_GUARD_TIME ( 403) 5039a0bf528SMauro Carvalho Chehab 5049a0bf528SMauro Carvalho Chehab /* fft size from TPS (2) (values according to DIB3000MB_REG_FFT) */ 5059a0bf528SMauro Carvalho Chehab #define DIB3000MB_REG_TPS_FFT ( 404) 5069a0bf528SMauro Carvalho Chehab 5079a0bf528SMauro Carvalho Chehab /* cell id from TPS (16) */ 5089a0bf528SMauro Carvalho Chehab #define DIB3000MB_REG_TPS_CELL_ID ( 406) 5099a0bf528SMauro Carvalho Chehab 5109a0bf528SMauro Carvalho Chehab /* TPS (68) */ 5119a0bf528SMauro Carvalho Chehab #define DIB3000MB_REG_TPS_1 ( 408) 5129a0bf528SMauro Carvalho Chehab #define DIB3000MB_REG_TPS_2 ( 409) 5139a0bf528SMauro Carvalho Chehab #define DIB3000MB_REG_TPS_3 ( 410) 5149a0bf528SMauro Carvalho Chehab #define DIB3000MB_REG_TPS_4 ( 411) 5159a0bf528SMauro Carvalho Chehab #define DIB3000MB_REG_TPS_5 ( 412) 5169a0bf528SMauro Carvalho Chehab 5179a0bf528SMauro Carvalho Chehab /* bit error rate (before RS correction) (21) */ 5189a0bf528SMauro Carvalho Chehab #define DIB3000MB_REG_BER_MSB ( 414) 5199a0bf528SMauro Carvalho Chehab #define DIB3000MB_REG_BER_LSB ( 415) 5209a0bf528SMauro Carvalho Chehab 5219a0bf528SMauro Carvalho Chehab /* packet error rate (uncorrected TS packets) (16) */ 5229a0bf528SMauro Carvalho Chehab #define DIB3000MB_REG_PACKET_ERROR_RATE ( 417) 5239a0bf528SMauro Carvalho Chehab 5249a0bf528SMauro Carvalho Chehab /* uncorrected packet count (16) */ 5259a0bf528SMauro Carvalho Chehab #define DIB3000MB_REG_UNC ( 420) 5269a0bf528SMauro Carvalho Chehab 5279a0bf528SMauro Carvalho Chehab /* viterbi locked (1) */ 5289a0bf528SMauro Carvalho Chehab #define DIB3000MB_REG_VIT_LCK ( 421) 5299a0bf528SMauro Carvalho Chehab 5309a0bf528SMauro Carvalho Chehab /* viterbi inidcator (16) */ 5319a0bf528SMauro Carvalho Chehab #define DIB3000MB_REG_VIT_INDICATOR ( 422) 5329a0bf528SMauro Carvalho Chehab 5339a0bf528SMauro Carvalho Chehab /* transport stream sync lock (1) */ 5349a0bf528SMauro Carvalho Chehab #define DIB3000MB_REG_TS_SYNC_LOCK ( 423) 5359a0bf528SMauro Carvalho Chehab 5369a0bf528SMauro Carvalho Chehab /* transport stream RS lock (1) */ 5379a0bf528SMauro Carvalho Chehab #define DIB3000MB_REG_TS_RS_LOCK ( 424) 5389a0bf528SMauro Carvalho Chehab 5399a0bf528SMauro Carvalho Chehab /* lock mask 0 value (1) */ 5409a0bf528SMauro Carvalho Chehab #define DIB3000MB_REG_LOCK0_VALUE ( 425) 5419a0bf528SMauro Carvalho Chehab 5429a0bf528SMauro Carvalho Chehab /* lock mask 1 value (1) */ 5439a0bf528SMauro Carvalho Chehab #define DIB3000MB_REG_LOCK1_VALUE ( 426) 5449a0bf528SMauro Carvalho Chehab 5459a0bf528SMauro Carvalho Chehab /* lock mask 2 value (1) */ 5469a0bf528SMauro Carvalho Chehab #define DIB3000MB_REG_LOCK2_VALUE ( 427) 5479a0bf528SMauro Carvalho Chehab 5489a0bf528SMauro Carvalho Chehab /* interrupt pending for auto search */ 5499a0bf528SMauro Carvalho Chehab #define DIB3000MB_REG_AS_IRQ_PENDING ( 434) 5509a0bf528SMauro Carvalho Chehab 5519a0bf528SMauro Carvalho Chehab #endif 552