1 /* 2 * Frontend driver for mobile DVB-T demodulator DiBcom 3000M-B 3 * DiBcom (http://www.dibcom.fr/) 4 * 5 * Copyright (C) 2004-5 Patrick Boettcher (patrick.boettcher@posteo.de) 6 * 7 * based on GPL code from DibCom, which has 8 * 9 * Copyright (C) 2004 Amaury Demol for DiBcom 10 * 11 * This program is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation, version 2. 14 * 15 * Acknowledgements 16 * 17 * Amaury Demol from DiBcom for providing specs and driver 18 * sources, on which this driver (and the dvb-dibusb) are based. 19 * 20 * see Documentation/dvb/README.dvb-usb for more information 21 * 22 */ 23 24 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 25 26 #include <linux/kernel.h> 27 #include <linux/module.h> 28 #include <linux/init.h> 29 #include <linux/delay.h> 30 #include <linux/string.h> 31 #include <linux/slab.h> 32 33 #include "dvb_frontend.h" 34 35 #include "dib3000.h" 36 #include "dib3000mb_priv.h" 37 38 /* Version information */ 39 #define DRIVER_VERSION "0.1" 40 #define DRIVER_DESC "DiBcom 3000M-B DVB-T demodulator" 41 #define DRIVER_AUTHOR "Patrick Boettcher, patrick.boettcher@posteo.de" 42 43 static int debug; 44 module_param(debug, int, 0644); 45 MODULE_PARM_DESC(debug, "set debugging level (1=info,2=xfer,4=setfe,8=getfe (|-able))."); 46 47 #define deb_info(args...) dprintk(0x01, args) 48 #define deb_i2c(args...) dprintk(0x02, args) 49 #define deb_srch(args...) dprintk(0x04, args) 50 #define deb_info(args...) dprintk(0x01, args) 51 #define deb_xfer(args...) dprintk(0x02, args) 52 #define deb_setf(args...) dprintk(0x04, args) 53 #define deb_getf(args...) dprintk(0x08, args) 54 55 static int dib3000_read_reg(struct dib3000_state *state, u16 reg) 56 { 57 u8 wb[] = { ((reg >> 8) | 0x80) & 0xff, reg & 0xff }; 58 u8 rb[2]; 59 struct i2c_msg msg[] = { 60 { .addr = state->config.demod_address, .flags = 0, .buf = wb, .len = 2 }, 61 { .addr = state->config.demod_address, .flags = I2C_M_RD, .buf = rb, .len = 2 }, 62 }; 63 64 if (i2c_transfer(state->i2c, msg, 2) != 2) 65 deb_i2c("i2c read error\n"); 66 67 deb_i2c("reading i2c bus (reg: %5d 0x%04x, val: %5d 0x%04x)\n",reg,reg, 68 (rb[0] << 8) | rb[1],(rb[0] << 8) | rb[1]); 69 70 return (rb[0] << 8) | rb[1]; 71 } 72 73 static int dib3000_write_reg(struct dib3000_state *state, u16 reg, u16 val) 74 { 75 u8 b[] = { 76 (reg >> 8) & 0xff, reg & 0xff, 77 (val >> 8) & 0xff, val & 0xff, 78 }; 79 struct i2c_msg msg[] = { 80 { .addr = state->config.demod_address, .flags = 0, .buf = b, .len = 4 } 81 }; 82 deb_i2c("writing i2c bus (reg: %5d 0x%04x, val: %5d 0x%04x)\n",reg,reg,val,val); 83 84 return i2c_transfer(state->i2c,msg, 1) != 1 ? -EREMOTEIO : 0; 85 } 86 87 static int dib3000_search_status(u16 irq,u16 lock) 88 { 89 if (irq & 0x02) { 90 if (lock & 0x01) { 91 deb_srch("auto search succeeded\n"); 92 return 1; // auto search succeeded 93 } else { 94 deb_srch("auto search not successful\n"); 95 return 0; // auto search failed 96 } 97 } else if (irq & 0x01) { 98 deb_srch("auto search failed\n"); 99 return 0; // auto search failed 100 } 101 return -1; // try again 102 } 103 104 /* for auto search */ 105 static u16 dib3000_seq[2][2][2] = /* fft,gua, inv */ 106 { /* fft */ 107 { /* gua */ 108 { 0, 1 }, /* 0 0 { 0,1 } */ 109 { 3, 9 }, /* 0 1 { 0,1 } */ 110 }, 111 { 112 { 2, 5 }, /* 1 0 { 0,1 } */ 113 { 6, 11 }, /* 1 1 { 0,1 } */ 114 } 115 }; 116 117 static int dib3000mb_get_frontend(struct dvb_frontend* fe, 118 struct dtv_frontend_properties *c); 119 120 static int dib3000mb_set_frontend(struct dvb_frontend *fe, int tuner) 121 { 122 struct dib3000_state* state = fe->demodulator_priv; 123 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 124 enum fe_code_rate fe_cr = FEC_NONE; 125 int search_state, seq; 126 127 if (tuner && fe->ops.tuner_ops.set_params) { 128 fe->ops.tuner_ops.set_params(fe); 129 if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0); 130 131 switch (c->bandwidth_hz) { 132 case 8000000: 133 wr_foreach(dib3000mb_reg_timing_freq, dib3000mb_timing_freq[2]); 134 wr_foreach(dib3000mb_reg_bandwidth, dib3000mb_bandwidth_8mhz); 135 break; 136 case 7000000: 137 wr_foreach(dib3000mb_reg_timing_freq, dib3000mb_timing_freq[1]); 138 wr_foreach(dib3000mb_reg_bandwidth, dib3000mb_bandwidth_7mhz); 139 break; 140 case 6000000: 141 wr_foreach(dib3000mb_reg_timing_freq, dib3000mb_timing_freq[0]); 142 wr_foreach(dib3000mb_reg_bandwidth, dib3000mb_bandwidth_6mhz); 143 break; 144 case 0: 145 return -EOPNOTSUPP; 146 default: 147 pr_err("unknown bandwidth value.\n"); 148 return -EINVAL; 149 } 150 deb_setf("bandwidth: %d MHZ\n", c->bandwidth_hz / 1000000); 151 } 152 wr(DIB3000MB_REG_LOCK1_MASK, DIB3000MB_LOCK1_SEARCH_4); 153 154 switch (c->transmission_mode) { 155 case TRANSMISSION_MODE_2K: 156 deb_setf("transmission mode: 2k\n"); 157 wr(DIB3000MB_REG_FFT, DIB3000_TRANSMISSION_MODE_2K); 158 break; 159 case TRANSMISSION_MODE_8K: 160 deb_setf("transmission mode: 8k\n"); 161 wr(DIB3000MB_REG_FFT, DIB3000_TRANSMISSION_MODE_8K); 162 break; 163 case TRANSMISSION_MODE_AUTO: 164 deb_setf("transmission mode: auto\n"); 165 break; 166 default: 167 return -EINVAL; 168 } 169 170 switch (c->guard_interval) { 171 case GUARD_INTERVAL_1_32: 172 deb_setf("guard 1_32\n"); 173 wr(DIB3000MB_REG_GUARD_TIME, DIB3000_GUARD_TIME_1_32); 174 break; 175 case GUARD_INTERVAL_1_16: 176 deb_setf("guard 1_16\n"); 177 wr(DIB3000MB_REG_GUARD_TIME, DIB3000_GUARD_TIME_1_16); 178 break; 179 case GUARD_INTERVAL_1_8: 180 deb_setf("guard 1_8\n"); 181 wr(DIB3000MB_REG_GUARD_TIME, DIB3000_GUARD_TIME_1_8); 182 break; 183 case GUARD_INTERVAL_1_4: 184 deb_setf("guard 1_4\n"); 185 wr(DIB3000MB_REG_GUARD_TIME, DIB3000_GUARD_TIME_1_4); 186 break; 187 case GUARD_INTERVAL_AUTO: 188 deb_setf("guard auto\n"); 189 break; 190 default: 191 return -EINVAL; 192 } 193 194 switch (c->inversion) { 195 case INVERSION_OFF: 196 deb_setf("inversion off\n"); 197 wr(DIB3000MB_REG_DDS_INV, DIB3000_DDS_INVERSION_OFF); 198 break; 199 case INVERSION_AUTO: 200 deb_setf("inversion auto\n"); 201 break; 202 case INVERSION_ON: 203 deb_setf("inversion on\n"); 204 wr(DIB3000MB_REG_DDS_INV, DIB3000_DDS_INVERSION_ON); 205 break; 206 default: 207 return -EINVAL; 208 } 209 210 switch (c->modulation) { 211 case QPSK: 212 deb_setf("modulation: qpsk\n"); 213 wr(DIB3000MB_REG_QAM, DIB3000_CONSTELLATION_QPSK); 214 break; 215 case QAM_16: 216 deb_setf("modulation: qam16\n"); 217 wr(DIB3000MB_REG_QAM, DIB3000_CONSTELLATION_16QAM); 218 break; 219 case QAM_64: 220 deb_setf("modulation: qam64\n"); 221 wr(DIB3000MB_REG_QAM, DIB3000_CONSTELLATION_64QAM); 222 break; 223 case QAM_AUTO: 224 break; 225 default: 226 return -EINVAL; 227 } 228 switch (c->hierarchy) { 229 case HIERARCHY_NONE: 230 deb_setf("hierarchy: none\n"); 231 /* fall through */ 232 case HIERARCHY_1: 233 deb_setf("hierarchy: alpha=1\n"); 234 wr(DIB3000MB_REG_VIT_ALPHA, DIB3000_ALPHA_1); 235 break; 236 case HIERARCHY_2: 237 deb_setf("hierarchy: alpha=2\n"); 238 wr(DIB3000MB_REG_VIT_ALPHA, DIB3000_ALPHA_2); 239 break; 240 case HIERARCHY_4: 241 deb_setf("hierarchy: alpha=4\n"); 242 wr(DIB3000MB_REG_VIT_ALPHA, DIB3000_ALPHA_4); 243 break; 244 case HIERARCHY_AUTO: 245 deb_setf("hierarchy: alpha=auto\n"); 246 break; 247 default: 248 return -EINVAL; 249 } 250 251 if (c->hierarchy == HIERARCHY_NONE) { 252 wr(DIB3000MB_REG_VIT_HRCH, DIB3000_HRCH_OFF); 253 wr(DIB3000MB_REG_VIT_HP, DIB3000_SELECT_HP); 254 fe_cr = c->code_rate_HP; 255 } else if (c->hierarchy != HIERARCHY_AUTO) { 256 wr(DIB3000MB_REG_VIT_HRCH, DIB3000_HRCH_ON); 257 wr(DIB3000MB_REG_VIT_HP, DIB3000_SELECT_LP); 258 fe_cr = c->code_rate_LP; 259 } 260 switch (fe_cr) { 261 case FEC_1_2: 262 deb_setf("fec: 1_2\n"); 263 wr(DIB3000MB_REG_VIT_CODE_RATE, DIB3000_FEC_1_2); 264 break; 265 case FEC_2_3: 266 deb_setf("fec: 2_3\n"); 267 wr(DIB3000MB_REG_VIT_CODE_RATE, DIB3000_FEC_2_3); 268 break; 269 case FEC_3_4: 270 deb_setf("fec: 3_4\n"); 271 wr(DIB3000MB_REG_VIT_CODE_RATE, DIB3000_FEC_3_4); 272 break; 273 case FEC_5_6: 274 deb_setf("fec: 5_6\n"); 275 wr(DIB3000MB_REG_VIT_CODE_RATE, DIB3000_FEC_5_6); 276 break; 277 case FEC_7_8: 278 deb_setf("fec: 7_8\n"); 279 wr(DIB3000MB_REG_VIT_CODE_RATE, DIB3000_FEC_7_8); 280 break; 281 case FEC_NONE: 282 deb_setf("fec: none\n"); 283 break; 284 case FEC_AUTO: 285 deb_setf("fec: auto\n"); 286 break; 287 default: 288 return -EINVAL; 289 } 290 291 seq = dib3000_seq 292 [c->transmission_mode == TRANSMISSION_MODE_AUTO] 293 [c->guard_interval == GUARD_INTERVAL_AUTO] 294 [c->inversion == INVERSION_AUTO]; 295 296 deb_setf("seq? %d\n", seq); 297 298 wr(DIB3000MB_REG_SEQ, seq); 299 300 wr(DIB3000MB_REG_ISI, seq ? DIB3000MB_ISI_INHIBIT : DIB3000MB_ISI_ACTIVATE); 301 302 if (c->transmission_mode == TRANSMISSION_MODE_2K) { 303 if (c->guard_interval == GUARD_INTERVAL_1_8) { 304 wr(DIB3000MB_REG_SYNC_IMPROVEMENT, DIB3000MB_SYNC_IMPROVE_2K_1_8); 305 } else { 306 wr(DIB3000MB_REG_SYNC_IMPROVEMENT, DIB3000MB_SYNC_IMPROVE_DEFAULT); 307 } 308 309 wr(DIB3000MB_REG_UNK_121, DIB3000MB_UNK_121_2K); 310 } else { 311 wr(DIB3000MB_REG_UNK_121, DIB3000MB_UNK_121_DEFAULT); 312 } 313 314 wr(DIB3000MB_REG_MOBILE_ALGO, DIB3000MB_MOBILE_ALGO_OFF); 315 wr(DIB3000MB_REG_MOBILE_MODE_QAM, DIB3000MB_MOBILE_MODE_QAM_OFF); 316 wr(DIB3000MB_REG_MOBILE_MODE, DIB3000MB_MOBILE_MODE_OFF); 317 318 wr_foreach(dib3000mb_reg_agc_bandwidth, dib3000mb_agc_bandwidth_high); 319 320 wr(DIB3000MB_REG_ISI, DIB3000MB_ISI_ACTIVATE); 321 322 wr(DIB3000MB_REG_RESTART, DIB3000MB_RESTART_AGC + DIB3000MB_RESTART_CTRL); 323 wr(DIB3000MB_REG_RESTART, DIB3000MB_RESTART_OFF); 324 325 /* wait for AGC lock */ 326 msleep(70); 327 328 wr_foreach(dib3000mb_reg_agc_bandwidth, dib3000mb_agc_bandwidth_low); 329 330 /* something has to be auto searched */ 331 if (c->modulation == QAM_AUTO || 332 c->hierarchy == HIERARCHY_AUTO || 333 fe_cr == FEC_AUTO || 334 c->inversion == INVERSION_AUTO) { 335 int as_count=0; 336 337 deb_setf("autosearch enabled.\n"); 338 339 wr(DIB3000MB_REG_ISI, DIB3000MB_ISI_INHIBIT); 340 341 wr(DIB3000MB_REG_RESTART, DIB3000MB_RESTART_AUTO_SEARCH); 342 wr(DIB3000MB_REG_RESTART, DIB3000MB_RESTART_OFF); 343 344 while ((search_state = 345 dib3000_search_status( 346 rd(DIB3000MB_REG_AS_IRQ_PENDING), 347 rd(DIB3000MB_REG_LOCK2_VALUE))) < 0 && as_count++ < 100) 348 msleep(1); 349 350 deb_setf("search_state after autosearch %d after %d checks\n", 351 search_state, as_count); 352 353 if (search_state == 1) { 354 if (dib3000mb_get_frontend(fe, c) == 0) { 355 deb_setf("reading tuning data from frontend succeeded.\n"); 356 return dib3000mb_set_frontend(fe, 0); 357 } 358 } 359 360 } else { 361 wr(DIB3000MB_REG_RESTART, DIB3000MB_RESTART_CTRL); 362 wr(DIB3000MB_REG_RESTART, DIB3000MB_RESTART_OFF); 363 } 364 365 return 0; 366 } 367 368 static int dib3000mb_fe_init(struct dvb_frontend* fe, int mobile_mode) 369 { 370 struct dib3000_state* state = fe->demodulator_priv; 371 372 deb_info("dib3000mb is getting up.\n"); 373 wr(DIB3000MB_REG_POWER_CONTROL, DIB3000MB_POWER_UP); 374 375 wr(DIB3000MB_REG_RESTART, DIB3000MB_RESTART_AGC); 376 377 wr(DIB3000MB_REG_RESET_DEVICE, DIB3000MB_RESET_DEVICE); 378 wr(DIB3000MB_REG_RESET_DEVICE, DIB3000MB_RESET_DEVICE_RST); 379 380 wr(DIB3000MB_REG_CLOCK, DIB3000MB_CLOCK_DEFAULT); 381 382 wr(DIB3000MB_REG_ELECT_OUT_MODE, DIB3000MB_ELECT_OUT_MODE_ON); 383 384 wr(DIB3000MB_REG_DDS_FREQ_MSB, DIB3000MB_DDS_FREQ_MSB); 385 wr(DIB3000MB_REG_DDS_FREQ_LSB, DIB3000MB_DDS_FREQ_LSB); 386 387 wr_foreach(dib3000mb_reg_timing_freq, dib3000mb_timing_freq[2]); 388 389 wr_foreach(dib3000mb_reg_impulse_noise, 390 dib3000mb_impulse_noise_values[DIB3000MB_IMPNOISE_OFF]); 391 392 wr_foreach(dib3000mb_reg_agc_gain, dib3000mb_default_agc_gain); 393 394 wr(DIB3000MB_REG_PHASE_NOISE, DIB3000MB_PHASE_NOISE_DEFAULT); 395 396 wr_foreach(dib3000mb_reg_phase_noise, dib3000mb_default_noise_phase); 397 398 wr_foreach(dib3000mb_reg_lock_duration, dib3000mb_default_lock_duration); 399 400 wr_foreach(dib3000mb_reg_agc_bandwidth, dib3000mb_agc_bandwidth_low); 401 402 wr(DIB3000MB_REG_LOCK0_MASK, DIB3000MB_LOCK0_DEFAULT); 403 wr(DIB3000MB_REG_LOCK1_MASK, DIB3000MB_LOCK1_SEARCH_4); 404 wr(DIB3000MB_REG_LOCK2_MASK, DIB3000MB_LOCK2_DEFAULT); 405 wr(DIB3000MB_REG_SEQ, dib3000_seq[1][1][1]); 406 407 wr_foreach(dib3000mb_reg_bandwidth, dib3000mb_bandwidth_8mhz); 408 409 wr(DIB3000MB_REG_UNK_68, DIB3000MB_UNK_68); 410 wr(DIB3000MB_REG_UNK_69, DIB3000MB_UNK_69); 411 wr(DIB3000MB_REG_UNK_71, DIB3000MB_UNK_71); 412 wr(DIB3000MB_REG_UNK_77, DIB3000MB_UNK_77); 413 wr(DIB3000MB_REG_UNK_78, DIB3000MB_UNK_78); 414 wr(DIB3000MB_REG_ISI, DIB3000MB_ISI_INHIBIT); 415 wr(DIB3000MB_REG_UNK_92, DIB3000MB_UNK_92); 416 wr(DIB3000MB_REG_UNK_96, DIB3000MB_UNK_96); 417 wr(DIB3000MB_REG_UNK_97, DIB3000MB_UNK_97); 418 wr(DIB3000MB_REG_UNK_106, DIB3000MB_UNK_106); 419 wr(DIB3000MB_REG_UNK_107, DIB3000MB_UNK_107); 420 wr(DIB3000MB_REG_UNK_108, DIB3000MB_UNK_108); 421 wr(DIB3000MB_REG_UNK_122, DIB3000MB_UNK_122); 422 wr(DIB3000MB_REG_MOBILE_MODE_QAM, DIB3000MB_MOBILE_MODE_QAM_OFF); 423 wr(DIB3000MB_REG_BERLEN, DIB3000MB_BERLEN_DEFAULT); 424 425 wr_foreach(dib3000mb_reg_filter_coeffs, dib3000mb_filter_coeffs); 426 427 wr(DIB3000MB_REG_MOBILE_ALGO, DIB3000MB_MOBILE_ALGO_ON); 428 wr(DIB3000MB_REG_MULTI_DEMOD_MSB, DIB3000MB_MULTI_DEMOD_MSB); 429 wr(DIB3000MB_REG_MULTI_DEMOD_LSB, DIB3000MB_MULTI_DEMOD_LSB); 430 431 wr(DIB3000MB_REG_OUTPUT_MODE, DIB3000MB_OUTPUT_MODE_SLAVE); 432 433 wr(DIB3000MB_REG_FIFO_142, DIB3000MB_FIFO_142); 434 wr(DIB3000MB_REG_MPEG2_OUT_MODE, DIB3000MB_MPEG2_OUT_MODE_188); 435 wr(DIB3000MB_REG_PID_PARSE, DIB3000MB_PID_PARSE_ACTIVATE); 436 wr(DIB3000MB_REG_FIFO, DIB3000MB_FIFO_INHIBIT); 437 wr(DIB3000MB_REG_FIFO_146, DIB3000MB_FIFO_146); 438 wr(DIB3000MB_REG_FIFO_147, DIB3000MB_FIFO_147); 439 440 wr(DIB3000MB_REG_DATA_IN_DIVERSITY, DIB3000MB_DATA_DIVERSITY_IN_OFF); 441 442 return 0; 443 } 444 445 static int dib3000mb_get_frontend(struct dvb_frontend* fe, 446 struct dtv_frontend_properties *c) 447 { 448 struct dib3000_state* state = fe->demodulator_priv; 449 enum fe_code_rate *cr; 450 u16 tps_val; 451 int inv_test1,inv_test2; 452 u32 dds_val, threshold = 0x800000; 453 454 if (!rd(DIB3000MB_REG_TPS_LOCK)) 455 return 0; 456 457 dds_val = ((rd(DIB3000MB_REG_DDS_VALUE_MSB) & 0xff) << 16) + rd(DIB3000MB_REG_DDS_VALUE_LSB); 458 deb_getf("DDS_VAL: %x %x %x\n", dds_val, rd(DIB3000MB_REG_DDS_VALUE_MSB), rd(DIB3000MB_REG_DDS_VALUE_LSB)); 459 if (dds_val < threshold) 460 inv_test1 = 0; 461 else if (dds_val == threshold) 462 inv_test1 = 1; 463 else 464 inv_test1 = 2; 465 466 dds_val = ((rd(DIB3000MB_REG_DDS_FREQ_MSB) & 0xff) << 16) + rd(DIB3000MB_REG_DDS_FREQ_LSB); 467 deb_getf("DDS_FREQ: %x %x %x\n", dds_val, rd(DIB3000MB_REG_DDS_FREQ_MSB), rd(DIB3000MB_REG_DDS_FREQ_LSB)); 468 if (dds_val < threshold) 469 inv_test2 = 0; 470 else if (dds_val == threshold) 471 inv_test2 = 1; 472 else 473 inv_test2 = 2; 474 475 c->inversion = 476 ((inv_test2 == 2) && (inv_test1==1 || inv_test1==0)) || 477 ((inv_test2 == 0) && (inv_test1==1 || inv_test1==2)) ? 478 INVERSION_ON : INVERSION_OFF; 479 480 deb_getf("inversion %d %d, %d\n", inv_test2, inv_test1, c->inversion); 481 482 switch ((tps_val = rd(DIB3000MB_REG_TPS_QAM))) { 483 case DIB3000_CONSTELLATION_QPSK: 484 deb_getf("QPSK\n"); 485 c->modulation = QPSK; 486 break; 487 case DIB3000_CONSTELLATION_16QAM: 488 deb_getf("QAM16\n"); 489 c->modulation = QAM_16; 490 break; 491 case DIB3000_CONSTELLATION_64QAM: 492 deb_getf("QAM64\n"); 493 c->modulation = QAM_64; 494 break; 495 default: 496 pr_err("Unexpected constellation returned by TPS (%d)\n", tps_val); 497 break; 498 } 499 deb_getf("TPS: %d\n", tps_val); 500 501 if (rd(DIB3000MB_REG_TPS_HRCH)) { 502 deb_getf("HRCH ON\n"); 503 cr = &c->code_rate_LP; 504 c->code_rate_HP = FEC_NONE; 505 switch ((tps_val = rd(DIB3000MB_REG_TPS_VIT_ALPHA))) { 506 case DIB3000_ALPHA_0: 507 deb_getf("HIERARCHY_NONE\n"); 508 c->hierarchy = HIERARCHY_NONE; 509 break; 510 case DIB3000_ALPHA_1: 511 deb_getf("HIERARCHY_1\n"); 512 c->hierarchy = HIERARCHY_1; 513 break; 514 case DIB3000_ALPHA_2: 515 deb_getf("HIERARCHY_2\n"); 516 c->hierarchy = HIERARCHY_2; 517 break; 518 case DIB3000_ALPHA_4: 519 deb_getf("HIERARCHY_4\n"); 520 c->hierarchy = HIERARCHY_4; 521 break; 522 default: 523 pr_err("Unexpected ALPHA value returned by TPS (%d)\n", tps_val); 524 break; 525 } 526 deb_getf("TPS: %d\n", tps_val); 527 528 tps_val = rd(DIB3000MB_REG_TPS_CODE_RATE_LP); 529 } else { 530 deb_getf("HRCH OFF\n"); 531 cr = &c->code_rate_HP; 532 c->code_rate_LP = FEC_NONE; 533 c->hierarchy = HIERARCHY_NONE; 534 535 tps_val = rd(DIB3000MB_REG_TPS_CODE_RATE_HP); 536 } 537 538 switch (tps_val) { 539 case DIB3000_FEC_1_2: 540 deb_getf("FEC_1_2\n"); 541 *cr = FEC_1_2; 542 break; 543 case DIB3000_FEC_2_3: 544 deb_getf("FEC_2_3\n"); 545 *cr = FEC_2_3; 546 break; 547 case DIB3000_FEC_3_4: 548 deb_getf("FEC_3_4\n"); 549 *cr = FEC_3_4; 550 break; 551 case DIB3000_FEC_5_6: 552 deb_getf("FEC_5_6\n"); 553 *cr = FEC_4_5; 554 break; 555 case DIB3000_FEC_7_8: 556 deb_getf("FEC_7_8\n"); 557 *cr = FEC_7_8; 558 break; 559 default: 560 pr_err("Unexpected FEC returned by TPS (%d)\n", tps_val); 561 break; 562 } 563 deb_getf("TPS: %d\n",tps_val); 564 565 switch ((tps_val = rd(DIB3000MB_REG_TPS_GUARD_TIME))) { 566 case DIB3000_GUARD_TIME_1_32: 567 deb_getf("GUARD_INTERVAL_1_32\n"); 568 c->guard_interval = GUARD_INTERVAL_1_32; 569 break; 570 case DIB3000_GUARD_TIME_1_16: 571 deb_getf("GUARD_INTERVAL_1_16\n"); 572 c->guard_interval = GUARD_INTERVAL_1_16; 573 break; 574 case DIB3000_GUARD_TIME_1_8: 575 deb_getf("GUARD_INTERVAL_1_8\n"); 576 c->guard_interval = GUARD_INTERVAL_1_8; 577 break; 578 case DIB3000_GUARD_TIME_1_4: 579 deb_getf("GUARD_INTERVAL_1_4\n"); 580 c->guard_interval = GUARD_INTERVAL_1_4; 581 break; 582 default: 583 pr_err("Unexpected Guard Time returned by TPS (%d)\n", tps_val); 584 break; 585 } 586 deb_getf("TPS: %d\n", tps_val); 587 588 switch ((tps_val = rd(DIB3000MB_REG_TPS_FFT))) { 589 case DIB3000_TRANSMISSION_MODE_2K: 590 deb_getf("TRANSMISSION_MODE_2K\n"); 591 c->transmission_mode = TRANSMISSION_MODE_2K; 592 break; 593 case DIB3000_TRANSMISSION_MODE_8K: 594 deb_getf("TRANSMISSION_MODE_8K\n"); 595 c->transmission_mode = TRANSMISSION_MODE_8K; 596 break; 597 default: 598 pr_err("unexpected transmission mode return by TPS (%d)\n", tps_val); 599 break; 600 } 601 deb_getf("TPS: %d\n", tps_val); 602 603 return 0; 604 } 605 606 static int dib3000mb_read_status(struct dvb_frontend *fe, 607 enum fe_status *stat) 608 { 609 struct dib3000_state* state = fe->demodulator_priv; 610 611 *stat = 0; 612 613 if (rd(DIB3000MB_REG_AGC_LOCK)) 614 *stat |= FE_HAS_SIGNAL; 615 if (rd(DIB3000MB_REG_CARRIER_LOCK)) 616 *stat |= FE_HAS_CARRIER; 617 if (rd(DIB3000MB_REG_VIT_LCK)) 618 *stat |= FE_HAS_VITERBI; 619 if (rd(DIB3000MB_REG_TS_SYNC_LOCK)) 620 *stat |= (FE_HAS_SYNC | FE_HAS_LOCK); 621 622 deb_getf("actual status is %2x\n",*stat); 623 624 deb_getf("autoval: tps: %d, qam: %d, hrch: %d, alpha: %d, hp: %d, lp: %d, guard: %d, fft: %d cell: %d\n", 625 rd(DIB3000MB_REG_TPS_LOCK), 626 rd(DIB3000MB_REG_TPS_QAM), 627 rd(DIB3000MB_REG_TPS_HRCH), 628 rd(DIB3000MB_REG_TPS_VIT_ALPHA), 629 rd(DIB3000MB_REG_TPS_CODE_RATE_HP), 630 rd(DIB3000MB_REG_TPS_CODE_RATE_LP), 631 rd(DIB3000MB_REG_TPS_GUARD_TIME), 632 rd(DIB3000MB_REG_TPS_FFT), 633 rd(DIB3000MB_REG_TPS_CELL_ID)); 634 635 //*stat = FE_HAS_SIGNAL | FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK; 636 return 0; 637 } 638 639 static int dib3000mb_read_ber(struct dvb_frontend* fe, u32 *ber) 640 { 641 struct dib3000_state* state = fe->demodulator_priv; 642 643 *ber = ((rd(DIB3000MB_REG_BER_MSB) << 16) | rd(DIB3000MB_REG_BER_LSB)); 644 return 0; 645 } 646 647 /* see dib3000-watch dvb-apps for exact calcuations of signal_strength and snr */ 648 static int dib3000mb_read_signal_strength(struct dvb_frontend* fe, u16 *strength) 649 { 650 struct dib3000_state* state = fe->demodulator_priv; 651 652 *strength = rd(DIB3000MB_REG_SIGNAL_POWER) * 0xffff / 0x170; 653 return 0; 654 } 655 656 static int dib3000mb_read_snr(struct dvb_frontend* fe, u16 *snr) 657 { 658 struct dib3000_state* state = fe->demodulator_priv; 659 short sigpow = rd(DIB3000MB_REG_SIGNAL_POWER); 660 int icipow = ((rd(DIB3000MB_REG_NOISE_POWER_MSB) & 0xff) << 16) | 661 rd(DIB3000MB_REG_NOISE_POWER_LSB); 662 *snr = (sigpow << 8) / ((icipow > 0) ? icipow : 1); 663 return 0; 664 } 665 666 static int dib3000mb_read_unc_blocks(struct dvb_frontend* fe, u32 *unc) 667 { 668 struct dib3000_state* state = fe->demodulator_priv; 669 670 *unc = rd(DIB3000MB_REG_PACKET_ERROR_RATE); 671 return 0; 672 } 673 674 static int dib3000mb_sleep(struct dvb_frontend* fe) 675 { 676 struct dib3000_state* state = fe->demodulator_priv; 677 deb_info("dib3000mb is going to bed.\n"); 678 wr(DIB3000MB_REG_POWER_CONTROL, DIB3000MB_POWER_DOWN); 679 return 0; 680 } 681 682 static int dib3000mb_fe_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings *tune) 683 { 684 tune->min_delay_ms = 800; 685 return 0; 686 } 687 688 static int dib3000mb_fe_init_nonmobile(struct dvb_frontend* fe) 689 { 690 return dib3000mb_fe_init(fe, 0); 691 } 692 693 static int dib3000mb_set_frontend_and_tuner(struct dvb_frontend *fe) 694 { 695 return dib3000mb_set_frontend(fe, 1); 696 } 697 698 static void dib3000mb_release(struct dvb_frontend* fe) 699 { 700 struct dib3000_state *state = fe->demodulator_priv; 701 kfree(state); 702 } 703 704 /* pid filter and transfer stuff */ 705 static int dib3000mb_pid_control(struct dvb_frontend *fe,int index, int pid,int onoff) 706 { 707 struct dib3000_state *state = fe->demodulator_priv; 708 pid = (onoff ? pid | DIB3000_ACTIVATE_PID_FILTERING : 0); 709 wr(index+DIB3000MB_REG_FIRST_PID,pid); 710 return 0; 711 } 712 713 static int dib3000mb_fifo_control(struct dvb_frontend *fe, int onoff) 714 { 715 struct dib3000_state *state = fe->demodulator_priv; 716 717 deb_xfer("%s fifo\n",onoff ? "enabling" : "disabling"); 718 if (onoff) { 719 wr(DIB3000MB_REG_FIFO, DIB3000MB_FIFO_ACTIVATE); 720 } else { 721 wr(DIB3000MB_REG_FIFO, DIB3000MB_FIFO_INHIBIT); 722 } 723 return 0; 724 } 725 726 static int dib3000mb_pid_parse(struct dvb_frontend *fe, int onoff) 727 { 728 struct dib3000_state *state = fe->demodulator_priv; 729 deb_xfer("%s pid parsing\n",onoff ? "enabling" : "disabling"); 730 wr(DIB3000MB_REG_PID_PARSE,onoff); 731 return 0; 732 } 733 734 static int dib3000mb_tuner_pass_ctrl(struct dvb_frontend *fe, int onoff, u8 pll_addr) 735 { 736 struct dib3000_state *state = fe->demodulator_priv; 737 if (onoff) { 738 wr(DIB3000MB_REG_TUNER, DIB3000_TUNER_WRITE_ENABLE(pll_addr)); 739 } else { 740 wr(DIB3000MB_REG_TUNER, DIB3000_TUNER_WRITE_DISABLE(pll_addr)); 741 } 742 return 0; 743 } 744 745 static const struct dvb_frontend_ops dib3000mb_ops; 746 747 struct dvb_frontend* dib3000mb_attach(const struct dib3000_config* config, 748 struct i2c_adapter* i2c, struct dib_fe_xfer_ops *xfer_ops) 749 { 750 struct dib3000_state* state = NULL; 751 752 /* allocate memory for the internal state */ 753 state = kzalloc(sizeof(struct dib3000_state), GFP_KERNEL); 754 if (state == NULL) 755 goto error; 756 757 /* setup the state */ 758 state->i2c = i2c; 759 memcpy(&state->config,config,sizeof(struct dib3000_config)); 760 761 /* check for the correct demod */ 762 if (rd(DIB3000_REG_MANUFACTOR_ID) != DIB3000_I2C_ID_DIBCOM) 763 goto error; 764 765 if (rd(DIB3000_REG_DEVICE_ID) != DIB3000MB_DEVICE_ID) 766 goto error; 767 768 /* create dvb_frontend */ 769 memcpy(&state->frontend.ops, &dib3000mb_ops, sizeof(struct dvb_frontend_ops)); 770 state->frontend.demodulator_priv = state; 771 772 /* set the xfer operations */ 773 xfer_ops->pid_parse = dib3000mb_pid_parse; 774 xfer_ops->fifo_ctrl = dib3000mb_fifo_control; 775 xfer_ops->pid_ctrl = dib3000mb_pid_control; 776 xfer_ops->tuner_pass_ctrl = dib3000mb_tuner_pass_ctrl; 777 778 return &state->frontend; 779 780 error: 781 kfree(state); 782 return NULL; 783 } 784 785 static const struct dvb_frontend_ops dib3000mb_ops = { 786 .delsys = { SYS_DVBT }, 787 .info = { 788 .name = "DiBcom 3000M-B DVB-T", 789 .frequency_min = 44250000, 790 .frequency_max = 867250000, 791 .frequency_stepsize = 62500, 792 .caps = FE_CAN_INVERSION_AUTO | 793 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 | 794 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO | 795 FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO | 796 FE_CAN_TRANSMISSION_MODE_AUTO | 797 FE_CAN_GUARD_INTERVAL_AUTO | 798 FE_CAN_RECOVER | 799 FE_CAN_HIERARCHY_AUTO, 800 }, 801 802 .release = dib3000mb_release, 803 804 .init = dib3000mb_fe_init_nonmobile, 805 .sleep = dib3000mb_sleep, 806 807 .set_frontend = dib3000mb_set_frontend_and_tuner, 808 .get_frontend = dib3000mb_get_frontend, 809 .get_tune_settings = dib3000mb_fe_get_tune_settings, 810 811 .read_status = dib3000mb_read_status, 812 .read_ber = dib3000mb_read_ber, 813 .read_signal_strength = dib3000mb_read_signal_strength, 814 .read_snr = dib3000mb_read_snr, 815 .read_ucblocks = dib3000mb_read_unc_blocks, 816 }; 817 818 MODULE_AUTHOR(DRIVER_AUTHOR); 819 MODULE_DESCRIPTION(DRIVER_DESC); 820 MODULE_LICENSE("GPL"); 821 822 EXPORT_SYMBOL(dib3000mb_attach); 823