1e5835488SYasunari Takiguchi /* SPDX-License-Identifier: GPL-2.0 */ 2e5835488SYasunari Takiguchi /* 3e5835488SYasunari Takiguchi * cxd2880_tnrdmd.h 4e5835488SYasunari Takiguchi * Sony CXD2880 DVB-T2/T tuner + demodulator driver 5e5835488SYasunari Takiguchi * common control interface 6e5835488SYasunari Takiguchi * 7e5835488SYasunari Takiguchi * Copyright (C) 2016, 2017, 2018 Sony Semiconductor Solutions Corporation 8e5835488SYasunari Takiguchi */ 9e5835488SYasunari Takiguchi 10e5835488SYasunari Takiguchi #ifndef CXD2880_TNRDMD_H 11e5835488SYasunari Takiguchi #define CXD2880_TNRDMD_H 12e5835488SYasunari Takiguchi 13e5835488SYasunari Takiguchi #include <linux/atomic.h> 14e5835488SYasunari Takiguchi 15e5835488SYasunari Takiguchi #include "cxd2880_common.h" 16e5835488SYasunari Takiguchi #include "cxd2880_io.h" 17e5835488SYasunari Takiguchi #include "cxd2880_dtv.h" 18e5835488SYasunari Takiguchi #include "cxd2880_dvbt.h" 19e5835488SYasunari Takiguchi #include "cxd2880_dvbt2.h" 20e5835488SYasunari Takiguchi 21e5835488SYasunari Takiguchi #define CXD2880_TNRDMD_MAX_CFG_MEM_COUNT 100 22e5835488SYasunari Takiguchi 23e5835488SYasunari Takiguchi #define slvt_unfreeze_reg(tnr_dmd) ((void)((tnr_dmd)->io->write_reg\ 24e5835488SYasunari Takiguchi ((tnr_dmd)->io, CXD2880_IO_TGT_DMD, 0x01, 0x00))) 25e5835488SYasunari Takiguchi 26e5835488SYasunari Takiguchi #define CXD2880_TNRDMD_INTERRUPT_TYPE_BUF_UNDERFLOW 0x0001 27e5835488SYasunari Takiguchi #define CXD2880_TNRDMD_INTERRUPT_TYPE_BUF_OVERFLOW 0x0002 28e5835488SYasunari Takiguchi #define CXD2880_TNRDMD_INTERRUPT_TYPE_BUF_ALMOST_EMPTY 0x0004 29e5835488SYasunari Takiguchi #define CXD2880_TNRDMD_INTERRUPT_TYPE_BUF_ALMOST_FULL 0x0008 30e5835488SYasunari Takiguchi #define CXD2880_TNRDMD_INTERRUPT_TYPE_BUF_RRDY 0x0010 31e5835488SYasunari Takiguchi #define CXD2880_TNRDMD_INTERRUPT_TYPE_ILLEGAL_COMMAND 0x0020 32e5835488SYasunari Takiguchi #define CXD2880_TNRDMD_INTERRUPT_TYPE_ILLEGAL_ACCESS 0x0040 33e5835488SYasunari Takiguchi #define CXD2880_TNRDMD_INTERRUPT_TYPE_CPU_ERROR 0x0100 34e5835488SYasunari Takiguchi #define CXD2880_TNRDMD_INTERRUPT_TYPE_LOCK 0x0200 35e5835488SYasunari Takiguchi #define CXD2880_TNRDMD_INTERRUPT_TYPE_INV_LOCK 0x0400 36e5835488SYasunari Takiguchi #define CXD2880_TNRDMD_INTERRUPT_TYPE_NOOFDM 0x0800 37e5835488SYasunari Takiguchi #define CXD2880_TNRDMD_INTERRUPT_TYPE_EWS 0x1000 38e5835488SYasunari Takiguchi #define CXD2880_TNRDMD_INTERRUPT_TYPE_EEW 0x2000 39e5835488SYasunari Takiguchi #define CXD2880_TNRDMD_INTERRUPT_TYPE_FEC_FAIL 0x4000 40e5835488SYasunari Takiguchi 41e5835488SYasunari Takiguchi #define CXD2880_TNRDMD_INTERRUPT_LOCK_SEL_L1POST_OK 0x01 42e5835488SYasunari Takiguchi #define CXD2880_TNRDMD_INTERRUPT_LOCK_SEL_DMD_LOCK 0x02 43e5835488SYasunari Takiguchi #define CXD2880_TNRDMD_INTERRUPT_LOCK_SEL_TS_LOCK 0x04 44e5835488SYasunari Takiguchi 45e5835488SYasunari Takiguchi enum cxd2880_tnrdmd_chip_id { 46e5835488SYasunari Takiguchi CXD2880_TNRDMD_CHIP_ID_UNKNOWN = 0x00, 47e5835488SYasunari Takiguchi CXD2880_TNRDMD_CHIP_ID_CXD2880_ES1_0X = 0x62, 48e5835488SYasunari Takiguchi CXD2880_TNRDMD_CHIP_ID_CXD2880_ES1_11 = 0x6a 49e5835488SYasunari Takiguchi }; 50e5835488SYasunari Takiguchi 51e5835488SYasunari Takiguchi #define CXD2880_TNRDMD_CHIP_ID_VALID(chip_id) \ 52e5835488SYasunari Takiguchi (((chip_id) == CXD2880_TNRDMD_CHIP_ID_CXD2880_ES1_0X) || \ 53e5835488SYasunari Takiguchi ((chip_id) == CXD2880_TNRDMD_CHIP_ID_CXD2880_ES1_11)) 54e5835488SYasunari Takiguchi 55e5835488SYasunari Takiguchi enum cxd2880_tnrdmd_state { 56e5835488SYasunari Takiguchi CXD2880_TNRDMD_STATE_UNKNOWN, 57e5835488SYasunari Takiguchi CXD2880_TNRDMD_STATE_SLEEP, 58e5835488SYasunari Takiguchi CXD2880_TNRDMD_STATE_ACTIVE, 59e5835488SYasunari Takiguchi CXD2880_TNRDMD_STATE_INVALID 60e5835488SYasunari Takiguchi }; 61e5835488SYasunari Takiguchi 62e5835488SYasunari Takiguchi enum cxd2880_tnrdmd_divermode { 63e5835488SYasunari Takiguchi CXD2880_TNRDMD_DIVERMODE_SINGLE, 64e5835488SYasunari Takiguchi CXD2880_TNRDMD_DIVERMODE_MAIN, 65e5835488SYasunari Takiguchi CXD2880_TNRDMD_DIVERMODE_SUB 66e5835488SYasunari Takiguchi }; 67e5835488SYasunari Takiguchi 68e5835488SYasunari Takiguchi enum cxd2880_tnrdmd_clockmode { 69e5835488SYasunari Takiguchi CXD2880_TNRDMD_CLOCKMODE_UNKNOWN, 70e5835488SYasunari Takiguchi CXD2880_TNRDMD_CLOCKMODE_A, 71e5835488SYasunari Takiguchi CXD2880_TNRDMD_CLOCKMODE_B, 72e5835488SYasunari Takiguchi CXD2880_TNRDMD_CLOCKMODE_C 73e5835488SYasunari Takiguchi }; 74e5835488SYasunari Takiguchi 75e5835488SYasunari Takiguchi enum cxd2880_tnrdmd_tsout_if { 76e5835488SYasunari Takiguchi CXD2880_TNRDMD_TSOUT_IF_TS, 77e5835488SYasunari Takiguchi CXD2880_TNRDMD_TSOUT_IF_SPI, 78e5835488SYasunari Takiguchi CXD2880_TNRDMD_TSOUT_IF_SDIO 79e5835488SYasunari Takiguchi }; 80e5835488SYasunari Takiguchi 81e5835488SYasunari Takiguchi enum cxd2880_tnrdmd_xtal_share { 82e5835488SYasunari Takiguchi CXD2880_TNRDMD_XTAL_SHARE_NONE, 83e5835488SYasunari Takiguchi CXD2880_TNRDMD_XTAL_SHARE_EXTREF, 84e5835488SYasunari Takiguchi CXD2880_TNRDMD_XTAL_SHARE_MASTER, 85e5835488SYasunari Takiguchi CXD2880_TNRDMD_XTAL_SHARE_SLAVE 86e5835488SYasunari Takiguchi }; 87e5835488SYasunari Takiguchi 88e5835488SYasunari Takiguchi enum cxd2880_tnrdmd_spectrum_sense { 89e5835488SYasunari Takiguchi CXD2880_TNRDMD_SPECTRUM_NORMAL, 90e5835488SYasunari Takiguchi CXD2880_TNRDMD_SPECTRUM_INV 91e5835488SYasunari Takiguchi }; 92e5835488SYasunari Takiguchi 93e5835488SYasunari Takiguchi enum cxd2880_tnrdmd_cfg_id { 94e5835488SYasunari Takiguchi CXD2880_TNRDMD_CFG_OUTPUT_SEL_MSB, 95e5835488SYasunari Takiguchi CXD2880_TNRDMD_CFG_TSVALID_ACTIVE_HI, 96e5835488SYasunari Takiguchi CXD2880_TNRDMD_CFG_TSSYNC_ACTIVE_HI, 97e5835488SYasunari Takiguchi CXD2880_TNRDMD_CFG_TSERR_ACTIVE_HI, 98e5835488SYasunari Takiguchi CXD2880_TNRDMD_CFG_LATCH_ON_POSEDGE, 99e5835488SYasunari Takiguchi CXD2880_TNRDMD_CFG_TSCLK_CONT, 100e5835488SYasunari Takiguchi CXD2880_TNRDMD_CFG_TSCLK_MASK, 101e5835488SYasunari Takiguchi CXD2880_TNRDMD_CFG_TSVALID_MASK, 102e5835488SYasunari Takiguchi CXD2880_TNRDMD_CFG_TSERR_MASK, 103e5835488SYasunari Takiguchi CXD2880_TNRDMD_CFG_TSERR_VALID_DIS, 104e5835488SYasunari Takiguchi CXD2880_TNRDMD_CFG_TSPIN_CURRENT, 105e5835488SYasunari Takiguchi CXD2880_TNRDMD_CFG_TSPIN_PULLUP_MANUAL, 106e5835488SYasunari Takiguchi CXD2880_TNRDMD_CFG_TSPIN_PULLUP, 107e5835488SYasunari Takiguchi CXD2880_TNRDMD_CFG_TSCLK_FREQ, 108e5835488SYasunari Takiguchi CXD2880_TNRDMD_CFG_TSBYTECLK_MANUAL, 109e5835488SYasunari Takiguchi CXD2880_TNRDMD_CFG_TS_PACKET_GAP, 110e5835488SYasunari Takiguchi CXD2880_TNRDMD_CFG_TS_BACKWARDS_COMPATIBLE, 111e5835488SYasunari Takiguchi CXD2880_TNRDMD_CFG_PWM_VALUE, 112e5835488SYasunari Takiguchi CXD2880_TNRDMD_CFG_INTERRUPT, 113e5835488SYasunari Takiguchi CXD2880_TNRDMD_CFG_INTERRUPT_LOCK_SEL, 114e5835488SYasunari Takiguchi CXD2880_TNRDMD_CFG_INTERRUPT_INV_LOCK_SEL, 115e5835488SYasunari Takiguchi CXD2880_TNRDMD_CFG_TS_BUF_ALMOST_EMPTY_THRS, 116e5835488SYasunari Takiguchi CXD2880_TNRDMD_CFG_TS_BUF_ALMOST_FULL_THRS, 117e5835488SYasunari Takiguchi CXD2880_TNRDMD_CFG_TS_BUF_RRDY_THRS, 118e5835488SYasunari Takiguchi CXD2880_TNRDMD_CFG_FIXED_CLOCKMODE, 119e5835488SYasunari Takiguchi CXD2880_TNRDMD_CFG_CABLE_INPUT, 120e5835488SYasunari Takiguchi CXD2880_TNRDMD_CFG_DVBT2_FEF_INTERMITTENT_BASE, 121e5835488SYasunari Takiguchi CXD2880_TNRDMD_CFG_DVBT2_FEF_INTERMITTENT_LITE, 122e5835488SYasunari Takiguchi CXD2880_TNRDMD_CFG_BLINDTUNE_DVBT2_FIRST, 123e5835488SYasunari Takiguchi CXD2880_TNRDMD_CFG_DVBT_BERN_PERIOD, 124e5835488SYasunari Takiguchi CXD2880_TNRDMD_CFG_DVBT_VBER_PERIOD, 125e5835488SYasunari Takiguchi CXD2880_TNRDMD_CFG_DVBT_PER_MES, 126e5835488SYasunari Takiguchi CXD2880_TNRDMD_CFG_DVBT2_BBER_MES, 127e5835488SYasunari Takiguchi CXD2880_TNRDMD_CFG_DVBT2_LBER_MES, 128e5835488SYasunari Takiguchi CXD2880_TNRDMD_CFG_DVBT2_PER_MES, 129e5835488SYasunari Takiguchi }; 130e5835488SYasunari Takiguchi 131e5835488SYasunari Takiguchi enum cxd2880_tnrdmd_lock_result { 132e5835488SYasunari Takiguchi CXD2880_TNRDMD_LOCK_RESULT_NOTDETECT, 133e5835488SYasunari Takiguchi CXD2880_TNRDMD_LOCK_RESULT_LOCKED, 134e5835488SYasunari Takiguchi CXD2880_TNRDMD_LOCK_RESULT_UNLOCKED 135e5835488SYasunari Takiguchi }; 136e5835488SYasunari Takiguchi 137e5835488SYasunari Takiguchi enum cxd2880_tnrdmd_gpio_mode { 138e5835488SYasunari Takiguchi CXD2880_TNRDMD_GPIO_MODE_OUTPUT = 0x00, 139e5835488SYasunari Takiguchi CXD2880_TNRDMD_GPIO_MODE_INPUT = 0x01, 140e5835488SYasunari Takiguchi CXD2880_TNRDMD_GPIO_MODE_INT = 0x02, 141e5835488SYasunari Takiguchi CXD2880_TNRDMD_GPIO_MODE_FEC_FAIL = 0x03, 142e5835488SYasunari Takiguchi CXD2880_TNRDMD_GPIO_MODE_PWM = 0x04, 143e5835488SYasunari Takiguchi CXD2880_TNRDMD_GPIO_MODE_EWS = 0x05, 144e5835488SYasunari Takiguchi CXD2880_TNRDMD_GPIO_MODE_EEW = 0x06 145e5835488SYasunari Takiguchi }; 146e5835488SYasunari Takiguchi 147e5835488SYasunari Takiguchi enum cxd2880_tnrdmd_serial_ts_clk { 148e5835488SYasunari Takiguchi CXD2880_TNRDMD_SERIAL_TS_CLK_FULL, 149e5835488SYasunari Takiguchi CXD2880_TNRDMD_SERIAL_TS_CLK_HALF 150e5835488SYasunari Takiguchi }; 151e5835488SYasunari Takiguchi 152e5835488SYasunari Takiguchi struct cxd2880_tnrdmd_cfg_mem { 153e5835488SYasunari Takiguchi enum cxd2880_io_tgt tgt; 154e5835488SYasunari Takiguchi u8 bank; 155e5835488SYasunari Takiguchi u8 address; 156e5835488SYasunari Takiguchi u8 value; 157e5835488SYasunari Takiguchi u8 bit_mask; 158e5835488SYasunari Takiguchi }; 159e5835488SYasunari Takiguchi 160e5835488SYasunari Takiguchi struct cxd2880_tnrdmd_pid_cfg { 161e5835488SYasunari Takiguchi u8 is_en; 162e5835488SYasunari Takiguchi u16 pid; 163e5835488SYasunari Takiguchi }; 164e5835488SYasunari Takiguchi 165e5835488SYasunari Takiguchi struct cxd2880_tnrdmd_pid_ftr_cfg { 166e5835488SYasunari Takiguchi u8 is_negative; 167e5835488SYasunari Takiguchi struct cxd2880_tnrdmd_pid_cfg pid_cfg[32]; 168e5835488SYasunari Takiguchi }; 169e5835488SYasunari Takiguchi 170e5835488SYasunari Takiguchi struct cxd2880_tnrdmd_lna_thrs { 171e5835488SYasunari Takiguchi u8 off_on; 172e5835488SYasunari Takiguchi u8 on_off; 173e5835488SYasunari Takiguchi }; 174e5835488SYasunari Takiguchi 175e5835488SYasunari Takiguchi struct cxd2880_tnrdmd_lna_thrs_tbl_air { 176e5835488SYasunari Takiguchi struct cxd2880_tnrdmd_lna_thrs thrs[24]; 177e5835488SYasunari Takiguchi }; 178e5835488SYasunari Takiguchi 179e5835488SYasunari Takiguchi struct cxd2880_tnrdmd_lna_thrs_tbl_cable { 180e5835488SYasunari Takiguchi struct cxd2880_tnrdmd_lna_thrs thrs[32]; 181e5835488SYasunari Takiguchi }; 182e5835488SYasunari Takiguchi 183e5835488SYasunari Takiguchi struct cxd2880_tnrdmd_create_param { 184e5835488SYasunari Takiguchi enum cxd2880_tnrdmd_tsout_if ts_output_if; 185e5835488SYasunari Takiguchi u8 en_internal_ldo; 186e5835488SYasunari Takiguchi enum cxd2880_tnrdmd_xtal_share xtal_share_type; 187e5835488SYasunari Takiguchi u8 xosc_cap; 188e5835488SYasunari Takiguchi u8 xosc_i; 189e5835488SYasunari Takiguchi u8 is_cxd2881gg; 190e5835488SYasunari Takiguchi u8 stationary_use; 191e5835488SYasunari Takiguchi }; 192e5835488SYasunari Takiguchi 193e5835488SYasunari Takiguchi struct cxd2880_tnrdmd_diver_create_param { 194e5835488SYasunari Takiguchi enum cxd2880_tnrdmd_tsout_if ts_output_if; 195e5835488SYasunari Takiguchi u8 en_internal_ldo; 196e5835488SYasunari Takiguchi u8 xosc_cap_main; 197e5835488SYasunari Takiguchi u8 xosc_i_main; 198e5835488SYasunari Takiguchi u8 xosc_i_sub; 199e5835488SYasunari Takiguchi u8 is_cxd2881gg; 200e5835488SYasunari Takiguchi u8 stationary_use; 201e5835488SYasunari Takiguchi }; 202e5835488SYasunari Takiguchi 203e5835488SYasunari Takiguchi struct cxd2880_tnrdmd { 204e5835488SYasunari Takiguchi struct cxd2880_tnrdmd *diver_sub; 205e5835488SYasunari Takiguchi struct cxd2880_io *io; 206e5835488SYasunari Takiguchi struct cxd2880_tnrdmd_create_param create_param; 207e5835488SYasunari Takiguchi enum cxd2880_tnrdmd_divermode diver_mode; 208e5835488SYasunari Takiguchi enum cxd2880_tnrdmd_clockmode fixed_clk_mode; 209e5835488SYasunari Takiguchi u8 is_cable_input; 210e5835488SYasunari Takiguchi u8 en_fef_intmtnt_base; 211e5835488SYasunari Takiguchi u8 en_fef_intmtnt_lite; 212e5835488SYasunari Takiguchi u8 blind_tune_dvbt2_first; 213e5835488SYasunari Takiguchi int (*rf_lvl_cmpstn)(struct cxd2880_tnrdmd *tnr_dmd, 214e5835488SYasunari Takiguchi int *rf_lvl_db); 215e5835488SYasunari Takiguchi struct cxd2880_tnrdmd_lna_thrs_tbl_air *lna_thrs_tbl_air; 216e5835488SYasunari Takiguchi struct cxd2880_tnrdmd_lna_thrs_tbl_cable *lna_thrs_tbl_cable; 217e5835488SYasunari Takiguchi u8 srl_ts_clk_mod_cnts; 218e5835488SYasunari Takiguchi enum cxd2880_tnrdmd_serial_ts_clk srl_ts_clk_frq; 219e5835488SYasunari Takiguchi u8 ts_byte_clk_manual_setting; 220e5835488SYasunari Takiguchi u8 is_ts_backwards_compatible_mode; 221e5835488SYasunari Takiguchi struct cxd2880_tnrdmd_cfg_mem cfg_mem[CXD2880_TNRDMD_MAX_CFG_MEM_COUNT]; 222e5835488SYasunari Takiguchi u8 cfg_mem_last_entry; 223e5835488SYasunari Takiguchi struct cxd2880_tnrdmd_pid_ftr_cfg pid_ftr_cfg; 224e5835488SYasunari Takiguchi u8 pid_ftr_cfg_en; 225e5835488SYasunari Takiguchi void *user; 226e5835488SYasunari Takiguchi enum cxd2880_tnrdmd_chip_id chip_id; 227e5835488SYasunari Takiguchi enum cxd2880_tnrdmd_state state; 228e5835488SYasunari Takiguchi enum cxd2880_tnrdmd_clockmode clk_mode; 229e5835488SYasunari Takiguchi u32 frequency_khz; 230e5835488SYasunari Takiguchi enum cxd2880_dtv_sys sys; 231e5835488SYasunari Takiguchi enum cxd2880_dtv_bandwidth bandwidth; 232e5835488SYasunari Takiguchi u8 scan_mode; 233e5835488SYasunari Takiguchi atomic_t cancel; 234e5835488SYasunari Takiguchi }; 235e5835488SYasunari Takiguchi 236e5835488SYasunari Takiguchi int cxd2880_tnrdmd_create(struct cxd2880_tnrdmd *tnr_dmd, 237e5835488SYasunari Takiguchi struct cxd2880_io *io, 238e5835488SYasunari Takiguchi struct cxd2880_tnrdmd_create_param 239e5835488SYasunari Takiguchi *create_param); 240e5835488SYasunari Takiguchi 241e5835488SYasunari Takiguchi int cxd2880_tnrdmd_diver_create(struct cxd2880_tnrdmd 242e5835488SYasunari Takiguchi *tnr_dmd_main, 243e5835488SYasunari Takiguchi struct cxd2880_io *io_main, 244e5835488SYasunari Takiguchi struct cxd2880_tnrdmd *tnr_dmd_sub, 245e5835488SYasunari Takiguchi struct cxd2880_io *io_sub, 246e5835488SYasunari Takiguchi struct 247e5835488SYasunari Takiguchi cxd2880_tnrdmd_diver_create_param 248e5835488SYasunari Takiguchi *create_param); 249e5835488SYasunari Takiguchi 250e5835488SYasunari Takiguchi int cxd2880_tnrdmd_init1(struct cxd2880_tnrdmd *tnr_dmd); 251e5835488SYasunari Takiguchi 252e5835488SYasunari Takiguchi int cxd2880_tnrdmd_init2(struct cxd2880_tnrdmd *tnr_dmd); 253e5835488SYasunari Takiguchi 254e5835488SYasunari Takiguchi int cxd2880_tnrdmd_check_internal_cpu_status(struct cxd2880_tnrdmd 255e5835488SYasunari Takiguchi *tnr_dmd, 256e5835488SYasunari Takiguchi u8 *task_completed); 257e5835488SYasunari Takiguchi 258e5835488SYasunari Takiguchi int cxd2880_tnrdmd_common_tune_setting1(struct cxd2880_tnrdmd 259e5835488SYasunari Takiguchi *tnr_dmd, 260e5835488SYasunari Takiguchi enum cxd2880_dtv_sys sys, 261e5835488SYasunari Takiguchi u32 frequency_khz, 262e5835488SYasunari Takiguchi enum cxd2880_dtv_bandwidth 263e5835488SYasunari Takiguchi bandwidth, u8 one_seg_opt, 264e5835488SYasunari Takiguchi u8 one_seg_opt_shft_dir); 265e5835488SYasunari Takiguchi 266e5835488SYasunari Takiguchi int cxd2880_tnrdmd_common_tune_setting2(struct cxd2880_tnrdmd 267e5835488SYasunari Takiguchi *tnr_dmd, 268e5835488SYasunari Takiguchi enum cxd2880_dtv_sys sys, 269e5835488SYasunari Takiguchi u8 en_fef_intmtnt_ctrl); 270e5835488SYasunari Takiguchi 271e5835488SYasunari Takiguchi int cxd2880_tnrdmd_sleep(struct cxd2880_tnrdmd *tnr_dmd); 272e5835488SYasunari Takiguchi 273e5835488SYasunari Takiguchi int cxd2880_tnrdmd_set_cfg(struct cxd2880_tnrdmd *tnr_dmd, 274e5835488SYasunari Takiguchi enum cxd2880_tnrdmd_cfg_id id, 275e5835488SYasunari Takiguchi int value); 276e5835488SYasunari Takiguchi 277e5835488SYasunari Takiguchi int cxd2880_tnrdmd_gpio_set_cfg(struct cxd2880_tnrdmd *tnr_dmd, 278e5835488SYasunari Takiguchi u8 id, 279e5835488SYasunari Takiguchi u8 en, 280e5835488SYasunari Takiguchi enum cxd2880_tnrdmd_gpio_mode mode, 281e5835488SYasunari Takiguchi u8 open_drain, u8 invert); 282e5835488SYasunari Takiguchi 283e5835488SYasunari Takiguchi int cxd2880_tnrdmd_gpio_set_cfg_sub(struct cxd2880_tnrdmd *tnr_dmd, 284e5835488SYasunari Takiguchi u8 id, 285e5835488SYasunari Takiguchi u8 en, 286e5835488SYasunari Takiguchi enum cxd2880_tnrdmd_gpio_mode 287e5835488SYasunari Takiguchi mode, u8 open_drain, 288e5835488SYasunari Takiguchi u8 invert); 289e5835488SYasunari Takiguchi 290e5835488SYasunari Takiguchi int cxd2880_tnrdmd_gpio_read(struct cxd2880_tnrdmd *tnr_dmd, 291e5835488SYasunari Takiguchi u8 id, u8 *value); 292e5835488SYasunari Takiguchi 293e5835488SYasunari Takiguchi int cxd2880_tnrdmd_gpio_read_sub(struct cxd2880_tnrdmd *tnr_dmd, 294e5835488SYasunari Takiguchi u8 id, u8 *value); 295e5835488SYasunari Takiguchi 296e5835488SYasunari Takiguchi int cxd2880_tnrdmd_gpio_write(struct cxd2880_tnrdmd *tnr_dmd, 297e5835488SYasunari Takiguchi u8 id, u8 value); 298e5835488SYasunari Takiguchi 299e5835488SYasunari Takiguchi int cxd2880_tnrdmd_gpio_write_sub(struct cxd2880_tnrdmd *tnr_dmd, 300e5835488SYasunari Takiguchi u8 id, u8 value); 301e5835488SYasunari Takiguchi 302e5835488SYasunari Takiguchi int cxd2880_tnrdmd_interrupt_read(struct cxd2880_tnrdmd *tnr_dmd, 303e5835488SYasunari Takiguchi u16 *value); 304e5835488SYasunari Takiguchi 305e5835488SYasunari Takiguchi int cxd2880_tnrdmd_interrupt_clear(struct cxd2880_tnrdmd *tnr_dmd, 306e5835488SYasunari Takiguchi u16 value); 307e5835488SYasunari Takiguchi 308e5835488SYasunari Takiguchi int cxd2880_tnrdmd_ts_buf_clear(struct cxd2880_tnrdmd *tnr_dmd, 309e5835488SYasunari Takiguchi u8 clear_overflow_flag, 310e5835488SYasunari Takiguchi u8 clear_underflow_flag, 311e5835488SYasunari Takiguchi u8 clear_buf); 312e5835488SYasunari Takiguchi 313e5835488SYasunari Takiguchi int cxd2880_tnrdmd_chip_id(struct cxd2880_tnrdmd *tnr_dmd, 314e5835488SYasunari Takiguchi enum cxd2880_tnrdmd_chip_id *chip_id); 315e5835488SYasunari Takiguchi 316e5835488SYasunari Takiguchi int cxd2880_tnrdmd_set_and_save_reg_bits(struct cxd2880_tnrdmd 317e5835488SYasunari Takiguchi *tnr_dmd, 318e5835488SYasunari Takiguchi enum cxd2880_io_tgt tgt, 319e5835488SYasunari Takiguchi u8 bank, u8 address, 320e5835488SYasunari Takiguchi u8 value, u8 bit_mask); 321e5835488SYasunari Takiguchi 322e5835488SYasunari Takiguchi int cxd2880_tnrdmd_set_scan_mode(struct cxd2880_tnrdmd *tnr_dmd, 323e5835488SYasunari Takiguchi enum cxd2880_dtv_sys sys, 324e5835488SYasunari Takiguchi u8 scan_mode_end); 325e5835488SYasunari Takiguchi 326e5835488SYasunari Takiguchi int cxd2880_tnrdmd_set_pid_ftr(struct cxd2880_tnrdmd *tnr_dmd, 327e5835488SYasunari Takiguchi struct cxd2880_tnrdmd_pid_ftr_cfg 328e5835488SYasunari Takiguchi *pid_ftr_cfg); 329e5835488SYasunari Takiguchi 330e5835488SYasunari Takiguchi int cxd2880_tnrdmd_set_rf_lvl_cmpstn(struct cxd2880_tnrdmd 331e5835488SYasunari Takiguchi *tnr_dmd, 332e5835488SYasunari Takiguchi int (*rf_lvl_cmpstn) 333e5835488SYasunari Takiguchi (struct cxd2880_tnrdmd *, 334e5835488SYasunari Takiguchi int *)); 335e5835488SYasunari Takiguchi 336e5835488SYasunari Takiguchi int cxd2880_tnrdmd_set_rf_lvl_cmpstn_sub(struct cxd2880_tnrdmd *tnr_dmd, 337e5835488SYasunari Takiguchi int (*rf_lvl_cmpstn) 338e5835488SYasunari Takiguchi (struct cxd2880_tnrdmd *, 339e5835488SYasunari Takiguchi int *)); 340e5835488SYasunari Takiguchi 341e5835488SYasunari Takiguchi int cxd2880_tnrdmd_set_lna_thrs(struct cxd2880_tnrdmd *tnr_dmd, 342e5835488SYasunari Takiguchi struct 343e5835488SYasunari Takiguchi cxd2880_tnrdmd_lna_thrs_tbl_air 344e5835488SYasunari Takiguchi *tbl_air, 345e5835488SYasunari Takiguchi struct 346e5835488SYasunari Takiguchi cxd2880_tnrdmd_lna_thrs_tbl_cable 347e5835488SYasunari Takiguchi *tbl_cable); 348e5835488SYasunari Takiguchi 349e5835488SYasunari Takiguchi int cxd2880_tnrdmd_set_lna_thrs_sub(struct cxd2880_tnrdmd *tnr_dmd, 350e5835488SYasunari Takiguchi struct 351e5835488SYasunari Takiguchi cxd2880_tnrdmd_lna_thrs_tbl_air 352e5835488SYasunari Takiguchi *tbl_air, 353e5835488SYasunari Takiguchi struct 354e5835488SYasunari Takiguchi cxd2880_tnrdmd_lna_thrs_tbl_cable 355e5835488SYasunari Takiguchi *tbl_cable); 356e5835488SYasunari Takiguchi 357e5835488SYasunari Takiguchi int cxd2880_tnrdmd_set_ts_pin_high_low(struct cxd2880_tnrdmd 358e5835488SYasunari Takiguchi *tnr_dmd, u8 en, u8 value); 359e5835488SYasunari Takiguchi 360e5835488SYasunari Takiguchi int cxd2880_tnrdmd_set_ts_output(struct cxd2880_tnrdmd *tnr_dmd, 361e5835488SYasunari Takiguchi u8 en); 362e5835488SYasunari Takiguchi 363e5835488SYasunari Takiguchi int slvt_freeze_reg(struct cxd2880_tnrdmd *tnr_dmd); 364e5835488SYasunari Takiguchi 365e5835488SYasunari Takiguchi #endif 366