1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * cxd2841er.c 4 * 5 * Sony digital demodulator driver for 6 * CXD2841ER - DVB-S/S2/T/T2/C/C2 7 * CXD2854ER - DVB-S/S2/T/T2/C/C2, ISDB-T/S 8 * 9 * Copyright 2012 Sony Corporation 10 * Copyright (C) 2014 NetUP Inc. 11 * Copyright (C) 2014 Sergey Kozlov <serjk@netup.ru> 12 * Copyright (C) 2014 Abylay Ospan <aospan@netup.ru> 13 */ 14 15 #include <linux/module.h> 16 #include <linux/init.h> 17 #include <linux/string.h> 18 #include <linux/slab.h> 19 #include <linux/bitops.h> 20 #include <linux/math64.h> 21 #include <linux/log2.h> 22 #include <linux/dynamic_debug.h> 23 #include <linux/kernel.h> 24 25 #include <media/dvb_math.h> 26 #include <media/dvb_frontend.h> 27 #include "cxd2841er.h" 28 #include "cxd2841er_priv.h" 29 30 #define MAX_WRITE_REGSIZE 16 31 #define LOG2_E_100X 144 32 33 #define INTLOG10X100(x) ((u32) (((u64) intlog10(x) * 100) >> 24)) 34 35 /* DVB-C constellation */ 36 enum sony_dvbc_constellation_t { 37 SONY_DVBC_CONSTELLATION_16QAM, 38 SONY_DVBC_CONSTELLATION_32QAM, 39 SONY_DVBC_CONSTELLATION_64QAM, 40 SONY_DVBC_CONSTELLATION_128QAM, 41 SONY_DVBC_CONSTELLATION_256QAM 42 }; 43 44 enum cxd2841er_state { 45 STATE_SHUTDOWN = 0, 46 STATE_SLEEP_S, 47 STATE_ACTIVE_S, 48 STATE_SLEEP_TC, 49 STATE_ACTIVE_TC 50 }; 51 52 struct cxd2841er_priv { 53 struct dvb_frontend frontend; 54 struct i2c_adapter *i2c; 55 u8 i2c_addr_slvx; 56 u8 i2c_addr_slvt; 57 const struct cxd2841er_config *config; 58 enum cxd2841er_state state; 59 u8 system; 60 enum cxd2841er_xtal xtal; 61 enum fe_caps caps; 62 u32 flags; 63 }; 64 65 static const struct cxd2841er_cnr_data s_cn_data[] = { 66 { 0x033e, 0 }, { 0x0339, 100 }, { 0x0333, 200 }, 67 { 0x032e, 300 }, { 0x0329, 400 }, { 0x0324, 500 }, 68 { 0x031e, 600 }, { 0x0319, 700 }, { 0x0314, 800 }, 69 { 0x030f, 900 }, { 0x030a, 1000 }, { 0x02ff, 1100 }, 70 { 0x02f4, 1200 }, { 0x02e9, 1300 }, { 0x02de, 1400 }, 71 { 0x02d4, 1500 }, { 0x02c9, 1600 }, { 0x02bf, 1700 }, 72 { 0x02b5, 1800 }, { 0x02ab, 1900 }, { 0x02a1, 2000 }, 73 { 0x029b, 2100 }, { 0x0295, 2200 }, { 0x0290, 2300 }, 74 { 0x028a, 2400 }, { 0x0284, 2500 }, { 0x027f, 2600 }, 75 { 0x0279, 2700 }, { 0x0274, 2800 }, { 0x026e, 2900 }, 76 { 0x0269, 3000 }, { 0x0262, 3100 }, { 0x025c, 3200 }, 77 { 0x0255, 3300 }, { 0x024f, 3400 }, { 0x0249, 3500 }, 78 { 0x0242, 3600 }, { 0x023c, 3700 }, { 0x0236, 3800 }, 79 { 0x0230, 3900 }, { 0x022a, 4000 }, { 0x0223, 4100 }, 80 { 0x021c, 4200 }, { 0x0215, 4300 }, { 0x020e, 4400 }, 81 { 0x0207, 4500 }, { 0x0201, 4600 }, { 0x01fa, 4700 }, 82 { 0x01f4, 4800 }, { 0x01ed, 4900 }, { 0x01e7, 5000 }, 83 { 0x01e0, 5100 }, { 0x01d9, 5200 }, { 0x01d2, 5300 }, 84 { 0x01cb, 5400 }, { 0x01c4, 5500 }, { 0x01be, 5600 }, 85 { 0x01b7, 5700 }, { 0x01b1, 5800 }, { 0x01aa, 5900 }, 86 { 0x01a4, 6000 }, { 0x019d, 6100 }, { 0x0196, 6200 }, 87 { 0x018f, 6300 }, { 0x0189, 6400 }, { 0x0182, 6500 }, 88 { 0x017c, 6600 }, { 0x0175, 6700 }, { 0x016f, 6800 }, 89 { 0x0169, 6900 }, { 0x0163, 7000 }, { 0x015c, 7100 }, 90 { 0x0156, 7200 }, { 0x0150, 7300 }, { 0x014a, 7400 }, 91 { 0x0144, 7500 }, { 0x013e, 7600 }, { 0x0138, 7700 }, 92 { 0x0132, 7800 }, { 0x012d, 7900 }, { 0x0127, 8000 }, 93 { 0x0121, 8100 }, { 0x011c, 8200 }, { 0x0116, 8300 }, 94 { 0x0111, 8400 }, { 0x010b, 8500 }, { 0x0106, 8600 }, 95 { 0x0101, 8700 }, { 0x00fc, 8800 }, { 0x00f7, 8900 }, 96 { 0x00f2, 9000 }, { 0x00ee, 9100 }, { 0x00ea, 9200 }, 97 { 0x00e6, 9300 }, { 0x00e2, 9400 }, { 0x00de, 9500 }, 98 { 0x00da, 9600 }, { 0x00d7, 9700 }, { 0x00d3, 9800 }, 99 { 0x00d0, 9900 }, { 0x00cc, 10000 }, { 0x00c7, 10100 }, 100 { 0x00c3, 10200 }, { 0x00bf, 10300 }, { 0x00ba, 10400 }, 101 { 0x00b6, 10500 }, { 0x00b2, 10600 }, { 0x00ae, 10700 }, 102 { 0x00aa, 10800 }, { 0x00a7, 10900 }, { 0x00a3, 11000 }, 103 { 0x009f, 11100 }, { 0x009c, 11200 }, { 0x0098, 11300 }, 104 { 0x0094, 11400 }, { 0x0091, 11500 }, { 0x008e, 11600 }, 105 { 0x008a, 11700 }, { 0x0087, 11800 }, { 0x0084, 11900 }, 106 { 0x0081, 12000 }, { 0x007e, 12100 }, { 0x007b, 12200 }, 107 { 0x0079, 12300 }, { 0x0076, 12400 }, { 0x0073, 12500 }, 108 { 0x0071, 12600 }, { 0x006e, 12700 }, { 0x006c, 12800 }, 109 { 0x0069, 12900 }, { 0x0067, 13000 }, { 0x0065, 13100 }, 110 { 0x0062, 13200 }, { 0x0060, 13300 }, { 0x005e, 13400 }, 111 { 0x005c, 13500 }, { 0x005a, 13600 }, { 0x0058, 13700 }, 112 { 0x0056, 13800 }, { 0x0054, 13900 }, { 0x0052, 14000 }, 113 { 0x0050, 14100 }, { 0x004e, 14200 }, { 0x004c, 14300 }, 114 { 0x004b, 14400 }, { 0x0049, 14500 }, { 0x0047, 14600 }, 115 { 0x0046, 14700 }, { 0x0044, 14800 }, { 0x0043, 14900 }, 116 { 0x0041, 15000 }, { 0x003f, 15100 }, { 0x003e, 15200 }, 117 { 0x003c, 15300 }, { 0x003b, 15400 }, { 0x003a, 15500 }, 118 { 0x0037, 15700 }, { 0x0036, 15800 }, { 0x0034, 15900 }, 119 { 0x0033, 16000 }, { 0x0032, 16100 }, { 0x0031, 16200 }, 120 { 0x0030, 16300 }, { 0x002f, 16400 }, { 0x002e, 16500 }, 121 { 0x002d, 16600 }, { 0x002c, 16700 }, { 0x002b, 16800 }, 122 { 0x002a, 16900 }, { 0x0029, 17000 }, { 0x0028, 17100 }, 123 { 0x0027, 17200 }, { 0x0026, 17300 }, { 0x0025, 17400 }, 124 { 0x0024, 17500 }, { 0x0023, 17600 }, { 0x0022, 17800 }, 125 { 0x0021, 17900 }, { 0x0020, 18000 }, { 0x001f, 18200 }, 126 { 0x001e, 18300 }, { 0x001d, 18500 }, { 0x001c, 18700 }, 127 { 0x001b, 18900 }, { 0x001a, 19000 }, { 0x0019, 19200 }, 128 { 0x0018, 19300 }, { 0x0017, 19500 }, { 0x0016, 19700 }, 129 { 0x0015, 19900 }, { 0x0014, 20000 }, 130 }; 131 132 static const struct cxd2841er_cnr_data s2_cn_data[] = { 133 { 0x05af, 0 }, { 0x0597, 100 }, { 0x057e, 200 }, 134 { 0x0567, 300 }, { 0x0550, 400 }, { 0x0539, 500 }, 135 { 0x0522, 600 }, { 0x050c, 700 }, { 0x04f6, 800 }, 136 { 0x04e1, 900 }, { 0x04cc, 1000 }, { 0x04b6, 1100 }, 137 { 0x04a1, 1200 }, { 0x048c, 1300 }, { 0x0477, 1400 }, 138 { 0x0463, 1500 }, { 0x044f, 1600 }, { 0x043c, 1700 }, 139 { 0x0428, 1800 }, { 0x0416, 1900 }, { 0x0403, 2000 }, 140 { 0x03ef, 2100 }, { 0x03dc, 2200 }, { 0x03c9, 2300 }, 141 { 0x03b6, 2400 }, { 0x03a4, 2500 }, { 0x0392, 2600 }, 142 { 0x0381, 2700 }, { 0x036f, 2800 }, { 0x035f, 2900 }, 143 { 0x034e, 3000 }, { 0x033d, 3100 }, { 0x032d, 3200 }, 144 { 0x031d, 3300 }, { 0x030d, 3400 }, { 0x02fd, 3500 }, 145 { 0x02ee, 3600 }, { 0x02df, 3700 }, { 0x02d0, 3800 }, 146 { 0x02c2, 3900 }, { 0x02b4, 4000 }, { 0x02a6, 4100 }, 147 { 0x0299, 4200 }, { 0x028c, 4300 }, { 0x027f, 4400 }, 148 { 0x0272, 4500 }, { 0x0265, 4600 }, { 0x0259, 4700 }, 149 { 0x024d, 4800 }, { 0x0241, 4900 }, { 0x0236, 5000 }, 150 { 0x022b, 5100 }, { 0x0220, 5200 }, { 0x0215, 5300 }, 151 { 0x020a, 5400 }, { 0x0200, 5500 }, { 0x01f6, 5600 }, 152 { 0x01ec, 5700 }, { 0x01e2, 5800 }, { 0x01d8, 5900 }, 153 { 0x01cf, 6000 }, { 0x01c6, 6100 }, { 0x01bc, 6200 }, 154 { 0x01b3, 6300 }, { 0x01aa, 6400 }, { 0x01a2, 6500 }, 155 { 0x0199, 6600 }, { 0x0191, 6700 }, { 0x0189, 6800 }, 156 { 0x0181, 6900 }, { 0x0179, 7000 }, { 0x0171, 7100 }, 157 { 0x0169, 7200 }, { 0x0161, 7300 }, { 0x015a, 7400 }, 158 { 0x0153, 7500 }, { 0x014b, 7600 }, { 0x0144, 7700 }, 159 { 0x013d, 7800 }, { 0x0137, 7900 }, { 0x0130, 8000 }, 160 { 0x012a, 8100 }, { 0x0124, 8200 }, { 0x011e, 8300 }, 161 { 0x0118, 8400 }, { 0x0112, 8500 }, { 0x010c, 8600 }, 162 { 0x0107, 8700 }, { 0x0101, 8800 }, { 0x00fc, 8900 }, 163 { 0x00f7, 9000 }, { 0x00f2, 9100 }, { 0x00ec, 9200 }, 164 { 0x00e7, 9300 }, { 0x00e2, 9400 }, { 0x00dd, 9500 }, 165 { 0x00d8, 9600 }, { 0x00d4, 9700 }, { 0x00cf, 9800 }, 166 { 0x00ca, 9900 }, { 0x00c6, 10000 }, { 0x00c2, 10100 }, 167 { 0x00be, 10200 }, { 0x00b9, 10300 }, { 0x00b5, 10400 }, 168 { 0x00b1, 10500 }, { 0x00ae, 10600 }, { 0x00aa, 10700 }, 169 { 0x00a6, 10800 }, { 0x00a3, 10900 }, { 0x009f, 11000 }, 170 { 0x009b, 11100 }, { 0x0098, 11200 }, { 0x0095, 11300 }, 171 { 0x0091, 11400 }, { 0x008e, 11500 }, { 0x008b, 11600 }, 172 { 0x0088, 11700 }, { 0x0085, 11800 }, { 0x0082, 11900 }, 173 { 0x007f, 12000 }, { 0x007c, 12100 }, { 0x007a, 12200 }, 174 { 0x0077, 12300 }, { 0x0074, 12400 }, { 0x0072, 12500 }, 175 { 0x006f, 12600 }, { 0x006d, 12700 }, { 0x006b, 12800 }, 176 { 0x0068, 12900 }, { 0x0066, 13000 }, { 0x0064, 13100 }, 177 { 0x0061, 13200 }, { 0x005f, 13300 }, { 0x005d, 13400 }, 178 { 0x005b, 13500 }, { 0x0059, 13600 }, { 0x0057, 13700 }, 179 { 0x0055, 13800 }, { 0x0053, 13900 }, { 0x0051, 14000 }, 180 { 0x004f, 14100 }, { 0x004e, 14200 }, { 0x004c, 14300 }, 181 { 0x004a, 14400 }, { 0x0049, 14500 }, { 0x0047, 14600 }, 182 { 0x0045, 14700 }, { 0x0044, 14800 }, { 0x0042, 14900 }, 183 { 0x0041, 15000 }, { 0x003f, 15100 }, { 0x003e, 15200 }, 184 { 0x003c, 15300 }, { 0x003b, 15400 }, { 0x003a, 15500 }, 185 { 0x0038, 15600 }, { 0x0037, 15700 }, { 0x0036, 15800 }, 186 { 0x0034, 15900 }, { 0x0033, 16000 }, { 0x0032, 16100 }, 187 { 0x0031, 16200 }, { 0x0030, 16300 }, { 0x002f, 16400 }, 188 { 0x002e, 16500 }, { 0x002d, 16600 }, { 0x002c, 16700 }, 189 { 0x002b, 16800 }, { 0x002a, 16900 }, { 0x0029, 17000 }, 190 { 0x0028, 17100 }, { 0x0027, 17200 }, { 0x0026, 17300 }, 191 { 0x0025, 17400 }, { 0x0024, 17500 }, { 0x0023, 17600 }, 192 { 0x0022, 17800 }, { 0x0021, 17900 }, { 0x0020, 18000 }, 193 { 0x001f, 18200 }, { 0x001e, 18300 }, { 0x001d, 18500 }, 194 { 0x001c, 18700 }, { 0x001b, 18900 }, { 0x001a, 19000 }, 195 { 0x0019, 19200 }, { 0x0018, 19300 }, { 0x0017, 19500 }, 196 { 0x0016, 19700 }, { 0x0015, 19900 }, { 0x0014, 20000 }, 197 }; 198 199 static int cxd2841er_freeze_regs(struct cxd2841er_priv *priv); 200 static int cxd2841er_unfreeze_regs(struct cxd2841er_priv *priv); 201 202 static void cxd2841er_i2c_debug(struct cxd2841er_priv *priv, 203 u8 addr, u8 reg, u8 write, 204 const u8 *data, u32 len) 205 { 206 dev_dbg(&priv->i2c->dev, 207 "cxd2841er: I2C %s addr %02x reg 0x%02x size %d data %*ph\n", 208 (write == 0 ? "read" : "write"), addr, reg, len, len, data); 209 } 210 211 static int cxd2841er_write_regs(struct cxd2841er_priv *priv, 212 u8 addr, u8 reg, const u8 *data, u32 len) 213 { 214 int ret; 215 u8 buf[MAX_WRITE_REGSIZE + 1]; 216 u8 i2c_addr = (addr == I2C_SLVX ? 217 priv->i2c_addr_slvx : priv->i2c_addr_slvt); 218 struct i2c_msg msg[1] = { 219 { 220 .addr = i2c_addr, 221 .flags = 0, 222 .len = len + 1, 223 .buf = buf, 224 } 225 }; 226 227 if (len + 1 >= sizeof(buf)) { 228 dev_warn(&priv->i2c->dev, "wr reg=%04x: len=%d is too big!\n", 229 reg, len + 1); 230 return -E2BIG; 231 } 232 233 cxd2841er_i2c_debug(priv, i2c_addr, reg, 1, data, len); 234 buf[0] = reg; 235 memcpy(&buf[1], data, len); 236 237 ret = i2c_transfer(priv->i2c, msg, 1); 238 if (ret >= 0 && ret != 1) 239 ret = -EIO; 240 if (ret < 0) { 241 dev_warn(&priv->i2c->dev, 242 "%s: i2c wr failed=%d addr=%02x reg=%02x len=%d\n", 243 KBUILD_MODNAME, ret, i2c_addr, reg, len); 244 return ret; 245 } 246 return 0; 247 } 248 249 static int cxd2841er_write_reg(struct cxd2841er_priv *priv, 250 u8 addr, u8 reg, u8 val) 251 { 252 u8 tmp = val; /* see gcc.gnu.org/bugzilla/show_bug.cgi?id=81715 */ 253 254 return cxd2841er_write_regs(priv, addr, reg, &tmp, 1); 255 } 256 257 static int cxd2841er_read_regs(struct cxd2841er_priv *priv, 258 u8 addr, u8 reg, u8 *val, u32 len) 259 { 260 int ret; 261 u8 i2c_addr = (addr == I2C_SLVX ? 262 priv->i2c_addr_slvx : priv->i2c_addr_slvt); 263 struct i2c_msg msg[2] = { 264 { 265 .addr = i2c_addr, 266 .flags = 0, 267 .len = 1, 268 .buf = ®, 269 }, { 270 .addr = i2c_addr, 271 .flags = I2C_M_RD, 272 .len = len, 273 .buf = val, 274 } 275 }; 276 277 ret = i2c_transfer(priv->i2c, msg, 2); 278 if (ret >= 0 && ret != 2) 279 ret = -EIO; 280 if (ret < 0) { 281 dev_warn(&priv->i2c->dev, 282 "%s: i2c rd failed=%d addr=%02x reg=%02x\n", 283 KBUILD_MODNAME, ret, i2c_addr, reg); 284 return ret; 285 } 286 cxd2841er_i2c_debug(priv, i2c_addr, reg, 0, val, len); 287 return 0; 288 } 289 290 static int cxd2841er_read_reg(struct cxd2841er_priv *priv, 291 u8 addr, u8 reg, u8 *val) 292 { 293 return cxd2841er_read_regs(priv, addr, reg, val, 1); 294 } 295 296 static int cxd2841er_set_reg_bits(struct cxd2841er_priv *priv, 297 u8 addr, u8 reg, u8 data, u8 mask) 298 { 299 int res; 300 u8 rdata; 301 302 if (mask != 0xff) { 303 res = cxd2841er_read_reg(priv, addr, reg, &rdata); 304 if (res) 305 return res; 306 data = ((data & mask) | (rdata & (mask ^ 0xFF))); 307 } 308 return cxd2841er_write_reg(priv, addr, reg, data); 309 } 310 311 static u32 cxd2841er_calc_iffreq_xtal(enum cxd2841er_xtal xtal, u32 ifhz) 312 { 313 u64 tmp; 314 315 tmp = (u64) ifhz * 16777216; 316 do_div(tmp, ((xtal == SONY_XTAL_24000) ? 48000000 : 41000000)); 317 318 return (u32) tmp; 319 } 320 321 static u32 cxd2841er_calc_iffreq(u32 ifhz) 322 { 323 return cxd2841er_calc_iffreq_xtal(SONY_XTAL_20500, ifhz); 324 } 325 326 static int cxd2841er_get_if_hz(struct cxd2841er_priv *priv, u32 def_hz) 327 { 328 u32 hz; 329 330 if (priv->frontend.ops.tuner_ops.get_if_frequency 331 && (priv->flags & CXD2841ER_AUTO_IFHZ)) 332 priv->frontend.ops.tuner_ops.get_if_frequency( 333 &priv->frontend, &hz); 334 else 335 hz = def_hz; 336 337 return hz; 338 } 339 340 static int cxd2841er_tuner_set(struct dvb_frontend *fe) 341 { 342 struct cxd2841er_priv *priv = fe->demodulator_priv; 343 344 if ((priv->flags & CXD2841ER_USE_GATECTRL) && fe->ops.i2c_gate_ctrl) 345 fe->ops.i2c_gate_ctrl(fe, 1); 346 if (fe->ops.tuner_ops.set_params) 347 fe->ops.tuner_ops.set_params(fe); 348 if ((priv->flags & CXD2841ER_USE_GATECTRL) && fe->ops.i2c_gate_ctrl) 349 fe->ops.i2c_gate_ctrl(fe, 0); 350 351 return 0; 352 } 353 354 static int cxd2841er_dvbs2_set_symbol_rate(struct cxd2841er_priv *priv, 355 u32 symbol_rate) 356 { 357 u32 reg_value = 0; 358 u8 data[3] = {0, 0, 0}; 359 360 dev_dbg(&priv->i2c->dev, "%s()\n", __func__); 361 /* 362 * regValue = (symbolRateKSps * 2^14 / 1000) + 0.5 363 * = ((symbolRateKSps * 2^14) + 500) / 1000 364 * = ((symbolRateKSps * 16384) + 500) / 1000 365 */ 366 reg_value = DIV_ROUND_CLOSEST(symbol_rate * 16384, 1000); 367 if ((reg_value == 0) || (reg_value > 0xFFFFF)) { 368 dev_err(&priv->i2c->dev, 369 "%s(): reg_value is out of range\n", __func__); 370 return -EINVAL; 371 } 372 data[0] = (u8)((reg_value >> 16) & 0x0F); 373 data[1] = (u8)((reg_value >> 8) & 0xFF); 374 data[2] = (u8)(reg_value & 0xFF); 375 /* Set SLV-T Bank : 0xAE */ 376 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xae); 377 cxd2841er_write_regs(priv, I2C_SLVT, 0x20, data, 3); 378 return 0; 379 } 380 381 static void cxd2841er_set_ts_clock_mode(struct cxd2841er_priv *priv, 382 u8 system); 383 384 static int cxd2841er_sleep_s_to_active_s(struct cxd2841er_priv *priv, 385 u8 system, u32 symbol_rate) 386 { 387 int ret; 388 u8 data[4] = { 0, 0, 0, 0 }; 389 390 if (priv->state != STATE_SLEEP_S) { 391 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n", 392 __func__, (int)priv->state); 393 return -EINVAL; 394 } 395 dev_dbg(&priv->i2c->dev, "%s()\n", __func__); 396 cxd2841er_set_ts_clock_mode(priv, SYS_DVBS); 397 /* Set demod mode */ 398 if (system == SYS_DVBS) { 399 data[0] = 0x0A; 400 } else if (system == SYS_DVBS2) { 401 data[0] = 0x0B; 402 } else { 403 dev_err(&priv->i2c->dev, "%s(): invalid delsys %d\n", 404 __func__, system); 405 return -EINVAL; 406 } 407 /* Set SLV-X Bank : 0x00 */ 408 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00); 409 cxd2841er_write_reg(priv, I2C_SLVX, 0x17, data[0]); 410 /* DVB-S/S2 */ 411 data[0] = 0x00; 412 /* Set SLV-T Bank : 0x00 */ 413 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00); 414 /* Enable S/S2 auto detection 1 */ 415 cxd2841er_write_reg(priv, I2C_SLVT, 0x2d, data[0]); 416 /* Set SLV-T Bank : 0xAE */ 417 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xae); 418 /* Enable S/S2 auto detection 2 */ 419 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, data[0]); 420 /* Set SLV-T Bank : 0x00 */ 421 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00); 422 /* Enable demod clock */ 423 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01); 424 /* Enable ADC clock */ 425 cxd2841er_write_reg(priv, I2C_SLVT, 0x31, 0x01); 426 /* Enable ADC 1 */ 427 cxd2841er_write_reg(priv, I2C_SLVT, 0x63, 0x16); 428 /* Enable ADC 2 */ 429 cxd2841er_write_reg(priv, I2C_SLVT, 0x65, 0x3f); 430 /* Set SLV-X Bank : 0x00 */ 431 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00); 432 /* Enable ADC 3 */ 433 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00); 434 /* Set SLV-T Bank : 0xA3 */ 435 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa3); 436 cxd2841er_write_reg(priv, I2C_SLVT, 0xac, 0x00); 437 data[0] = 0x07; 438 data[1] = 0x3B; 439 data[2] = 0x08; 440 data[3] = 0xC5; 441 /* Set SLV-T Bank : 0xAB */ 442 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xab); 443 cxd2841er_write_regs(priv, I2C_SLVT, 0x98, data, 4); 444 data[0] = 0x05; 445 data[1] = 0x80; 446 data[2] = 0x0A; 447 data[3] = 0x80; 448 cxd2841er_write_regs(priv, I2C_SLVT, 0xa8, data, 4); 449 data[0] = 0x0C; 450 data[1] = 0xCC; 451 cxd2841er_write_regs(priv, I2C_SLVT, 0xc3, data, 2); 452 /* Set demod parameter */ 453 ret = cxd2841er_dvbs2_set_symbol_rate(priv, symbol_rate); 454 if (ret != 0) 455 return ret; 456 /* Set SLV-T Bank : 0x00 */ 457 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00); 458 /* disable Hi-Z setting 1 */ 459 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x10); 460 /* disable Hi-Z setting 2 */ 461 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00); 462 priv->state = STATE_ACTIVE_S; 463 return 0; 464 } 465 466 static int cxd2841er_sleep_tc_to_active_t_band(struct cxd2841er_priv *priv, 467 u32 bandwidth); 468 469 static int cxd2841er_sleep_tc_to_active_t2_band(struct cxd2841er_priv *priv, 470 u32 bandwidth); 471 472 static int cxd2841er_sleep_tc_to_active_c_band(struct cxd2841er_priv *priv, 473 u32 bandwidth); 474 475 static int cxd2841er_sleep_tc_to_active_i(struct cxd2841er_priv *priv, 476 u32 bandwidth); 477 478 static int cxd2841er_active_i_to_sleep_tc(struct cxd2841er_priv *priv); 479 480 static int cxd2841er_sleep_tc_to_shutdown(struct cxd2841er_priv *priv); 481 482 static int cxd2841er_shutdown_to_sleep_tc(struct cxd2841er_priv *priv); 483 484 static int cxd2841er_sleep_tc(struct dvb_frontend *fe); 485 486 static int cxd2841er_retune_active(struct cxd2841er_priv *priv, 487 struct dtv_frontend_properties *p) 488 { 489 dev_dbg(&priv->i2c->dev, "%s()\n", __func__); 490 if (priv->state != STATE_ACTIVE_S && 491 priv->state != STATE_ACTIVE_TC) { 492 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n", 493 __func__, priv->state); 494 return -EINVAL; 495 } 496 /* Set SLV-T Bank : 0x00 */ 497 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00); 498 /* disable TS output */ 499 cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01); 500 if (priv->state == STATE_ACTIVE_S) 501 return cxd2841er_dvbs2_set_symbol_rate( 502 priv, p->symbol_rate / 1000); 503 else if (priv->state == STATE_ACTIVE_TC) { 504 switch (priv->system) { 505 case SYS_DVBT: 506 return cxd2841er_sleep_tc_to_active_t_band( 507 priv, p->bandwidth_hz); 508 case SYS_DVBT2: 509 return cxd2841er_sleep_tc_to_active_t2_band( 510 priv, p->bandwidth_hz); 511 case SYS_DVBC_ANNEX_A: 512 return cxd2841er_sleep_tc_to_active_c_band( 513 priv, p->bandwidth_hz); 514 case SYS_ISDBT: 515 cxd2841er_active_i_to_sleep_tc(priv); 516 cxd2841er_sleep_tc_to_shutdown(priv); 517 cxd2841er_shutdown_to_sleep_tc(priv); 518 return cxd2841er_sleep_tc_to_active_i( 519 priv, p->bandwidth_hz); 520 } 521 } 522 dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n", 523 __func__, priv->system); 524 return -EINVAL; 525 } 526 527 static int cxd2841er_active_s_to_sleep_s(struct cxd2841er_priv *priv) 528 { 529 dev_dbg(&priv->i2c->dev, "%s()\n", __func__); 530 if (priv->state != STATE_ACTIVE_S) { 531 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n", 532 __func__, priv->state); 533 return -EINVAL; 534 } 535 /* Set SLV-T Bank : 0x00 */ 536 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00); 537 /* disable TS output */ 538 cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01); 539 /* enable Hi-Z setting 1 */ 540 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x1f); 541 /* enable Hi-Z setting 2 */ 542 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff); 543 /* Set SLV-X Bank : 0x00 */ 544 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00); 545 /* disable ADC 1 */ 546 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01); 547 /* Set SLV-T Bank : 0x00 */ 548 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00); 549 /* disable ADC clock */ 550 cxd2841er_write_reg(priv, I2C_SLVT, 0x31, 0x00); 551 /* disable ADC 2 */ 552 cxd2841er_write_reg(priv, I2C_SLVT, 0x63, 0x16); 553 /* disable ADC 3 */ 554 cxd2841er_write_reg(priv, I2C_SLVT, 0x65, 0x27); 555 /* SADC Bias ON */ 556 cxd2841er_write_reg(priv, I2C_SLVT, 0x69, 0x06); 557 /* disable demod clock */ 558 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00); 559 /* Set SLV-T Bank : 0xAE */ 560 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xae); 561 /* disable S/S2 auto detection1 */ 562 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00); 563 /* Set SLV-T Bank : 0x00 */ 564 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00); 565 /* disable S/S2 auto detection2 */ 566 cxd2841er_write_reg(priv, I2C_SLVT, 0x2d, 0x00); 567 priv->state = STATE_SLEEP_S; 568 return 0; 569 } 570 571 static int cxd2841er_sleep_s_to_shutdown(struct cxd2841er_priv *priv) 572 { 573 dev_dbg(&priv->i2c->dev, "%s()\n", __func__); 574 if (priv->state != STATE_SLEEP_S) { 575 dev_dbg(&priv->i2c->dev, "%s(): invalid demod state %d\n", 576 __func__, priv->state); 577 return -EINVAL; 578 } 579 /* Set SLV-T Bank : 0x00 */ 580 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00); 581 /* Disable DSQOUT */ 582 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f); 583 /* Disable DSQIN */ 584 cxd2841er_write_reg(priv, I2C_SLVT, 0x9c, 0x00); 585 /* Set SLV-X Bank : 0x00 */ 586 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00); 587 /* Disable oscillator */ 588 cxd2841er_write_reg(priv, I2C_SLVX, 0x15, 0x01); 589 /* Set demod mode */ 590 cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x01); 591 priv->state = STATE_SHUTDOWN; 592 return 0; 593 } 594 595 static int cxd2841er_sleep_tc_to_shutdown(struct cxd2841er_priv *priv) 596 { 597 dev_dbg(&priv->i2c->dev, "%s()\n", __func__); 598 if (priv->state != STATE_SLEEP_TC) { 599 dev_dbg(&priv->i2c->dev, "%s(): invalid demod state %d\n", 600 __func__, priv->state); 601 return -EINVAL; 602 } 603 /* Set SLV-X Bank : 0x00 */ 604 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00); 605 /* Disable oscillator */ 606 cxd2841er_write_reg(priv, I2C_SLVX, 0x15, 0x01); 607 /* Set demod mode */ 608 cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x01); 609 priv->state = STATE_SHUTDOWN; 610 return 0; 611 } 612 613 static int cxd2841er_active_t_to_sleep_tc(struct cxd2841er_priv *priv) 614 { 615 dev_dbg(&priv->i2c->dev, "%s()\n", __func__); 616 if (priv->state != STATE_ACTIVE_TC) { 617 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n", 618 __func__, priv->state); 619 return -EINVAL; 620 } 621 /* Set SLV-T Bank : 0x00 */ 622 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00); 623 /* disable TS output */ 624 cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01); 625 /* enable Hi-Z setting 1 */ 626 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f); 627 /* enable Hi-Z setting 2 */ 628 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff); 629 /* Set SLV-X Bank : 0x00 */ 630 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00); 631 /* disable ADC 1 */ 632 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01); 633 /* Set SLV-T Bank : 0x00 */ 634 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00); 635 /* Disable ADC 2 */ 636 cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a); 637 /* Disable ADC 3 */ 638 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a); 639 /* Disable ADC clock */ 640 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00); 641 /* Disable RF level monitor */ 642 cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00); 643 /* Disable demod clock */ 644 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00); 645 priv->state = STATE_SLEEP_TC; 646 return 0; 647 } 648 649 static int cxd2841er_active_t2_to_sleep_tc(struct cxd2841er_priv *priv) 650 { 651 dev_dbg(&priv->i2c->dev, "%s()\n", __func__); 652 if (priv->state != STATE_ACTIVE_TC) { 653 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n", 654 __func__, priv->state); 655 return -EINVAL; 656 } 657 /* Set SLV-T Bank : 0x00 */ 658 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00); 659 /* disable TS output */ 660 cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01); 661 /* enable Hi-Z setting 1 */ 662 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f); 663 /* enable Hi-Z setting 2 */ 664 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff); 665 /* Cancel DVB-T2 setting */ 666 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x13); 667 cxd2841er_write_reg(priv, I2C_SLVT, 0x83, 0x40); 668 cxd2841er_write_reg(priv, I2C_SLVT, 0x86, 0x21); 669 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x9e, 0x09, 0x0f); 670 cxd2841er_write_reg(priv, I2C_SLVT, 0x9f, 0xfb); 671 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2a); 672 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x38, 0x00, 0x0f); 673 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2b); 674 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x11, 0x00, 0x3f); 675 /* Set SLV-X Bank : 0x00 */ 676 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00); 677 /* disable ADC 1 */ 678 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01); 679 /* Set SLV-T Bank : 0x00 */ 680 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00); 681 /* Disable ADC 2 */ 682 cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a); 683 /* Disable ADC 3 */ 684 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a); 685 /* Disable ADC clock */ 686 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00); 687 /* Disable RF level monitor */ 688 cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00); 689 /* Disable demod clock */ 690 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00); 691 priv->state = STATE_SLEEP_TC; 692 return 0; 693 } 694 695 static int cxd2841er_active_c_to_sleep_tc(struct cxd2841er_priv *priv) 696 { 697 dev_dbg(&priv->i2c->dev, "%s()\n", __func__); 698 if (priv->state != STATE_ACTIVE_TC) { 699 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n", 700 __func__, priv->state); 701 return -EINVAL; 702 } 703 /* Set SLV-T Bank : 0x00 */ 704 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00); 705 /* disable TS output */ 706 cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01); 707 /* enable Hi-Z setting 1 */ 708 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f); 709 /* enable Hi-Z setting 2 */ 710 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff); 711 /* Cancel DVB-C setting */ 712 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11); 713 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa3, 0x00, 0x1f); 714 /* Set SLV-X Bank : 0x00 */ 715 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00); 716 /* disable ADC 1 */ 717 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01); 718 /* Set SLV-T Bank : 0x00 */ 719 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00); 720 /* Disable ADC 2 */ 721 cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a); 722 /* Disable ADC 3 */ 723 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a); 724 /* Disable ADC clock */ 725 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00); 726 /* Disable RF level monitor */ 727 cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00); 728 /* Disable demod clock */ 729 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00); 730 priv->state = STATE_SLEEP_TC; 731 return 0; 732 } 733 734 static int cxd2841er_active_i_to_sleep_tc(struct cxd2841er_priv *priv) 735 { 736 dev_dbg(&priv->i2c->dev, "%s()\n", __func__); 737 if (priv->state != STATE_ACTIVE_TC) { 738 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n", 739 __func__, priv->state); 740 return -EINVAL; 741 } 742 /* Set SLV-T Bank : 0x00 */ 743 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00); 744 /* disable TS output */ 745 cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01); 746 /* enable Hi-Z setting 1 */ 747 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f); 748 /* enable Hi-Z setting 2 */ 749 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff); 750 751 /* TODO: Cancel demod parameter */ 752 753 /* Set SLV-X Bank : 0x00 */ 754 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00); 755 /* disable ADC 1 */ 756 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01); 757 /* Set SLV-T Bank : 0x00 */ 758 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00); 759 /* Disable ADC 2 */ 760 cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a); 761 /* Disable ADC 3 */ 762 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a); 763 /* Disable ADC clock */ 764 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00); 765 /* Disable RF level monitor */ 766 cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00); 767 /* Disable demod clock */ 768 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00); 769 priv->state = STATE_SLEEP_TC; 770 return 0; 771 } 772 773 static int cxd2841er_shutdown_to_sleep_s(struct cxd2841er_priv *priv) 774 { 775 dev_dbg(&priv->i2c->dev, "%s()\n", __func__); 776 if (priv->state != STATE_SHUTDOWN) { 777 dev_dbg(&priv->i2c->dev, "%s(): invalid demod state %d\n", 778 __func__, priv->state); 779 return -EINVAL; 780 } 781 /* Set SLV-X Bank : 0x00 */ 782 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00); 783 /* Clear all demodulator registers */ 784 cxd2841er_write_reg(priv, I2C_SLVX, 0x02, 0x00); 785 usleep_range(3000, 5000); 786 /* Set SLV-X Bank : 0x00 */ 787 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00); 788 /* Set demod SW reset */ 789 cxd2841er_write_reg(priv, I2C_SLVX, 0x10, 0x01); 790 791 switch (priv->xtal) { 792 case SONY_XTAL_20500: 793 cxd2841er_write_reg(priv, I2C_SLVX, 0x14, 0x00); 794 break; 795 case SONY_XTAL_24000: 796 /* Select demod frequency */ 797 cxd2841er_write_reg(priv, I2C_SLVX, 0x12, 0x00); 798 cxd2841er_write_reg(priv, I2C_SLVX, 0x14, 0x03); 799 break; 800 case SONY_XTAL_41000: 801 cxd2841er_write_reg(priv, I2C_SLVX, 0x14, 0x01); 802 break; 803 default: 804 dev_dbg(&priv->i2c->dev, "%s(): invalid demod xtal %d\n", 805 __func__, priv->xtal); 806 return -EINVAL; 807 } 808 809 /* Set demod mode */ 810 cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x0a); 811 /* Clear demod SW reset */ 812 cxd2841er_write_reg(priv, I2C_SLVX, 0x10, 0x00); 813 usleep_range(1000, 2000); 814 /* Set SLV-T Bank : 0x00 */ 815 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00); 816 /* enable DSQOUT */ 817 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x1F); 818 /* enable DSQIN */ 819 cxd2841er_write_reg(priv, I2C_SLVT, 0x9C, 0x40); 820 /* TADC Bias On */ 821 cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a); 822 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a); 823 /* SADC Bias On */ 824 cxd2841er_write_reg(priv, I2C_SLVT, 0x63, 0x16); 825 cxd2841er_write_reg(priv, I2C_SLVT, 0x65, 0x27); 826 cxd2841er_write_reg(priv, I2C_SLVT, 0x69, 0x06); 827 priv->state = STATE_SLEEP_S; 828 return 0; 829 } 830 831 static int cxd2841er_shutdown_to_sleep_tc(struct cxd2841er_priv *priv) 832 { 833 u8 data = 0; 834 835 dev_dbg(&priv->i2c->dev, "%s()\n", __func__); 836 if (priv->state != STATE_SHUTDOWN) { 837 dev_dbg(&priv->i2c->dev, "%s(): invalid demod state %d\n", 838 __func__, priv->state); 839 return -EINVAL; 840 } 841 /* Set SLV-X Bank : 0x00 */ 842 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00); 843 /* Clear all demodulator registers */ 844 cxd2841er_write_reg(priv, I2C_SLVX, 0x02, 0x00); 845 usleep_range(3000, 5000); 846 /* Set SLV-X Bank : 0x00 */ 847 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00); 848 /* Set demod SW reset */ 849 cxd2841er_write_reg(priv, I2C_SLVX, 0x10, 0x01); 850 /* Select ADC clock mode */ 851 cxd2841er_write_reg(priv, I2C_SLVX, 0x13, 0x00); 852 853 switch (priv->xtal) { 854 case SONY_XTAL_20500: 855 data = 0x0; 856 break; 857 case SONY_XTAL_24000: 858 /* Select demod frequency */ 859 cxd2841er_write_reg(priv, I2C_SLVX, 0x12, 0x00); 860 data = 0x3; 861 break; 862 case SONY_XTAL_41000: 863 cxd2841er_write_reg(priv, I2C_SLVX, 0x12, 0x00); 864 data = 0x1; 865 break; 866 } 867 cxd2841er_write_reg(priv, I2C_SLVX, 0x14, data); 868 /* Clear demod SW reset */ 869 cxd2841er_write_reg(priv, I2C_SLVX, 0x10, 0x00); 870 usleep_range(1000, 2000); 871 /* Set SLV-T Bank : 0x00 */ 872 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00); 873 /* TADC Bias On */ 874 cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a); 875 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a); 876 /* SADC Bias On */ 877 cxd2841er_write_reg(priv, I2C_SLVT, 0x63, 0x16); 878 cxd2841er_write_reg(priv, I2C_SLVT, 0x65, 0x27); 879 cxd2841er_write_reg(priv, I2C_SLVT, 0x69, 0x06); 880 priv->state = STATE_SLEEP_TC; 881 return 0; 882 } 883 884 static int cxd2841er_tune_done(struct cxd2841er_priv *priv) 885 { 886 dev_dbg(&priv->i2c->dev, "%s()\n", __func__); 887 /* Set SLV-T Bank : 0x00 */ 888 cxd2841er_write_reg(priv, I2C_SLVT, 0, 0); 889 /* SW Reset */ 890 cxd2841er_write_reg(priv, I2C_SLVT, 0xfe, 0x01); 891 /* Enable TS output */ 892 cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x00); 893 return 0; 894 } 895 896 /* Set TS parallel mode */ 897 static void cxd2841er_set_ts_clock_mode(struct cxd2841er_priv *priv, 898 u8 system) 899 { 900 u8 serial_ts, ts_rate_ctrl_off, ts_in_off; 901 902 dev_dbg(&priv->i2c->dev, "%s()\n", __func__); 903 /* Set SLV-T Bank : 0x00 */ 904 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00); 905 cxd2841er_read_reg(priv, I2C_SLVT, 0xc4, &serial_ts); 906 cxd2841er_read_reg(priv, I2C_SLVT, 0xd3, &ts_rate_ctrl_off); 907 cxd2841er_read_reg(priv, I2C_SLVT, 0xde, &ts_in_off); 908 dev_dbg(&priv->i2c->dev, "%s(): ser_ts=0x%02x rate_ctrl_off=0x%02x in_off=0x%02x\n", 909 __func__, serial_ts, ts_rate_ctrl_off, ts_in_off); 910 911 /* 912 * slave Bank Addr Bit default Name 913 * <SLV-T> 00h C4h [1:0] 2'b?? OSERCKMODE 914 */ 915 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xc4, 916 ((priv->flags & CXD2841ER_TS_SERIAL) ? 0x01 : 0x00), 0x03); 917 /* 918 * slave Bank Addr Bit default Name 919 * <SLV-T> 00h D1h [1:0] 2'b?? OSERDUTYMODE 920 */ 921 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd1, 922 ((priv->flags & CXD2841ER_TS_SERIAL) ? 0x01 : 0x00), 0x03); 923 /* 924 * slave Bank Addr Bit default Name 925 * <SLV-T> 00h D9h [7:0] 8'h08 OTSCKPERIOD 926 */ 927 cxd2841er_write_reg(priv, I2C_SLVT, 0xd9, 0x08); 928 /* 929 * Disable TS IF Clock 930 * slave Bank Addr Bit default Name 931 * <SLV-T> 00h 32h [0] 1'b1 OREG_CK_TSIF_EN 932 */ 933 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x32, 0x00, 0x01); 934 /* 935 * slave Bank Addr Bit default Name 936 * <SLV-T> 00h 33h [1:0] 2'b01 OREG_CKSEL_TSIF 937 */ 938 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x33, 939 ((priv->flags & CXD2841ER_TS_SERIAL) ? 0x01 : 0x00), 0x03); 940 /* 941 * Enable TS IF Clock 942 * slave Bank Addr Bit default Name 943 * <SLV-T> 00h 32h [0] 1'b1 OREG_CK_TSIF_EN 944 */ 945 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x32, 0x01, 0x01); 946 947 if (system == SYS_DVBT) { 948 /* Enable parity period for DVB-T */ 949 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10); 950 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x66, 0x01, 0x01); 951 } else if (system == SYS_DVBC_ANNEX_A) { 952 /* Enable parity period for DVB-C */ 953 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40); 954 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x66, 0x01, 0x01); 955 } 956 } 957 958 static u8 cxd2841er_chip_id(struct cxd2841er_priv *priv) 959 { 960 u8 chip_id = 0; 961 962 dev_dbg(&priv->i2c->dev, "%s()\n", __func__); 963 if (cxd2841er_write_reg(priv, I2C_SLVT, 0, 0) == 0) 964 cxd2841er_read_reg(priv, I2C_SLVT, 0xfd, &chip_id); 965 else if (cxd2841er_write_reg(priv, I2C_SLVX, 0, 0) == 0) 966 cxd2841er_read_reg(priv, I2C_SLVX, 0xfd, &chip_id); 967 968 return chip_id; 969 } 970 971 static int cxd2841er_read_status_s(struct dvb_frontend *fe, 972 enum fe_status *status) 973 { 974 u8 reg = 0; 975 struct cxd2841er_priv *priv = fe->demodulator_priv; 976 977 dev_dbg(&priv->i2c->dev, "%s()\n", __func__); 978 *status = 0; 979 if (priv->state != STATE_ACTIVE_S) { 980 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n", 981 __func__, priv->state); 982 return -EINVAL; 983 } 984 /* Set SLV-T Bank : 0xA0 */ 985 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0); 986 /* 987 * slave Bank Addr Bit Signal name 988 * <SLV-T> A0h 11h [2] ITSLOCK 989 */ 990 cxd2841er_read_reg(priv, I2C_SLVT, 0x11, ®); 991 if (reg & 0x04) { 992 *status = FE_HAS_SIGNAL 993 | FE_HAS_CARRIER 994 | FE_HAS_VITERBI 995 | FE_HAS_SYNC 996 | FE_HAS_LOCK; 997 } 998 dev_dbg(&priv->i2c->dev, "%s(): result 0x%x\n", __func__, *status); 999 return 0; 1000 } 1001 1002 static int cxd2841er_read_status_t_t2(struct cxd2841er_priv *priv, 1003 u8 *sync, u8 *tslock, u8 *unlock) 1004 { 1005 u8 data = 0; 1006 1007 dev_dbg(&priv->i2c->dev, "%s()\n", __func__); 1008 if (priv->state != STATE_ACTIVE_TC) 1009 return -EINVAL; 1010 if (priv->system == SYS_DVBT) { 1011 /* Set SLV-T Bank : 0x10 */ 1012 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10); 1013 } else { 1014 /* Set SLV-T Bank : 0x20 */ 1015 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20); 1016 } 1017 cxd2841er_read_reg(priv, I2C_SLVT, 0x10, &data); 1018 if ((data & 0x07) == 0x07) { 1019 dev_dbg(&priv->i2c->dev, 1020 "%s(): invalid hardware state detected\n", __func__); 1021 *sync = 0; 1022 *tslock = 0; 1023 *unlock = 0; 1024 } else { 1025 *sync = ((data & 0x07) == 0x6 ? 1 : 0); 1026 *tslock = ((data & 0x20) ? 1 : 0); 1027 *unlock = ((data & 0x10) ? 1 : 0); 1028 } 1029 return 0; 1030 } 1031 1032 static int cxd2841er_read_status_c(struct cxd2841er_priv *priv, u8 *tslock) 1033 { 1034 u8 data; 1035 1036 dev_dbg(&priv->i2c->dev, "%s()\n", __func__); 1037 if (priv->state != STATE_ACTIVE_TC) 1038 return -EINVAL; 1039 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40); 1040 cxd2841er_read_reg(priv, I2C_SLVT, 0x88, &data); 1041 if ((data & 0x01) == 0) { 1042 *tslock = 0; 1043 } else { 1044 cxd2841er_read_reg(priv, I2C_SLVT, 0x10, &data); 1045 *tslock = ((data & 0x20) ? 1 : 0); 1046 } 1047 return 0; 1048 } 1049 1050 static int cxd2841er_read_status_i(struct cxd2841er_priv *priv, 1051 u8 *sync, u8 *tslock, u8 *unlock) 1052 { 1053 u8 data = 0; 1054 1055 dev_dbg(&priv->i2c->dev, "%s()\n", __func__); 1056 if (priv->state != STATE_ACTIVE_TC) 1057 return -EINVAL; 1058 /* Set SLV-T Bank : 0x60 */ 1059 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60); 1060 cxd2841er_read_reg(priv, I2C_SLVT, 0x10, &data); 1061 dev_dbg(&priv->i2c->dev, 1062 "%s(): lock=0x%x\n", __func__, data); 1063 *sync = ((data & 0x02) ? 1 : 0); 1064 *tslock = ((data & 0x01) ? 1 : 0); 1065 *unlock = ((data & 0x10) ? 1 : 0); 1066 return 0; 1067 } 1068 1069 static int cxd2841er_read_status_tc(struct dvb_frontend *fe, 1070 enum fe_status *status) 1071 { 1072 int ret = 0; 1073 u8 sync = 0; 1074 u8 tslock = 0; 1075 u8 unlock = 0; 1076 struct cxd2841er_priv *priv = fe->demodulator_priv; 1077 1078 *status = 0; 1079 if (priv->state == STATE_ACTIVE_TC) { 1080 if (priv->system == SYS_DVBT || priv->system == SYS_DVBT2) { 1081 ret = cxd2841er_read_status_t_t2( 1082 priv, &sync, &tslock, &unlock); 1083 if (ret) 1084 goto done; 1085 if (unlock) 1086 goto done; 1087 if (sync) 1088 *status = FE_HAS_SIGNAL | 1089 FE_HAS_CARRIER | 1090 FE_HAS_VITERBI | 1091 FE_HAS_SYNC; 1092 if (tslock) 1093 *status |= FE_HAS_LOCK; 1094 } else if (priv->system == SYS_ISDBT) { 1095 ret = cxd2841er_read_status_i( 1096 priv, &sync, &tslock, &unlock); 1097 if (ret) 1098 goto done; 1099 if (unlock) 1100 goto done; 1101 if (sync) 1102 *status = FE_HAS_SIGNAL | 1103 FE_HAS_CARRIER | 1104 FE_HAS_VITERBI | 1105 FE_HAS_SYNC; 1106 if (tslock) 1107 *status |= FE_HAS_LOCK; 1108 } else if (priv->system == SYS_DVBC_ANNEX_A) { 1109 ret = cxd2841er_read_status_c(priv, &tslock); 1110 if (ret) 1111 goto done; 1112 if (tslock) 1113 *status = FE_HAS_SIGNAL | 1114 FE_HAS_CARRIER | 1115 FE_HAS_VITERBI | 1116 FE_HAS_SYNC | 1117 FE_HAS_LOCK; 1118 } 1119 } 1120 done: 1121 dev_dbg(&priv->i2c->dev, "%s(): status 0x%x\n", __func__, *status); 1122 return ret; 1123 } 1124 1125 static int cxd2841er_get_carrier_offset_s_s2(struct cxd2841er_priv *priv, 1126 int *offset) 1127 { 1128 u8 data[3]; 1129 u8 is_hs_mode; 1130 s32 cfrl_ctrlval; 1131 s32 temp_div, temp_q, temp_r; 1132 1133 if (priv->state != STATE_ACTIVE_S) { 1134 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n", 1135 __func__, priv->state); 1136 return -EINVAL; 1137 } 1138 /* 1139 * Get High Sampling Rate mode 1140 * slave Bank Addr Bit Signal name 1141 * <SLV-T> A0h 10h [0] ITRL_LOCK 1142 */ 1143 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0); 1144 cxd2841er_read_reg(priv, I2C_SLVT, 0x10, &data[0]); 1145 if (data[0] & 0x01) { 1146 /* 1147 * slave Bank Addr Bit Signal name 1148 * <SLV-T> A0h 50h [4] IHSMODE 1149 */ 1150 cxd2841er_read_reg(priv, I2C_SLVT, 0x50, &data[0]); 1151 is_hs_mode = (data[0] & 0x10 ? 1 : 0); 1152 } else { 1153 dev_dbg(&priv->i2c->dev, 1154 "%s(): unable to detect sampling rate mode\n", 1155 __func__); 1156 return -EINVAL; 1157 } 1158 /* 1159 * slave Bank Addr Bit Signal name 1160 * <SLV-T> A0h 45h [4:0] ICFRL_CTRLVAL[20:16] 1161 * <SLV-T> A0h 46h [7:0] ICFRL_CTRLVAL[15:8] 1162 * <SLV-T> A0h 47h [7:0] ICFRL_CTRLVAL[7:0] 1163 */ 1164 cxd2841er_read_regs(priv, I2C_SLVT, 0x45, data, 3); 1165 cfrl_ctrlval = sign_extend32((((u32)data[0] & 0x1F) << 16) | 1166 (((u32)data[1] & 0xFF) << 8) | 1167 ((u32)data[2] & 0xFF), 20); 1168 temp_div = (is_hs_mode ? 1048576 : 1572864); 1169 if (cfrl_ctrlval > 0) { 1170 temp_q = div_s64_rem(97375LL * cfrl_ctrlval, 1171 temp_div, &temp_r); 1172 } else { 1173 temp_q = div_s64_rem(-97375LL * cfrl_ctrlval, 1174 temp_div, &temp_r); 1175 } 1176 if (temp_r >= temp_div / 2) 1177 temp_q++; 1178 if (cfrl_ctrlval > 0) 1179 temp_q *= -1; 1180 *offset = temp_q; 1181 return 0; 1182 } 1183 1184 static int cxd2841er_get_carrier_offset_i(struct cxd2841er_priv *priv, 1185 u32 bandwidth, int *offset) 1186 { 1187 u8 data[4]; 1188 1189 dev_dbg(&priv->i2c->dev, "%s()\n", __func__); 1190 if (priv->state != STATE_ACTIVE_TC) { 1191 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n", 1192 __func__, priv->state); 1193 return -EINVAL; 1194 } 1195 if (priv->system != SYS_ISDBT) { 1196 dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n", 1197 __func__, priv->system); 1198 return -EINVAL; 1199 } 1200 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60); 1201 cxd2841er_read_regs(priv, I2C_SLVT, 0x4c, data, sizeof(data)); 1202 *offset = -1 * sign_extend32( 1203 ((u32)(data[0] & 0x1F) << 24) | ((u32)data[1] << 16) | 1204 ((u32)data[2] << 8) | (u32)data[3], 29); 1205 1206 switch (bandwidth) { 1207 case 6000000: 1208 *offset = -1 * ((*offset) * 8/264); 1209 break; 1210 case 7000000: 1211 *offset = -1 * ((*offset) * 8/231); 1212 break; 1213 case 8000000: 1214 *offset = -1 * ((*offset) * 8/198); 1215 break; 1216 default: 1217 dev_dbg(&priv->i2c->dev, "%s(): invalid bandwidth %d\n", 1218 __func__, bandwidth); 1219 return -EINVAL; 1220 } 1221 1222 dev_dbg(&priv->i2c->dev, "%s(): bandwidth %d offset %d\n", 1223 __func__, bandwidth, *offset); 1224 1225 return 0; 1226 } 1227 1228 static int cxd2841er_get_carrier_offset_t(struct cxd2841er_priv *priv, 1229 u32 bandwidth, int *offset) 1230 { 1231 u8 data[4]; 1232 1233 dev_dbg(&priv->i2c->dev, "%s()\n", __func__); 1234 if (priv->state != STATE_ACTIVE_TC) { 1235 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n", 1236 __func__, priv->state); 1237 return -EINVAL; 1238 } 1239 if (priv->system != SYS_DVBT) { 1240 dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n", 1241 __func__, priv->system); 1242 return -EINVAL; 1243 } 1244 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10); 1245 cxd2841er_read_regs(priv, I2C_SLVT, 0x4c, data, sizeof(data)); 1246 *offset = -1 * sign_extend32( 1247 ((u32)(data[0] & 0x1F) << 24) | ((u32)data[1] << 16) | 1248 ((u32)data[2] << 8) | (u32)data[3], 29); 1249 *offset *= (bandwidth / 1000000); 1250 *offset /= 235; 1251 return 0; 1252 } 1253 1254 static int cxd2841er_get_carrier_offset_t2(struct cxd2841er_priv *priv, 1255 u32 bandwidth, int *offset) 1256 { 1257 u8 data[4]; 1258 1259 dev_dbg(&priv->i2c->dev, "%s()\n", __func__); 1260 if (priv->state != STATE_ACTIVE_TC) { 1261 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n", 1262 __func__, priv->state); 1263 return -EINVAL; 1264 } 1265 if (priv->system != SYS_DVBT2) { 1266 dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n", 1267 __func__, priv->system); 1268 return -EINVAL; 1269 } 1270 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20); 1271 cxd2841er_read_regs(priv, I2C_SLVT, 0x4c, data, sizeof(data)); 1272 *offset = -1 * sign_extend32( 1273 ((u32)(data[0] & 0x0F) << 24) | ((u32)data[1] << 16) | 1274 ((u32)data[2] << 8) | (u32)data[3], 27); 1275 switch (bandwidth) { 1276 case 1712000: 1277 *offset /= 582; 1278 break; 1279 case 5000000: 1280 case 6000000: 1281 case 7000000: 1282 case 8000000: 1283 *offset *= (bandwidth / 1000000); 1284 *offset /= 940; 1285 break; 1286 default: 1287 dev_dbg(&priv->i2c->dev, "%s(): invalid bandwidth %d\n", 1288 __func__, bandwidth); 1289 return -EINVAL; 1290 } 1291 return 0; 1292 } 1293 1294 static int cxd2841er_get_carrier_offset_c(struct cxd2841er_priv *priv, 1295 int *offset) 1296 { 1297 u8 data[2]; 1298 1299 dev_dbg(&priv->i2c->dev, "%s()\n", __func__); 1300 if (priv->state != STATE_ACTIVE_TC) { 1301 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n", 1302 __func__, priv->state); 1303 return -EINVAL; 1304 } 1305 if (priv->system != SYS_DVBC_ANNEX_A) { 1306 dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n", 1307 __func__, priv->system); 1308 return -EINVAL; 1309 } 1310 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40); 1311 cxd2841er_read_regs(priv, I2C_SLVT, 0x15, data, sizeof(data)); 1312 *offset = div_s64(41000LL * sign_extend32((((u32)data[0] & 0x3f) << 8) 1313 | (u32)data[1], 13), 16384); 1314 return 0; 1315 } 1316 1317 static int cxd2841er_read_packet_errors_c( 1318 struct cxd2841er_priv *priv, u32 *penum) 1319 { 1320 u8 data[3]; 1321 1322 *penum = 0; 1323 if (priv->state != STATE_ACTIVE_TC) { 1324 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n", 1325 __func__, priv->state); 1326 return -EINVAL; 1327 } 1328 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40); 1329 cxd2841er_read_regs(priv, I2C_SLVT, 0xea, data, sizeof(data)); 1330 if (data[2] & 0x01) 1331 *penum = ((u32)data[0] << 8) | (u32)data[1]; 1332 return 0; 1333 } 1334 1335 static int cxd2841er_read_packet_errors_t( 1336 struct cxd2841er_priv *priv, u32 *penum) 1337 { 1338 u8 data[3]; 1339 1340 *penum = 0; 1341 if (priv->state != STATE_ACTIVE_TC) { 1342 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n", 1343 __func__, priv->state); 1344 return -EINVAL; 1345 } 1346 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10); 1347 cxd2841er_read_regs(priv, I2C_SLVT, 0xea, data, sizeof(data)); 1348 if (data[2] & 0x01) 1349 *penum = ((u32)data[0] << 8) | (u32)data[1]; 1350 return 0; 1351 } 1352 1353 static int cxd2841er_read_packet_errors_t2( 1354 struct cxd2841er_priv *priv, u32 *penum) 1355 { 1356 u8 data[3]; 1357 1358 *penum = 0; 1359 if (priv->state != STATE_ACTIVE_TC) { 1360 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n", 1361 __func__, priv->state); 1362 return -EINVAL; 1363 } 1364 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x24); 1365 cxd2841er_read_regs(priv, I2C_SLVT, 0xfd, data, sizeof(data)); 1366 if (data[0] & 0x01) 1367 *penum = ((u32)data[1] << 8) | (u32)data[2]; 1368 return 0; 1369 } 1370 1371 static int cxd2841er_read_packet_errors_i( 1372 struct cxd2841er_priv *priv, u32 *penum) 1373 { 1374 u8 data[2]; 1375 1376 *penum = 0; 1377 if (priv->state != STATE_ACTIVE_TC) { 1378 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n", 1379 __func__, priv->state); 1380 return -EINVAL; 1381 } 1382 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60); 1383 cxd2841er_read_regs(priv, I2C_SLVT, 0xA1, data, 1); 1384 1385 if (!(data[0] & 0x01)) 1386 return 0; 1387 1388 /* Layer A */ 1389 cxd2841er_read_regs(priv, I2C_SLVT, 0xA2, data, sizeof(data)); 1390 *penum = ((u32)data[0] << 8) | (u32)data[1]; 1391 1392 /* Layer B */ 1393 cxd2841er_read_regs(priv, I2C_SLVT, 0xA4, data, sizeof(data)); 1394 *penum += ((u32)data[0] << 8) | (u32)data[1]; 1395 1396 /* Layer C */ 1397 cxd2841er_read_regs(priv, I2C_SLVT, 0xA6, data, sizeof(data)); 1398 *penum += ((u32)data[0] << 8) | (u32)data[1]; 1399 1400 return 0; 1401 } 1402 1403 static int cxd2841er_read_ber_c(struct cxd2841er_priv *priv, 1404 u32 *bit_error, u32 *bit_count) 1405 { 1406 u8 data[3]; 1407 u32 bit_err, period_exp; 1408 1409 dev_dbg(&priv->i2c->dev, "%s()\n", __func__); 1410 if (priv->state != STATE_ACTIVE_TC) { 1411 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n", 1412 __func__, priv->state); 1413 return -EINVAL; 1414 } 1415 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40); 1416 cxd2841er_read_regs(priv, I2C_SLVT, 0x62, data, sizeof(data)); 1417 if (!(data[0] & 0x80)) { 1418 dev_dbg(&priv->i2c->dev, 1419 "%s(): no valid BER data\n", __func__); 1420 return -EINVAL; 1421 } 1422 bit_err = ((u32)(data[0] & 0x3f) << 16) | 1423 ((u32)data[1] << 8) | 1424 (u32)data[2]; 1425 cxd2841er_read_reg(priv, I2C_SLVT, 0x60, data); 1426 period_exp = data[0] & 0x1f; 1427 1428 if ((period_exp <= 11) && (bit_err > (1 << period_exp) * 204 * 8)) { 1429 dev_dbg(&priv->i2c->dev, 1430 "%s(): period_exp(%u) or bit_err(%u) not in range. no valid BER data\n", 1431 __func__, period_exp, bit_err); 1432 return -EINVAL; 1433 } 1434 1435 dev_dbg(&priv->i2c->dev, 1436 "%s(): period_exp(%u) or bit_err(%u) count=%d\n", 1437 __func__, period_exp, bit_err, 1438 ((1 << period_exp) * 204 * 8)); 1439 1440 *bit_error = bit_err; 1441 *bit_count = ((1 << period_exp) * 204 * 8); 1442 1443 return 0; 1444 } 1445 1446 static int cxd2841er_read_ber_i(struct cxd2841er_priv *priv, 1447 u32 *bit_error, u32 *bit_count) 1448 { 1449 u8 data[3]; 1450 u8 pktnum[2]; 1451 1452 dev_dbg(&priv->i2c->dev, "%s()\n", __func__); 1453 if (priv->state != STATE_ACTIVE_TC) { 1454 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n", 1455 __func__, priv->state); 1456 return -EINVAL; 1457 } 1458 1459 cxd2841er_freeze_regs(priv); 1460 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60); 1461 cxd2841er_read_regs(priv, I2C_SLVT, 0x5B, pktnum, sizeof(pktnum)); 1462 cxd2841er_read_regs(priv, I2C_SLVT, 0x16, data, sizeof(data)); 1463 cxd2841er_unfreeze_regs(priv); 1464 1465 if (!pktnum[0] && !pktnum[1]) { 1466 dev_dbg(&priv->i2c->dev, 1467 "%s(): no valid BER data\n", __func__); 1468 return -EINVAL; 1469 } 1470 1471 *bit_error = ((u32)(data[0] & 0x7F) << 16) | 1472 ((u32)data[1] << 8) | data[2]; 1473 *bit_count = ((((u32)pktnum[0] << 8) | pktnum[1]) * 204 * 8); 1474 dev_dbg(&priv->i2c->dev, "%s(): bit_error=%u bit_count=%u\n", 1475 __func__, *bit_error, *bit_count); 1476 1477 return 0; 1478 } 1479 1480 static int cxd2841er_mon_read_ber_s(struct cxd2841er_priv *priv, 1481 u32 *bit_error, u32 *bit_count) 1482 { 1483 u8 data[11]; 1484 1485 /* Set SLV-T Bank : 0xA0 */ 1486 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0); 1487 /* 1488 * slave Bank Addr Bit Signal name 1489 * <SLV-T> A0h 35h [0] IFVBER_VALID 1490 * <SLV-T> A0h 36h [5:0] IFVBER_BITERR[21:16] 1491 * <SLV-T> A0h 37h [7:0] IFVBER_BITERR[15:8] 1492 * <SLV-T> A0h 38h [7:0] IFVBER_BITERR[7:0] 1493 * <SLV-T> A0h 3Dh [5:0] IFVBER_BITNUM[21:16] 1494 * <SLV-T> A0h 3Eh [7:0] IFVBER_BITNUM[15:8] 1495 * <SLV-T> A0h 3Fh [7:0] IFVBER_BITNUM[7:0] 1496 */ 1497 cxd2841er_read_regs(priv, I2C_SLVT, 0x35, data, 11); 1498 if (data[0] & 0x01) { 1499 *bit_error = ((u32)(data[1] & 0x3F) << 16) | 1500 ((u32)(data[2] & 0xFF) << 8) | 1501 (u32)(data[3] & 0xFF); 1502 *bit_count = ((u32)(data[8] & 0x3F) << 16) | 1503 ((u32)(data[9] & 0xFF) << 8) | 1504 (u32)(data[10] & 0xFF); 1505 if ((*bit_count == 0) || (*bit_error > *bit_count)) { 1506 dev_dbg(&priv->i2c->dev, 1507 "%s(): invalid bit_error %d, bit_count %d\n", 1508 __func__, *bit_error, *bit_count); 1509 return -EINVAL; 1510 } 1511 return 0; 1512 } 1513 dev_dbg(&priv->i2c->dev, "%s(): no data available\n", __func__); 1514 return -EINVAL; 1515 } 1516 1517 1518 static int cxd2841er_mon_read_ber_s2(struct cxd2841er_priv *priv, 1519 u32 *bit_error, u32 *bit_count) 1520 { 1521 u8 data[5]; 1522 u32 period; 1523 1524 /* Set SLV-T Bank : 0xB2 */ 1525 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xb2); 1526 /* 1527 * slave Bank Addr Bit Signal name 1528 * <SLV-T> B2h 30h [0] IFLBER_VALID 1529 * <SLV-T> B2h 31h [3:0] IFLBER_BITERR[27:24] 1530 * <SLV-T> B2h 32h [7:0] IFLBER_BITERR[23:16] 1531 * <SLV-T> B2h 33h [7:0] IFLBER_BITERR[15:8] 1532 * <SLV-T> B2h 34h [7:0] IFLBER_BITERR[7:0] 1533 */ 1534 cxd2841er_read_regs(priv, I2C_SLVT, 0x30, data, 5); 1535 if (data[0] & 0x01) { 1536 /* Bit error count */ 1537 *bit_error = ((u32)(data[1] & 0x0F) << 24) | 1538 ((u32)(data[2] & 0xFF) << 16) | 1539 ((u32)(data[3] & 0xFF) << 8) | 1540 (u32)(data[4] & 0xFF); 1541 1542 /* Set SLV-T Bank : 0xA0 */ 1543 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0); 1544 cxd2841er_read_reg(priv, I2C_SLVT, 0x7a, data); 1545 /* Measurement period */ 1546 period = (u32)(1 << (data[0] & 0x0F)); 1547 if (period == 0) { 1548 dev_dbg(&priv->i2c->dev, 1549 "%s(): period is 0\n", __func__); 1550 return -EINVAL; 1551 } 1552 if (*bit_error > (period * 64800)) { 1553 dev_dbg(&priv->i2c->dev, 1554 "%s(): invalid bit_err 0x%x period 0x%x\n", 1555 __func__, *bit_error, period); 1556 return -EINVAL; 1557 } 1558 *bit_count = period * 64800; 1559 1560 return 0; 1561 } else { 1562 dev_dbg(&priv->i2c->dev, 1563 "%s(): no data available\n", __func__); 1564 } 1565 return -EINVAL; 1566 } 1567 1568 static int cxd2841er_read_ber_t2(struct cxd2841er_priv *priv, 1569 u32 *bit_error, u32 *bit_count) 1570 { 1571 u8 data[4]; 1572 u32 period_exp, n_ldpc; 1573 1574 if (priv->state != STATE_ACTIVE_TC) { 1575 dev_dbg(&priv->i2c->dev, 1576 "%s(): invalid state %d\n", __func__, priv->state); 1577 return -EINVAL; 1578 } 1579 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20); 1580 cxd2841er_read_regs(priv, I2C_SLVT, 0x39, data, sizeof(data)); 1581 if (!(data[0] & 0x10)) { 1582 dev_dbg(&priv->i2c->dev, 1583 "%s(): no valid BER data\n", __func__); 1584 return -EINVAL; 1585 } 1586 *bit_error = ((u32)(data[0] & 0x0f) << 24) | 1587 ((u32)data[1] << 16) | 1588 ((u32)data[2] << 8) | 1589 (u32)data[3]; 1590 cxd2841er_read_reg(priv, I2C_SLVT, 0x6f, data); 1591 period_exp = data[0] & 0x0f; 1592 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x22); 1593 cxd2841er_read_reg(priv, I2C_SLVT, 0x5e, data); 1594 n_ldpc = ((data[0] & 0x03) == 0 ? 16200 : 64800); 1595 if (*bit_error > ((1U << period_exp) * n_ldpc)) { 1596 dev_dbg(&priv->i2c->dev, 1597 "%s(): invalid BER value\n", __func__); 1598 return -EINVAL; 1599 } 1600 1601 /* 1602 * FIXME: the right thing would be to return bit_error untouched, 1603 * but, as we don't know the scale returned by the counters, let's 1604 * at least preserver BER = bit_error/bit_count. 1605 */ 1606 if (period_exp >= 4) { 1607 *bit_count = (1U << (period_exp - 4)) * (n_ldpc / 200); 1608 *bit_error *= 3125ULL; 1609 } else { 1610 *bit_count = (1U << period_exp) * (n_ldpc / 200); 1611 *bit_error *= 50000ULL; 1612 } 1613 return 0; 1614 } 1615 1616 static int cxd2841er_read_ber_t(struct cxd2841er_priv *priv, 1617 u32 *bit_error, u32 *bit_count) 1618 { 1619 u8 data[2]; 1620 u32 period; 1621 1622 if (priv->state != STATE_ACTIVE_TC) { 1623 dev_dbg(&priv->i2c->dev, 1624 "%s(): invalid state %d\n", __func__, priv->state); 1625 return -EINVAL; 1626 } 1627 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10); 1628 cxd2841er_read_reg(priv, I2C_SLVT, 0x39, data); 1629 if (!(data[0] & 0x01)) { 1630 dev_dbg(&priv->i2c->dev, 1631 "%s(): no valid BER data\n", __func__); 1632 return 0; 1633 } 1634 cxd2841er_read_regs(priv, I2C_SLVT, 0x22, data, sizeof(data)); 1635 *bit_error = ((u32)data[0] << 8) | (u32)data[1]; 1636 cxd2841er_read_reg(priv, I2C_SLVT, 0x6f, data); 1637 period = ((data[0] & 0x07) == 0) ? 256 : (4096 << (data[0] & 0x07)); 1638 1639 /* 1640 * FIXME: the right thing would be to return bit_error untouched, 1641 * but, as we don't know the scale returned by the counters, let's 1642 * at least preserver BER = bit_error/bit_count. 1643 */ 1644 *bit_count = period / 128; 1645 *bit_error *= 78125ULL; 1646 return 0; 1647 } 1648 1649 static int cxd2841er_freeze_regs(struct cxd2841er_priv *priv) 1650 { 1651 /* 1652 * Freeze registers: ensure multiple separate register reads 1653 * are from the same snapshot 1654 */ 1655 cxd2841er_write_reg(priv, I2C_SLVT, 0x01, 0x01); 1656 return 0; 1657 } 1658 1659 static int cxd2841er_unfreeze_regs(struct cxd2841er_priv *priv) 1660 { 1661 /* 1662 * un-freeze registers 1663 */ 1664 cxd2841er_write_reg(priv, I2C_SLVT, 0x01, 0x00); 1665 return 0; 1666 } 1667 1668 static u32 cxd2841er_dvbs_read_snr(struct cxd2841er_priv *priv, 1669 u8 delsys, u32 *snr) 1670 { 1671 u8 data[3]; 1672 u32 res = 0, value; 1673 int min_index, max_index, index; 1674 static const struct cxd2841er_cnr_data *cn_data; 1675 1676 cxd2841er_freeze_regs(priv); 1677 /* Set SLV-T Bank : 0xA1 */ 1678 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa1); 1679 /* 1680 * slave Bank Addr Bit Signal name 1681 * <SLV-T> A1h 10h [0] ICPM_QUICKRDY 1682 * <SLV-T> A1h 11h [4:0] ICPM_QUICKCNDT[12:8] 1683 * <SLV-T> A1h 12h [7:0] ICPM_QUICKCNDT[7:0] 1684 */ 1685 cxd2841er_read_regs(priv, I2C_SLVT, 0x10, data, 3); 1686 cxd2841er_unfreeze_regs(priv); 1687 1688 if (data[0] & 0x01) { 1689 value = ((u32)(data[1] & 0x1F) << 8) | (u32)(data[2] & 0xFF); 1690 min_index = 0; 1691 if (delsys == SYS_DVBS) { 1692 cn_data = s_cn_data; 1693 max_index = ARRAY_SIZE(s_cn_data) - 1; 1694 } else { 1695 cn_data = s2_cn_data; 1696 max_index = ARRAY_SIZE(s2_cn_data) - 1; 1697 } 1698 if (value >= cn_data[min_index].value) { 1699 res = cn_data[min_index].cnr_x1000; 1700 goto done; 1701 } 1702 if (value <= cn_data[max_index].value) { 1703 res = cn_data[max_index].cnr_x1000; 1704 goto done; 1705 } 1706 while ((max_index - min_index) > 1) { 1707 index = (max_index + min_index) / 2; 1708 if (value == cn_data[index].value) { 1709 res = cn_data[index].cnr_x1000; 1710 goto done; 1711 } else if (value > cn_data[index].value) 1712 max_index = index; 1713 else 1714 min_index = index; 1715 if ((max_index - min_index) <= 1) { 1716 if (value == cn_data[max_index].value) { 1717 res = cn_data[max_index].cnr_x1000; 1718 goto done; 1719 } else { 1720 res = cn_data[min_index].cnr_x1000; 1721 goto done; 1722 } 1723 } 1724 } 1725 } else { 1726 dev_dbg(&priv->i2c->dev, 1727 "%s(): no data available\n", __func__); 1728 return -EINVAL; 1729 } 1730 done: 1731 *snr = res; 1732 return 0; 1733 } 1734 1735 static uint32_t sony_log(uint32_t x) 1736 { 1737 return (((10000>>8)*(intlog2(x)>>16) + LOG2_E_100X/2)/LOG2_E_100X); 1738 } 1739 1740 static int cxd2841er_read_snr_c(struct cxd2841er_priv *priv, u32 *snr) 1741 { 1742 u32 reg; 1743 u8 data[2]; 1744 enum sony_dvbc_constellation_t qam = SONY_DVBC_CONSTELLATION_16QAM; 1745 1746 *snr = 0; 1747 if (priv->state != STATE_ACTIVE_TC) { 1748 dev_dbg(&priv->i2c->dev, 1749 "%s(): invalid state %d\n", 1750 __func__, priv->state); 1751 return -EINVAL; 1752 } 1753 1754 cxd2841er_freeze_regs(priv); 1755 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40); 1756 cxd2841er_read_regs(priv, I2C_SLVT, 0x19, data, 1); 1757 qam = (enum sony_dvbc_constellation_t) (data[0] & 0x07); 1758 cxd2841er_read_regs(priv, I2C_SLVT, 0x4C, data, 2); 1759 cxd2841er_unfreeze_regs(priv); 1760 1761 reg = ((u32)(data[0]&0x1f) << 8) | (u32)data[1]; 1762 if (reg == 0) { 1763 dev_dbg(&priv->i2c->dev, 1764 "%s(): reg value out of range\n", __func__); 1765 return 0; 1766 } 1767 1768 switch (qam) { 1769 case SONY_DVBC_CONSTELLATION_16QAM: 1770 case SONY_DVBC_CONSTELLATION_64QAM: 1771 case SONY_DVBC_CONSTELLATION_256QAM: 1772 /* SNR(dB) = -9.50 * ln(IREG_SNR_ESTIMATE / (24320)) */ 1773 if (reg < 126) 1774 reg = 126; 1775 *snr = -95 * (int32_t)sony_log(reg) + 95941; 1776 break; 1777 case SONY_DVBC_CONSTELLATION_32QAM: 1778 case SONY_DVBC_CONSTELLATION_128QAM: 1779 /* SNR(dB) = -8.75 * ln(IREG_SNR_ESTIMATE / (20800)) */ 1780 if (reg < 69) 1781 reg = 69; 1782 *snr = -88 * (int32_t)sony_log(reg) + 86999; 1783 break; 1784 default: 1785 return -EINVAL; 1786 } 1787 1788 return 0; 1789 } 1790 1791 static int cxd2841er_read_snr_t(struct cxd2841er_priv *priv, u32 *snr) 1792 { 1793 u32 reg; 1794 u8 data[2]; 1795 1796 *snr = 0; 1797 if (priv->state != STATE_ACTIVE_TC) { 1798 dev_dbg(&priv->i2c->dev, 1799 "%s(): invalid state %d\n", __func__, priv->state); 1800 return -EINVAL; 1801 } 1802 1803 cxd2841er_freeze_regs(priv); 1804 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10); 1805 cxd2841er_read_regs(priv, I2C_SLVT, 0x28, data, sizeof(data)); 1806 cxd2841er_unfreeze_regs(priv); 1807 1808 reg = ((u32)data[0] << 8) | (u32)data[1]; 1809 if (reg == 0) { 1810 dev_dbg(&priv->i2c->dev, 1811 "%s(): reg value out of range\n", __func__); 1812 return 0; 1813 } 1814 if (reg > 4996) 1815 reg = 4996; 1816 *snr = 100 * ((INTLOG10X100(reg) - INTLOG10X100(5350 - reg)) + 285); 1817 return 0; 1818 } 1819 1820 static int cxd2841er_read_snr_t2(struct cxd2841er_priv *priv, u32 *snr) 1821 { 1822 u32 reg; 1823 u8 data[2]; 1824 1825 *snr = 0; 1826 if (priv->state != STATE_ACTIVE_TC) { 1827 dev_dbg(&priv->i2c->dev, 1828 "%s(): invalid state %d\n", __func__, priv->state); 1829 return -EINVAL; 1830 } 1831 1832 cxd2841er_freeze_regs(priv); 1833 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20); 1834 cxd2841er_read_regs(priv, I2C_SLVT, 0x28, data, sizeof(data)); 1835 cxd2841er_unfreeze_regs(priv); 1836 1837 reg = ((u32)data[0] << 8) | (u32)data[1]; 1838 if (reg == 0) { 1839 dev_dbg(&priv->i2c->dev, 1840 "%s(): reg value out of range\n", __func__); 1841 return 0; 1842 } 1843 if (reg > 10876) 1844 reg = 10876; 1845 *snr = 100 * ((INTLOG10X100(reg) - INTLOG10X100(12600 - reg)) + 320); 1846 return 0; 1847 } 1848 1849 static int cxd2841er_read_snr_i(struct cxd2841er_priv *priv, u32 *snr) 1850 { 1851 u32 reg; 1852 u8 data[2]; 1853 1854 *snr = 0; 1855 if (priv->state != STATE_ACTIVE_TC) { 1856 dev_dbg(&priv->i2c->dev, 1857 "%s(): invalid state %d\n", __func__, 1858 priv->state); 1859 return -EINVAL; 1860 } 1861 1862 cxd2841er_freeze_regs(priv); 1863 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60); 1864 cxd2841er_read_regs(priv, I2C_SLVT, 0x28, data, sizeof(data)); 1865 cxd2841er_unfreeze_regs(priv); 1866 1867 reg = ((u32)data[0] << 8) | (u32)data[1]; 1868 if (reg == 0) { 1869 dev_dbg(&priv->i2c->dev, 1870 "%s(): reg value out of range\n", __func__); 1871 return 0; 1872 } 1873 *snr = 10000 * (intlog10(reg) >> 24) - 9031; 1874 return 0; 1875 } 1876 1877 static u16 cxd2841er_read_agc_gain_c(struct cxd2841er_priv *priv, 1878 u8 delsys) 1879 { 1880 u8 data[2]; 1881 1882 cxd2841er_write_reg( 1883 priv, I2C_SLVT, 0x00, 0x40); 1884 cxd2841er_read_regs(priv, I2C_SLVT, 0x49, data, 2); 1885 dev_dbg(&priv->i2c->dev, 1886 "%s(): AGC value=%u\n", 1887 __func__, (((u16)data[0] & 0x0F) << 8) | 1888 (u16)(data[1] & 0xFF)); 1889 return ((((u16)data[0] & 0x0F) << 8) | (u16)(data[1] & 0xFF)) << 4; 1890 } 1891 1892 static u16 cxd2841er_read_agc_gain_t_t2(struct cxd2841er_priv *priv, 1893 u8 delsys) 1894 { 1895 u8 data[2]; 1896 1897 cxd2841er_write_reg( 1898 priv, I2C_SLVT, 0x00, (delsys == SYS_DVBT ? 0x10 : 0x20)); 1899 cxd2841er_read_regs(priv, I2C_SLVT, 0x26, data, 2); 1900 dev_dbg(&priv->i2c->dev, 1901 "%s(): AGC value=%u\n", 1902 __func__, (((u16)data[0] & 0x0F) << 8) | 1903 (u16)(data[1] & 0xFF)); 1904 return ((((u16)data[0] & 0x0F) << 8) | (u16)(data[1] & 0xFF)) << 4; 1905 } 1906 1907 static u16 cxd2841er_read_agc_gain_i(struct cxd2841er_priv *priv, 1908 u8 delsys) 1909 { 1910 u8 data[2]; 1911 1912 cxd2841er_write_reg( 1913 priv, I2C_SLVT, 0x00, 0x60); 1914 cxd2841er_read_regs(priv, I2C_SLVT, 0x26, data, 2); 1915 1916 dev_dbg(&priv->i2c->dev, 1917 "%s(): AGC value=%u\n", 1918 __func__, (((u16)data[0] & 0x0F) << 8) | 1919 (u16)(data[1] & 0xFF)); 1920 return ((((u16)data[0] & 0x0F) << 8) | (u16)(data[1] & 0xFF)) << 4; 1921 } 1922 1923 static u16 cxd2841er_read_agc_gain_s(struct cxd2841er_priv *priv) 1924 { 1925 u8 data[2]; 1926 1927 /* Set SLV-T Bank : 0xA0 */ 1928 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0); 1929 /* 1930 * slave Bank Addr Bit Signal name 1931 * <SLV-T> A0h 1Fh [4:0] IRFAGC_GAIN[12:8] 1932 * <SLV-T> A0h 20h [7:0] IRFAGC_GAIN[7:0] 1933 */ 1934 cxd2841er_read_regs(priv, I2C_SLVT, 0x1f, data, 2); 1935 return ((((u16)data[0] & 0x1F) << 8) | (u16)(data[1] & 0xFF)) << 3; 1936 } 1937 1938 static void cxd2841er_read_ber(struct dvb_frontend *fe) 1939 { 1940 struct dtv_frontend_properties *p = &fe->dtv_property_cache; 1941 struct cxd2841er_priv *priv = fe->demodulator_priv; 1942 u32 ret, bit_error = 0, bit_count = 0; 1943 1944 dev_dbg(&priv->i2c->dev, "%s()\n", __func__); 1945 switch (p->delivery_system) { 1946 case SYS_DVBC_ANNEX_A: 1947 case SYS_DVBC_ANNEX_B: 1948 case SYS_DVBC_ANNEX_C: 1949 ret = cxd2841er_read_ber_c(priv, &bit_error, &bit_count); 1950 break; 1951 case SYS_ISDBT: 1952 ret = cxd2841er_read_ber_i(priv, &bit_error, &bit_count); 1953 break; 1954 case SYS_DVBS: 1955 ret = cxd2841er_mon_read_ber_s(priv, &bit_error, &bit_count); 1956 break; 1957 case SYS_DVBS2: 1958 ret = cxd2841er_mon_read_ber_s2(priv, &bit_error, &bit_count); 1959 break; 1960 case SYS_DVBT: 1961 ret = cxd2841er_read_ber_t(priv, &bit_error, &bit_count); 1962 break; 1963 case SYS_DVBT2: 1964 ret = cxd2841er_read_ber_t2(priv, &bit_error, &bit_count); 1965 break; 1966 default: 1967 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 1968 p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 1969 return; 1970 } 1971 1972 if (!ret) { 1973 p->post_bit_error.stat[0].scale = FE_SCALE_COUNTER; 1974 p->post_bit_error.stat[0].uvalue += bit_error; 1975 p->post_bit_count.stat[0].scale = FE_SCALE_COUNTER; 1976 p->post_bit_count.stat[0].uvalue += bit_count; 1977 } else { 1978 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 1979 p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 1980 } 1981 } 1982 1983 static void cxd2841er_read_signal_strength(struct dvb_frontend *fe) 1984 { 1985 struct dtv_frontend_properties *p = &fe->dtv_property_cache; 1986 struct cxd2841er_priv *priv = fe->demodulator_priv; 1987 s32 strength; 1988 1989 dev_dbg(&priv->i2c->dev, "%s()\n", __func__); 1990 switch (p->delivery_system) { 1991 case SYS_DVBT: 1992 case SYS_DVBT2: 1993 strength = cxd2841er_read_agc_gain_t_t2(priv, 1994 p->delivery_system); 1995 p->strength.stat[0].scale = FE_SCALE_DECIBEL; 1996 /* Formula was empirically determinated @ 410 MHz */ 1997 p->strength.stat[0].uvalue = strength * 366 / 100 - 89520; 1998 break; /* Code moved out of the function */ 1999 case SYS_DVBC_ANNEX_A: 2000 case SYS_DVBC_ANNEX_B: 2001 case SYS_DVBC_ANNEX_C: 2002 strength = cxd2841er_read_agc_gain_c(priv, 2003 p->delivery_system); 2004 p->strength.stat[0].scale = FE_SCALE_DECIBEL; 2005 /* 2006 * Formula was empirically determinated via linear regression, 2007 * using frequencies: 175 MHz, 410 MHz and 800 MHz, and a 2008 * stream modulated with QAM64 2009 */ 2010 p->strength.stat[0].uvalue = strength * 4045 / 1000 - 85224; 2011 break; 2012 case SYS_ISDBT: 2013 strength = cxd2841er_read_agc_gain_i(priv, p->delivery_system); 2014 p->strength.stat[0].scale = FE_SCALE_DECIBEL; 2015 /* 2016 * Formula was empirically determinated via linear regression, 2017 * using frequencies: 175 MHz, 410 MHz and 800 MHz. 2018 */ 2019 p->strength.stat[0].uvalue = strength * 3775 / 1000 - 90185; 2020 break; 2021 case SYS_DVBS: 2022 case SYS_DVBS2: 2023 strength = 65535 - cxd2841er_read_agc_gain_s(priv); 2024 p->strength.stat[0].scale = FE_SCALE_RELATIVE; 2025 p->strength.stat[0].uvalue = strength; 2026 break; 2027 default: 2028 p->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 2029 break; 2030 } 2031 } 2032 2033 static void cxd2841er_read_snr(struct dvb_frontend *fe) 2034 { 2035 u32 tmp = 0; 2036 int ret = 0; 2037 struct dtv_frontend_properties *p = &fe->dtv_property_cache; 2038 struct cxd2841er_priv *priv = fe->demodulator_priv; 2039 2040 dev_dbg(&priv->i2c->dev, "%s()\n", __func__); 2041 switch (p->delivery_system) { 2042 case SYS_DVBC_ANNEX_A: 2043 case SYS_DVBC_ANNEX_B: 2044 case SYS_DVBC_ANNEX_C: 2045 ret = cxd2841er_read_snr_c(priv, &tmp); 2046 break; 2047 case SYS_DVBT: 2048 ret = cxd2841er_read_snr_t(priv, &tmp); 2049 break; 2050 case SYS_DVBT2: 2051 ret = cxd2841er_read_snr_t2(priv, &tmp); 2052 break; 2053 case SYS_ISDBT: 2054 ret = cxd2841er_read_snr_i(priv, &tmp); 2055 break; 2056 case SYS_DVBS: 2057 case SYS_DVBS2: 2058 ret = cxd2841er_dvbs_read_snr(priv, p->delivery_system, &tmp); 2059 break; 2060 default: 2061 dev_dbg(&priv->i2c->dev, "%s(): unknown delivery system %d\n", 2062 __func__, p->delivery_system); 2063 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 2064 return; 2065 } 2066 2067 dev_dbg(&priv->i2c->dev, "%s(): snr=%d\n", 2068 __func__, (int32_t)tmp); 2069 2070 if (!ret) { 2071 p->cnr.stat[0].scale = FE_SCALE_DECIBEL; 2072 p->cnr.stat[0].svalue = tmp; 2073 } else { 2074 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 2075 } 2076 } 2077 2078 static void cxd2841er_read_ucblocks(struct dvb_frontend *fe) 2079 { 2080 struct dtv_frontend_properties *p = &fe->dtv_property_cache; 2081 struct cxd2841er_priv *priv = fe->demodulator_priv; 2082 u32 ucblocks = 0; 2083 2084 dev_dbg(&priv->i2c->dev, "%s()\n", __func__); 2085 switch (p->delivery_system) { 2086 case SYS_DVBC_ANNEX_A: 2087 case SYS_DVBC_ANNEX_B: 2088 case SYS_DVBC_ANNEX_C: 2089 cxd2841er_read_packet_errors_c(priv, &ucblocks); 2090 break; 2091 case SYS_DVBT: 2092 cxd2841er_read_packet_errors_t(priv, &ucblocks); 2093 break; 2094 case SYS_DVBT2: 2095 cxd2841er_read_packet_errors_t2(priv, &ucblocks); 2096 break; 2097 case SYS_ISDBT: 2098 cxd2841er_read_packet_errors_i(priv, &ucblocks); 2099 break; 2100 default: 2101 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 2102 return; 2103 } 2104 dev_dbg(&priv->i2c->dev, "%s() ucblocks=%u\n", __func__, ucblocks); 2105 2106 p->block_error.stat[0].scale = FE_SCALE_COUNTER; 2107 p->block_error.stat[0].uvalue = ucblocks; 2108 } 2109 2110 static int cxd2841er_dvbt2_set_profile( 2111 struct cxd2841er_priv *priv, enum cxd2841er_dvbt2_profile_t profile) 2112 { 2113 u8 tune_mode; 2114 u8 seq_not2d_time; 2115 2116 dev_dbg(&priv->i2c->dev, "%s()\n", __func__); 2117 switch (profile) { 2118 case DVBT2_PROFILE_BASE: 2119 tune_mode = 0x01; 2120 /* Set early unlock time */ 2121 seq_not2d_time = (priv->xtal == SONY_XTAL_24000)?0x0E:0x0C; 2122 break; 2123 case DVBT2_PROFILE_LITE: 2124 tune_mode = 0x05; 2125 /* Set early unlock time */ 2126 seq_not2d_time = (priv->xtal == SONY_XTAL_24000)?0x2E:0x28; 2127 break; 2128 case DVBT2_PROFILE_ANY: 2129 tune_mode = 0x00; 2130 /* Set early unlock time */ 2131 seq_not2d_time = (priv->xtal == SONY_XTAL_24000)?0x2E:0x28; 2132 break; 2133 default: 2134 return -EINVAL; 2135 } 2136 /* Set SLV-T Bank : 0x2E */ 2137 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2e); 2138 /* Set profile and tune mode */ 2139 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x10, tune_mode, 0x07); 2140 /* Set SLV-T Bank : 0x2B */ 2141 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2b); 2142 /* Set early unlock detection time */ 2143 cxd2841er_write_reg(priv, I2C_SLVT, 0x9d, seq_not2d_time); 2144 return 0; 2145 } 2146 2147 static int cxd2841er_dvbt2_set_plp_config(struct cxd2841er_priv *priv, 2148 u8 is_auto, u8 plp_id) 2149 { 2150 if (is_auto) { 2151 dev_dbg(&priv->i2c->dev, 2152 "%s() using auto PLP selection\n", __func__); 2153 } else { 2154 dev_dbg(&priv->i2c->dev, 2155 "%s() using manual PLP selection, ID %d\n", 2156 __func__, plp_id); 2157 } 2158 /* Set SLV-T Bank : 0x23 */ 2159 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x23); 2160 if (!is_auto) { 2161 /* Manual PLP selection mode. Set the data PLP Id. */ 2162 cxd2841er_write_reg(priv, I2C_SLVT, 0xaf, plp_id); 2163 } 2164 /* Auto PLP select (Scanning mode = 0x00). Data PLP select = 0x01. */ 2165 cxd2841er_write_reg(priv, I2C_SLVT, 0xad, (is_auto ? 0x00 : 0x01)); 2166 return 0; 2167 } 2168 2169 static int cxd2841er_sleep_tc_to_active_t2_band(struct cxd2841er_priv *priv, 2170 u32 bandwidth) 2171 { 2172 u32 iffreq, ifhz; 2173 u8 data[MAX_WRITE_REGSIZE]; 2174 2175 static const uint8_t nominalRate8bw[3][5] = { 2176 /* TRCG Nominal Rate [37:0] */ 2177 {0x11, 0xF0, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */ 2178 {0x15, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */ 2179 {0x11, 0xF0, 0x00, 0x00, 0x00} /* 41MHz XTal */ 2180 }; 2181 2182 static const uint8_t nominalRate7bw[3][5] = { 2183 /* TRCG Nominal Rate [37:0] */ 2184 {0x14, 0x80, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */ 2185 {0x18, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */ 2186 {0x14, 0x80, 0x00, 0x00, 0x00} /* 41MHz XTal */ 2187 }; 2188 2189 static const uint8_t nominalRate6bw[3][5] = { 2190 /* TRCG Nominal Rate [37:0] */ 2191 {0x17, 0xEA, 0xAA, 0xAA, 0xAA}, /* 20.5MHz XTal */ 2192 {0x1C, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */ 2193 {0x17, 0xEA, 0xAA, 0xAA, 0xAA} /* 41MHz XTal */ 2194 }; 2195 2196 static const uint8_t nominalRate5bw[3][5] = { 2197 /* TRCG Nominal Rate [37:0] */ 2198 {0x1C, 0xB3, 0x33, 0x33, 0x33}, /* 20.5MHz XTal */ 2199 {0x21, 0x99, 0x99, 0x99, 0x99}, /* 24MHz XTal */ 2200 {0x1C, 0xB3, 0x33, 0x33, 0x33} /* 41MHz XTal */ 2201 }; 2202 2203 static const uint8_t nominalRate17bw[3][5] = { 2204 /* TRCG Nominal Rate [37:0] */ 2205 {0x58, 0xE2, 0xAF, 0xE0, 0xBC}, /* 20.5MHz XTal */ 2206 {0x68, 0x0F, 0xA2, 0x32, 0xD0}, /* 24MHz XTal */ 2207 {0x58, 0xE2, 0xAF, 0xE0, 0xBC} /* 41MHz XTal */ 2208 }; 2209 2210 static const uint8_t itbCoef8bw[3][14] = { 2211 {0x26, 0xAF, 0x06, 0xCD, 0x13, 0xBB, 0x28, 0xBA, 2212 0x23, 0xA9, 0x1F, 0xA8, 0x2C, 0xC8}, /* 20.5MHz XTal */ 2213 {0x2F, 0xBA, 0x28, 0x9B, 0x28, 0x9D, 0x28, 0xA1, 2214 0x29, 0xA5, 0x2A, 0xAC, 0x29, 0xB5}, /* 24MHz XTal */ 2215 {0x26, 0xAF, 0x06, 0xCD, 0x13, 0xBB, 0x28, 0xBA, 2216 0x23, 0xA9, 0x1F, 0xA8, 0x2C, 0xC8} /* 41MHz XTal */ 2217 }; 2218 2219 static const uint8_t itbCoef7bw[3][14] = { 2220 {0x2C, 0xBD, 0x02, 0xCF, 0x04, 0xF8, 0x23, 0xA6, 2221 0x29, 0xB0, 0x26, 0xA9, 0x21, 0xA5}, /* 20.5MHz XTal */ 2222 {0x30, 0xB1, 0x29, 0x9A, 0x28, 0x9C, 0x28, 0xA0, 2223 0x29, 0xA2, 0x2B, 0xA6, 0x2B, 0xAD}, /* 24MHz XTal */ 2224 {0x2C, 0xBD, 0x02, 0xCF, 0x04, 0xF8, 0x23, 0xA6, 2225 0x29, 0xB0, 0x26, 0xA9, 0x21, 0xA5} /* 41MHz XTal */ 2226 }; 2227 2228 static const uint8_t itbCoef6bw[3][14] = { 2229 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 2230 0x00, 0xCF, 0x00, 0xE6, 0x23, 0xA4}, /* 20.5MHz XTal */ 2231 {0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E, 2232 0x29, 0xA4, 0x29, 0xA2, 0x29, 0xA8}, /* 24MHz XTal */ 2233 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 2234 0x00, 0xCF, 0x00, 0xE6, 0x23, 0xA4} /* 41MHz XTal */ 2235 }; 2236 2237 static const uint8_t itbCoef5bw[3][14] = { 2238 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 2239 0x00, 0xCF, 0x00, 0xE6, 0x23, 0xA4}, /* 20.5MHz XTal */ 2240 {0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E, 2241 0x29, 0xA4, 0x29, 0xA2, 0x29, 0xA8}, /* 24MHz XTal */ 2242 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 2243 0x00, 0xCF, 0x00, 0xE6, 0x23, 0xA4} /* 41MHz XTal */ 2244 }; 2245 2246 static const uint8_t itbCoef17bw[3][14] = { 2247 {0x25, 0xA0, 0x36, 0x8D, 0x2E, 0x94, 0x28, 0x9B, 2248 0x32, 0x90, 0x2C, 0x9D, 0x29, 0x99}, /* 20.5MHz XTal */ 2249 {0x33, 0x8E, 0x2B, 0x97, 0x2D, 0x95, 0x37, 0x8B, 2250 0x30, 0x97, 0x2D, 0x9A, 0x21, 0xA4}, /* 24MHz XTal */ 2251 {0x25, 0xA0, 0x36, 0x8D, 0x2E, 0x94, 0x28, 0x9B, 2252 0x32, 0x90, 0x2C, 0x9D, 0x29, 0x99} /* 41MHz XTal */ 2253 }; 2254 2255 /* Set SLV-T Bank : 0x20 */ 2256 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20); 2257 2258 switch (bandwidth) { 2259 case 8000000: 2260 /* <Timing Recovery setting> */ 2261 cxd2841er_write_regs(priv, I2C_SLVT, 2262 0x9F, nominalRate8bw[priv->xtal], 5); 2263 2264 /* Set SLV-T Bank : 0x27 */ 2265 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27); 2266 cxd2841er_set_reg_bits(priv, I2C_SLVT, 2267 0x7a, 0x00, 0x0f); 2268 2269 /* Set SLV-T Bank : 0x10 */ 2270 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10); 2271 2272 /* Group delay equaliser settings for 2273 * ASCOT2D, ASCOT2E and ASCOT3 tuners 2274 */ 2275 if (priv->flags & CXD2841ER_ASCOT) 2276 cxd2841er_write_regs(priv, I2C_SLVT, 2277 0xA6, itbCoef8bw[priv->xtal], 14); 2278 /* <IF freq setting> */ 2279 ifhz = cxd2841er_get_if_hz(priv, 4800000); 2280 iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz); 2281 data[0] = (u8) ((iffreq >> 16) & 0xff); 2282 data[1] = (u8)((iffreq >> 8) & 0xff); 2283 data[2] = (u8)(iffreq & 0xff); 2284 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3); 2285 /* System bandwidth setting */ 2286 cxd2841er_set_reg_bits( 2287 priv, I2C_SLVT, 0xD7, 0x00, 0x07); 2288 break; 2289 case 7000000: 2290 /* <Timing Recovery setting> */ 2291 cxd2841er_write_regs(priv, I2C_SLVT, 2292 0x9F, nominalRate7bw[priv->xtal], 5); 2293 2294 /* Set SLV-T Bank : 0x27 */ 2295 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27); 2296 cxd2841er_set_reg_bits(priv, I2C_SLVT, 2297 0x7a, 0x00, 0x0f); 2298 2299 /* Set SLV-T Bank : 0x10 */ 2300 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10); 2301 2302 /* Group delay equaliser settings for 2303 * ASCOT2D, ASCOT2E and ASCOT3 tuners 2304 */ 2305 if (priv->flags & CXD2841ER_ASCOT) 2306 cxd2841er_write_regs(priv, I2C_SLVT, 2307 0xA6, itbCoef7bw[priv->xtal], 14); 2308 /* <IF freq setting> */ 2309 ifhz = cxd2841er_get_if_hz(priv, 4200000); 2310 iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz); 2311 data[0] = (u8) ((iffreq >> 16) & 0xff); 2312 data[1] = (u8)((iffreq >> 8) & 0xff); 2313 data[2] = (u8)(iffreq & 0xff); 2314 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3); 2315 /* System bandwidth setting */ 2316 cxd2841er_set_reg_bits( 2317 priv, I2C_SLVT, 0xD7, 0x02, 0x07); 2318 break; 2319 case 6000000: 2320 /* <Timing Recovery setting> */ 2321 cxd2841er_write_regs(priv, I2C_SLVT, 2322 0x9F, nominalRate6bw[priv->xtal], 5); 2323 2324 /* Set SLV-T Bank : 0x27 */ 2325 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27); 2326 cxd2841er_set_reg_bits(priv, I2C_SLVT, 2327 0x7a, 0x00, 0x0f); 2328 2329 /* Set SLV-T Bank : 0x10 */ 2330 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10); 2331 2332 /* Group delay equaliser settings for 2333 * ASCOT2D, ASCOT2E and ASCOT3 tuners 2334 */ 2335 if (priv->flags & CXD2841ER_ASCOT) 2336 cxd2841er_write_regs(priv, I2C_SLVT, 2337 0xA6, itbCoef6bw[priv->xtal], 14); 2338 /* <IF freq setting> */ 2339 ifhz = cxd2841er_get_if_hz(priv, 3600000); 2340 iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz); 2341 data[0] = (u8) ((iffreq >> 16) & 0xff); 2342 data[1] = (u8)((iffreq >> 8) & 0xff); 2343 data[2] = (u8)(iffreq & 0xff); 2344 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3); 2345 /* System bandwidth setting */ 2346 cxd2841er_set_reg_bits( 2347 priv, I2C_SLVT, 0xD7, 0x04, 0x07); 2348 break; 2349 case 5000000: 2350 /* <Timing Recovery setting> */ 2351 cxd2841er_write_regs(priv, I2C_SLVT, 2352 0x9F, nominalRate5bw[priv->xtal], 5); 2353 2354 /* Set SLV-T Bank : 0x27 */ 2355 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27); 2356 cxd2841er_set_reg_bits(priv, I2C_SLVT, 2357 0x7a, 0x00, 0x0f); 2358 2359 /* Set SLV-T Bank : 0x10 */ 2360 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10); 2361 2362 /* Group delay equaliser settings for 2363 * ASCOT2D, ASCOT2E and ASCOT3 tuners 2364 */ 2365 if (priv->flags & CXD2841ER_ASCOT) 2366 cxd2841er_write_regs(priv, I2C_SLVT, 2367 0xA6, itbCoef5bw[priv->xtal], 14); 2368 /* <IF freq setting> */ 2369 ifhz = cxd2841er_get_if_hz(priv, 3600000); 2370 iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz); 2371 data[0] = (u8) ((iffreq >> 16) & 0xff); 2372 data[1] = (u8)((iffreq >> 8) & 0xff); 2373 data[2] = (u8)(iffreq & 0xff); 2374 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3); 2375 /* System bandwidth setting */ 2376 cxd2841er_set_reg_bits( 2377 priv, I2C_SLVT, 0xD7, 0x06, 0x07); 2378 break; 2379 case 1712000: 2380 /* <Timing Recovery setting> */ 2381 cxd2841er_write_regs(priv, I2C_SLVT, 2382 0x9F, nominalRate17bw[priv->xtal], 5); 2383 2384 /* Set SLV-T Bank : 0x27 */ 2385 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27); 2386 cxd2841er_set_reg_bits(priv, I2C_SLVT, 2387 0x7a, 0x03, 0x0f); 2388 2389 /* Set SLV-T Bank : 0x10 */ 2390 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10); 2391 2392 /* Group delay equaliser settings for 2393 * ASCOT2D, ASCOT2E and ASCOT3 tuners 2394 */ 2395 if (priv->flags & CXD2841ER_ASCOT) 2396 cxd2841er_write_regs(priv, I2C_SLVT, 2397 0xA6, itbCoef17bw[priv->xtal], 14); 2398 /* <IF freq setting> */ 2399 ifhz = cxd2841er_get_if_hz(priv, 3500000); 2400 iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz); 2401 data[0] = (u8) ((iffreq >> 16) & 0xff); 2402 data[1] = (u8)((iffreq >> 8) & 0xff); 2403 data[2] = (u8)(iffreq & 0xff); 2404 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3); 2405 /* System bandwidth setting */ 2406 cxd2841er_set_reg_bits( 2407 priv, I2C_SLVT, 0xD7, 0x03, 0x07); 2408 break; 2409 default: 2410 return -EINVAL; 2411 } 2412 return 0; 2413 } 2414 2415 static int cxd2841er_sleep_tc_to_active_t_band( 2416 struct cxd2841er_priv *priv, u32 bandwidth) 2417 { 2418 u8 data[MAX_WRITE_REGSIZE]; 2419 u32 iffreq, ifhz; 2420 static const u8 nominalRate8bw[3][5] = { 2421 /* TRCG Nominal Rate [37:0] */ 2422 {0x11, 0xF0, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */ 2423 {0x15, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */ 2424 {0x11, 0xF0, 0x00, 0x00, 0x00} /* 41MHz XTal */ 2425 }; 2426 static const u8 nominalRate7bw[3][5] = { 2427 /* TRCG Nominal Rate [37:0] */ 2428 {0x14, 0x80, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */ 2429 {0x18, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */ 2430 {0x14, 0x80, 0x00, 0x00, 0x00} /* 41MHz XTal */ 2431 }; 2432 static const u8 nominalRate6bw[3][5] = { 2433 /* TRCG Nominal Rate [37:0] */ 2434 {0x17, 0xEA, 0xAA, 0xAA, 0xAA}, /* 20.5MHz XTal */ 2435 {0x1C, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */ 2436 {0x17, 0xEA, 0xAA, 0xAA, 0xAA} /* 41MHz XTal */ 2437 }; 2438 static const u8 nominalRate5bw[3][5] = { 2439 /* TRCG Nominal Rate [37:0] */ 2440 {0x1C, 0xB3, 0x33, 0x33, 0x33}, /* 20.5MHz XTal */ 2441 {0x21, 0x99, 0x99, 0x99, 0x99}, /* 24MHz XTal */ 2442 {0x1C, 0xB3, 0x33, 0x33, 0x33} /* 41MHz XTal */ 2443 }; 2444 2445 static const u8 itbCoef8bw[3][14] = { 2446 {0x26, 0xAF, 0x06, 0xCD, 0x13, 0xBB, 0x28, 0xBA, 0x23, 0xA9, 2447 0x1F, 0xA8, 0x2C, 0xC8}, /* 20.5MHz XTal */ 2448 {0x2F, 0xBA, 0x28, 0x9B, 0x28, 0x9D, 0x28, 0xA1, 0x29, 0xA5, 2449 0x2A, 0xAC, 0x29, 0xB5}, /* 24MHz XTal */ 2450 {0x26, 0xAF, 0x06, 0xCD, 0x13, 0xBB, 0x28, 0xBA, 0x23, 0xA9, 2451 0x1F, 0xA8, 0x2C, 0xC8} /* 41MHz XTal */ 2452 }; 2453 static const u8 itbCoef7bw[3][14] = { 2454 {0x2C, 0xBD, 0x02, 0xCF, 0x04, 0xF8, 0x23, 0xA6, 0x29, 0xB0, 2455 0x26, 0xA9, 0x21, 0xA5}, /* 20.5MHz XTal */ 2456 {0x30, 0xB1, 0x29, 0x9A, 0x28, 0x9C, 0x28, 0xA0, 0x29, 0xA2, 2457 0x2B, 0xA6, 0x2B, 0xAD}, /* 24MHz XTal */ 2458 {0x2C, 0xBD, 0x02, 0xCF, 0x04, 0xF8, 0x23, 0xA6, 0x29, 0xB0, 2459 0x26, 0xA9, 0x21, 0xA5} /* 41MHz XTal */ 2460 }; 2461 static const u8 itbCoef6bw[3][14] = { 2462 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00, 0xCF, 2463 0x00, 0xE6, 0x23, 0xA4}, /* 20.5MHz XTal */ 2464 {0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E, 0x29, 0xA4, 2465 0x29, 0xA2, 0x29, 0xA8}, /* 24MHz XTal */ 2466 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00, 0xCF, 2467 0x00, 0xE6, 0x23, 0xA4} /* 41MHz XTal */ 2468 }; 2469 static const u8 itbCoef5bw[3][14] = { 2470 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00, 0xCF, 2471 0x00, 0xE6, 0x23, 0xA4}, /* 20.5MHz XTal */ 2472 {0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E, 0x29, 0xA4, 2473 0x29, 0xA2, 0x29, 0xA8}, /* 24MHz XTal */ 2474 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00, 0xCF, 2475 0x00, 0xE6, 0x23, 0xA4} /* 41MHz XTal */ 2476 }; 2477 2478 /* Set SLV-T Bank : 0x13 */ 2479 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x13); 2480 /* Echo performance optimization setting */ 2481 data[0] = 0x01; 2482 data[1] = 0x14; 2483 cxd2841er_write_regs(priv, I2C_SLVT, 0x9C, data, 2); 2484 2485 /* Set SLV-T Bank : 0x10 */ 2486 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10); 2487 2488 switch (bandwidth) { 2489 case 8000000: 2490 /* <Timing Recovery setting> */ 2491 cxd2841er_write_regs(priv, I2C_SLVT, 2492 0x9F, nominalRate8bw[priv->xtal], 5); 2493 /* Group delay equaliser settings for 2494 * ASCOT2D, ASCOT2E and ASCOT3 tuners 2495 */ 2496 if (priv->flags & CXD2841ER_ASCOT) 2497 cxd2841er_write_regs(priv, I2C_SLVT, 2498 0xA6, itbCoef8bw[priv->xtal], 14); 2499 /* <IF freq setting> */ 2500 ifhz = cxd2841er_get_if_hz(priv, 4800000); 2501 iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz); 2502 data[0] = (u8) ((iffreq >> 16) & 0xff); 2503 data[1] = (u8)((iffreq >> 8) & 0xff); 2504 data[2] = (u8)(iffreq & 0xff); 2505 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3); 2506 /* System bandwidth setting */ 2507 cxd2841er_set_reg_bits( 2508 priv, I2C_SLVT, 0xD7, 0x00, 0x07); 2509 2510 /* Demod core latency setting */ 2511 if (priv->xtal == SONY_XTAL_24000) { 2512 data[0] = 0x15; 2513 data[1] = 0x28; 2514 } else { 2515 data[0] = 0x01; 2516 data[1] = 0xE0; 2517 } 2518 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2); 2519 2520 /* Notch filter setting */ 2521 data[0] = 0x01; 2522 data[1] = 0x02; 2523 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x17); 2524 cxd2841er_write_regs(priv, I2C_SLVT, 0x38, data, 2); 2525 break; 2526 case 7000000: 2527 /* <Timing Recovery setting> */ 2528 cxd2841er_write_regs(priv, I2C_SLVT, 2529 0x9F, nominalRate7bw[priv->xtal], 5); 2530 /* Group delay equaliser settings for 2531 * ASCOT2D, ASCOT2E and ASCOT3 tuners 2532 */ 2533 if (priv->flags & CXD2841ER_ASCOT) 2534 cxd2841er_write_regs(priv, I2C_SLVT, 2535 0xA6, itbCoef7bw[priv->xtal], 14); 2536 /* <IF freq setting> */ 2537 ifhz = cxd2841er_get_if_hz(priv, 4200000); 2538 iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz); 2539 data[0] = (u8) ((iffreq >> 16) & 0xff); 2540 data[1] = (u8)((iffreq >> 8) & 0xff); 2541 data[2] = (u8)(iffreq & 0xff); 2542 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3); 2543 /* System bandwidth setting */ 2544 cxd2841er_set_reg_bits( 2545 priv, I2C_SLVT, 0xD7, 0x02, 0x07); 2546 2547 /* Demod core latency setting */ 2548 if (priv->xtal == SONY_XTAL_24000) { 2549 data[0] = 0x1F; 2550 data[1] = 0xF8; 2551 } else { 2552 data[0] = 0x12; 2553 data[1] = 0xF8; 2554 } 2555 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2); 2556 2557 /* Notch filter setting */ 2558 data[0] = 0x00; 2559 data[1] = 0x03; 2560 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x17); 2561 cxd2841er_write_regs(priv, I2C_SLVT, 0x38, data, 2); 2562 break; 2563 case 6000000: 2564 /* <Timing Recovery setting> */ 2565 cxd2841er_write_regs(priv, I2C_SLVT, 2566 0x9F, nominalRate6bw[priv->xtal], 5); 2567 /* Group delay equaliser settings for 2568 * ASCOT2D, ASCOT2E and ASCOT3 tuners 2569 */ 2570 if (priv->flags & CXD2841ER_ASCOT) 2571 cxd2841er_write_regs(priv, I2C_SLVT, 2572 0xA6, itbCoef6bw[priv->xtal], 14); 2573 /* <IF freq setting> */ 2574 ifhz = cxd2841er_get_if_hz(priv, 3600000); 2575 iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz); 2576 data[0] = (u8) ((iffreq >> 16) & 0xff); 2577 data[1] = (u8)((iffreq >> 8) & 0xff); 2578 data[2] = (u8)(iffreq & 0xff); 2579 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3); 2580 /* System bandwidth setting */ 2581 cxd2841er_set_reg_bits( 2582 priv, I2C_SLVT, 0xD7, 0x04, 0x07); 2583 2584 /* Demod core latency setting */ 2585 if (priv->xtal == SONY_XTAL_24000) { 2586 data[0] = 0x25; 2587 data[1] = 0x4C; 2588 } else { 2589 data[0] = 0x1F; 2590 data[1] = 0xDC; 2591 } 2592 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2); 2593 2594 /* Notch filter setting */ 2595 data[0] = 0x00; 2596 data[1] = 0x03; 2597 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x17); 2598 cxd2841er_write_regs(priv, I2C_SLVT, 0x38, data, 2); 2599 break; 2600 case 5000000: 2601 /* <Timing Recovery setting> */ 2602 cxd2841er_write_regs(priv, I2C_SLVT, 2603 0x9F, nominalRate5bw[priv->xtal], 5); 2604 /* Group delay equaliser settings for 2605 * ASCOT2D, ASCOT2E and ASCOT3 tuners 2606 */ 2607 if (priv->flags & CXD2841ER_ASCOT) 2608 cxd2841er_write_regs(priv, I2C_SLVT, 2609 0xA6, itbCoef5bw[priv->xtal], 14); 2610 /* <IF freq setting> */ 2611 ifhz = cxd2841er_get_if_hz(priv, 3600000); 2612 iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz); 2613 data[0] = (u8) ((iffreq >> 16) & 0xff); 2614 data[1] = (u8)((iffreq >> 8) & 0xff); 2615 data[2] = (u8)(iffreq & 0xff); 2616 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3); 2617 /* System bandwidth setting */ 2618 cxd2841er_set_reg_bits( 2619 priv, I2C_SLVT, 0xD7, 0x06, 0x07); 2620 2621 /* Demod core latency setting */ 2622 if (priv->xtal == SONY_XTAL_24000) { 2623 data[0] = 0x2C; 2624 data[1] = 0xC2; 2625 } else { 2626 data[0] = 0x26; 2627 data[1] = 0x3C; 2628 } 2629 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2); 2630 2631 /* Notch filter setting */ 2632 data[0] = 0x00; 2633 data[1] = 0x03; 2634 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x17); 2635 cxd2841er_write_regs(priv, I2C_SLVT, 0x38, data, 2); 2636 break; 2637 } 2638 2639 return 0; 2640 } 2641 2642 static int cxd2841er_sleep_tc_to_active_i_band( 2643 struct cxd2841er_priv *priv, u32 bandwidth) 2644 { 2645 u32 iffreq, ifhz; 2646 u8 data[3]; 2647 2648 /* TRCG Nominal Rate */ 2649 static const u8 nominalRate8bw[3][5] = { 2650 {0x00, 0x00, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */ 2651 {0x11, 0xB8, 0x00, 0x00, 0x00}, /* 24MHz XTal */ 2652 {0x00, 0x00, 0x00, 0x00, 0x00} /* 41MHz XTal */ 2653 }; 2654 2655 static const u8 nominalRate7bw[3][5] = { 2656 {0x00, 0x00, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */ 2657 {0x14, 0x40, 0x00, 0x00, 0x00}, /* 24MHz XTal */ 2658 {0x00, 0x00, 0x00, 0x00, 0x00} /* 41MHz XTal */ 2659 }; 2660 2661 static const u8 nominalRate6bw[3][5] = { 2662 {0x14, 0x2E, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */ 2663 {0x17, 0xA0, 0x00, 0x00, 0x00}, /* 24MHz XTal */ 2664 {0x14, 0x2E, 0x00, 0x00, 0x00} /* 41MHz XTal */ 2665 }; 2666 2667 static const u8 itbCoef8bw[3][14] = { 2668 {0x00}, /* 20.5MHz XTal */ 2669 {0x2F, 0xBA, 0x28, 0x9B, 0x28, 0x9D, 0x28, 0xA1, 0x29, 2670 0xA5, 0x2A, 0xAC, 0x29, 0xB5}, /* 24MHz Xtal */ 2671 {0x0}, /* 41MHz XTal */ 2672 }; 2673 2674 static const u8 itbCoef7bw[3][14] = { 2675 {0x00}, /* 20.5MHz XTal */ 2676 {0x30, 0xB1, 0x29, 0x9A, 0x28, 0x9C, 0x28, 0xA0, 0x29, 2677 0xA2, 0x2B, 0xA6, 0x2B, 0xAD}, /* 24MHz Xtal */ 2678 {0x00}, /* 41MHz XTal */ 2679 }; 2680 2681 static const u8 itbCoef6bw[3][14] = { 2682 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00, 2683 0xCF, 0x00, 0xE6, 0x23, 0xA4}, /* 20.5MHz XTal */ 2684 {0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E, 0x29, 2685 0xA4, 0x29, 0xA2, 0x29, 0xA8}, /* 24MHz Xtal */ 2686 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00, 2687 0xCF, 0x00, 0xE6, 0x23, 0xA4}, /* 41MHz XTal */ 2688 }; 2689 2690 dev_dbg(&priv->i2c->dev, "%s() bandwidth=%u\n", __func__, bandwidth); 2691 /* Set SLV-T Bank : 0x10 */ 2692 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10); 2693 2694 /* 20.5/41MHz Xtal support is not available 2695 * on ISDB-T 7MHzBW and 8MHzBW 2696 */ 2697 if (priv->xtal != SONY_XTAL_24000 && bandwidth > 6000000) { 2698 dev_err(&priv->i2c->dev, 2699 "%s(): bandwidth %d supported only for 24MHz xtal\n", 2700 __func__, bandwidth); 2701 return -EINVAL; 2702 } 2703 2704 switch (bandwidth) { 2705 case 8000000: 2706 /* TRCG Nominal Rate */ 2707 cxd2841er_write_regs(priv, I2C_SLVT, 2708 0x9F, nominalRate8bw[priv->xtal], 5); 2709 /* Group delay equaliser settings for ASCOT tuners optimized */ 2710 if (priv->flags & CXD2841ER_ASCOT) 2711 cxd2841er_write_regs(priv, I2C_SLVT, 2712 0xA6, itbCoef8bw[priv->xtal], 14); 2713 2714 /* IF freq setting */ 2715 ifhz = cxd2841er_get_if_hz(priv, 4750000); 2716 iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz); 2717 data[0] = (u8) ((iffreq >> 16) & 0xff); 2718 data[1] = (u8)((iffreq >> 8) & 0xff); 2719 data[2] = (u8)(iffreq & 0xff); 2720 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3); 2721 2722 /* System bandwidth setting */ 2723 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd7, 0x0, 0x7); 2724 2725 /* Demod core latency setting */ 2726 data[0] = 0x13; 2727 data[1] = 0xFC; 2728 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2); 2729 2730 /* Acquisition optimization setting */ 2731 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x12); 2732 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x71, 0x03, 0x07); 2733 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x15); 2734 cxd2841er_write_reg(priv, I2C_SLVT, 0xBE, 0x03); 2735 break; 2736 case 7000000: 2737 /* TRCG Nominal Rate */ 2738 cxd2841er_write_regs(priv, I2C_SLVT, 2739 0x9F, nominalRate7bw[priv->xtal], 5); 2740 /* Group delay equaliser settings for ASCOT tuners optimized */ 2741 if (priv->flags & CXD2841ER_ASCOT) 2742 cxd2841er_write_regs(priv, I2C_SLVT, 2743 0xA6, itbCoef7bw[priv->xtal], 14); 2744 2745 /* IF freq setting */ 2746 ifhz = cxd2841er_get_if_hz(priv, 4150000); 2747 iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz); 2748 data[0] = (u8) ((iffreq >> 16) & 0xff); 2749 data[1] = (u8)((iffreq >> 8) & 0xff); 2750 data[2] = (u8)(iffreq & 0xff); 2751 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3); 2752 2753 /* System bandwidth setting */ 2754 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd7, 0x02, 0x7); 2755 2756 /* Demod core latency setting */ 2757 data[0] = 0x1A; 2758 data[1] = 0xFA; 2759 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2); 2760 2761 /* Acquisition optimization setting */ 2762 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x12); 2763 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x71, 0x03, 0x07); 2764 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x15); 2765 cxd2841er_write_reg(priv, I2C_SLVT, 0xBE, 0x02); 2766 break; 2767 case 6000000: 2768 /* TRCG Nominal Rate */ 2769 cxd2841er_write_regs(priv, I2C_SLVT, 2770 0x9F, nominalRate6bw[priv->xtal], 5); 2771 /* Group delay equaliser settings for ASCOT tuners optimized */ 2772 if (priv->flags & CXD2841ER_ASCOT) 2773 cxd2841er_write_regs(priv, I2C_SLVT, 2774 0xA6, itbCoef6bw[priv->xtal], 14); 2775 2776 /* IF freq setting */ 2777 ifhz = cxd2841er_get_if_hz(priv, 3550000); 2778 iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz); 2779 data[0] = (u8) ((iffreq >> 16) & 0xff); 2780 data[1] = (u8)((iffreq >> 8) & 0xff); 2781 data[2] = (u8)(iffreq & 0xff); 2782 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3); 2783 2784 /* System bandwidth setting */ 2785 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd7, 0x04, 0x7); 2786 2787 /* Demod core latency setting */ 2788 if (priv->xtal == SONY_XTAL_24000) { 2789 data[0] = 0x1F; 2790 data[1] = 0x79; 2791 } else { 2792 data[0] = 0x1A; 2793 data[1] = 0xE2; 2794 } 2795 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2); 2796 2797 /* Acquisition optimization setting */ 2798 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x12); 2799 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x71, 0x07, 0x07); 2800 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x15); 2801 cxd2841er_write_reg(priv, I2C_SLVT, 0xBE, 0x02); 2802 break; 2803 default: 2804 dev_dbg(&priv->i2c->dev, "%s(): invalid bandwidth %d\n", 2805 __func__, bandwidth); 2806 return -EINVAL; 2807 } 2808 return 0; 2809 } 2810 2811 static int cxd2841er_sleep_tc_to_active_c_band(struct cxd2841er_priv *priv, 2812 u32 bandwidth) 2813 { 2814 u8 bw7_8mhz_b10_a6[] = { 2815 0x2D, 0xC7, 0x04, 0xF4, 0x07, 0xC5, 0x2A, 0xB8, 2816 0x27, 0x9E, 0x27, 0xA4, 0x29, 0xAB }; 2817 u8 bw6mhz_b10_a6[] = { 2818 0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 2819 0x00, 0xCF, 0x00, 0xE6, 0x23, 0xA4 }; 2820 u8 b10_b6[3]; 2821 u32 iffreq, ifhz; 2822 2823 if (bandwidth != 6000000 && 2824 bandwidth != 7000000 && 2825 bandwidth != 8000000) { 2826 dev_info(&priv->i2c->dev, "%s(): unsupported bandwidth %d. Forcing 8Mhz!\n", 2827 __func__, bandwidth); 2828 bandwidth = 8000000; 2829 } 2830 2831 dev_dbg(&priv->i2c->dev, "%s() bw=%d\n", __func__, bandwidth); 2832 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10); 2833 switch (bandwidth) { 2834 case 8000000: 2835 case 7000000: 2836 if (priv->flags & CXD2841ER_ASCOT) 2837 cxd2841er_write_regs( 2838 priv, I2C_SLVT, 0xa6, 2839 bw7_8mhz_b10_a6, sizeof(bw7_8mhz_b10_a6)); 2840 ifhz = cxd2841er_get_if_hz(priv, 4900000); 2841 iffreq = cxd2841er_calc_iffreq(ifhz); 2842 break; 2843 case 6000000: 2844 if (priv->flags & CXD2841ER_ASCOT) 2845 cxd2841er_write_regs( 2846 priv, I2C_SLVT, 0xa6, 2847 bw6mhz_b10_a6, sizeof(bw6mhz_b10_a6)); 2848 ifhz = cxd2841er_get_if_hz(priv, 3700000); 2849 iffreq = cxd2841er_calc_iffreq(ifhz); 2850 break; 2851 default: 2852 dev_err(&priv->i2c->dev, "%s(): unsupported bandwidth %d\n", 2853 __func__, bandwidth); 2854 return -EINVAL; 2855 } 2856 /* <IF freq setting> */ 2857 b10_b6[0] = (u8) ((iffreq >> 16) & 0xff); 2858 b10_b6[1] = (u8)((iffreq >> 8) & 0xff); 2859 b10_b6[2] = (u8)(iffreq & 0xff); 2860 cxd2841er_write_regs(priv, I2C_SLVT, 0xb6, b10_b6, sizeof(b10_b6)); 2861 /* Set SLV-T Bank : 0x11 */ 2862 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11); 2863 switch (bandwidth) { 2864 case 8000000: 2865 case 7000000: 2866 cxd2841er_set_reg_bits( 2867 priv, I2C_SLVT, 0xa3, 0x00, 0x1f); 2868 break; 2869 case 6000000: 2870 cxd2841er_set_reg_bits( 2871 priv, I2C_SLVT, 0xa3, 0x14, 0x1f); 2872 break; 2873 } 2874 /* Set SLV-T Bank : 0x40 */ 2875 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40); 2876 switch (bandwidth) { 2877 case 8000000: 2878 cxd2841er_set_reg_bits( 2879 priv, I2C_SLVT, 0x26, 0x0b, 0x0f); 2880 cxd2841er_write_reg(priv, I2C_SLVT, 0x27, 0x3e); 2881 break; 2882 case 7000000: 2883 cxd2841er_set_reg_bits( 2884 priv, I2C_SLVT, 0x26, 0x09, 0x0f); 2885 cxd2841er_write_reg(priv, I2C_SLVT, 0x27, 0xd6); 2886 break; 2887 case 6000000: 2888 cxd2841er_set_reg_bits( 2889 priv, I2C_SLVT, 0x26, 0x08, 0x0f); 2890 cxd2841er_write_reg(priv, I2C_SLVT, 0x27, 0x6e); 2891 break; 2892 } 2893 return 0; 2894 } 2895 2896 static int cxd2841er_sleep_tc_to_active_t(struct cxd2841er_priv *priv, 2897 u32 bandwidth) 2898 { 2899 u8 data[2] = { 0x09, 0x54 }; 2900 u8 data24m[3] = {0xDC, 0x6C, 0x00}; 2901 2902 dev_dbg(&priv->i2c->dev, "%s()\n", __func__); 2903 cxd2841er_set_ts_clock_mode(priv, SYS_DVBT); 2904 /* Set SLV-X Bank : 0x00 */ 2905 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00); 2906 /* Set demod mode */ 2907 cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x01); 2908 /* Set SLV-T Bank : 0x00 */ 2909 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00); 2910 /* Enable demod clock */ 2911 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01); 2912 /* Disable RF level monitor */ 2913 cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00); 2914 /* Enable ADC clock */ 2915 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00); 2916 /* Enable ADC 1 */ 2917 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x1a); 2918 /* Enable ADC 2 & 3 */ 2919 if (priv->xtal == SONY_XTAL_41000) { 2920 data[0] = 0x0A; 2921 data[1] = 0xD4; 2922 } 2923 cxd2841er_write_regs(priv, I2C_SLVT, 0x43, data, 2); 2924 /* Enable ADC 4 */ 2925 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00); 2926 /* Set SLV-T Bank : 0x10 */ 2927 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10); 2928 /* IFAGC gain settings */ 2929 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd2, 0x0c, 0x1f); 2930 /* Set SLV-T Bank : 0x11 */ 2931 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11); 2932 /* BBAGC TARGET level setting */ 2933 cxd2841er_write_reg(priv, I2C_SLVT, 0x6a, 0x50); 2934 /* Set SLV-T Bank : 0x10 */ 2935 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10); 2936 /* ASCOT setting */ 2937 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa5, 2938 ((priv->flags & CXD2841ER_ASCOT) ? 0x01 : 0x00), 0x01); 2939 /* Set SLV-T Bank : 0x18 */ 2940 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x18); 2941 /* Pre-RS BER monitor setting */ 2942 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x36, 0x40, 0x07); 2943 /* FEC Auto Recovery setting */ 2944 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x30, 0x01, 0x01); 2945 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x31, 0x01, 0x01); 2946 /* Set SLV-T Bank : 0x00 */ 2947 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00); 2948 /* TSIF setting */ 2949 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xce, 0x01, 0x01); 2950 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcf, 0x01, 0x01); 2951 2952 if (priv->xtal == SONY_XTAL_24000) { 2953 /* Set SLV-T Bank : 0x10 */ 2954 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10); 2955 cxd2841er_write_reg(priv, I2C_SLVT, 0xBF, 0x60); 2956 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x18); 2957 cxd2841er_write_regs(priv, I2C_SLVT, 0x24, data24m, 3); 2958 } 2959 2960 cxd2841er_sleep_tc_to_active_t_band(priv, bandwidth); 2961 /* Set SLV-T Bank : 0x00 */ 2962 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00); 2963 /* Disable HiZ Setting 1 */ 2964 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x28); 2965 /* Disable HiZ Setting 2 */ 2966 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00); 2967 priv->state = STATE_ACTIVE_TC; 2968 return 0; 2969 } 2970 2971 static int cxd2841er_sleep_tc_to_active_t2(struct cxd2841er_priv *priv, 2972 u32 bandwidth) 2973 { 2974 u8 data[MAX_WRITE_REGSIZE]; 2975 2976 dev_dbg(&priv->i2c->dev, "%s()\n", __func__); 2977 cxd2841er_set_ts_clock_mode(priv, SYS_DVBT2); 2978 /* Set SLV-X Bank : 0x00 */ 2979 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00); 2980 /* Set demod mode */ 2981 cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x02); 2982 /* Set SLV-T Bank : 0x00 */ 2983 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00); 2984 /* Enable demod clock */ 2985 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01); 2986 /* Disable RF level monitor */ 2987 cxd2841er_write_reg(priv, I2C_SLVT, 0x59, 0x00); 2988 cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00); 2989 /* Enable ADC clock */ 2990 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00); 2991 /* Enable ADC 1 */ 2992 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x1a); 2993 2994 if (priv->xtal == SONY_XTAL_41000) { 2995 data[0] = 0x0A; 2996 data[1] = 0xD4; 2997 } else { 2998 data[0] = 0x09; 2999 data[1] = 0x54; 3000 } 3001 3002 cxd2841er_write_regs(priv, I2C_SLVT, 0x43, data, 2); 3003 /* Enable ADC 4 */ 3004 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00); 3005 /* Set SLV-T Bank : 0x10 */ 3006 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10); 3007 /* IFAGC gain settings */ 3008 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd2, 0x0c, 0x1f); 3009 /* Set SLV-T Bank : 0x11 */ 3010 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11); 3011 /* BBAGC TARGET level setting */ 3012 cxd2841er_write_reg(priv, I2C_SLVT, 0x6a, 0x50); 3013 /* Set SLV-T Bank : 0x10 */ 3014 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10); 3015 /* ASCOT setting */ 3016 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa5, 3017 ((priv->flags & CXD2841ER_ASCOT) ? 0x01 : 0x00), 0x01); 3018 /* Set SLV-T Bank : 0x20 */ 3019 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20); 3020 /* Acquisition optimization setting */ 3021 cxd2841er_write_reg(priv, I2C_SLVT, 0x8b, 0x3c); 3022 /* Set SLV-T Bank : 0x2b */ 3023 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2b); 3024 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x76, 0x20, 0x70); 3025 /* Set SLV-T Bank : 0x23 */ 3026 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x23); 3027 /* L1 Control setting */ 3028 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xE6, 0x00, 0x03); 3029 /* Set SLV-T Bank : 0x00 */ 3030 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00); 3031 /* TSIF setting */ 3032 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xce, 0x01, 0x01); 3033 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcf, 0x01, 0x01); 3034 /* DVB-T2 initial setting */ 3035 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x13); 3036 cxd2841er_write_reg(priv, I2C_SLVT, 0x83, 0x10); 3037 cxd2841er_write_reg(priv, I2C_SLVT, 0x86, 0x34); 3038 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x9e, 0x09, 0x0f); 3039 cxd2841er_write_reg(priv, I2C_SLVT, 0x9f, 0xd8); 3040 /* Set SLV-T Bank : 0x2a */ 3041 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2a); 3042 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x38, 0x04, 0x0f); 3043 /* Set SLV-T Bank : 0x2b */ 3044 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2b); 3045 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x11, 0x20, 0x3f); 3046 3047 /* 24MHz Xtal setting */ 3048 if (priv->xtal == SONY_XTAL_24000) { 3049 /* Set SLV-T Bank : 0x11 */ 3050 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11); 3051 data[0] = 0xEB; 3052 data[1] = 0x03; 3053 data[2] = 0x3B; 3054 cxd2841er_write_regs(priv, I2C_SLVT, 0x33, data, 3); 3055 3056 /* Set SLV-T Bank : 0x20 */ 3057 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20); 3058 data[0] = 0x5E; 3059 data[1] = 0x5E; 3060 data[2] = 0x47; 3061 cxd2841er_write_regs(priv, I2C_SLVT, 0x95, data, 3); 3062 3063 cxd2841er_write_reg(priv, I2C_SLVT, 0x99, 0x18); 3064 3065 data[0] = 0x3F; 3066 data[1] = 0xFF; 3067 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2); 3068 3069 /* Set SLV-T Bank : 0x24 */ 3070 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x24); 3071 data[0] = 0x0B; 3072 data[1] = 0x72; 3073 cxd2841er_write_regs(priv, I2C_SLVT, 0x34, data, 2); 3074 3075 data[0] = 0x93; 3076 data[1] = 0xF3; 3077 data[2] = 0x00; 3078 cxd2841er_write_regs(priv, I2C_SLVT, 0xD2, data, 3); 3079 3080 data[0] = 0x05; 3081 data[1] = 0xB8; 3082 data[2] = 0xD8; 3083 cxd2841er_write_regs(priv, I2C_SLVT, 0xDD, data, 3); 3084 3085 cxd2841er_write_reg(priv, I2C_SLVT, 0xE0, 0x00); 3086 3087 /* Set SLV-T Bank : 0x25 */ 3088 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x25); 3089 cxd2841er_write_reg(priv, I2C_SLVT, 0xED, 0x60); 3090 3091 /* Set SLV-T Bank : 0x27 */ 3092 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27); 3093 cxd2841er_write_reg(priv, I2C_SLVT, 0xFA, 0x34); 3094 3095 /* Set SLV-T Bank : 0x2B */ 3096 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2B); 3097 cxd2841er_write_reg(priv, I2C_SLVT, 0x4B, 0x2F); 3098 cxd2841er_write_reg(priv, I2C_SLVT, 0x9E, 0x0E); 3099 3100 /* Set SLV-T Bank : 0x2D */ 3101 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2D); 3102 data[0] = 0x89; 3103 data[1] = 0x89; 3104 cxd2841er_write_regs(priv, I2C_SLVT, 0x24, data, 2); 3105 3106 /* Set SLV-T Bank : 0x5E */ 3107 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x5E); 3108 data[0] = 0x24; 3109 data[1] = 0x95; 3110 cxd2841er_write_regs(priv, I2C_SLVT, 0x8C, data, 2); 3111 } 3112 3113 cxd2841er_sleep_tc_to_active_t2_band(priv, bandwidth); 3114 3115 /* Set SLV-T Bank : 0x00 */ 3116 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00); 3117 /* Disable HiZ Setting 1 */ 3118 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x28); 3119 /* Disable HiZ Setting 2 */ 3120 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00); 3121 priv->state = STATE_ACTIVE_TC; 3122 return 0; 3123 } 3124 3125 /* ISDB-Tb part */ 3126 static int cxd2841er_sleep_tc_to_active_i(struct cxd2841er_priv *priv, 3127 u32 bandwidth) 3128 { 3129 u8 data[2] = { 0x09, 0x54 }; 3130 u8 data24m[2] = {0x60, 0x00}; 3131 u8 data24m2[3] = {0xB7, 0x1B, 0x00}; 3132 3133 dev_dbg(&priv->i2c->dev, "%s()\n", __func__); 3134 cxd2841er_set_ts_clock_mode(priv, SYS_DVBT); 3135 /* Set SLV-X Bank : 0x00 */ 3136 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00); 3137 /* Set demod mode */ 3138 cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x06); 3139 /* Set SLV-T Bank : 0x00 */ 3140 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00); 3141 /* Enable demod clock */ 3142 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01); 3143 /* Enable RF level monitor */ 3144 cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x01); 3145 cxd2841er_write_reg(priv, I2C_SLVT, 0x59, 0x01); 3146 /* Enable ADC clock */ 3147 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00); 3148 /* Enable ADC 1 */ 3149 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x1a); 3150 /* xtal freq 20.5MHz or 24M */ 3151 cxd2841er_write_regs(priv, I2C_SLVT, 0x43, data, 2); 3152 /* Enable ADC 4 */ 3153 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00); 3154 /* ASCOT setting */ 3155 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa5, 3156 ((priv->flags & CXD2841ER_ASCOT) ? 0x01 : 0x00), 0x01); 3157 /* FEC Auto Recovery setting */ 3158 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x30, 0x01, 0x01); 3159 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x31, 0x00, 0x01); 3160 /* ISDB-T initial setting */ 3161 /* Set SLV-T Bank : 0x00 */ 3162 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00); 3163 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xce, 0x00, 0x01); 3164 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcf, 0x00, 0x01); 3165 /* Set SLV-T Bank : 0x10 */ 3166 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10); 3167 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x69, 0x04, 0x07); 3168 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x6B, 0x03, 0x07); 3169 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x9D, 0x50, 0xFF); 3170 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xD3, 0x06, 0x1F); 3171 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xED, 0x00, 0x01); 3172 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xE2, 0xCE, 0x80); 3173 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xF2, 0x13, 0x10); 3174 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xDE, 0x2E, 0x3F); 3175 /* Set SLV-T Bank : 0x15 */ 3176 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x15); 3177 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xDE, 0x02, 0x03); 3178 /* Set SLV-T Bank : 0x1E */ 3179 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x1E); 3180 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x73, 0x68, 0xFF); 3181 /* Set SLV-T Bank : 0x63 */ 3182 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x63); 3183 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x81, 0x00, 0x01); 3184 3185 /* for xtal 24MHz */ 3186 /* Set SLV-T Bank : 0x10 */ 3187 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10); 3188 cxd2841er_write_regs(priv, I2C_SLVT, 0xBF, data24m, 2); 3189 /* Set SLV-T Bank : 0x60 */ 3190 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60); 3191 cxd2841er_write_regs(priv, I2C_SLVT, 0xA8, data24m2, 3); 3192 3193 cxd2841er_sleep_tc_to_active_i_band(priv, bandwidth); 3194 /* Set SLV-T Bank : 0x00 */ 3195 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00); 3196 /* Disable HiZ Setting 1 */ 3197 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x28); 3198 /* Disable HiZ Setting 2 */ 3199 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00); 3200 priv->state = STATE_ACTIVE_TC; 3201 return 0; 3202 } 3203 3204 static int cxd2841er_sleep_tc_to_active_c(struct cxd2841er_priv *priv, 3205 u32 bandwidth) 3206 { 3207 u8 data[2] = { 0x09, 0x54 }; 3208 3209 dev_dbg(&priv->i2c->dev, "%s()\n", __func__); 3210 cxd2841er_set_ts_clock_mode(priv, SYS_DVBC_ANNEX_A); 3211 /* Set SLV-X Bank : 0x00 */ 3212 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00); 3213 /* Set demod mode */ 3214 cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x04); 3215 /* Set SLV-T Bank : 0x00 */ 3216 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00); 3217 /* Enable demod clock */ 3218 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01); 3219 /* Disable RF level monitor */ 3220 cxd2841er_write_reg(priv, I2C_SLVT, 0x59, 0x00); 3221 cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00); 3222 /* Enable ADC clock */ 3223 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00); 3224 /* Enable ADC 1 */ 3225 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x1a); 3226 /* xtal freq 20.5MHz */ 3227 cxd2841er_write_regs(priv, I2C_SLVT, 0x43, data, 2); 3228 /* Enable ADC 4 */ 3229 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00); 3230 /* Set SLV-T Bank : 0x10 */ 3231 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10); 3232 /* IFAGC gain settings */ 3233 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd2, 0x09, 0x1f); 3234 /* Set SLV-T Bank : 0x11 */ 3235 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11); 3236 /* BBAGC TARGET level setting */ 3237 cxd2841er_write_reg(priv, I2C_SLVT, 0x6a, 0x48); 3238 /* Set SLV-T Bank : 0x10 */ 3239 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10); 3240 /* ASCOT setting */ 3241 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa5, 3242 ((priv->flags & CXD2841ER_ASCOT) ? 0x01 : 0x00), 0x01); 3243 /* Set SLV-T Bank : 0x40 */ 3244 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40); 3245 /* Demod setting */ 3246 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xc3, 0x00, 0x04); 3247 /* Set SLV-T Bank : 0x00 */ 3248 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00); 3249 /* TSIF setting */ 3250 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xce, 0x01, 0x01); 3251 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcf, 0x01, 0x01); 3252 3253 cxd2841er_sleep_tc_to_active_c_band(priv, bandwidth); 3254 /* Set SLV-T Bank : 0x00 */ 3255 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00); 3256 /* Disable HiZ Setting 1 */ 3257 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x28); 3258 /* Disable HiZ Setting 2 */ 3259 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00); 3260 priv->state = STATE_ACTIVE_TC; 3261 return 0; 3262 } 3263 3264 static int cxd2841er_get_frontend(struct dvb_frontend *fe, 3265 struct dtv_frontend_properties *p) 3266 { 3267 enum fe_status status = 0; 3268 struct cxd2841er_priv *priv = fe->demodulator_priv; 3269 3270 dev_dbg(&priv->i2c->dev, "%s()\n", __func__); 3271 if (priv->state == STATE_ACTIVE_S) 3272 cxd2841er_read_status_s(fe, &status); 3273 else if (priv->state == STATE_ACTIVE_TC) 3274 cxd2841er_read_status_tc(fe, &status); 3275 3276 if (priv->state == STATE_ACTIVE_TC || priv->state == STATE_ACTIVE_S) 3277 cxd2841er_read_signal_strength(fe); 3278 else 3279 p->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 3280 3281 if (status & FE_HAS_LOCK) { 3282 cxd2841er_read_snr(fe); 3283 cxd2841er_read_ucblocks(fe); 3284 3285 cxd2841er_read_ber(fe); 3286 } else { 3287 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 3288 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 3289 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 3290 p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 3291 } 3292 return 0; 3293 } 3294 3295 static int cxd2841er_set_frontend_s(struct dvb_frontend *fe) 3296 { 3297 int ret = 0, i, timeout, carr_offset; 3298 enum fe_status status; 3299 struct cxd2841er_priv *priv = fe->demodulator_priv; 3300 struct dtv_frontend_properties *p = &fe->dtv_property_cache; 3301 u32 symbol_rate = p->symbol_rate/1000; 3302 3303 dev_dbg(&priv->i2c->dev, "%s(): %s frequency=%d symbol_rate=%d xtal=%d\n", 3304 __func__, 3305 (p->delivery_system == SYS_DVBS ? "DVB-S" : "DVB-S2"), 3306 p->frequency, symbol_rate, priv->xtal); 3307 3308 if (priv->flags & CXD2841ER_EARLY_TUNE) 3309 cxd2841er_tuner_set(fe); 3310 3311 switch (priv->state) { 3312 case STATE_SLEEP_S: 3313 ret = cxd2841er_sleep_s_to_active_s( 3314 priv, p->delivery_system, symbol_rate); 3315 break; 3316 case STATE_ACTIVE_S: 3317 ret = cxd2841er_retune_active(priv, p); 3318 break; 3319 default: 3320 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n", 3321 __func__, priv->state); 3322 ret = -EINVAL; 3323 goto done; 3324 } 3325 if (ret) { 3326 dev_dbg(&priv->i2c->dev, "%s(): tune failed\n", __func__); 3327 goto done; 3328 } 3329 3330 if (!(priv->flags & CXD2841ER_EARLY_TUNE)) 3331 cxd2841er_tuner_set(fe); 3332 3333 cxd2841er_tune_done(priv); 3334 timeout = ((3000000 + (symbol_rate - 1)) / symbol_rate) + 150; 3335 3336 i = 0; 3337 do { 3338 usleep_range(CXD2841ER_DVBS_POLLING_INVL*1000, 3339 (CXD2841ER_DVBS_POLLING_INVL + 2) * 1000); 3340 cxd2841er_read_status_s(fe, &status); 3341 if (status & FE_HAS_LOCK) 3342 break; 3343 i++; 3344 } while (i < timeout / CXD2841ER_DVBS_POLLING_INVL); 3345 3346 if (status & FE_HAS_LOCK) { 3347 if (cxd2841er_get_carrier_offset_s_s2( 3348 priv, &carr_offset)) { 3349 ret = -EINVAL; 3350 goto done; 3351 } 3352 dev_dbg(&priv->i2c->dev, "%s(): carrier_offset=%d\n", 3353 __func__, carr_offset); 3354 } 3355 done: 3356 /* Reset stats */ 3357 p->strength.stat[0].scale = FE_SCALE_RELATIVE; 3358 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 3359 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 3360 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 3361 p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 3362 3363 return ret; 3364 } 3365 3366 static int cxd2841er_set_frontend_tc(struct dvb_frontend *fe) 3367 { 3368 int ret = 0, timeout; 3369 enum fe_status status; 3370 struct cxd2841er_priv *priv = fe->demodulator_priv; 3371 struct dtv_frontend_properties *p = &fe->dtv_property_cache; 3372 3373 dev_dbg(&priv->i2c->dev, "%s() delivery_system=%d bandwidth_hz=%d\n", 3374 __func__, p->delivery_system, p->bandwidth_hz); 3375 3376 if (priv->flags & CXD2841ER_EARLY_TUNE) 3377 cxd2841er_tuner_set(fe); 3378 3379 /* deconfigure/put demod to sleep on delsys switch if active */ 3380 if (priv->state == STATE_ACTIVE_TC && 3381 priv->system != p->delivery_system) { 3382 dev_dbg(&priv->i2c->dev, "%s(): old_delsys=%d, new_delsys=%d -> sleep\n", 3383 __func__, priv->system, p->delivery_system); 3384 cxd2841er_sleep_tc(fe); 3385 } 3386 3387 if (p->delivery_system == SYS_DVBT) { 3388 priv->system = SYS_DVBT; 3389 switch (priv->state) { 3390 case STATE_SLEEP_TC: 3391 ret = cxd2841er_sleep_tc_to_active_t( 3392 priv, p->bandwidth_hz); 3393 break; 3394 case STATE_ACTIVE_TC: 3395 ret = cxd2841er_retune_active(priv, p); 3396 break; 3397 default: 3398 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n", 3399 __func__, priv->state); 3400 ret = -EINVAL; 3401 } 3402 } else if (p->delivery_system == SYS_DVBT2) { 3403 priv->system = SYS_DVBT2; 3404 cxd2841er_dvbt2_set_plp_config(priv, 3405 (int)(p->stream_id > 255), p->stream_id); 3406 cxd2841er_dvbt2_set_profile(priv, DVBT2_PROFILE_BASE); 3407 switch (priv->state) { 3408 case STATE_SLEEP_TC: 3409 ret = cxd2841er_sleep_tc_to_active_t2(priv, 3410 p->bandwidth_hz); 3411 break; 3412 case STATE_ACTIVE_TC: 3413 ret = cxd2841er_retune_active(priv, p); 3414 break; 3415 default: 3416 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n", 3417 __func__, priv->state); 3418 ret = -EINVAL; 3419 } 3420 } else if (p->delivery_system == SYS_ISDBT) { 3421 priv->system = SYS_ISDBT; 3422 switch (priv->state) { 3423 case STATE_SLEEP_TC: 3424 ret = cxd2841er_sleep_tc_to_active_i( 3425 priv, p->bandwidth_hz); 3426 break; 3427 case STATE_ACTIVE_TC: 3428 ret = cxd2841er_retune_active(priv, p); 3429 break; 3430 default: 3431 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n", 3432 __func__, priv->state); 3433 ret = -EINVAL; 3434 } 3435 } else if (p->delivery_system == SYS_DVBC_ANNEX_A || 3436 p->delivery_system == SYS_DVBC_ANNEX_C) { 3437 priv->system = SYS_DVBC_ANNEX_A; 3438 /* correct bandwidth */ 3439 if (p->bandwidth_hz != 6000000 && 3440 p->bandwidth_hz != 7000000 && 3441 p->bandwidth_hz != 8000000) { 3442 p->bandwidth_hz = 8000000; 3443 dev_dbg(&priv->i2c->dev, "%s(): forcing bandwidth to %d\n", 3444 __func__, p->bandwidth_hz); 3445 } 3446 3447 switch (priv->state) { 3448 case STATE_SLEEP_TC: 3449 ret = cxd2841er_sleep_tc_to_active_c( 3450 priv, p->bandwidth_hz); 3451 break; 3452 case STATE_ACTIVE_TC: 3453 ret = cxd2841er_retune_active(priv, p); 3454 break; 3455 default: 3456 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n", 3457 __func__, priv->state); 3458 ret = -EINVAL; 3459 } 3460 } else { 3461 dev_dbg(&priv->i2c->dev, 3462 "%s(): invalid delivery system %d\n", 3463 __func__, p->delivery_system); 3464 ret = -EINVAL; 3465 } 3466 if (ret) 3467 goto done; 3468 3469 if (!(priv->flags & CXD2841ER_EARLY_TUNE)) 3470 cxd2841er_tuner_set(fe); 3471 3472 cxd2841er_tune_done(priv); 3473 3474 if (priv->flags & CXD2841ER_NO_WAIT_LOCK) 3475 goto done; 3476 3477 timeout = 2500; 3478 while (timeout > 0) { 3479 ret = cxd2841er_read_status_tc(fe, &status); 3480 if (ret) 3481 goto done; 3482 if (status & FE_HAS_LOCK) 3483 break; 3484 msleep(20); 3485 timeout -= 20; 3486 } 3487 if (timeout < 0) 3488 dev_dbg(&priv->i2c->dev, 3489 "%s(): LOCK wait timeout\n", __func__); 3490 done: 3491 return ret; 3492 } 3493 3494 static int cxd2841er_tune_s(struct dvb_frontend *fe, 3495 bool re_tune, 3496 unsigned int mode_flags, 3497 unsigned int *delay, 3498 enum fe_status *status) 3499 { 3500 int ret, carrier_offset; 3501 struct cxd2841er_priv *priv = fe->demodulator_priv; 3502 struct dtv_frontend_properties *p = &fe->dtv_property_cache; 3503 3504 dev_dbg(&priv->i2c->dev, "%s() re_tune=%d\n", __func__, re_tune); 3505 if (re_tune) { 3506 ret = cxd2841er_set_frontend_s(fe); 3507 if (ret) 3508 return ret; 3509 cxd2841er_read_status_s(fe, status); 3510 if (*status & FE_HAS_LOCK) { 3511 if (cxd2841er_get_carrier_offset_s_s2( 3512 priv, &carrier_offset)) 3513 return -EINVAL; 3514 p->frequency += carrier_offset; 3515 ret = cxd2841er_set_frontend_s(fe); 3516 if (ret) 3517 return ret; 3518 } 3519 } 3520 *delay = HZ / 5; 3521 return cxd2841er_read_status_s(fe, status); 3522 } 3523 3524 static int cxd2841er_tune_tc(struct dvb_frontend *fe, 3525 bool re_tune, 3526 unsigned int mode_flags, 3527 unsigned int *delay, 3528 enum fe_status *status) 3529 { 3530 int ret, carrier_offset; 3531 struct cxd2841er_priv *priv = fe->demodulator_priv; 3532 struct dtv_frontend_properties *p = &fe->dtv_property_cache; 3533 3534 dev_dbg(&priv->i2c->dev, "%s(): re_tune %d bandwidth=%d\n", __func__, 3535 re_tune, p->bandwidth_hz); 3536 if (re_tune) { 3537 ret = cxd2841er_set_frontend_tc(fe); 3538 if (ret) 3539 return ret; 3540 cxd2841er_read_status_tc(fe, status); 3541 if (*status & FE_HAS_LOCK) { 3542 switch (priv->system) { 3543 case SYS_ISDBT: 3544 ret = cxd2841er_get_carrier_offset_i( 3545 priv, p->bandwidth_hz, 3546 &carrier_offset); 3547 if (ret) 3548 return ret; 3549 break; 3550 case SYS_DVBT: 3551 ret = cxd2841er_get_carrier_offset_t( 3552 priv, p->bandwidth_hz, 3553 &carrier_offset); 3554 if (ret) 3555 return ret; 3556 break; 3557 case SYS_DVBT2: 3558 ret = cxd2841er_get_carrier_offset_t2( 3559 priv, p->bandwidth_hz, 3560 &carrier_offset); 3561 if (ret) 3562 return ret; 3563 break; 3564 case SYS_DVBC_ANNEX_A: 3565 ret = cxd2841er_get_carrier_offset_c( 3566 priv, &carrier_offset); 3567 if (ret) 3568 return ret; 3569 break; 3570 default: 3571 dev_dbg(&priv->i2c->dev, 3572 "%s(): invalid delivery system %d\n", 3573 __func__, priv->system); 3574 return -EINVAL; 3575 } 3576 dev_dbg(&priv->i2c->dev, "%s(): carrier offset %d\n", 3577 __func__, carrier_offset); 3578 p->frequency += carrier_offset; 3579 ret = cxd2841er_set_frontend_tc(fe); 3580 if (ret) 3581 return ret; 3582 } 3583 } 3584 *delay = HZ / 5; 3585 return cxd2841er_read_status_tc(fe, status); 3586 } 3587 3588 static int cxd2841er_sleep_s(struct dvb_frontend *fe) 3589 { 3590 struct cxd2841er_priv *priv = fe->demodulator_priv; 3591 3592 dev_dbg(&priv->i2c->dev, "%s()\n", __func__); 3593 cxd2841er_active_s_to_sleep_s(fe->demodulator_priv); 3594 cxd2841er_sleep_s_to_shutdown(fe->demodulator_priv); 3595 return 0; 3596 } 3597 3598 static int cxd2841er_sleep_tc(struct dvb_frontend *fe) 3599 { 3600 struct cxd2841er_priv *priv = fe->demodulator_priv; 3601 3602 dev_dbg(&priv->i2c->dev, "%s()\n", __func__); 3603 3604 if (priv->state == STATE_ACTIVE_TC) { 3605 switch (priv->system) { 3606 case SYS_DVBT: 3607 cxd2841er_active_t_to_sleep_tc(priv); 3608 break; 3609 case SYS_DVBT2: 3610 cxd2841er_active_t2_to_sleep_tc(priv); 3611 break; 3612 case SYS_ISDBT: 3613 cxd2841er_active_i_to_sleep_tc(priv); 3614 break; 3615 case SYS_DVBC_ANNEX_A: 3616 cxd2841er_active_c_to_sleep_tc(priv); 3617 break; 3618 default: 3619 dev_warn(&priv->i2c->dev, 3620 "%s(): unknown delivery system %d\n", 3621 __func__, priv->system); 3622 } 3623 } 3624 if (priv->state != STATE_SLEEP_TC) { 3625 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n", 3626 __func__, priv->state); 3627 return -EINVAL; 3628 } 3629 return 0; 3630 } 3631 3632 static int cxd2841er_shutdown_tc(struct dvb_frontend *fe) 3633 { 3634 struct cxd2841er_priv *priv = fe->demodulator_priv; 3635 3636 dev_dbg(&priv->i2c->dev, "%s()\n", __func__); 3637 3638 if (!cxd2841er_sleep_tc(fe)) 3639 cxd2841er_sleep_tc_to_shutdown(priv); 3640 return 0; 3641 } 3642 3643 static int cxd2841er_send_burst(struct dvb_frontend *fe, 3644 enum fe_sec_mini_cmd burst) 3645 { 3646 u8 data; 3647 struct cxd2841er_priv *priv = fe->demodulator_priv; 3648 3649 dev_dbg(&priv->i2c->dev, "%s(): burst mode %s\n", __func__, 3650 (burst == SEC_MINI_A ? "A" : "B")); 3651 if (priv->state != STATE_SLEEP_S && 3652 priv->state != STATE_ACTIVE_S) { 3653 dev_err(&priv->i2c->dev, "%s(): invalid demod state %d\n", 3654 __func__, priv->state); 3655 return -EINVAL; 3656 } 3657 data = (burst == SEC_MINI_A ? 0 : 1); 3658 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xbb); 3659 cxd2841er_write_reg(priv, I2C_SLVT, 0x34, 0x01); 3660 cxd2841er_write_reg(priv, I2C_SLVT, 0x35, data); 3661 return 0; 3662 } 3663 3664 static int cxd2841er_set_tone(struct dvb_frontend *fe, 3665 enum fe_sec_tone_mode tone) 3666 { 3667 u8 data; 3668 struct cxd2841er_priv *priv = fe->demodulator_priv; 3669 3670 dev_dbg(&priv->i2c->dev, "%s(): tone %s\n", __func__, 3671 (tone == SEC_TONE_ON ? "On" : "Off")); 3672 if (priv->state != STATE_SLEEP_S && 3673 priv->state != STATE_ACTIVE_S) { 3674 dev_err(&priv->i2c->dev, "%s(): invalid demod state %d\n", 3675 __func__, priv->state); 3676 return -EINVAL; 3677 } 3678 data = (tone == SEC_TONE_ON ? 1 : 0); 3679 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xbb); 3680 cxd2841er_write_reg(priv, I2C_SLVT, 0x36, data); 3681 return 0; 3682 } 3683 3684 static int cxd2841er_send_diseqc_msg(struct dvb_frontend *fe, 3685 struct dvb_diseqc_master_cmd *cmd) 3686 { 3687 int i; 3688 u8 data[12]; 3689 struct cxd2841er_priv *priv = fe->demodulator_priv; 3690 3691 if (priv->state != STATE_SLEEP_S && 3692 priv->state != STATE_ACTIVE_S) { 3693 dev_err(&priv->i2c->dev, "%s(): invalid demod state %d\n", 3694 __func__, priv->state); 3695 return -EINVAL; 3696 } 3697 dev_dbg(&priv->i2c->dev, 3698 "%s(): cmd->len %d\n", __func__, cmd->msg_len); 3699 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xbb); 3700 /* DiDEqC enable */ 3701 cxd2841er_write_reg(priv, I2C_SLVT, 0x33, 0x01); 3702 /* cmd1 length & data */ 3703 cxd2841er_write_reg(priv, I2C_SLVT, 0x3d, cmd->msg_len); 3704 memset(data, 0, sizeof(data)); 3705 for (i = 0; i < cmd->msg_len && i < sizeof(data); i++) 3706 data[i] = cmd->msg[i]; 3707 cxd2841er_write_regs(priv, I2C_SLVT, 0x3e, data, sizeof(data)); 3708 /* repeat count for cmd1 */ 3709 cxd2841er_write_reg(priv, I2C_SLVT, 0x37, 1); 3710 /* repeat count for cmd2: always 0 */ 3711 cxd2841er_write_reg(priv, I2C_SLVT, 0x38, 0); 3712 /* start transmit */ 3713 cxd2841er_write_reg(priv, I2C_SLVT, 0x32, 0x01); 3714 /* wait for 1 sec timeout */ 3715 for (i = 0; i < 50; i++) { 3716 cxd2841er_read_reg(priv, I2C_SLVT, 0x10, data); 3717 if (!data[0]) { 3718 dev_dbg(&priv->i2c->dev, 3719 "%s(): DiSEqC cmd has been sent\n", __func__); 3720 return 0; 3721 } 3722 msleep(20); 3723 } 3724 dev_dbg(&priv->i2c->dev, 3725 "%s(): DiSEqC cmd transmit timeout\n", __func__); 3726 return -ETIMEDOUT; 3727 } 3728 3729 static void cxd2841er_release(struct dvb_frontend *fe) 3730 { 3731 struct cxd2841er_priv *priv = fe->demodulator_priv; 3732 3733 dev_dbg(&priv->i2c->dev, "%s()\n", __func__); 3734 kfree(priv); 3735 } 3736 3737 static int cxd2841er_i2c_gate_ctrl(struct dvb_frontend *fe, int enable) 3738 { 3739 struct cxd2841er_priv *priv = fe->demodulator_priv; 3740 3741 dev_dbg(&priv->i2c->dev, "%s(): enable=%d\n", __func__, enable); 3742 cxd2841er_set_reg_bits( 3743 priv, I2C_SLVX, 0x8, (enable ? 0x01 : 0x00), 0x01); 3744 return 0; 3745 } 3746 3747 static enum dvbfe_algo cxd2841er_get_algo(struct dvb_frontend *fe) 3748 { 3749 struct cxd2841er_priv *priv = fe->demodulator_priv; 3750 3751 dev_dbg(&priv->i2c->dev, "%s()\n", __func__); 3752 return DVBFE_ALGO_HW; 3753 } 3754 3755 static void cxd2841er_init_stats(struct dvb_frontend *fe) 3756 { 3757 struct dtv_frontend_properties *p = &fe->dtv_property_cache; 3758 3759 p->strength.len = 1; 3760 p->strength.stat[0].scale = FE_SCALE_RELATIVE; 3761 p->cnr.len = 1; 3762 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 3763 p->block_error.len = 1; 3764 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 3765 p->post_bit_error.len = 1; 3766 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 3767 p->post_bit_count.len = 1; 3768 p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 3769 } 3770 3771 3772 static int cxd2841er_init_s(struct dvb_frontend *fe) 3773 { 3774 struct cxd2841er_priv *priv = fe->demodulator_priv; 3775 3776 /* sanity. force demod to SHUTDOWN state */ 3777 if (priv->state == STATE_SLEEP_S) { 3778 dev_dbg(&priv->i2c->dev, "%s() forcing sleep->shutdown\n", 3779 __func__); 3780 cxd2841er_sleep_s_to_shutdown(priv); 3781 } else if (priv->state == STATE_ACTIVE_S) { 3782 dev_dbg(&priv->i2c->dev, "%s() forcing active->sleep->shutdown\n", 3783 __func__); 3784 cxd2841er_active_s_to_sleep_s(priv); 3785 cxd2841er_sleep_s_to_shutdown(priv); 3786 } 3787 3788 dev_dbg(&priv->i2c->dev, "%s()\n", __func__); 3789 cxd2841er_shutdown_to_sleep_s(priv); 3790 /* SONY_DEMOD_CONFIG_SAT_IFAGCNEG set to 1 */ 3791 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0); 3792 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xb9, 0x01, 0x01); 3793 3794 cxd2841er_init_stats(fe); 3795 3796 return 0; 3797 } 3798 3799 static int cxd2841er_init_tc(struct dvb_frontend *fe) 3800 { 3801 struct cxd2841er_priv *priv = fe->demodulator_priv; 3802 struct dtv_frontend_properties *p = &fe->dtv_property_cache; 3803 3804 dev_dbg(&priv->i2c->dev, "%s() bandwidth_hz=%d\n", 3805 __func__, p->bandwidth_hz); 3806 cxd2841er_shutdown_to_sleep_tc(priv); 3807 /* SONY_DEMOD_CONFIG_IFAGCNEG = 1 (0 for NO_AGCNEG */ 3808 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10); 3809 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcb, 3810 ((priv->flags & CXD2841ER_NO_AGCNEG) ? 0x00 : 0x40), 0x40); 3811 /* SONY_DEMOD_CONFIG_IFAGC_ADC_FS = 0 */ 3812 cxd2841er_write_reg(priv, I2C_SLVT, 0xcd, 0x50); 3813 /* SONY_DEMOD_CONFIG_PARALLEL_SEL = 1 */ 3814 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00); 3815 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xc4, 3816 ((priv->flags & CXD2841ER_TS_SERIAL) ? 0x80 : 0x00), 0x80); 3817 3818 /* clear TSCFG bits 3+4 */ 3819 if (priv->flags & CXD2841ER_TSBITS) 3820 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xc4, 0x00, 0x18); 3821 3822 cxd2841er_init_stats(fe); 3823 3824 return 0; 3825 } 3826 3827 static const struct dvb_frontend_ops cxd2841er_dvbs_s2_ops; 3828 static struct dvb_frontend_ops cxd2841er_t_c_ops; 3829 3830 static struct dvb_frontend *cxd2841er_attach(struct cxd2841er_config *cfg, 3831 struct i2c_adapter *i2c, 3832 u8 system) 3833 { 3834 u8 chip_id = 0; 3835 const char *type; 3836 const char *name; 3837 struct cxd2841er_priv *priv = NULL; 3838 3839 /* allocate memory for the internal state */ 3840 priv = kzalloc(sizeof(struct cxd2841er_priv), GFP_KERNEL); 3841 if (!priv) 3842 return NULL; 3843 priv->i2c = i2c; 3844 priv->config = cfg; 3845 priv->i2c_addr_slvx = (cfg->i2c_addr + 4) >> 1; 3846 priv->i2c_addr_slvt = (cfg->i2c_addr) >> 1; 3847 priv->xtal = cfg->xtal; 3848 priv->flags = cfg->flags; 3849 priv->frontend.demodulator_priv = priv; 3850 dev_info(&priv->i2c->dev, 3851 "%s(): I2C adapter %p SLVX addr %x SLVT addr %x\n", 3852 __func__, priv->i2c, 3853 priv->i2c_addr_slvx, priv->i2c_addr_slvt); 3854 chip_id = cxd2841er_chip_id(priv); 3855 switch (chip_id) { 3856 case CXD2837ER_CHIP_ID: 3857 snprintf(cxd2841er_t_c_ops.info.name, 128, 3858 "Sony CXD2837ER DVB-T/T2/C demodulator"); 3859 name = "CXD2837ER"; 3860 type = "C/T/T2"; 3861 break; 3862 case CXD2838ER_CHIP_ID: 3863 snprintf(cxd2841er_t_c_ops.info.name, 128, 3864 "Sony CXD2838ER ISDB-T demodulator"); 3865 cxd2841er_t_c_ops.delsys[0] = SYS_ISDBT; 3866 cxd2841er_t_c_ops.delsys[1] = SYS_UNDEFINED; 3867 cxd2841er_t_c_ops.delsys[2] = SYS_UNDEFINED; 3868 name = "CXD2838ER"; 3869 type = "ISDB-T"; 3870 break; 3871 case CXD2841ER_CHIP_ID: 3872 snprintf(cxd2841er_t_c_ops.info.name, 128, 3873 "Sony CXD2841ER DVB-T/T2/C demodulator"); 3874 name = "CXD2841ER"; 3875 type = "T/T2/C/ISDB-T"; 3876 break; 3877 case CXD2843ER_CHIP_ID: 3878 snprintf(cxd2841er_t_c_ops.info.name, 128, 3879 "Sony CXD2843ER DVB-T/T2/C/C2 demodulator"); 3880 name = "CXD2843ER"; 3881 type = "C/C2/T/T2"; 3882 break; 3883 case CXD2854ER_CHIP_ID: 3884 snprintf(cxd2841er_t_c_ops.info.name, 128, 3885 "Sony CXD2854ER DVB-T/T2/C and ISDB-T demodulator"); 3886 cxd2841er_t_c_ops.delsys[3] = SYS_ISDBT; 3887 name = "CXD2854ER"; 3888 type = "C/C2/T/T2/ISDB-T"; 3889 break; 3890 default: 3891 dev_err(&priv->i2c->dev, "%s(): invalid chip ID 0x%02x\n", 3892 __func__, chip_id); 3893 priv->frontend.demodulator_priv = NULL; 3894 kfree(priv); 3895 return NULL; 3896 } 3897 3898 /* create dvb_frontend */ 3899 if (system == SYS_DVBS) { 3900 memcpy(&priv->frontend.ops, 3901 &cxd2841er_dvbs_s2_ops, 3902 sizeof(struct dvb_frontend_ops)); 3903 type = "S/S2"; 3904 } else { 3905 memcpy(&priv->frontend.ops, 3906 &cxd2841er_t_c_ops, 3907 sizeof(struct dvb_frontend_ops)); 3908 } 3909 3910 dev_info(&priv->i2c->dev, 3911 "%s(): attaching %s DVB-%s frontend\n", 3912 __func__, name, type); 3913 dev_info(&priv->i2c->dev, "%s(): chip ID 0x%02x OK.\n", 3914 __func__, chip_id); 3915 return &priv->frontend; 3916 } 3917 3918 struct dvb_frontend *cxd2841er_attach_s(struct cxd2841er_config *cfg, 3919 struct i2c_adapter *i2c) 3920 { 3921 return cxd2841er_attach(cfg, i2c, SYS_DVBS); 3922 } 3923 EXPORT_SYMBOL(cxd2841er_attach_s); 3924 3925 struct dvb_frontend *cxd2841er_attach_t_c(struct cxd2841er_config *cfg, 3926 struct i2c_adapter *i2c) 3927 { 3928 return cxd2841er_attach(cfg, i2c, 0); 3929 } 3930 EXPORT_SYMBOL(cxd2841er_attach_t_c); 3931 3932 static const struct dvb_frontend_ops cxd2841er_dvbs_s2_ops = { 3933 .delsys = { SYS_DVBS, SYS_DVBS2 }, 3934 .info = { 3935 .name = "Sony CXD2841ER DVB-S/S2 demodulator", 3936 .frequency_min_hz = 500 * MHz, 3937 .frequency_max_hz = 2500 * MHz, 3938 .symbol_rate_min = 1000000, 3939 .symbol_rate_max = 45000000, 3940 .symbol_rate_tolerance = 500, 3941 .caps = FE_CAN_INVERSION_AUTO | 3942 FE_CAN_FEC_AUTO | 3943 FE_CAN_QPSK, 3944 }, 3945 .init = cxd2841er_init_s, 3946 .sleep = cxd2841er_sleep_s, 3947 .release = cxd2841er_release, 3948 .set_frontend = cxd2841er_set_frontend_s, 3949 .get_frontend = cxd2841er_get_frontend, 3950 .read_status = cxd2841er_read_status_s, 3951 .i2c_gate_ctrl = cxd2841er_i2c_gate_ctrl, 3952 .get_frontend_algo = cxd2841er_get_algo, 3953 .set_tone = cxd2841er_set_tone, 3954 .diseqc_send_burst = cxd2841er_send_burst, 3955 .diseqc_send_master_cmd = cxd2841er_send_diseqc_msg, 3956 .tune = cxd2841er_tune_s 3957 }; 3958 3959 static struct dvb_frontend_ops cxd2841er_t_c_ops = { 3960 .delsys = { SYS_DVBT, SYS_DVBT2, SYS_DVBC_ANNEX_A }, 3961 .info = { 3962 .name = "", /* will set in attach function */ 3963 .caps = FE_CAN_FEC_1_2 | 3964 FE_CAN_FEC_2_3 | 3965 FE_CAN_FEC_3_4 | 3966 FE_CAN_FEC_5_6 | 3967 FE_CAN_FEC_7_8 | 3968 FE_CAN_FEC_AUTO | 3969 FE_CAN_QPSK | 3970 FE_CAN_QAM_16 | 3971 FE_CAN_QAM_32 | 3972 FE_CAN_QAM_64 | 3973 FE_CAN_QAM_128 | 3974 FE_CAN_QAM_256 | 3975 FE_CAN_QAM_AUTO | 3976 FE_CAN_TRANSMISSION_MODE_AUTO | 3977 FE_CAN_GUARD_INTERVAL_AUTO | 3978 FE_CAN_HIERARCHY_AUTO | 3979 FE_CAN_MUTE_TS | 3980 FE_CAN_2G_MODULATION, 3981 .frequency_min_hz = 42 * MHz, 3982 .frequency_max_hz = 1002 * MHz, 3983 .symbol_rate_min = 870000, 3984 .symbol_rate_max = 11700000 3985 }, 3986 .init = cxd2841er_init_tc, 3987 .sleep = cxd2841er_shutdown_tc, 3988 .release = cxd2841er_release, 3989 .set_frontend = cxd2841er_set_frontend_tc, 3990 .get_frontend = cxd2841er_get_frontend, 3991 .read_status = cxd2841er_read_status_tc, 3992 .tune = cxd2841er_tune_tc, 3993 .i2c_gate_ctrl = cxd2841er_i2c_gate_ctrl, 3994 .get_frontend_algo = cxd2841er_get_algo 3995 }; 3996 3997 MODULE_DESCRIPTION("Sony CXD2837/38/41/43/54ER DVB-C/C2/T/T2/S/S2 demodulator driver"); 3998 MODULE_AUTHOR("Sergey Kozlov <serjk@netup.ru>, Abylay Ospan <aospan@netup.ru>"); 3999 MODULE_LICENSE("GPL"); 4000