1a6dc60ffSKozlov Sergey /* 2a6dc60ffSKozlov Sergey * cxd2841er.c 3a6dc60ffSKozlov Sergey * 483808c23SAbylay Ospan * Sony digital demodulator driver for 59ca1736fSAbylay Ospan * CXD2841ER - DVB-S/S2/T/T2/C/C2 69ca1736fSAbylay Ospan * CXD2854ER - DVB-S/S2/T/T2/C/C2, ISDB-T/S 7a6dc60ffSKozlov Sergey * 8a6dc60ffSKozlov Sergey * Copyright 2012 Sony Corporation 9a6dc60ffSKozlov Sergey * Copyright (C) 2014 NetUP Inc. 10a6dc60ffSKozlov Sergey * Copyright (C) 2014 Sergey Kozlov <serjk@netup.ru> 11a6dc60ffSKozlov Sergey * Copyright (C) 2014 Abylay Ospan <aospan@netup.ru> 12a6dc60ffSKozlov Sergey * 13a6dc60ffSKozlov Sergey * This program is free software; you can redistribute it and/or modify 14a6dc60ffSKozlov Sergey * it under the terms of the GNU General Public License as published by 15a6dc60ffSKozlov Sergey * the Free Software Foundation; either version 2 of the License, or 16a6dc60ffSKozlov Sergey * (at your option) any later version. 17a6dc60ffSKozlov Sergey * 18a6dc60ffSKozlov Sergey * This program is distributed in the hope that it will be useful, 19a6dc60ffSKozlov Sergey * but WITHOUT ANY WARRANTY; without even the implied warranty of 20a6dc60ffSKozlov Sergey * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21a6dc60ffSKozlov Sergey * GNU General Public License for more details. 22a6dc60ffSKozlov Sergey */ 23a6dc60ffSKozlov Sergey 24a6dc60ffSKozlov Sergey #include <linux/module.h> 25a6dc60ffSKozlov Sergey #include <linux/init.h> 26a6dc60ffSKozlov Sergey #include <linux/string.h> 27a6dc60ffSKozlov Sergey #include <linux/slab.h> 28a6dc60ffSKozlov Sergey #include <linux/bitops.h> 29a6dc60ffSKozlov Sergey #include <linux/math64.h> 30a6dc60ffSKozlov Sergey #include <linux/log2.h> 31a6dc60ffSKozlov Sergey #include <linux/dynamic_debug.h> 32a6dc60ffSKozlov Sergey 33a6dc60ffSKozlov Sergey #include "dvb_math.h" 34a6dc60ffSKozlov Sergey #include "dvb_frontend.h" 35a6dc60ffSKozlov Sergey #include "cxd2841er.h" 36a6dc60ffSKozlov Sergey #include "cxd2841er_priv.h" 37a6dc60ffSKozlov Sergey 38d13a7b67SMauro Carvalho Chehab #define MAX_WRITE_REGSIZE 16 39d13a7b67SMauro Carvalho Chehab 40a6dc60ffSKozlov Sergey enum cxd2841er_state { 41a6dc60ffSKozlov Sergey STATE_SHUTDOWN = 0, 42a6dc60ffSKozlov Sergey STATE_SLEEP_S, 43a6dc60ffSKozlov Sergey STATE_ACTIVE_S, 44a6dc60ffSKozlov Sergey STATE_SLEEP_TC, 45a6dc60ffSKozlov Sergey STATE_ACTIVE_TC 46a6dc60ffSKozlov Sergey }; 47a6dc60ffSKozlov Sergey 48a6dc60ffSKozlov Sergey struct cxd2841er_priv { 49a6dc60ffSKozlov Sergey struct dvb_frontend frontend; 50a6dc60ffSKozlov Sergey struct i2c_adapter *i2c; 51a6dc60ffSKozlov Sergey u8 i2c_addr_slvx; 52a6dc60ffSKozlov Sergey u8 i2c_addr_slvt; 53a6dc60ffSKozlov Sergey const struct cxd2841er_config *config; 54a6dc60ffSKozlov Sergey enum cxd2841er_state state; 55a6dc60ffSKozlov Sergey u8 system; 5683808c23SAbylay Ospan enum cxd2841er_xtal xtal; 573f3b48a0SAbylay Ospan enum fe_caps caps; 58a6dc60ffSKozlov Sergey }; 59a6dc60ffSKozlov Sergey 60a6dc60ffSKozlov Sergey static const struct cxd2841er_cnr_data s_cn_data[] = { 61a6dc60ffSKozlov Sergey { 0x033e, 0 }, { 0x0339, 100 }, { 0x0333, 200 }, 62a6dc60ffSKozlov Sergey { 0x032e, 300 }, { 0x0329, 400 }, { 0x0324, 500 }, 63a6dc60ffSKozlov Sergey { 0x031e, 600 }, { 0x0319, 700 }, { 0x0314, 800 }, 64a6dc60ffSKozlov Sergey { 0x030f, 900 }, { 0x030a, 1000 }, { 0x02ff, 1100 }, 65a6dc60ffSKozlov Sergey { 0x02f4, 1200 }, { 0x02e9, 1300 }, { 0x02de, 1400 }, 66a6dc60ffSKozlov Sergey { 0x02d4, 1500 }, { 0x02c9, 1600 }, { 0x02bf, 1700 }, 67a6dc60ffSKozlov Sergey { 0x02b5, 1800 }, { 0x02ab, 1900 }, { 0x02a1, 2000 }, 68a6dc60ffSKozlov Sergey { 0x029b, 2100 }, { 0x0295, 2200 }, { 0x0290, 2300 }, 69a6dc60ffSKozlov Sergey { 0x028a, 2400 }, { 0x0284, 2500 }, { 0x027f, 2600 }, 70a6dc60ffSKozlov Sergey { 0x0279, 2700 }, { 0x0274, 2800 }, { 0x026e, 2900 }, 71a6dc60ffSKozlov Sergey { 0x0269, 3000 }, { 0x0262, 3100 }, { 0x025c, 3200 }, 72a6dc60ffSKozlov Sergey { 0x0255, 3300 }, { 0x024f, 3400 }, { 0x0249, 3500 }, 73a6dc60ffSKozlov Sergey { 0x0242, 3600 }, { 0x023c, 3700 }, { 0x0236, 3800 }, 74a6dc60ffSKozlov Sergey { 0x0230, 3900 }, { 0x022a, 4000 }, { 0x0223, 4100 }, 75a6dc60ffSKozlov Sergey { 0x021c, 4200 }, { 0x0215, 4300 }, { 0x020e, 4400 }, 76a6dc60ffSKozlov Sergey { 0x0207, 4500 }, { 0x0201, 4600 }, { 0x01fa, 4700 }, 77a6dc60ffSKozlov Sergey { 0x01f4, 4800 }, { 0x01ed, 4900 }, { 0x01e7, 5000 }, 78a6dc60ffSKozlov Sergey { 0x01e0, 5100 }, { 0x01d9, 5200 }, { 0x01d2, 5300 }, 79a6dc60ffSKozlov Sergey { 0x01cb, 5400 }, { 0x01c4, 5500 }, { 0x01be, 5600 }, 80a6dc60ffSKozlov Sergey { 0x01b7, 5700 }, { 0x01b1, 5800 }, { 0x01aa, 5900 }, 81a6dc60ffSKozlov Sergey { 0x01a4, 6000 }, { 0x019d, 6100 }, { 0x0196, 6200 }, 82a6dc60ffSKozlov Sergey { 0x018f, 6300 }, { 0x0189, 6400 }, { 0x0182, 6500 }, 83a6dc60ffSKozlov Sergey { 0x017c, 6600 }, { 0x0175, 6700 }, { 0x016f, 6800 }, 84a6dc60ffSKozlov Sergey { 0x0169, 6900 }, { 0x0163, 7000 }, { 0x015c, 7100 }, 85a6dc60ffSKozlov Sergey { 0x0156, 7200 }, { 0x0150, 7300 }, { 0x014a, 7400 }, 86a6dc60ffSKozlov Sergey { 0x0144, 7500 }, { 0x013e, 7600 }, { 0x0138, 7700 }, 87a6dc60ffSKozlov Sergey { 0x0132, 7800 }, { 0x012d, 7900 }, { 0x0127, 8000 }, 88a6dc60ffSKozlov Sergey { 0x0121, 8100 }, { 0x011c, 8200 }, { 0x0116, 8300 }, 89a6dc60ffSKozlov Sergey { 0x0111, 8400 }, { 0x010b, 8500 }, { 0x0106, 8600 }, 90a6dc60ffSKozlov Sergey { 0x0101, 8700 }, { 0x00fc, 8800 }, { 0x00f7, 8900 }, 91a6dc60ffSKozlov Sergey { 0x00f2, 9000 }, { 0x00ee, 9100 }, { 0x00ea, 9200 }, 92a6dc60ffSKozlov Sergey { 0x00e6, 9300 }, { 0x00e2, 9400 }, { 0x00de, 9500 }, 93a6dc60ffSKozlov Sergey { 0x00da, 9600 }, { 0x00d7, 9700 }, { 0x00d3, 9800 }, 94a6dc60ffSKozlov Sergey { 0x00d0, 9900 }, { 0x00cc, 10000 }, { 0x00c7, 10100 }, 95a6dc60ffSKozlov Sergey { 0x00c3, 10200 }, { 0x00bf, 10300 }, { 0x00ba, 10400 }, 96a6dc60ffSKozlov Sergey { 0x00b6, 10500 }, { 0x00b2, 10600 }, { 0x00ae, 10700 }, 97a6dc60ffSKozlov Sergey { 0x00aa, 10800 }, { 0x00a7, 10900 }, { 0x00a3, 11000 }, 98a6dc60ffSKozlov Sergey { 0x009f, 11100 }, { 0x009c, 11200 }, { 0x0098, 11300 }, 99a6dc60ffSKozlov Sergey { 0x0094, 11400 }, { 0x0091, 11500 }, { 0x008e, 11600 }, 100a6dc60ffSKozlov Sergey { 0x008a, 11700 }, { 0x0087, 11800 }, { 0x0084, 11900 }, 101a6dc60ffSKozlov Sergey { 0x0081, 12000 }, { 0x007e, 12100 }, { 0x007b, 12200 }, 102a6dc60ffSKozlov Sergey { 0x0079, 12300 }, { 0x0076, 12400 }, { 0x0073, 12500 }, 103a6dc60ffSKozlov Sergey { 0x0071, 12600 }, { 0x006e, 12700 }, { 0x006c, 12800 }, 104a6dc60ffSKozlov Sergey { 0x0069, 12900 }, { 0x0067, 13000 }, { 0x0065, 13100 }, 105a6dc60ffSKozlov Sergey { 0x0062, 13200 }, { 0x0060, 13300 }, { 0x005e, 13400 }, 106a6dc60ffSKozlov Sergey { 0x005c, 13500 }, { 0x005a, 13600 }, { 0x0058, 13700 }, 107a6dc60ffSKozlov Sergey { 0x0056, 13800 }, { 0x0054, 13900 }, { 0x0052, 14000 }, 108a6dc60ffSKozlov Sergey { 0x0050, 14100 }, { 0x004e, 14200 }, { 0x004c, 14300 }, 109a6dc60ffSKozlov Sergey { 0x004b, 14400 }, { 0x0049, 14500 }, { 0x0047, 14600 }, 110a6dc60ffSKozlov Sergey { 0x0046, 14700 }, { 0x0044, 14800 }, { 0x0043, 14900 }, 111a6dc60ffSKozlov Sergey { 0x0041, 15000 }, { 0x003f, 15100 }, { 0x003e, 15200 }, 112a6dc60ffSKozlov Sergey { 0x003c, 15300 }, { 0x003b, 15400 }, { 0x003a, 15500 }, 113a6dc60ffSKozlov Sergey { 0x0037, 15700 }, { 0x0036, 15800 }, { 0x0034, 15900 }, 114a6dc60ffSKozlov Sergey { 0x0033, 16000 }, { 0x0032, 16100 }, { 0x0031, 16200 }, 115a6dc60ffSKozlov Sergey { 0x0030, 16300 }, { 0x002f, 16400 }, { 0x002e, 16500 }, 116a6dc60ffSKozlov Sergey { 0x002d, 16600 }, { 0x002c, 16700 }, { 0x002b, 16800 }, 117a6dc60ffSKozlov Sergey { 0x002a, 16900 }, { 0x0029, 17000 }, { 0x0028, 17100 }, 118a6dc60ffSKozlov Sergey { 0x0027, 17200 }, { 0x0026, 17300 }, { 0x0025, 17400 }, 119a6dc60ffSKozlov Sergey { 0x0024, 17500 }, { 0x0023, 17600 }, { 0x0022, 17800 }, 120a6dc60ffSKozlov Sergey { 0x0021, 17900 }, { 0x0020, 18000 }, { 0x001f, 18200 }, 121a6dc60ffSKozlov Sergey { 0x001e, 18300 }, { 0x001d, 18500 }, { 0x001c, 18700 }, 122a6dc60ffSKozlov Sergey { 0x001b, 18900 }, { 0x001a, 19000 }, { 0x0019, 19200 }, 123a6dc60ffSKozlov Sergey { 0x0018, 19300 }, { 0x0017, 19500 }, { 0x0016, 19700 }, 124a6dc60ffSKozlov Sergey { 0x0015, 19900 }, { 0x0014, 20000 }, 125a6dc60ffSKozlov Sergey }; 126a6dc60ffSKozlov Sergey 127a6dc60ffSKozlov Sergey static const struct cxd2841er_cnr_data s2_cn_data[] = { 128a6dc60ffSKozlov Sergey { 0x05af, 0 }, { 0x0597, 100 }, { 0x057e, 200 }, 129a6dc60ffSKozlov Sergey { 0x0567, 300 }, { 0x0550, 400 }, { 0x0539, 500 }, 130a6dc60ffSKozlov Sergey { 0x0522, 600 }, { 0x050c, 700 }, { 0x04f6, 800 }, 131a6dc60ffSKozlov Sergey { 0x04e1, 900 }, { 0x04cc, 1000 }, { 0x04b6, 1100 }, 132a6dc60ffSKozlov Sergey { 0x04a1, 1200 }, { 0x048c, 1300 }, { 0x0477, 1400 }, 133a6dc60ffSKozlov Sergey { 0x0463, 1500 }, { 0x044f, 1600 }, { 0x043c, 1700 }, 134a6dc60ffSKozlov Sergey { 0x0428, 1800 }, { 0x0416, 1900 }, { 0x0403, 2000 }, 135a6dc60ffSKozlov Sergey { 0x03ef, 2100 }, { 0x03dc, 2200 }, { 0x03c9, 2300 }, 136a6dc60ffSKozlov Sergey { 0x03b6, 2400 }, { 0x03a4, 2500 }, { 0x0392, 2600 }, 137a6dc60ffSKozlov Sergey { 0x0381, 2700 }, { 0x036f, 2800 }, { 0x035f, 2900 }, 138a6dc60ffSKozlov Sergey { 0x034e, 3000 }, { 0x033d, 3100 }, { 0x032d, 3200 }, 139a6dc60ffSKozlov Sergey { 0x031d, 3300 }, { 0x030d, 3400 }, { 0x02fd, 3500 }, 140a6dc60ffSKozlov Sergey { 0x02ee, 3600 }, { 0x02df, 3700 }, { 0x02d0, 3800 }, 141a6dc60ffSKozlov Sergey { 0x02c2, 3900 }, { 0x02b4, 4000 }, { 0x02a6, 4100 }, 142a6dc60ffSKozlov Sergey { 0x0299, 4200 }, { 0x028c, 4300 }, { 0x027f, 4400 }, 143a6dc60ffSKozlov Sergey { 0x0272, 4500 }, { 0x0265, 4600 }, { 0x0259, 4700 }, 144a6dc60ffSKozlov Sergey { 0x024d, 4800 }, { 0x0241, 4900 }, { 0x0236, 5000 }, 145a6dc60ffSKozlov Sergey { 0x022b, 5100 }, { 0x0220, 5200 }, { 0x0215, 5300 }, 146a6dc60ffSKozlov Sergey { 0x020a, 5400 }, { 0x0200, 5500 }, { 0x01f6, 5600 }, 147a6dc60ffSKozlov Sergey { 0x01ec, 5700 }, { 0x01e2, 5800 }, { 0x01d8, 5900 }, 148a6dc60ffSKozlov Sergey { 0x01cf, 6000 }, { 0x01c6, 6100 }, { 0x01bc, 6200 }, 149a6dc60ffSKozlov Sergey { 0x01b3, 6300 }, { 0x01aa, 6400 }, { 0x01a2, 6500 }, 150a6dc60ffSKozlov Sergey { 0x0199, 6600 }, { 0x0191, 6700 }, { 0x0189, 6800 }, 151a6dc60ffSKozlov Sergey { 0x0181, 6900 }, { 0x0179, 7000 }, { 0x0171, 7100 }, 152a6dc60ffSKozlov Sergey { 0x0169, 7200 }, { 0x0161, 7300 }, { 0x015a, 7400 }, 153a6dc60ffSKozlov Sergey { 0x0153, 7500 }, { 0x014b, 7600 }, { 0x0144, 7700 }, 154a6dc60ffSKozlov Sergey { 0x013d, 7800 }, { 0x0137, 7900 }, { 0x0130, 8000 }, 155a6dc60ffSKozlov Sergey { 0x012a, 8100 }, { 0x0124, 8200 }, { 0x011e, 8300 }, 156a6dc60ffSKozlov Sergey { 0x0118, 8400 }, { 0x0112, 8500 }, { 0x010c, 8600 }, 157a6dc60ffSKozlov Sergey { 0x0107, 8700 }, { 0x0101, 8800 }, { 0x00fc, 8900 }, 158a6dc60ffSKozlov Sergey { 0x00f7, 9000 }, { 0x00f2, 9100 }, { 0x00ec, 9200 }, 159a6dc60ffSKozlov Sergey { 0x00e7, 9300 }, { 0x00e2, 9400 }, { 0x00dd, 9500 }, 160a6dc60ffSKozlov Sergey { 0x00d8, 9600 }, { 0x00d4, 9700 }, { 0x00cf, 9800 }, 161a6dc60ffSKozlov Sergey { 0x00ca, 9900 }, { 0x00c6, 10000 }, { 0x00c2, 10100 }, 162a6dc60ffSKozlov Sergey { 0x00be, 10200 }, { 0x00b9, 10300 }, { 0x00b5, 10400 }, 163a6dc60ffSKozlov Sergey { 0x00b1, 10500 }, { 0x00ae, 10600 }, { 0x00aa, 10700 }, 164a6dc60ffSKozlov Sergey { 0x00a6, 10800 }, { 0x00a3, 10900 }, { 0x009f, 11000 }, 165a6dc60ffSKozlov Sergey { 0x009b, 11100 }, { 0x0098, 11200 }, { 0x0095, 11300 }, 166a6dc60ffSKozlov Sergey { 0x0091, 11400 }, { 0x008e, 11500 }, { 0x008b, 11600 }, 167a6dc60ffSKozlov Sergey { 0x0088, 11700 }, { 0x0085, 11800 }, { 0x0082, 11900 }, 168a6dc60ffSKozlov Sergey { 0x007f, 12000 }, { 0x007c, 12100 }, { 0x007a, 12200 }, 169a6dc60ffSKozlov Sergey { 0x0077, 12300 }, { 0x0074, 12400 }, { 0x0072, 12500 }, 170a6dc60ffSKozlov Sergey { 0x006f, 12600 }, { 0x006d, 12700 }, { 0x006b, 12800 }, 171a6dc60ffSKozlov Sergey { 0x0068, 12900 }, { 0x0066, 13000 }, { 0x0064, 13100 }, 172a6dc60ffSKozlov Sergey { 0x0061, 13200 }, { 0x005f, 13300 }, { 0x005d, 13400 }, 173a6dc60ffSKozlov Sergey { 0x005b, 13500 }, { 0x0059, 13600 }, { 0x0057, 13700 }, 174a6dc60ffSKozlov Sergey { 0x0055, 13800 }, { 0x0053, 13900 }, { 0x0051, 14000 }, 175a6dc60ffSKozlov Sergey { 0x004f, 14100 }, { 0x004e, 14200 }, { 0x004c, 14300 }, 176a6dc60ffSKozlov Sergey { 0x004a, 14400 }, { 0x0049, 14500 }, { 0x0047, 14600 }, 177a6dc60ffSKozlov Sergey { 0x0045, 14700 }, { 0x0044, 14800 }, { 0x0042, 14900 }, 178a6dc60ffSKozlov Sergey { 0x0041, 15000 }, { 0x003f, 15100 }, { 0x003e, 15200 }, 179a6dc60ffSKozlov Sergey { 0x003c, 15300 }, { 0x003b, 15400 }, { 0x003a, 15500 }, 180a6dc60ffSKozlov Sergey { 0x0038, 15600 }, { 0x0037, 15700 }, { 0x0036, 15800 }, 181a6dc60ffSKozlov Sergey { 0x0034, 15900 }, { 0x0033, 16000 }, { 0x0032, 16100 }, 182a6dc60ffSKozlov Sergey { 0x0031, 16200 }, { 0x0030, 16300 }, { 0x002f, 16400 }, 183a6dc60ffSKozlov Sergey { 0x002e, 16500 }, { 0x002d, 16600 }, { 0x002c, 16700 }, 184a6dc60ffSKozlov Sergey { 0x002b, 16800 }, { 0x002a, 16900 }, { 0x0029, 17000 }, 185a6dc60ffSKozlov Sergey { 0x0028, 17100 }, { 0x0027, 17200 }, { 0x0026, 17300 }, 186a6dc60ffSKozlov Sergey { 0x0025, 17400 }, { 0x0024, 17500 }, { 0x0023, 17600 }, 187a6dc60ffSKozlov Sergey { 0x0022, 17800 }, { 0x0021, 17900 }, { 0x0020, 18000 }, 188a6dc60ffSKozlov Sergey { 0x001f, 18200 }, { 0x001e, 18300 }, { 0x001d, 18500 }, 189a6dc60ffSKozlov Sergey { 0x001c, 18700 }, { 0x001b, 18900 }, { 0x001a, 19000 }, 190a6dc60ffSKozlov Sergey { 0x0019, 19200 }, { 0x0018, 19300 }, { 0x0017, 19500 }, 191a6dc60ffSKozlov Sergey { 0x0016, 19700 }, { 0x0015, 19900 }, { 0x0014, 20000 }, 192a6dc60ffSKozlov Sergey }; 193a6dc60ffSKozlov Sergey 194a6dc60ffSKozlov Sergey #define MAKE_IFFREQ_CONFIG(iffreq) ((u32)(((iffreq)/41.0)*16777216.0 + 0.5)) 19583808c23SAbylay Ospan #define MAKE_IFFREQ_CONFIG_XTAL(xtal, iffreq) ((xtal == SONY_XTAL_24000) ? \ 19683808c23SAbylay Ospan (u32)(((iffreq)/48.0)*16777216.0 + 0.5) : \ 19783808c23SAbylay Ospan (u32)(((iffreq)/41.0)*16777216.0 + 0.5)) 198a6dc60ffSKozlov Sergey 199a6dc60ffSKozlov Sergey static void cxd2841er_i2c_debug(struct cxd2841er_priv *priv, 200a6dc60ffSKozlov Sergey u8 addr, u8 reg, u8 write, 201a6dc60ffSKozlov Sergey const u8 *data, u32 len) 202a6dc60ffSKozlov Sergey { 203a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, 204a6dc60ffSKozlov Sergey "cxd2841er: I2C %s addr %02x reg 0x%02x size %d\n", 205a6dc60ffSKozlov Sergey (write == 0 ? "read" : "write"), addr, reg, len); 206a6dc60ffSKozlov Sergey print_hex_dump_bytes("cxd2841er: I2C data: ", 207a6dc60ffSKozlov Sergey DUMP_PREFIX_OFFSET, data, len); 208a6dc60ffSKozlov Sergey } 209a6dc60ffSKozlov Sergey 210a6dc60ffSKozlov Sergey static int cxd2841er_write_regs(struct cxd2841er_priv *priv, 211a6dc60ffSKozlov Sergey u8 addr, u8 reg, const u8 *data, u32 len) 212a6dc60ffSKozlov Sergey { 213a6dc60ffSKozlov Sergey int ret; 214d13a7b67SMauro Carvalho Chehab u8 buf[MAX_WRITE_REGSIZE + 1]; 215a6dc60ffSKozlov Sergey u8 i2c_addr = (addr == I2C_SLVX ? 216a6dc60ffSKozlov Sergey priv->i2c_addr_slvx : priv->i2c_addr_slvt); 217a6dc60ffSKozlov Sergey struct i2c_msg msg[1] = { 218a6dc60ffSKozlov Sergey { 219a6dc60ffSKozlov Sergey .addr = i2c_addr, 220a6dc60ffSKozlov Sergey .flags = 0, 221d13a7b67SMauro Carvalho Chehab .len = len + 1, 222a6dc60ffSKozlov Sergey .buf = buf, 223a6dc60ffSKozlov Sergey } 224a6dc60ffSKozlov Sergey }; 225a6dc60ffSKozlov Sergey 226d13a7b67SMauro Carvalho Chehab if (len + 1 >= sizeof(buf)) { 227d13a7b67SMauro Carvalho Chehab dev_warn(&priv->i2c->dev, "wr reg=%04x: len=%d is too big!\n", 228d13a7b67SMauro Carvalho Chehab reg, len + 1); 229d13a7b67SMauro Carvalho Chehab return -E2BIG; 230d13a7b67SMauro Carvalho Chehab } 231d13a7b67SMauro Carvalho Chehab 232a6dc60ffSKozlov Sergey cxd2841er_i2c_debug(priv, i2c_addr, reg, 1, data, len); 233a6dc60ffSKozlov Sergey buf[0] = reg; 234a6dc60ffSKozlov Sergey memcpy(&buf[1], data, len); 235a6dc60ffSKozlov Sergey 236a6dc60ffSKozlov Sergey ret = i2c_transfer(priv->i2c, msg, 1); 237a6dc60ffSKozlov Sergey if (ret >= 0 && ret != 1) 238a6dc60ffSKozlov Sergey ret = -EIO; 239a6dc60ffSKozlov Sergey if (ret < 0) { 240a6dc60ffSKozlov Sergey dev_warn(&priv->i2c->dev, 241a6dc60ffSKozlov Sergey "%s: i2c wr failed=%d addr=%02x reg=%02x len=%d\n", 242a6dc60ffSKozlov Sergey KBUILD_MODNAME, ret, i2c_addr, reg, len); 243a6dc60ffSKozlov Sergey return ret; 244a6dc60ffSKozlov Sergey } 245a6dc60ffSKozlov Sergey return 0; 246a6dc60ffSKozlov Sergey } 247a6dc60ffSKozlov Sergey 248a6dc60ffSKozlov Sergey static int cxd2841er_write_reg(struct cxd2841er_priv *priv, 249a6dc60ffSKozlov Sergey u8 addr, u8 reg, u8 val) 250a6dc60ffSKozlov Sergey { 251a6dc60ffSKozlov Sergey return cxd2841er_write_regs(priv, addr, reg, &val, 1); 252a6dc60ffSKozlov Sergey } 253a6dc60ffSKozlov Sergey 254a6dc60ffSKozlov Sergey static int cxd2841er_read_regs(struct cxd2841er_priv *priv, 255a6dc60ffSKozlov Sergey u8 addr, u8 reg, u8 *val, u32 len) 256a6dc60ffSKozlov Sergey { 257a6dc60ffSKozlov Sergey int ret; 258a6dc60ffSKozlov Sergey u8 i2c_addr = (addr == I2C_SLVX ? 259a6dc60ffSKozlov Sergey priv->i2c_addr_slvx : priv->i2c_addr_slvt); 260a6dc60ffSKozlov Sergey struct i2c_msg msg[2] = { 261a6dc60ffSKozlov Sergey { 262a6dc60ffSKozlov Sergey .addr = i2c_addr, 263a6dc60ffSKozlov Sergey .flags = 0, 264a6dc60ffSKozlov Sergey .len = 1, 265a6dc60ffSKozlov Sergey .buf = ®, 266a6dc60ffSKozlov Sergey }, { 267a6dc60ffSKozlov Sergey .addr = i2c_addr, 268a6dc60ffSKozlov Sergey .flags = I2C_M_RD, 269a6dc60ffSKozlov Sergey .len = len, 270a6dc60ffSKozlov Sergey .buf = val, 271a6dc60ffSKozlov Sergey } 272a6dc60ffSKozlov Sergey }; 273a6dc60ffSKozlov Sergey 274a6dc60ffSKozlov Sergey ret = i2c_transfer(priv->i2c, &msg[0], 1); 275a6dc60ffSKozlov Sergey if (ret >= 0 && ret != 1) 276a6dc60ffSKozlov Sergey ret = -EIO; 277a6dc60ffSKozlov Sergey if (ret < 0) { 278a6dc60ffSKozlov Sergey dev_warn(&priv->i2c->dev, 279a6dc60ffSKozlov Sergey "%s: i2c rw failed=%d addr=%02x reg=%02x\n", 280a6dc60ffSKozlov Sergey KBUILD_MODNAME, ret, i2c_addr, reg); 281a6dc60ffSKozlov Sergey return ret; 282a6dc60ffSKozlov Sergey } 283a6dc60ffSKozlov Sergey ret = i2c_transfer(priv->i2c, &msg[1], 1); 284a6dc60ffSKozlov Sergey if (ret >= 0 && ret != 1) 285a6dc60ffSKozlov Sergey ret = -EIO; 286a6dc60ffSKozlov Sergey if (ret < 0) { 287a6dc60ffSKozlov Sergey dev_warn(&priv->i2c->dev, 288a6dc60ffSKozlov Sergey "%s: i2c rd failed=%d addr=%02x reg=%02x\n", 289a6dc60ffSKozlov Sergey KBUILD_MODNAME, ret, i2c_addr, reg); 290a6dc60ffSKozlov Sergey return ret; 291a6dc60ffSKozlov Sergey } 2926c77161aSAbylay Ospan cxd2841er_i2c_debug(priv, i2c_addr, reg, 0, val, len); 293a6dc60ffSKozlov Sergey return 0; 294a6dc60ffSKozlov Sergey } 295a6dc60ffSKozlov Sergey 296a6dc60ffSKozlov Sergey static int cxd2841er_read_reg(struct cxd2841er_priv *priv, 297a6dc60ffSKozlov Sergey u8 addr, u8 reg, u8 *val) 298a6dc60ffSKozlov Sergey { 299a6dc60ffSKozlov Sergey return cxd2841er_read_regs(priv, addr, reg, val, 1); 300a6dc60ffSKozlov Sergey } 301a6dc60ffSKozlov Sergey 302a6dc60ffSKozlov Sergey static int cxd2841er_set_reg_bits(struct cxd2841er_priv *priv, 303a6dc60ffSKozlov Sergey u8 addr, u8 reg, u8 data, u8 mask) 304a6dc60ffSKozlov Sergey { 305a6dc60ffSKozlov Sergey int res; 306a6dc60ffSKozlov Sergey u8 rdata; 307a6dc60ffSKozlov Sergey 308a6dc60ffSKozlov Sergey if (mask != 0xff) { 309a6dc60ffSKozlov Sergey res = cxd2841er_read_reg(priv, addr, reg, &rdata); 310a6dc60ffSKozlov Sergey if (res) 311a6dc60ffSKozlov Sergey return res; 312a6dc60ffSKozlov Sergey data = ((data & mask) | (rdata & (mask ^ 0xFF))); 313a6dc60ffSKozlov Sergey } 314a6dc60ffSKozlov Sergey return cxd2841er_write_reg(priv, addr, reg, data); 315a6dc60ffSKozlov Sergey } 316a6dc60ffSKozlov Sergey 317a6dc60ffSKozlov Sergey static int cxd2841er_dvbs2_set_symbol_rate(struct cxd2841er_priv *priv, 318a6dc60ffSKozlov Sergey u32 symbol_rate) 319a6dc60ffSKozlov Sergey { 320a6dc60ffSKozlov Sergey u32 reg_value = 0; 321a6dc60ffSKozlov Sergey u8 data[3] = {0, 0, 0}; 322a6dc60ffSKozlov Sergey 323a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s()\n", __func__); 324a6dc60ffSKozlov Sergey /* 325a6dc60ffSKozlov Sergey * regValue = (symbolRateKSps * 2^14 / 1000) + 0.5 326a6dc60ffSKozlov Sergey * = ((symbolRateKSps * 2^14) + 500) / 1000 327a6dc60ffSKozlov Sergey * = ((symbolRateKSps * 16384) + 500) / 1000 328a6dc60ffSKozlov Sergey */ 329a6dc60ffSKozlov Sergey reg_value = DIV_ROUND_CLOSEST(symbol_rate * 16384, 1000); 330a6dc60ffSKozlov Sergey if ((reg_value == 0) || (reg_value > 0xFFFFF)) { 331a6dc60ffSKozlov Sergey dev_err(&priv->i2c->dev, 332a6dc60ffSKozlov Sergey "%s(): reg_value is out of range\n", __func__); 333a6dc60ffSKozlov Sergey return -EINVAL; 334a6dc60ffSKozlov Sergey } 335a6dc60ffSKozlov Sergey data[0] = (u8)((reg_value >> 16) & 0x0F); 336a6dc60ffSKozlov Sergey data[1] = (u8)((reg_value >> 8) & 0xFF); 337a6dc60ffSKozlov Sergey data[2] = (u8)(reg_value & 0xFF); 338a6dc60ffSKozlov Sergey /* Set SLV-T Bank : 0xAE */ 339a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xae); 340a6dc60ffSKozlov Sergey cxd2841er_write_regs(priv, I2C_SLVT, 0x20, data, 3); 341a6dc60ffSKozlov Sergey return 0; 342a6dc60ffSKozlov Sergey } 343a6dc60ffSKozlov Sergey 344a6dc60ffSKozlov Sergey static void cxd2841er_set_ts_clock_mode(struct cxd2841er_priv *priv, 345a6dc60ffSKozlov Sergey u8 system); 346a6dc60ffSKozlov Sergey 347a6dc60ffSKozlov Sergey static int cxd2841er_sleep_s_to_active_s(struct cxd2841er_priv *priv, 348a6dc60ffSKozlov Sergey u8 system, u32 symbol_rate) 349a6dc60ffSKozlov Sergey { 350a6dc60ffSKozlov Sergey int ret; 351a6dc60ffSKozlov Sergey u8 data[4] = { 0, 0, 0, 0 }; 352a6dc60ffSKozlov Sergey 353a6dc60ffSKozlov Sergey if (priv->state != STATE_SLEEP_S) { 354a6dc60ffSKozlov Sergey dev_err(&priv->i2c->dev, "%s(): invalid state %d\n", 355a6dc60ffSKozlov Sergey __func__, (int)priv->state); 356a6dc60ffSKozlov Sergey return -EINVAL; 357a6dc60ffSKozlov Sergey } 358a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s()\n", __func__); 359a6dc60ffSKozlov Sergey cxd2841er_set_ts_clock_mode(priv, SYS_DVBS); 360a6dc60ffSKozlov Sergey /* Set demod mode */ 361a6dc60ffSKozlov Sergey if (system == SYS_DVBS) { 362a6dc60ffSKozlov Sergey data[0] = 0x0A; 363a6dc60ffSKozlov Sergey } else if (system == SYS_DVBS2) { 364a6dc60ffSKozlov Sergey data[0] = 0x0B; 365a6dc60ffSKozlov Sergey } else { 366a6dc60ffSKozlov Sergey dev_err(&priv->i2c->dev, "%s(): invalid delsys %d\n", 367a6dc60ffSKozlov Sergey __func__, system); 368a6dc60ffSKozlov Sergey return -EINVAL; 369a6dc60ffSKozlov Sergey } 370a6dc60ffSKozlov Sergey /* Set SLV-X Bank : 0x00 */ 371a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00); 372a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVX, 0x17, data[0]); 373a6dc60ffSKozlov Sergey /* DVB-S/S2 */ 374a6dc60ffSKozlov Sergey data[0] = 0x00; 375a6dc60ffSKozlov Sergey /* Set SLV-T Bank : 0x00 */ 376a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00); 377a6dc60ffSKozlov Sergey /* Enable S/S2 auto detection 1 */ 378a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x2d, data[0]); 379a6dc60ffSKozlov Sergey /* Set SLV-T Bank : 0xAE */ 380a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xae); 381a6dc60ffSKozlov Sergey /* Enable S/S2 auto detection 2 */ 382a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x30, data[0]); 383a6dc60ffSKozlov Sergey /* Set SLV-T Bank : 0x00 */ 384a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00); 385a6dc60ffSKozlov Sergey /* Enable demod clock */ 386a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01); 387a6dc60ffSKozlov Sergey /* Enable ADC clock */ 388a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x31, 0x01); 389a6dc60ffSKozlov Sergey /* Enable ADC 1 */ 390a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x63, 0x16); 391a6dc60ffSKozlov Sergey /* Enable ADC 2 */ 392a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x65, 0x3f); 393a6dc60ffSKozlov Sergey /* Set SLV-X Bank : 0x00 */ 394a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00); 395a6dc60ffSKozlov Sergey /* Enable ADC 3 */ 396a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00); 397a6dc60ffSKozlov Sergey /* Set SLV-T Bank : 0xA3 */ 398a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa3); 399a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0xac, 0x00); 400a6dc60ffSKozlov Sergey data[0] = 0x07; 401a6dc60ffSKozlov Sergey data[1] = 0x3B; 402a6dc60ffSKozlov Sergey data[2] = 0x08; 403a6dc60ffSKozlov Sergey data[3] = 0xC5; 404a6dc60ffSKozlov Sergey /* Set SLV-T Bank : 0xAB */ 405a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xab); 406a6dc60ffSKozlov Sergey cxd2841er_write_regs(priv, I2C_SLVT, 0x98, data, 4); 407a6dc60ffSKozlov Sergey data[0] = 0x05; 408a6dc60ffSKozlov Sergey data[1] = 0x80; 409a6dc60ffSKozlov Sergey data[2] = 0x0A; 410a6dc60ffSKozlov Sergey data[3] = 0x80; 411a6dc60ffSKozlov Sergey cxd2841er_write_regs(priv, I2C_SLVT, 0xa8, data, 4); 412a6dc60ffSKozlov Sergey data[0] = 0x0C; 413a6dc60ffSKozlov Sergey data[1] = 0xCC; 414a6dc60ffSKozlov Sergey cxd2841er_write_regs(priv, I2C_SLVT, 0xc3, data, 2); 415a6dc60ffSKozlov Sergey /* Set demod parameter */ 416a6dc60ffSKozlov Sergey ret = cxd2841er_dvbs2_set_symbol_rate(priv, symbol_rate); 417a6dc60ffSKozlov Sergey if (ret != 0) 418a6dc60ffSKozlov Sergey return ret; 419a6dc60ffSKozlov Sergey /* Set SLV-T Bank : 0x00 */ 420a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00); 421a6dc60ffSKozlov Sergey /* disable Hi-Z setting 1 */ 422a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x10); 423a6dc60ffSKozlov Sergey /* disable Hi-Z setting 2 */ 424a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00); 425a6dc60ffSKozlov Sergey priv->state = STATE_ACTIVE_S; 426a6dc60ffSKozlov Sergey return 0; 427a6dc60ffSKozlov Sergey } 428a6dc60ffSKozlov Sergey 429a6dc60ffSKozlov Sergey static int cxd2841er_sleep_tc_to_active_t_band(struct cxd2841er_priv *priv, 430a6dc60ffSKozlov Sergey u32 bandwidth); 431a6dc60ffSKozlov Sergey 432a6dc60ffSKozlov Sergey static int cxd2841er_sleep_tc_to_active_t2_band(struct cxd2841er_priv *priv, 433a6dc60ffSKozlov Sergey u32 bandwidth); 434a6dc60ffSKozlov Sergey 435a6dc60ffSKozlov Sergey static int cxd2841er_sleep_tc_to_active_c_band(struct cxd2841er_priv *priv, 436a6dc60ffSKozlov Sergey u32 bandwidth); 437a6dc60ffSKozlov Sergey 43876344a3fSMauro Carvalho Chehab static int cxd2841er_sleep_tc_to_active_i(struct cxd2841er_priv *priv, 43976344a3fSMauro Carvalho Chehab u32 bandwidth); 44076344a3fSMauro Carvalho Chehab 44176344a3fSMauro Carvalho Chehab static int cxd2841er_active_i_to_sleep_tc(struct cxd2841er_priv *priv); 44276344a3fSMauro Carvalho Chehab 44376344a3fSMauro Carvalho Chehab static int cxd2841er_sleep_tc_to_shutdown(struct cxd2841er_priv *priv); 44476344a3fSMauro Carvalho Chehab 44576344a3fSMauro Carvalho Chehab static int cxd2841er_shutdown_to_sleep_tc(struct cxd2841er_priv *priv); 44676344a3fSMauro Carvalho Chehab 447a6dc60ffSKozlov Sergey static int cxd2841er_retune_active(struct cxd2841er_priv *priv, 448a6dc60ffSKozlov Sergey struct dtv_frontend_properties *p) 449a6dc60ffSKozlov Sergey { 450a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s()\n", __func__); 451a6dc60ffSKozlov Sergey if (priv->state != STATE_ACTIVE_S && 452a6dc60ffSKozlov Sergey priv->state != STATE_ACTIVE_TC) { 453a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n", 454a6dc60ffSKozlov Sergey __func__, priv->state); 455a6dc60ffSKozlov Sergey return -EINVAL; 456a6dc60ffSKozlov Sergey } 457a6dc60ffSKozlov Sergey /* Set SLV-T Bank : 0x00 */ 458a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00); 459a6dc60ffSKozlov Sergey /* disable TS output */ 460a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01); 461a6dc60ffSKozlov Sergey if (priv->state == STATE_ACTIVE_S) 462a6dc60ffSKozlov Sergey return cxd2841er_dvbs2_set_symbol_rate( 463a6dc60ffSKozlov Sergey priv, p->symbol_rate / 1000); 464a6dc60ffSKozlov Sergey else if (priv->state == STATE_ACTIVE_TC) { 465a6dc60ffSKozlov Sergey switch (priv->system) { 466a6dc60ffSKozlov Sergey case SYS_DVBT: 467a6dc60ffSKozlov Sergey return cxd2841er_sleep_tc_to_active_t_band( 468a6dc60ffSKozlov Sergey priv, p->bandwidth_hz); 469a6dc60ffSKozlov Sergey case SYS_DVBT2: 470a6dc60ffSKozlov Sergey return cxd2841er_sleep_tc_to_active_t2_band( 471a6dc60ffSKozlov Sergey priv, p->bandwidth_hz); 472a6dc60ffSKozlov Sergey case SYS_DVBC_ANNEX_A: 473a6dc60ffSKozlov Sergey return cxd2841er_sleep_tc_to_active_c_band( 47476344a3fSMauro Carvalho Chehab priv, p->bandwidth_hz); 47576344a3fSMauro Carvalho Chehab case SYS_ISDBT: 47676344a3fSMauro Carvalho Chehab cxd2841er_active_i_to_sleep_tc(priv); 47776344a3fSMauro Carvalho Chehab cxd2841er_sleep_tc_to_shutdown(priv); 47876344a3fSMauro Carvalho Chehab cxd2841er_shutdown_to_sleep_tc(priv); 47976344a3fSMauro Carvalho Chehab return cxd2841er_sleep_tc_to_active_i( 48076344a3fSMauro Carvalho Chehab priv, p->bandwidth_hz); 481a6dc60ffSKozlov Sergey } 482a6dc60ffSKozlov Sergey } 483a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n", 484a6dc60ffSKozlov Sergey __func__, priv->system); 485a6dc60ffSKozlov Sergey return -EINVAL; 486a6dc60ffSKozlov Sergey } 487a6dc60ffSKozlov Sergey 488a6dc60ffSKozlov Sergey static int cxd2841er_active_s_to_sleep_s(struct cxd2841er_priv *priv) 489a6dc60ffSKozlov Sergey { 490a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s()\n", __func__); 491a6dc60ffSKozlov Sergey if (priv->state != STATE_ACTIVE_S) { 492a6dc60ffSKozlov Sergey dev_err(&priv->i2c->dev, "%s(): invalid state %d\n", 493a6dc60ffSKozlov Sergey __func__, priv->state); 494a6dc60ffSKozlov Sergey return -EINVAL; 495a6dc60ffSKozlov Sergey } 496a6dc60ffSKozlov Sergey /* Set SLV-T Bank : 0x00 */ 497a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00); 498a6dc60ffSKozlov Sergey /* disable TS output */ 499a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01); 500a6dc60ffSKozlov Sergey /* enable Hi-Z setting 1 */ 501a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x1f); 502a6dc60ffSKozlov Sergey /* enable Hi-Z setting 2 */ 503a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff); 504a6dc60ffSKozlov Sergey /* Set SLV-X Bank : 0x00 */ 505a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00); 506a6dc60ffSKozlov Sergey /* disable ADC 1 */ 507a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01); 508a6dc60ffSKozlov Sergey /* Set SLV-T Bank : 0x00 */ 509a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00); 510a6dc60ffSKozlov Sergey /* disable ADC clock */ 511a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x31, 0x00); 512a6dc60ffSKozlov Sergey /* disable ADC 2 */ 513a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x63, 0x16); 514a6dc60ffSKozlov Sergey /* disable ADC 3 */ 515a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x65, 0x27); 516a6dc60ffSKozlov Sergey /* SADC Bias ON */ 517a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x69, 0x06); 518a6dc60ffSKozlov Sergey /* disable demod clock */ 519a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00); 520a6dc60ffSKozlov Sergey /* Set SLV-T Bank : 0xAE */ 521a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xae); 522a6dc60ffSKozlov Sergey /* disable S/S2 auto detection1 */ 523a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00); 524a6dc60ffSKozlov Sergey /* Set SLV-T Bank : 0x00 */ 525a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00); 526a6dc60ffSKozlov Sergey /* disable S/S2 auto detection2 */ 527a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x2d, 0x00); 528a6dc60ffSKozlov Sergey priv->state = STATE_SLEEP_S; 529a6dc60ffSKozlov Sergey return 0; 530a6dc60ffSKozlov Sergey } 531a6dc60ffSKozlov Sergey 532a6dc60ffSKozlov Sergey static int cxd2841er_sleep_s_to_shutdown(struct cxd2841er_priv *priv) 533a6dc60ffSKozlov Sergey { 534a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s()\n", __func__); 535a6dc60ffSKozlov Sergey if (priv->state != STATE_SLEEP_S) { 536a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s(): invalid demod state %d\n", 537a6dc60ffSKozlov Sergey __func__, priv->state); 538a6dc60ffSKozlov Sergey return -EINVAL; 539a6dc60ffSKozlov Sergey } 540a6dc60ffSKozlov Sergey /* Set SLV-T Bank : 0x00 */ 541a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00); 542a6dc60ffSKozlov Sergey /* Disable DSQOUT */ 543a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f); 544a6dc60ffSKozlov Sergey /* Disable DSQIN */ 545a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x9c, 0x00); 546a6dc60ffSKozlov Sergey /* Set SLV-X Bank : 0x00 */ 547a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00); 548a6dc60ffSKozlov Sergey /* Disable oscillator */ 549a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVX, 0x15, 0x01); 550a6dc60ffSKozlov Sergey /* Set demod mode */ 551a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x01); 552a6dc60ffSKozlov Sergey priv->state = STATE_SHUTDOWN; 553a6dc60ffSKozlov Sergey return 0; 554a6dc60ffSKozlov Sergey } 555a6dc60ffSKozlov Sergey 556a6dc60ffSKozlov Sergey static int cxd2841er_sleep_tc_to_shutdown(struct cxd2841er_priv *priv) 557a6dc60ffSKozlov Sergey { 558a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s()\n", __func__); 559a6dc60ffSKozlov Sergey if (priv->state != STATE_SLEEP_TC) { 560a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s(): invalid demod state %d\n", 561a6dc60ffSKozlov Sergey __func__, priv->state); 562a6dc60ffSKozlov Sergey return -EINVAL; 563a6dc60ffSKozlov Sergey } 564a6dc60ffSKozlov Sergey /* Set SLV-X Bank : 0x00 */ 565a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00); 566a6dc60ffSKozlov Sergey /* Disable oscillator */ 567a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVX, 0x15, 0x01); 568a6dc60ffSKozlov Sergey /* Set demod mode */ 569a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x01); 570a6dc60ffSKozlov Sergey priv->state = STATE_SHUTDOWN; 571a6dc60ffSKozlov Sergey return 0; 572a6dc60ffSKozlov Sergey } 573a6dc60ffSKozlov Sergey 574a6dc60ffSKozlov Sergey static int cxd2841er_active_t_to_sleep_tc(struct cxd2841er_priv *priv) 575a6dc60ffSKozlov Sergey { 576a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s()\n", __func__); 577a6dc60ffSKozlov Sergey if (priv->state != STATE_ACTIVE_TC) { 578a6dc60ffSKozlov Sergey dev_err(&priv->i2c->dev, "%s(): invalid state %d\n", 579a6dc60ffSKozlov Sergey __func__, priv->state); 580a6dc60ffSKozlov Sergey return -EINVAL; 581a6dc60ffSKozlov Sergey } 582a6dc60ffSKozlov Sergey /* Set SLV-T Bank : 0x00 */ 583a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00); 584a6dc60ffSKozlov Sergey /* disable TS output */ 585a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01); 586a6dc60ffSKozlov Sergey /* enable Hi-Z setting 1 */ 587a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f); 588a6dc60ffSKozlov Sergey /* enable Hi-Z setting 2 */ 589a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff); 590a6dc60ffSKozlov Sergey /* Set SLV-X Bank : 0x00 */ 591a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00); 592a6dc60ffSKozlov Sergey /* disable ADC 1 */ 593a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01); 594a6dc60ffSKozlov Sergey /* Set SLV-T Bank : 0x00 */ 595a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00); 596a6dc60ffSKozlov Sergey /* Disable ADC 2 */ 597a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a); 598a6dc60ffSKozlov Sergey /* Disable ADC 3 */ 599a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a); 600a6dc60ffSKozlov Sergey /* Disable ADC clock */ 601a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00); 602a6dc60ffSKozlov Sergey /* Disable RF level monitor */ 603a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00); 604a6dc60ffSKozlov Sergey /* Disable demod clock */ 605a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00); 606a6dc60ffSKozlov Sergey priv->state = STATE_SLEEP_TC; 607a6dc60ffSKozlov Sergey return 0; 608a6dc60ffSKozlov Sergey } 609a6dc60ffSKozlov Sergey 610a6dc60ffSKozlov Sergey static int cxd2841er_active_t2_to_sleep_tc(struct cxd2841er_priv *priv) 611a6dc60ffSKozlov Sergey { 612a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s()\n", __func__); 613a6dc60ffSKozlov Sergey if (priv->state != STATE_ACTIVE_TC) { 614a6dc60ffSKozlov Sergey dev_err(&priv->i2c->dev, "%s(): invalid state %d\n", 615a6dc60ffSKozlov Sergey __func__, priv->state); 616a6dc60ffSKozlov Sergey return -EINVAL; 617a6dc60ffSKozlov Sergey } 618a6dc60ffSKozlov Sergey /* Set SLV-T Bank : 0x00 */ 619a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00); 620a6dc60ffSKozlov Sergey /* disable TS output */ 621a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01); 622a6dc60ffSKozlov Sergey /* enable Hi-Z setting 1 */ 623a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f); 624a6dc60ffSKozlov Sergey /* enable Hi-Z setting 2 */ 625a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff); 626a6dc60ffSKozlov Sergey /* Cancel DVB-T2 setting */ 627a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x13); 628a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x83, 0x40); 629a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x86, 0x21); 630a6dc60ffSKozlov Sergey cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x9e, 0x09, 0x0f); 631a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x9f, 0xfb); 632a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2a); 633a6dc60ffSKozlov Sergey cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x38, 0x00, 0x0f); 634a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2b); 635a6dc60ffSKozlov Sergey cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x11, 0x00, 0x3f); 636a6dc60ffSKozlov Sergey /* Set SLV-X Bank : 0x00 */ 637a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00); 638a6dc60ffSKozlov Sergey /* disable ADC 1 */ 639a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01); 640a6dc60ffSKozlov Sergey /* Set SLV-T Bank : 0x00 */ 641a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00); 642a6dc60ffSKozlov Sergey /* Disable ADC 2 */ 643a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a); 644a6dc60ffSKozlov Sergey /* Disable ADC 3 */ 645a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a); 646a6dc60ffSKozlov Sergey /* Disable ADC clock */ 647a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00); 648a6dc60ffSKozlov Sergey /* Disable RF level monitor */ 649a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00); 650a6dc60ffSKozlov Sergey /* Disable demod clock */ 651a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00); 652a6dc60ffSKozlov Sergey priv->state = STATE_SLEEP_TC; 653a6dc60ffSKozlov Sergey return 0; 654a6dc60ffSKozlov Sergey } 655a6dc60ffSKozlov Sergey 656a6dc60ffSKozlov Sergey static int cxd2841er_active_c_to_sleep_tc(struct cxd2841er_priv *priv) 657a6dc60ffSKozlov Sergey { 658a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s()\n", __func__); 659a6dc60ffSKozlov Sergey if (priv->state != STATE_ACTIVE_TC) { 660a6dc60ffSKozlov Sergey dev_err(&priv->i2c->dev, "%s(): invalid state %d\n", 661a6dc60ffSKozlov Sergey __func__, priv->state); 662a6dc60ffSKozlov Sergey return -EINVAL; 663a6dc60ffSKozlov Sergey } 664a6dc60ffSKozlov Sergey /* Set SLV-T Bank : 0x00 */ 665a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00); 666a6dc60ffSKozlov Sergey /* disable TS output */ 667a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01); 668a6dc60ffSKozlov Sergey /* enable Hi-Z setting 1 */ 669a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f); 670a6dc60ffSKozlov Sergey /* enable Hi-Z setting 2 */ 671a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff); 672a6dc60ffSKozlov Sergey /* Cancel DVB-C setting */ 673a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11); 674a6dc60ffSKozlov Sergey cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa3, 0x00, 0x1f); 675a6dc60ffSKozlov Sergey /* Set SLV-X Bank : 0x00 */ 676a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00); 677a6dc60ffSKozlov Sergey /* disable ADC 1 */ 678a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01); 679a6dc60ffSKozlov Sergey /* Set SLV-T Bank : 0x00 */ 680a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00); 681a6dc60ffSKozlov Sergey /* Disable ADC 2 */ 682a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a); 683a6dc60ffSKozlov Sergey /* Disable ADC 3 */ 684a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a); 685a6dc60ffSKozlov Sergey /* Disable ADC clock */ 686a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00); 687a6dc60ffSKozlov Sergey /* Disable RF level monitor */ 688a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00); 689a6dc60ffSKozlov Sergey /* Disable demod clock */ 690a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00); 691a6dc60ffSKozlov Sergey priv->state = STATE_SLEEP_TC; 692a6dc60ffSKozlov Sergey return 0; 693a6dc60ffSKozlov Sergey } 694a6dc60ffSKozlov Sergey 69583808c23SAbylay Ospan static int cxd2841er_active_i_to_sleep_tc(struct cxd2841er_priv *priv) 69683808c23SAbylay Ospan { 69783808c23SAbylay Ospan dev_dbg(&priv->i2c->dev, "%s()\n", __func__); 69883808c23SAbylay Ospan if (priv->state != STATE_ACTIVE_TC) { 69983808c23SAbylay Ospan dev_err(&priv->i2c->dev, "%s(): invalid state %d\n", 70083808c23SAbylay Ospan __func__, priv->state); 70183808c23SAbylay Ospan return -EINVAL; 70283808c23SAbylay Ospan } 70383808c23SAbylay Ospan /* Set SLV-T Bank : 0x00 */ 70483808c23SAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00); 70583808c23SAbylay Ospan /* disable TS output */ 70683808c23SAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01); 70783808c23SAbylay Ospan /* enable Hi-Z setting 1 */ 70883808c23SAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f); 70983808c23SAbylay Ospan /* enable Hi-Z setting 2 */ 71083808c23SAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff); 71183808c23SAbylay Ospan 71283808c23SAbylay Ospan /* TODO: Cancel demod parameter */ 71383808c23SAbylay Ospan 71483808c23SAbylay Ospan /* Set SLV-X Bank : 0x00 */ 71583808c23SAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00); 71683808c23SAbylay Ospan /* disable ADC 1 */ 71783808c23SAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01); 71883808c23SAbylay Ospan /* Set SLV-T Bank : 0x00 */ 71983808c23SAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00); 72083808c23SAbylay Ospan /* Disable ADC 2 */ 72183808c23SAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a); 72283808c23SAbylay Ospan /* Disable ADC 3 */ 72383808c23SAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a); 72483808c23SAbylay Ospan /* Disable ADC clock */ 72583808c23SAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00); 72683808c23SAbylay Ospan /* Disable RF level monitor */ 72783808c23SAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00); 72883808c23SAbylay Ospan /* Disable demod clock */ 72983808c23SAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00); 73083808c23SAbylay Ospan priv->state = STATE_SLEEP_TC; 73183808c23SAbylay Ospan return 0; 73283808c23SAbylay Ospan } 73383808c23SAbylay Ospan 734a6dc60ffSKozlov Sergey static int cxd2841er_shutdown_to_sleep_s(struct cxd2841er_priv *priv) 735a6dc60ffSKozlov Sergey { 736a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s()\n", __func__); 737a6dc60ffSKozlov Sergey if (priv->state != STATE_SHUTDOWN) { 738a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s(): invalid demod state %d\n", 739a6dc60ffSKozlov Sergey __func__, priv->state); 740a6dc60ffSKozlov Sergey return -EINVAL; 741a6dc60ffSKozlov Sergey } 742a6dc60ffSKozlov Sergey /* Set SLV-X Bank : 0x00 */ 743a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00); 744a6dc60ffSKozlov Sergey /* Clear all demodulator registers */ 745a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVX, 0x02, 0x00); 746a6dc60ffSKozlov Sergey usleep_range(3000, 5000); 747a6dc60ffSKozlov Sergey /* Set SLV-X Bank : 0x00 */ 748a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00); 749a6dc60ffSKozlov Sergey /* Set demod SW reset */ 750a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVX, 0x10, 0x01); 75183808c23SAbylay Ospan 75283808c23SAbylay Ospan switch (priv->xtal) { 75383808c23SAbylay Ospan case SONY_XTAL_20500: 754a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVX, 0x14, 0x00); 75583808c23SAbylay Ospan break; 75683808c23SAbylay Ospan case SONY_XTAL_24000: 75783808c23SAbylay Ospan /* Select demod frequency */ 75883808c23SAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVX, 0x12, 0x00); 75983808c23SAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVX, 0x14, 0x03); 76083808c23SAbylay Ospan break; 76183808c23SAbylay Ospan case SONY_XTAL_41000: 76283808c23SAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVX, 0x14, 0x01); 76383808c23SAbylay Ospan break; 76483808c23SAbylay Ospan default: 76583808c23SAbylay Ospan dev_dbg(&priv->i2c->dev, "%s(): invalid demod xtal %d\n", 76683808c23SAbylay Ospan __func__, priv->xtal); 76783808c23SAbylay Ospan return -EINVAL; 76883808c23SAbylay Ospan } 76983808c23SAbylay Ospan 770a6dc60ffSKozlov Sergey /* Set demod mode */ 771a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x0a); 772a6dc60ffSKozlov Sergey /* Clear demod SW reset */ 773a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVX, 0x10, 0x00); 774a6dc60ffSKozlov Sergey usleep_range(1000, 2000); 775a6dc60ffSKozlov Sergey /* Set SLV-T Bank : 0x00 */ 776a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00); 777a6dc60ffSKozlov Sergey /* enable DSQOUT */ 778a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x1F); 779a6dc60ffSKozlov Sergey /* enable DSQIN */ 780a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x9C, 0x40); 781a6dc60ffSKozlov Sergey /* TADC Bias On */ 782a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a); 783a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a); 784a6dc60ffSKozlov Sergey /* SADC Bias On */ 785a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x63, 0x16); 786a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x65, 0x27); 787a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x69, 0x06); 788a6dc60ffSKozlov Sergey priv->state = STATE_SLEEP_S; 789a6dc60ffSKozlov Sergey return 0; 790a6dc60ffSKozlov Sergey } 791a6dc60ffSKozlov Sergey 792a6dc60ffSKozlov Sergey static int cxd2841er_shutdown_to_sleep_tc(struct cxd2841er_priv *priv) 793a6dc60ffSKozlov Sergey { 7946c77161aSAbylay Ospan u8 data = 0; 7953f3b48a0SAbylay Ospan 796a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s()\n", __func__); 797a6dc60ffSKozlov Sergey if (priv->state != STATE_SHUTDOWN) { 798a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s(): invalid demod state %d\n", 799a6dc60ffSKozlov Sergey __func__, priv->state); 800a6dc60ffSKozlov Sergey return -EINVAL; 801a6dc60ffSKozlov Sergey } 802a6dc60ffSKozlov Sergey /* Set SLV-X Bank : 0x00 */ 803a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00); 804a6dc60ffSKozlov Sergey /* Clear all demodulator registers */ 805a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVX, 0x02, 0x00); 806a6dc60ffSKozlov Sergey usleep_range(3000, 5000); 807a6dc60ffSKozlov Sergey /* Set SLV-X Bank : 0x00 */ 808a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00); 809a6dc60ffSKozlov Sergey /* Set demod SW reset */ 810a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVX, 0x10, 0x01); 8116c77161aSAbylay Ospan /* Select ADC clock mode */ 812a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVX, 0x13, 0x00); 8136c77161aSAbylay Ospan 8146c77161aSAbylay Ospan switch (priv->xtal) { 8156c77161aSAbylay Ospan case SONY_XTAL_20500: 8166c77161aSAbylay Ospan data = 0x0; 8176c77161aSAbylay Ospan break; 8186c77161aSAbylay Ospan case SONY_XTAL_24000: 8196c77161aSAbylay Ospan /* Select demod frequency */ 8206c77161aSAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVX, 0x12, 0x00); 8216c77161aSAbylay Ospan data = 0x3; 8226c77161aSAbylay Ospan break; 8236c77161aSAbylay Ospan case SONY_XTAL_41000: 8246c77161aSAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVX, 0x12, 0x00); 8256c77161aSAbylay Ospan data = 0x1; 8266c77161aSAbylay Ospan break; 8276c77161aSAbylay Ospan } 8286c77161aSAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVX, 0x14, data); 829a6dc60ffSKozlov Sergey /* Clear demod SW reset */ 830a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVX, 0x10, 0x00); 831a6dc60ffSKozlov Sergey usleep_range(1000, 2000); 832a6dc60ffSKozlov Sergey /* Set SLV-T Bank : 0x00 */ 833a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00); 834a6dc60ffSKozlov Sergey /* TADC Bias On */ 835a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a); 836a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a); 837a6dc60ffSKozlov Sergey /* SADC Bias On */ 838a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x63, 0x16); 839a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x65, 0x27); 840a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x69, 0x06); 841a6dc60ffSKozlov Sergey priv->state = STATE_SLEEP_TC; 842a6dc60ffSKozlov Sergey return 0; 843a6dc60ffSKozlov Sergey } 844a6dc60ffSKozlov Sergey 845a6dc60ffSKozlov Sergey static int cxd2841er_tune_done(struct cxd2841er_priv *priv) 846a6dc60ffSKozlov Sergey { 847a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s()\n", __func__); 848a6dc60ffSKozlov Sergey /* Set SLV-T Bank : 0x00 */ 849a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0, 0); 850a6dc60ffSKozlov Sergey /* SW Reset */ 851a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0xfe, 0x01); 852a6dc60ffSKozlov Sergey /* Enable TS output */ 853a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x00); 854a6dc60ffSKozlov Sergey return 0; 855a6dc60ffSKozlov Sergey } 856a6dc60ffSKozlov Sergey 857a6dc60ffSKozlov Sergey /* Set TS parallel mode */ 858a6dc60ffSKozlov Sergey static void cxd2841er_set_ts_clock_mode(struct cxd2841er_priv *priv, 859a6dc60ffSKozlov Sergey u8 system) 860a6dc60ffSKozlov Sergey { 861a6dc60ffSKozlov Sergey u8 serial_ts, ts_rate_ctrl_off, ts_in_off; 862a6dc60ffSKozlov Sergey 863a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s()\n", __func__); 864a6dc60ffSKozlov Sergey /* Set SLV-T Bank : 0x00 */ 865a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00); 866a6dc60ffSKozlov Sergey cxd2841er_read_reg(priv, I2C_SLVT, 0xc4, &serial_ts); 867a6dc60ffSKozlov Sergey cxd2841er_read_reg(priv, I2C_SLVT, 0xd3, &ts_rate_ctrl_off); 868a6dc60ffSKozlov Sergey cxd2841er_read_reg(priv, I2C_SLVT, 0xde, &ts_in_off); 869a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s(): ser_ts=0x%02x rate_ctrl_off=0x%02x in_off=0x%02x\n", 870a6dc60ffSKozlov Sergey __func__, serial_ts, ts_rate_ctrl_off, ts_in_off); 871a6dc60ffSKozlov Sergey 872a6dc60ffSKozlov Sergey /* 873a6dc60ffSKozlov Sergey * slave Bank Addr Bit default Name 874a6dc60ffSKozlov Sergey * <SLV-T> 00h D9h [7:0] 8'h08 OTSCKPERIOD 875a6dc60ffSKozlov Sergey */ 876a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0xd9, 0x08); 877a6dc60ffSKozlov Sergey /* 878a6dc60ffSKozlov Sergey * Disable TS IF Clock 879a6dc60ffSKozlov Sergey * slave Bank Addr Bit default Name 880a6dc60ffSKozlov Sergey * <SLV-T> 00h 32h [0] 1'b1 OREG_CK_TSIF_EN 881a6dc60ffSKozlov Sergey */ 882a6dc60ffSKozlov Sergey cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x32, 0x00, 0x01); 883a6dc60ffSKozlov Sergey /* 884a6dc60ffSKozlov Sergey * slave Bank Addr Bit default Name 885a6dc60ffSKozlov Sergey * <SLV-T> 00h 33h [1:0] 2'b01 OREG_CKSEL_TSIF 886a6dc60ffSKozlov Sergey */ 887a6dc60ffSKozlov Sergey cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x33, 0x00, 0x03); 888a6dc60ffSKozlov Sergey /* 889a6dc60ffSKozlov Sergey * Enable TS IF Clock 890a6dc60ffSKozlov Sergey * slave Bank Addr Bit default Name 891a6dc60ffSKozlov Sergey * <SLV-T> 00h 32h [0] 1'b1 OREG_CK_TSIF_EN 892a6dc60ffSKozlov Sergey */ 893a6dc60ffSKozlov Sergey cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x32, 0x01, 0x01); 894a6dc60ffSKozlov Sergey 895a6dc60ffSKozlov Sergey if (system == SYS_DVBT) { 896a6dc60ffSKozlov Sergey /* Enable parity period for DVB-T */ 897a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10); 898a6dc60ffSKozlov Sergey cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x66, 0x01, 0x01); 899a6dc60ffSKozlov Sergey } else if (system == SYS_DVBC_ANNEX_A) { 900a6dc60ffSKozlov Sergey /* Enable parity period for DVB-C */ 901a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40); 902a6dc60ffSKozlov Sergey cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x66, 0x01, 0x01); 903a6dc60ffSKozlov Sergey } 904a6dc60ffSKozlov Sergey } 905a6dc60ffSKozlov Sergey 906a6dc60ffSKozlov Sergey static u8 cxd2841er_chip_id(struct cxd2841er_priv *priv) 907a6dc60ffSKozlov Sergey { 90883808c23SAbylay Ospan u8 chip_id = 0; 909a6dc60ffSKozlov Sergey 910a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s()\n", __func__); 91183808c23SAbylay Ospan if (cxd2841er_write_reg(priv, I2C_SLVT, 0, 0) == 0) 912a6dc60ffSKozlov Sergey cxd2841er_read_reg(priv, I2C_SLVT, 0xfd, &chip_id); 91383808c23SAbylay Ospan else if (cxd2841er_write_reg(priv, I2C_SLVX, 0, 0) == 0) 91483808c23SAbylay Ospan cxd2841er_read_reg(priv, I2C_SLVX, 0xfd, &chip_id); 91583808c23SAbylay Ospan 916a6dc60ffSKozlov Sergey return chip_id; 917a6dc60ffSKozlov Sergey } 918a6dc60ffSKozlov Sergey 919a6dc60ffSKozlov Sergey static int cxd2841er_read_status_s(struct dvb_frontend *fe, 920a6dc60ffSKozlov Sergey enum fe_status *status) 921a6dc60ffSKozlov Sergey { 922a6dc60ffSKozlov Sergey u8 reg = 0; 923a6dc60ffSKozlov Sergey struct cxd2841er_priv *priv = fe->demodulator_priv; 924a6dc60ffSKozlov Sergey 925a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s()\n", __func__); 926a6dc60ffSKozlov Sergey *status = 0; 927a6dc60ffSKozlov Sergey if (priv->state != STATE_ACTIVE_S) { 928a6dc60ffSKozlov Sergey dev_err(&priv->i2c->dev, "%s(): invalid state %d\n", 929a6dc60ffSKozlov Sergey __func__, priv->state); 930a6dc60ffSKozlov Sergey return -EINVAL; 931a6dc60ffSKozlov Sergey } 932a6dc60ffSKozlov Sergey /* Set SLV-T Bank : 0xA0 */ 933a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0); 934a6dc60ffSKozlov Sergey /* 935a6dc60ffSKozlov Sergey * slave Bank Addr Bit Signal name 936a6dc60ffSKozlov Sergey * <SLV-T> A0h 11h [2] ITSLOCK 937a6dc60ffSKozlov Sergey */ 938a6dc60ffSKozlov Sergey cxd2841er_read_reg(priv, I2C_SLVT, 0x11, ®); 939a6dc60ffSKozlov Sergey if (reg & 0x04) { 940a6dc60ffSKozlov Sergey *status = FE_HAS_SIGNAL 941a6dc60ffSKozlov Sergey | FE_HAS_CARRIER 942a6dc60ffSKozlov Sergey | FE_HAS_VITERBI 943a6dc60ffSKozlov Sergey | FE_HAS_SYNC 944a6dc60ffSKozlov Sergey | FE_HAS_LOCK; 945a6dc60ffSKozlov Sergey } 946a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s(): result 0x%x\n", __func__, *status); 947a6dc60ffSKozlov Sergey return 0; 948a6dc60ffSKozlov Sergey } 949a6dc60ffSKozlov Sergey 950a6dc60ffSKozlov Sergey static int cxd2841er_read_status_t_t2(struct cxd2841er_priv *priv, 951a6dc60ffSKozlov Sergey u8 *sync, u8 *tslock, u8 *unlock) 952a6dc60ffSKozlov Sergey { 953a6dc60ffSKozlov Sergey u8 data = 0; 954a6dc60ffSKozlov Sergey 955a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s()\n", __func__); 956a6dc60ffSKozlov Sergey if (priv->state != STATE_ACTIVE_TC) 957a6dc60ffSKozlov Sergey return -EINVAL; 958a6dc60ffSKozlov Sergey if (priv->system == SYS_DVBT) { 959a6dc60ffSKozlov Sergey /* Set SLV-T Bank : 0x10 */ 960a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10); 961a6dc60ffSKozlov Sergey } else { 962a6dc60ffSKozlov Sergey /* Set SLV-T Bank : 0x20 */ 963a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20); 964a6dc60ffSKozlov Sergey } 965a6dc60ffSKozlov Sergey cxd2841er_read_reg(priv, I2C_SLVT, 0x10, &data); 966a6dc60ffSKozlov Sergey if ((data & 0x07) == 0x07) { 967a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, 968a6dc60ffSKozlov Sergey "%s(): invalid hardware state detected\n", __func__); 969a6dc60ffSKozlov Sergey *sync = 0; 970a6dc60ffSKozlov Sergey *tslock = 0; 971a6dc60ffSKozlov Sergey *unlock = 0; 972a6dc60ffSKozlov Sergey } else { 973a6dc60ffSKozlov Sergey *sync = ((data & 0x07) == 0x6 ? 1 : 0); 974a6dc60ffSKozlov Sergey *tslock = ((data & 0x20) ? 1 : 0); 975a6dc60ffSKozlov Sergey *unlock = ((data & 0x10) ? 1 : 0); 976a6dc60ffSKozlov Sergey } 977a6dc60ffSKozlov Sergey return 0; 978a6dc60ffSKozlov Sergey } 979a6dc60ffSKozlov Sergey 980a6dc60ffSKozlov Sergey static int cxd2841er_read_status_c(struct cxd2841er_priv *priv, u8 *tslock) 981a6dc60ffSKozlov Sergey { 982a6dc60ffSKozlov Sergey u8 data; 983a6dc60ffSKozlov Sergey 984a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s()\n", __func__); 985a6dc60ffSKozlov Sergey if (priv->state != STATE_ACTIVE_TC) 986a6dc60ffSKozlov Sergey return -EINVAL; 987a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40); 988a6dc60ffSKozlov Sergey cxd2841er_read_reg(priv, I2C_SLVT, 0x88, &data); 989a6dc60ffSKozlov Sergey if ((data & 0x01) == 0) { 990a6dc60ffSKozlov Sergey *tslock = 0; 991a6dc60ffSKozlov Sergey } else { 992a6dc60ffSKozlov Sergey cxd2841er_read_reg(priv, I2C_SLVT, 0x10, &data); 993a6dc60ffSKozlov Sergey *tslock = ((data & 0x20) ? 1 : 0); 994a6dc60ffSKozlov Sergey } 995a6dc60ffSKozlov Sergey return 0; 996a6dc60ffSKozlov Sergey } 997a6dc60ffSKozlov Sergey 99883808c23SAbylay Ospan static int cxd2841er_read_status_i(struct cxd2841er_priv *priv, 99983808c23SAbylay Ospan u8 *sync, u8 *tslock, u8 *unlock) 100083808c23SAbylay Ospan { 100183808c23SAbylay Ospan u8 data = 0; 100283808c23SAbylay Ospan 100383808c23SAbylay Ospan dev_dbg(&priv->i2c->dev, "%s()\n", __func__); 100483808c23SAbylay Ospan if (priv->state != STATE_ACTIVE_TC) 100583808c23SAbylay Ospan return -EINVAL; 100683808c23SAbylay Ospan /* Set SLV-T Bank : 0x60 */ 100783808c23SAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60); 100883808c23SAbylay Ospan cxd2841er_read_reg(priv, I2C_SLVT, 0x10, &data); 100983808c23SAbylay Ospan dev_dbg(&priv->i2c->dev, 101083808c23SAbylay Ospan "%s(): lock=0x%x\n", __func__, data); 101183808c23SAbylay Ospan *sync = ((data & 0x02) ? 1 : 0); 101283808c23SAbylay Ospan *tslock = ((data & 0x01) ? 1 : 0); 101383808c23SAbylay Ospan *unlock = ((data & 0x10) ? 1 : 0); 101483808c23SAbylay Ospan return 0; 101583808c23SAbylay Ospan } 101683808c23SAbylay Ospan 1017a6dc60ffSKozlov Sergey static int cxd2841er_read_status_tc(struct dvb_frontend *fe, 1018a6dc60ffSKozlov Sergey enum fe_status *status) 1019a6dc60ffSKozlov Sergey { 1020a6dc60ffSKozlov Sergey int ret = 0; 1021a6dc60ffSKozlov Sergey u8 sync = 0; 1022a6dc60ffSKozlov Sergey u8 tslock = 0; 1023a6dc60ffSKozlov Sergey u8 unlock = 0; 1024a6dc60ffSKozlov Sergey struct cxd2841er_priv *priv = fe->demodulator_priv; 1025a6dc60ffSKozlov Sergey 1026a6dc60ffSKozlov Sergey *status = 0; 1027a6dc60ffSKozlov Sergey if (priv->state == STATE_ACTIVE_TC) { 1028a6dc60ffSKozlov Sergey if (priv->system == SYS_DVBT || priv->system == SYS_DVBT2) { 1029a6dc60ffSKozlov Sergey ret = cxd2841er_read_status_t_t2( 1030a6dc60ffSKozlov Sergey priv, &sync, &tslock, &unlock); 1031a6dc60ffSKozlov Sergey if (ret) 1032a6dc60ffSKozlov Sergey goto done; 1033a6dc60ffSKozlov Sergey if (unlock) 1034a6dc60ffSKozlov Sergey goto done; 1035a6dc60ffSKozlov Sergey if (sync) 1036a6dc60ffSKozlov Sergey *status = FE_HAS_SIGNAL | 1037a6dc60ffSKozlov Sergey FE_HAS_CARRIER | 1038a6dc60ffSKozlov Sergey FE_HAS_VITERBI | 1039a6dc60ffSKozlov Sergey FE_HAS_SYNC; 1040a6dc60ffSKozlov Sergey if (tslock) 1041a6dc60ffSKozlov Sergey *status |= FE_HAS_LOCK; 104283808c23SAbylay Ospan } else if (priv->system == SYS_ISDBT) { 104383808c23SAbylay Ospan ret = cxd2841er_read_status_i( 104483808c23SAbylay Ospan priv, &sync, &tslock, &unlock); 104583808c23SAbylay Ospan if (ret) 104683808c23SAbylay Ospan goto done; 104783808c23SAbylay Ospan if (unlock) 104883808c23SAbylay Ospan goto done; 104983808c23SAbylay Ospan if (sync) 105083808c23SAbylay Ospan *status = FE_HAS_SIGNAL | 105183808c23SAbylay Ospan FE_HAS_CARRIER | 105283808c23SAbylay Ospan FE_HAS_VITERBI | 105383808c23SAbylay Ospan FE_HAS_SYNC; 105483808c23SAbylay Ospan if (tslock) 105583808c23SAbylay Ospan *status |= FE_HAS_LOCK; 1056a6dc60ffSKozlov Sergey } else if (priv->system == SYS_DVBC_ANNEX_A) { 1057a6dc60ffSKozlov Sergey ret = cxd2841er_read_status_c(priv, &tslock); 1058a6dc60ffSKozlov Sergey if (ret) 1059a6dc60ffSKozlov Sergey goto done; 1060a6dc60ffSKozlov Sergey if (tslock) 1061a6dc60ffSKozlov Sergey *status = FE_HAS_SIGNAL | 1062a6dc60ffSKozlov Sergey FE_HAS_CARRIER | 1063a6dc60ffSKozlov Sergey FE_HAS_VITERBI | 1064a6dc60ffSKozlov Sergey FE_HAS_SYNC | 1065a6dc60ffSKozlov Sergey FE_HAS_LOCK; 1066a6dc60ffSKozlov Sergey } 1067a6dc60ffSKozlov Sergey } 1068a6dc60ffSKozlov Sergey done: 1069a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s(): status 0x%x\n", __func__, *status); 1070a6dc60ffSKozlov Sergey return ret; 1071a6dc60ffSKozlov Sergey } 1072a6dc60ffSKozlov Sergey 1073a6dc60ffSKozlov Sergey static int cxd2841er_get_carrier_offset_s_s2(struct cxd2841er_priv *priv, 1074a6dc60ffSKozlov Sergey int *offset) 1075a6dc60ffSKozlov Sergey { 1076a6dc60ffSKozlov Sergey u8 data[3]; 1077a6dc60ffSKozlov Sergey u8 is_hs_mode; 1078a6dc60ffSKozlov Sergey s32 cfrl_ctrlval; 1079a6dc60ffSKozlov Sergey s32 temp_div, temp_q, temp_r; 1080a6dc60ffSKozlov Sergey 1081a6dc60ffSKozlov Sergey if (priv->state != STATE_ACTIVE_S) { 1082a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n", 1083a6dc60ffSKozlov Sergey __func__, priv->state); 1084a6dc60ffSKozlov Sergey return -EINVAL; 1085a6dc60ffSKozlov Sergey } 1086a6dc60ffSKozlov Sergey /* 1087a6dc60ffSKozlov Sergey * Get High Sampling Rate mode 1088a6dc60ffSKozlov Sergey * slave Bank Addr Bit Signal name 1089a6dc60ffSKozlov Sergey * <SLV-T> A0h 10h [0] ITRL_LOCK 1090a6dc60ffSKozlov Sergey */ 1091a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0); 1092a6dc60ffSKozlov Sergey cxd2841er_read_reg(priv, I2C_SLVT, 0x10, &data[0]); 1093a6dc60ffSKozlov Sergey if (data[0] & 0x01) { 1094a6dc60ffSKozlov Sergey /* 1095a6dc60ffSKozlov Sergey * slave Bank Addr Bit Signal name 1096a6dc60ffSKozlov Sergey * <SLV-T> A0h 50h [4] IHSMODE 1097a6dc60ffSKozlov Sergey */ 1098a6dc60ffSKozlov Sergey cxd2841er_read_reg(priv, I2C_SLVT, 0x50, &data[0]); 1099a6dc60ffSKozlov Sergey is_hs_mode = (data[0] & 0x10 ? 1 : 0); 1100a6dc60ffSKozlov Sergey } else { 1101a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, 1102a6dc60ffSKozlov Sergey "%s(): unable to detect sampling rate mode\n", 1103a6dc60ffSKozlov Sergey __func__); 1104a6dc60ffSKozlov Sergey return -EINVAL; 1105a6dc60ffSKozlov Sergey } 1106a6dc60ffSKozlov Sergey /* 1107a6dc60ffSKozlov Sergey * slave Bank Addr Bit Signal name 1108a6dc60ffSKozlov Sergey * <SLV-T> A0h 45h [4:0] ICFRL_CTRLVAL[20:16] 1109a6dc60ffSKozlov Sergey * <SLV-T> A0h 46h [7:0] ICFRL_CTRLVAL[15:8] 1110a6dc60ffSKozlov Sergey * <SLV-T> A0h 47h [7:0] ICFRL_CTRLVAL[7:0] 1111a6dc60ffSKozlov Sergey */ 1112a6dc60ffSKozlov Sergey cxd2841er_read_regs(priv, I2C_SLVT, 0x45, data, 3); 1113a6dc60ffSKozlov Sergey cfrl_ctrlval = sign_extend32((((u32)data[0] & 0x1F) << 16) | 1114a6dc60ffSKozlov Sergey (((u32)data[1] & 0xFF) << 8) | 1115a6dc60ffSKozlov Sergey ((u32)data[2] & 0xFF), 20); 1116a6dc60ffSKozlov Sergey temp_div = (is_hs_mode ? 1048576 : 1572864); 1117a6dc60ffSKozlov Sergey if (cfrl_ctrlval > 0) { 1118a6dc60ffSKozlov Sergey temp_q = div_s64_rem(97375LL * cfrl_ctrlval, 1119a6dc60ffSKozlov Sergey temp_div, &temp_r); 1120a6dc60ffSKozlov Sergey } else { 1121a6dc60ffSKozlov Sergey temp_q = div_s64_rem(-97375LL * cfrl_ctrlval, 1122a6dc60ffSKozlov Sergey temp_div, &temp_r); 1123a6dc60ffSKozlov Sergey } 1124a6dc60ffSKozlov Sergey if (temp_r >= temp_div / 2) 1125a6dc60ffSKozlov Sergey temp_q++; 1126a6dc60ffSKozlov Sergey if (cfrl_ctrlval > 0) 1127a6dc60ffSKozlov Sergey temp_q *= -1; 1128a6dc60ffSKozlov Sergey *offset = temp_q; 1129a6dc60ffSKozlov Sergey return 0; 1130a6dc60ffSKozlov Sergey } 1131a6dc60ffSKozlov Sergey 113276344a3fSMauro Carvalho Chehab static int cxd2841er_get_carrier_offset_i(struct cxd2841er_priv *priv, 113376344a3fSMauro Carvalho Chehab u32 bandwidth, int *offset) 113476344a3fSMauro Carvalho Chehab { 113576344a3fSMauro Carvalho Chehab u8 data[4]; 113676344a3fSMauro Carvalho Chehab 113776344a3fSMauro Carvalho Chehab dev_dbg(&priv->i2c->dev, "%s()\n", __func__); 113876344a3fSMauro Carvalho Chehab if (priv->state != STATE_ACTIVE_TC) { 113976344a3fSMauro Carvalho Chehab dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n", 114076344a3fSMauro Carvalho Chehab __func__, priv->state); 114176344a3fSMauro Carvalho Chehab return -EINVAL; 114276344a3fSMauro Carvalho Chehab } 114376344a3fSMauro Carvalho Chehab if (priv->system != SYS_ISDBT) { 114476344a3fSMauro Carvalho Chehab dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n", 114576344a3fSMauro Carvalho Chehab __func__, priv->system); 114676344a3fSMauro Carvalho Chehab return -EINVAL; 114776344a3fSMauro Carvalho Chehab } 114876344a3fSMauro Carvalho Chehab cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60); 114976344a3fSMauro Carvalho Chehab cxd2841er_read_regs(priv, I2C_SLVT, 0x4c, data, sizeof(data)); 115076344a3fSMauro Carvalho Chehab *offset = -1 * sign_extend32( 115176344a3fSMauro Carvalho Chehab ((u32)(data[0] & 0x1F) << 24) | ((u32)data[1] << 16) | 115276344a3fSMauro Carvalho Chehab ((u32)data[2] << 8) | (u32)data[3], 29); 115376344a3fSMauro Carvalho Chehab 115476344a3fSMauro Carvalho Chehab switch (bandwidth) { 115576344a3fSMauro Carvalho Chehab case 6000000: 115676344a3fSMauro Carvalho Chehab *offset = -1 * ((*offset) * 8/264); 115776344a3fSMauro Carvalho Chehab break; 115876344a3fSMauro Carvalho Chehab case 7000000: 115976344a3fSMauro Carvalho Chehab *offset = -1 * ((*offset) * 8/231); 116076344a3fSMauro Carvalho Chehab break; 116176344a3fSMauro Carvalho Chehab case 8000000: 116276344a3fSMauro Carvalho Chehab *offset = -1 * ((*offset) * 8/198); 116376344a3fSMauro Carvalho Chehab break; 116476344a3fSMauro Carvalho Chehab default: 116576344a3fSMauro Carvalho Chehab dev_dbg(&priv->i2c->dev, "%s(): invalid bandwidth %d\n", 116676344a3fSMauro Carvalho Chehab __func__, bandwidth); 116776344a3fSMauro Carvalho Chehab return -EINVAL; 116876344a3fSMauro Carvalho Chehab } 116976344a3fSMauro Carvalho Chehab 117076344a3fSMauro Carvalho Chehab dev_dbg(&priv->i2c->dev, "%s(): bandwidth %d offset %d\n", 117176344a3fSMauro Carvalho Chehab __func__, bandwidth, *offset); 117276344a3fSMauro Carvalho Chehab 117376344a3fSMauro Carvalho Chehab return 0; 117476344a3fSMauro Carvalho Chehab } 117576344a3fSMauro Carvalho Chehab 1176c5ea46daSAbylay Ospan static int cxd2841er_get_carrier_offset_t(struct cxd2841er_priv *priv, 1177c5ea46daSAbylay Ospan u32 bandwidth, int *offset) 1178c5ea46daSAbylay Ospan { 1179c5ea46daSAbylay Ospan u8 data[4]; 1180c5ea46daSAbylay Ospan 1181c5ea46daSAbylay Ospan dev_dbg(&priv->i2c->dev, "%s()\n", __func__); 1182c5ea46daSAbylay Ospan if (priv->state != STATE_ACTIVE_TC) { 1183c5ea46daSAbylay Ospan dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n", 1184c5ea46daSAbylay Ospan __func__, priv->state); 1185c5ea46daSAbylay Ospan return -EINVAL; 1186c5ea46daSAbylay Ospan } 1187c5ea46daSAbylay Ospan if (priv->system != SYS_DVBT) { 1188c5ea46daSAbylay Ospan dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n", 1189c5ea46daSAbylay Ospan __func__, priv->system); 1190c5ea46daSAbylay Ospan return -EINVAL; 1191c5ea46daSAbylay Ospan } 1192c5ea46daSAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10); 1193c5ea46daSAbylay Ospan cxd2841er_read_regs(priv, I2C_SLVT, 0x4c, data, sizeof(data)); 1194c5ea46daSAbylay Ospan *offset = -1 * sign_extend32( 1195c5ea46daSAbylay Ospan ((u32)(data[0] & 0x1F) << 24) | ((u32)data[1] << 16) | 1196c5ea46daSAbylay Ospan ((u32)data[2] << 8) | (u32)data[3], 29); 11974da093ceSAbylay Ospan *offset *= (bandwidth / 1000000); 11984da093ceSAbylay Ospan *offset /= 235; 1199c5ea46daSAbylay Ospan return 0; 1200c5ea46daSAbylay Ospan } 1201c5ea46daSAbylay Ospan 1202c8946c8dSMauro Carvalho Chehab static int cxd2841er_get_carrier_offset_t2(struct cxd2841er_priv *priv, 1203c8946c8dSMauro Carvalho Chehab u32 bandwidth, int *offset) 1204a6dc60ffSKozlov Sergey { 1205a6dc60ffSKozlov Sergey u8 data[4]; 1206a6dc60ffSKozlov Sergey 1207a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s()\n", __func__); 1208a6dc60ffSKozlov Sergey if (priv->state != STATE_ACTIVE_TC) { 1209a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n", 1210a6dc60ffSKozlov Sergey __func__, priv->state); 1211a6dc60ffSKozlov Sergey return -EINVAL; 1212a6dc60ffSKozlov Sergey } 1213a6dc60ffSKozlov Sergey if (priv->system != SYS_DVBT2) { 1214a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n", 1215a6dc60ffSKozlov Sergey __func__, priv->system); 1216a6dc60ffSKozlov Sergey return -EINVAL; 1217a6dc60ffSKozlov Sergey } 1218a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20); 1219a6dc60ffSKozlov Sergey cxd2841er_read_regs(priv, I2C_SLVT, 0x4c, data, sizeof(data)); 1220a6dc60ffSKozlov Sergey *offset = -1 * sign_extend32( 1221a6dc60ffSKozlov Sergey ((u32)(data[0] & 0x0F) << 24) | ((u32)data[1] << 16) | 1222a6dc60ffSKozlov Sergey ((u32)data[2] << 8) | (u32)data[3], 27); 1223a6dc60ffSKozlov Sergey switch (bandwidth) { 1224a6dc60ffSKozlov Sergey case 1712000: 1225a6dc60ffSKozlov Sergey *offset /= 582; 1226a6dc60ffSKozlov Sergey break; 1227a6dc60ffSKozlov Sergey case 5000000: 1228a6dc60ffSKozlov Sergey case 6000000: 1229a6dc60ffSKozlov Sergey case 7000000: 1230a6dc60ffSKozlov Sergey case 8000000: 1231a6dc60ffSKozlov Sergey *offset *= (bandwidth / 1000000); 1232a6dc60ffSKozlov Sergey *offset /= 940; 1233a6dc60ffSKozlov Sergey break; 1234a6dc60ffSKozlov Sergey default: 1235a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s(): invalid bandwidth %d\n", 1236a6dc60ffSKozlov Sergey __func__, bandwidth); 1237a6dc60ffSKozlov Sergey return -EINVAL; 1238a6dc60ffSKozlov Sergey } 1239a6dc60ffSKozlov Sergey return 0; 1240a6dc60ffSKozlov Sergey } 1241a6dc60ffSKozlov Sergey 1242c8946c8dSMauro Carvalho Chehab static int cxd2841er_get_carrier_offset_c(struct cxd2841er_priv *priv, 1243c8946c8dSMauro Carvalho Chehab int *offset) 1244a6dc60ffSKozlov Sergey { 1245a6dc60ffSKozlov Sergey u8 data[2]; 1246a6dc60ffSKozlov Sergey 1247a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s()\n", __func__); 1248a6dc60ffSKozlov Sergey if (priv->state != STATE_ACTIVE_TC) { 1249a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n", 1250a6dc60ffSKozlov Sergey __func__, priv->state); 1251a6dc60ffSKozlov Sergey return -EINVAL; 1252a6dc60ffSKozlov Sergey } 1253a6dc60ffSKozlov Sergey if (priv->system != SYS_DVBC_ANNEX_A) { 1254a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n", 1255a6dc60ffSKozlov Sergey __func__, priv->system); 1256a6dc60ffSKozlov Sergey return -EINVAL; 1257a6dc60ffSKozlov Sergey } 1258a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40); 1259a6dc60ffSKozlov Sergey cxd2841er_read_regs(priv, I2C_SLVT, 0x15, data, sizeof(data)); 1260a6dc60ffSKozlov Sergey *offset = div_s64(41000LL * sign_extend32((((u32)data[0] & 0x3f) << 8) 1261a6dc60ffSKozlov Sergey | (u32)data[1], 13), 16384); 1262a6dc60ffSKozlov Sergey return 0; 1263a6dc60ffSKozlov Sergey } 1264a6dc60ffSKozlov Sergey 1265a6dc60ffSKozlov Sergey static int cxd2841er_read_packet_errors_t( 1266a6dc60ffSKozlov Sergey struct cxd2841er_priv *priv, u32 *penum) 1267a6dc60ffSKozlov Sergey { 1268a6dc60ffSKozlov Sergey u8 data[3]; 1269a6dc60ffSKozlov Sergey 1270a6dc60ffSKozlov Sergey *penum = 0; 1271a6dc60ffSKozlov Sergey if (priv->state != STATE_ACTIVE_TC) { 1272a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n", 1273a6dc60ffSKozlov Sergey __func__, priv->state); 1274a6dc60ffSKozlov Sergey return -EINVAL; 1275a6dc60ffSKozlov Sergey } 1276a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10); 1277a6dc60ffSKozlov Sergey cxd2841er_read_regs(priv, I2C_SLVT, 0xea, data, sizeof(data)); 1278a6dc60ffSKozlov Sergey if (data[2] & 0x01) 1279a6dc60ffSKozlov Sergey *penum = ((u32)data[0] << 8) | (u32)data[1]; 1280a6dc60ffSKozlov Sergey return 0; 1281a6dc60ffSKozlov Sergey } 1282a6dc60ffSKozlov Sergey 1283a6dc60ffSKozlov Sergey static int cxd2841er_read_packet_errors_t2( 1284a6dc60ffSKozlov Sergey struct cxd2841er_priv *priv, u32 *penum) 1285a6dc60ffSKozlov Sergey { 1286a6dc60ffSKozlov Sergey u8 data[3]; 1287a6dc60ffSKozlov Sergey 1288a6dc60ffSKozlov Sergey *penum = 0; 1289a6dc60ffSKozlov Sergey if (priv->state != STATE_ACTIVE_TC) { 1290a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n", 1291a6dc60ffSKozlov Sergey __func__, priv->state); 1292a6dc60ffSKozlov Sergey return -EINVAL; 1293a6dc60ffSKozlov Sergey } 1294a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x24); 1295a6dc60ffSKozlov Sergey cxd2841er_read_regs(priv, I2C_SLVT, 0xfd, data, sizeof(data)); 1296a6dc60ffSKozlov Sergey if (data[0] & 0x01) 1297a6dc60ffSKozlov Sergey *penum = ((u32)data[1] << 8) | (u32)data[2]; 1298a6dc60ffSKozlov Sergey return 0; 1299a6dc60ffSKozlov Sergey } 1300a6dc60ffSKozlov Sergey 130183808c23SAbylay Ospan static int cxd2841er_read_packet_errors_i( 130283808c23SAbylay Ospan struct cxd2841er_priv *priv, u32 *penum) 130383808c23SAbylay Ospan { 130483808c23SAbylay Ospan u8 data[2]; 130583808c23SAbylay Ospan 130683808c23SAbylay Ospan *penum = 0; 130783808c23SAbylay Ospan if (priv->state != STATE_ACTIVE_TC) { 130883808c23SAbylay Ospan dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n", 130983808c23SAbylay Ospan __func__, priv->state); 131083808c23SAbylay Ospan return -EINVAL; 131183808c23SAbylay Ospan } 131283808c23SAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60); 131383808c23SAbylay Ospan cxd2841er_read_regs(priv, I2C_SLVT, 0xA1, data, 1); 131483808c23SAbylay Ospan 131583808c23SAbylay Ospan if (!(data[0] & 0x01)) 131683808c23SAbylay Ospan return 0; 131783808c23SAbylay Ospan 131883808c23SAbylay Ospan /* Layer A */ 131983808c23SAbylay Ospan cxd2841er_read_regs(priv, I2C_SLVT, 0xA2, data, sizeof(data)); 132083808c23SAbylay Ospan *penum = ((u32)data[0] << 8) | (u32)data[1]; 132183808c23SAbylay Ospan 132283808c23SAbylay Ospan /* Layer B */ 132383808c23SAbylay Ospan cxd2841er_read_regs(priv, I2C_SLVT, 0xA4, data, sizeof(data)); 132483808c23SAbylay Ospan *penum += ((u32)data[0] << 8) | (u32)data[1]; 132583808c23SAbylay Ospan 132683808c23SAbylay Ospan /* Layer C */ 132783808c23SAbylay Ospan cxd2841er_read_regs(priv, I2C_SLVT, 0xA6, data, sizeof(data)); 132883808c23SAbylay Ospan *penum += ((u32)data[0] << 8) | (u32)data[1]; 132983808c23SAbylay Ospan 133083808c23SAbylay Ospan return 0; 133183808c23SAbylay Ospan } 133283808c23SAbylay Ospan 13334216be14SMauro Carvalho Chehab static int cxd2841er_mon_read_ber_s(struct cxd2841er_priv *priv, 13344216be14SMauro Carvalho Chehab u32 *bit_error, u32 *bit_count) 1335a6dc60ffSKozlov Sergey { 1336a6dc60ffSKozlov Sergey u8 data[11]; 1337a6dc60ffSKozlov Sergey 1338a6dc60ffSKozlov Sergey /* Set SLV-T Bank : 0xA0 */ 1339a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0); 1340a6dc60ffSKozlov Sergey /* 1341a6dc60ffSKozlov Sergey * slave Bank Addr Bit Signal name 1342a6dc60ffSKozlov Sergey * <SLV-T> A0h 35h [0] IFVBER_VALID 1343a6dc60ffSKozlov Sergey * <SLV-T> A0h 36h [5:0] IFVBER_BITERR[21:16] 1344a6dc60ffSKozlov Sergey * <SLV-T> A0h 37h [7:0] IFVBER_BITERR[15:8] 1345a6dc60ffSKozlov Sergey * <SLV-T> A0h 38h [7:0] IFVBER_BITERR[7:0] 1346a6dc60ffSKozlov Sergey * <SLV-T> A0h 3Dh [5:0] IFVBER_BITNUM[21:16] 1347a6dc60ffSKozlov Sergey * <SLV-T> A0h 3Eh [7:0] IFVBER_BITNUM[15:8] 1348a6dc60ffSKozlov Sergey * <SLV-T> A0h 3Fh [7:0] IFVBER_BITNUM[7:0] 1349a6dc60ffSKozlov Sergey */ 1350a6dc60ffSKozlov Sergey cxd2841er_read_regs(priv, I2C_SLVT, 0x35, data, 11); 1351a6dc60ffSKozlov Sergey if (data[0] & 0x01) { 13524216be14SMauro Carvalho Chehab *bit_error = ((u32)(data[1] & 0x3F) << 16) | 1353a6dc60ffSKozlov Sergey ((u32)(data[2] & 0xFF) << 8) | 1354a6dc60ffSKozlov Sergey (u32)(data[3] & 0xFF); 13554216be14SMauro Carvalho Chehab *bit_count = ((u32)(data[8] & 0x3F) << 16) | 1356a6dc60ffSKozlov Sergey ((u32)(data[9] & 0xFF) << 8) | 1357a6dc60ffSKozlov Sergey (u32)(data[10] & 0xFF); 13584216be14SMauro Carvalho Chehab if ((*bit_count == 0) || (*bit_error > *bit_count)) { 1359a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, 1360a6dc60ffSKozlov Sergey "%s(): invalid bit_error %d, bit_count %d\n", 13614216be14SMauro Carvalho Chehab __func__, *bit_error, *bit_count); 1362f1b26622SMauro Carvalho Chehab return -EINVAL; 1363a6dc60ffSKozlov Sergey } 1364a6dc60ffSKozlov Sergey return 0; 1365a6dc60ffSKozlov Sergey } 1366f1b26622SMauro Carvalho Chehab dev_dbg(&priv->i2c->dev, "%s(): no data available\n", __func__); 1367f1b26622SMauro Carvalho Chehab return -EINVAL; 1368f1b26622SMauro Carvalho Chehab } 1369a6dc60ffSKozlov Sergey 1370a6dc60ffSKozlov Sergey 13714216be14SMauro Carvalho Chehab static int cxd2841er_mon_read_ber_s2(struct cxd2841er_priv *priv, 13724216be14SMauro Carvalho Chehab u32 *bit_error, u32 *bit_count) 1373a6dc60ffSKozlov Sergey { 1374a6dc60ffSKozlov Sergey u8 data[5]; 13754216be14SMauro Carvalho Chehab u32 period; 1376a6dc60ffSKozlov Sergey 1377a6dc60ffSKozlov Sergey /* Set SLV-T Bank : 0xB2 */ 1378a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xb2); 1379a6dc60ffSKozlov Sergey /* 1380a6dc60ffSKozlov Sergey * slave Bank Addr Bit Signal name 1381a6dc60ffSKozlov Sergey * <SLV-T> B2h 30h [0] IFLBER_VALID 1382a6dc60ffSKozlov Sergey * <SLV-T> B2h 31h [3:0] IFLBER_BITERR[27:24] 1383a6dc60ffSKozlov Sergey * <SLV-T> B2h 32h [7:0] IFLBER_BITERR[23:16] 1384a6dc60ffSKozlov Sergey * <SLV-T> B2h 33h [7:0] IFLBER_BITERR[15:8] 1385a6dc60ffSKozlov Sergey * <SLV-T> B2h 34h [7:0] IFLBER_BITERR[7:0] 1386a6dc60ffSKozlov Sergey */ 1387a6dc60ffSKozlov Sergey cxd2841er_read_regs(priv, I2C_SLVT, 0x30, data, 5); 1388a6dc60ffSKozlov Sergey if (data[0] & 0x01) { 1389a6dc60ffSKozlov Sergey /* Bit error count */ 13904216be14SMauro Carvalho Chehab *bit_error = ((u32)(data[1] & 0x0F) << 24) | 1391a6dc60ffSKozlov Sergey ((u32)(data[2] & 0xFF) << 16) | 1392a6dc60ffSKozlov Sergey ((u32)(data[3] & 0xFF) << 8) | 1393a6dc60ffSKozlov Sergey (u32)(data[4] & 0xFF); 1394a6dc60ffSKozlov Sergey 1395a6dc60ffSKozlov Sergey /* Set SLV-T Bank : 0xA0 */ 1396a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0); 1397a6dc60ffSKozlov Sergey cxd2841er_read_reg(priv, I2C_SLVT, 0x7a, data); 1398a6dc60ffSKozlov Sergey /* Measurement period */ 1399a6dc60ffSKozlov Sergey period = (u32)(1 << (data[0] & 0x0F)); 1400a6dc60ffSKozlov Sergey if (period == 0) { 1401a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, 1402a6dc60ffSKozlov Sergey "%s(): period is 0\n", __func__); 1403f1b26622SMauro Carvalho Chehab return -EINVAL; 1404a6dc60ffSKozlov Sergey } 14054216be14SMauro Carvalho Chehab if (*bit_error > (period * 64800)) { 1406a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, 1407a6dc60ffSKozlov Sergey "%s(): invalid bit_err 0x%x period 0x%x\n", 14084216be14SMauro Carvalho Chehab __func__, *bit_error, period); 1409f1b26622SMauro Carvalho Chehab return -EINVAL; 1410a6dc60ffSKozlov Sergey } 14114216be14SMauro Carvalho Chehab *bit_count = period * 64800; 14124216be14SMauro Carvalho Chehab 1413f1b26622SMauro Carvalho Chehab return 0; 1414a6dc60ffSKozlov Sergey } else { 1415a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, 1416a6dc60ffSKozlov Sergey "%s(): no data available\n", __func__); 1417a6dc60ffSKozlov Sergey } 1418f1b26622SMauro Carvalho Chehab return -EINVAL; 1419a6dc60ffSKozlov Sergey } 1420a6dc60ffSKozlov Sergey 14214216be14SMauro Carvalho Chehab static int cxd2841er_read_ber_t2(struct cxd2841er_priv *priv, 14224216be14SMauro Carvalho Chehab u32 *bit_error, u32 *bit_count) 1423a6dc60ffSKozlov Sergey { 1424a6dc60ffSKozlov Sergey u8 data[4]; 14254216be14SMauro Carvalho Chehab u32 period_exp, n_ldpc; 1426a6dc60ffSKozlov Sergey 1427a6dc60ffSKozlov Sergey if (priv->state != STATE_ACTIVE_TC) { 1428a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, 1429a6dc60ffSKozlov Sergey "%s(): invalid state %d\n", __func__, priv->state); 1430a6dc60ffSKozlov Sergey return -EINVAL; 1431a6dc60ffSKozlov Sergey } 1432a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20); 1433a6dc60ffSKozlov Sergey cxd2841er_read_regs(priv, I2C_SLVT, 0x39, data, sizeof(data)); 1434a6dc60ffSKozlov Sergey if (!(data[0] & 0x10)) { 1435a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, 1436a6dc60ffSKozlov Sergey "%s(): no valid BER data\n", __func__); 14374216be14SMauro Carvalho Chehab return -EINVAL; 1438a6dc60ffSKozlov Sergey } 14394216be14SMauro Carvalho Chehab *bit_error = ((u32)(data[0] & 0x0f) << 24) | 1440a6dc60ffSKozlov Sergey ((u32)data[1] << 16) | 1441a6dc60ffSKozlov Sergey ((u32)data[2] << 8) | 1442a6dc60ffSKozlov Sergey (u32)data[3]; 1443a6dc60ffSKozlov Sergey cxd2841er_read_reg(priv, I2C_SLVT, 0x6f, data); 1444a6dc60ffSKozlov Sergey period_exp = data[0] & 0x0f; 1445a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x22); 1446a6dc60ffSKozlov Sergey cxd2841er_read_reg(priv, I2C_SLVT, 0x5e, data); 1447a6dc60ffSKozlov Sergey n_ldpc = ((data[0] & 0x03) == 0 ? 16200 : 64800); 14484216be14SMauro Carvalho Chehab if (*bit_error > ((1U << period_exp) * n_ldpc)) { 1449a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, 1450a6dc60ffSKozlov Sergey "%s(): invalid BER value\n", __func__); 1451a6dc60ffSKozlov Sergey return -EINVAL; 1452a6dc60ffSKozlov Sergey } 14534216be14SMauro Carvalho Chehab 14544216be14SMauro Carvalho Chehab /* 14554216be14SMauro Carvalho Chehab * FIXME: the right thing would be to return bit_error untouched, 14564216be14SMauro Carvalho Chehab * but, as we don't know the scale returned by the counters, let's 14574216be14SMauro Carvalho Chehab * at least preserver BER = bit_error/bit_count. 14584216be14SMauro Carvalho Chehab */ 1459a6dc60ffSKozlov Sergey if (period_exp >= 4) { 14604216be14SMauro Carvalho Chehab *bit_count = (1U << (period_exp - 4)) * (n_ldpc / 200); 14614216be14SMauro Carvalho Chehab *bit_error *= 3125ULL; 1462a6dc60ffSKozlov Sergey } else { 14634216be14SMauro Carvalho Chehab *bit_count = (1U << period_exp) * (n_ldpc / 200); 14644216be14SMauro Carvalho Chehab *bit_error *= 50000ULL;; 1465a6dc60ffSKozlov Sergey } 1466a6dc60ffSKozlov Sergey return 0; 1467a6dc60ffSKozlov Sergey } 1468a6dc60ffSKozlov Sergey 14694216be14SMauro Carvalho Chehab static int cxd2841er_read_ber_t(struct cxd2841er_priv *priv, 14704216be14SMauro Carvalho Chehab u32 *bit_error, u32 *bit_count) 1471a6dc60ffSKozlov Sergey { 1472a6dc60ffSKozlov Sergey u8 data[2]; 14734216be14SMauro Carvalho Chehab u32 period; 1474a6dc60ffSKozlov Sergey 1475a6dc60ffSKozlov Sergey if (priv->state != STATE_ACTIVE_TC) { 1476a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, 1477a6dc60ffSKozlov Sergey "%s(): invalid state %d\n", __func__, priv->state); 1478a6dc60ffSKozlov Sergey return -EINVAL; 1479a6dc60ffSKozlov Sergey } 1480a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10); 1481a6dc60ffSKozlov Sergey cxd2841er_read_reg(priv, I2C_SLVT, 0x39, data); 1482a6dc60ffSKozlov Sergey if (!(data[0] & 0x01)) { 1483a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, 1484a6dc60ffSKozlov Sergey "%s(): no valid BER data\n", __func__); 1485a6dc60ffSKozlov Sergey return 0; 1486a6dc60ffSKozlov Sergey } 1487a6dc60ffSKozlov Sergey cxd2841er_read_regs(priv, I2C_SLVT, 0x22, data, sizeof(data)); 14884216be14SMauro Carvalho Chehab *bit_error = ((u32)data[0] << 8) | (u32)data[1]; 1489a6dc60ffSKozlov Sergey cxd2841er_read_reg(priv, I2C_SLVT, 0x6f, data); 1490a6dc60ffSKozlov Sergey period = ((data[0] & 0x07) == 0) ? 256 : (4096 << (data[0] & 0x07)); 14914216be14SMauro Carvalho Chehab 14924216be14SMauro Carvalho Chehab /* 14934216be14SMauro Carvalho Chehab * FIXME: the right thing would be to return bit_error untouched, 14944216be14SMauro Carvalho Chehab * but, as we don't know the scale returned by the counters, let's 14954216be14SMauro Carvalho Chehab * at least preserver BER = bit_error/bit_count. 14964216be14SMauro Carvalho Chehab */ 14974216be14SMauro Carvalho Chehab *bit_count = period / 128; 14984216be14SMauro Carvalho Chehab *bit_error *= 78125ULL; 1499a6dc60ffSKozlov Sergey return 0; 1500a6dc60ffSKozlov Sergey } 1501a6dc60ffSKozlov Sergey 1502a6dc60ffSKozlov Sergey static u32 cxd2841er_dvbs_read_snr(struct cxd2841er_priv *priv, u8 delsys) 1503a6dc60ffSKozlov Sergey { 1504a6dc60ffSKozlov Sergey u8 data[3]; 1505a6dc60ffSKozlov Sergey u32 res = 0, value; 1506a6dc60ffSKozlov Sergey int min_index, max_index, index; 1507a6dc60ffSKozlov Sergey static const struct cxd2841er_cnr_data *cn_data; 1508a6dc60ffSKozlov Sergey 1509a6dc60ffSKozlov Sergey /* Set SLV-T Bank : 0xA1 */ 1510a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa1); 1511a6dc60ffSKozlov Sergey /* 1512a6dc60ffSKozlov Sergey * slave Bank Addr Bit Signal name 1513a6dc60ffSKozlov Sergey * <SLV-T> A1h 10h [0] ICPM_QUICKRDY 1514a6dc60ffSKozlov Sergey * <SLV-T> A1h 11h [4:0] ICPM_QUICKCNDT[12:8] 1515a6dc60ffSKozlov Sergey * <SLV-T> A1h 12h [7:0] ICPM_QUICKCNDT[7:0] 1516a6dc60ffSKozlov Sergey */ 1517a6dc60ffSKozlov Sergey cxd2841er_read_regs(priv, I2C_SLVT, 0x10, data, 3); 1518a6dc60ffSKozlov Sergey if (data[0] & 0x01) { 1519a6dc60ffSKozlov Sergey value = ((u32)(data[1] & 0x1F) << 8) | (u32)(data[2] & 0xFF); 1520a6dc60ffSKozlov Sergey min_index = 0; 1521a6dc60ffSKozlov Sergey if (delsys == SYS_DVBS) { 1522a6dc60ffSKozlov Sergey cn_data = s_cn_data; 1523a6dc60ffSKozlov Sergey max_index = sizeof(s_cn_data) / 1524a6dc60ffSKozlov Sergey sizeof(s_cn_data[0]) - 1; 1525a6dc60ffSKozlov Sergey } else { 1526a6dc60ffSKozlov Sergey cn_data = s2_cn_data; 1527a6dc60ffSKozlov Sergey max_index = sizeof(s2_cn_data) / 1528a6dc60ffSKozlov Sergey sizeof(s2_cn_data[0]) - 1; 1529a6dc60ffSKozlov Sergey } 1530a6dc60ffSKozlov Sergey if (value >= cn_data[min_index].value) { 1531a6dc60ffSKozlov Sergey res = cn_data[min_index].cnr_x1000; 1532a6dc60ffSKozlov Sergey goto done; 1533a6dc60ffSKozlov Sergey } 1534a6dc60ffSKozlov Sergey if (value <= cn_data[max_index].value) { 1535a6dc60ffSKozlov Sergey res = cn_data[max_index].cnr_x1000; 1536a6dc60ffSKozlov Sergey goto done; 1537a6dc60ffSKozlov Sergey } 1538a6dc60ffSKozlov Sergey while ((max_index - min_index) > 1) { 1539a6dc60ffSKozlov Sergey index = (max_index + min_index) / 2; 1540a6dc60ffSKozlov Sergey if (value == cn_data[index].value) { 1541a6dc60ffSKozlov Sergey res = cn_data[index].cnr_x1000; 1542a6dc60ffSKozlov Sergey goto done; 1543a6dc60ffSKozlov Sergey } else if (value > cn_data[index].value) 1544a6dc60ffSKozlov Sergey max_index = index; 1545a6dc60ffSKozlov Sergey else 1546a6dc60ffSKozlov Sergey min_index = index; 1547a6dc60ffSKozlov Sergey if ((max_index - min_index) <= 1) { 1548a6dc60ffSKozlov Sergey if (value == cn_data[max_index].value) { 1549a6dc60ffSKozlov Sergey res = cn_data[max_index].cnr_x1000; 1550a6dc60ffSKozlov Sergey goto done; 1551a6dc60ffSKozlov Sergey } else { 1552a6dc60ffSKozlov Sergey res = cn_data[min_index].cnr_x1000; 1553a6dc60ffSKozlov Sergey goto done; 1554a6dc60ffSKozlov Sergey } 1555a6dc60ffSKozlov Sergey } 1556a6dc60ffSKozlov Sergey } 1557a6dc60ffSKozlov Sergey } else { 1558a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, 1559a6dc60ffSKozlov Sergey "%s(): no data available\n", __func__); 1560a6dc60ffSKozlov Sergey } 1561a6dc60ffSKozlov Sergey done: 1562a6dc60ffSKozlov Sergey return res; 1563a6dc60ffSKozlov Sergey } 1564a6dc60ffSKozlov Sergey 1565a6dc60ffSKozlov Sergey static int cxd2841er_read_snr_t(struct cxd2841er_priv *priv, u32 *snr) 1566a6dc60ffSKozlov Sergey { 1567a6dc60ffSKozlov Sergey u32 reg; 1568a6dc60ffSKozlov Sergey u8 data[2]; 1569a6dc60ffSKozlov Sergey 1570a6dc60ffSKozlov Sergey *snr = 0; 1571a6dc60ffSKozlov Sergey if (priv->state != STATE_ACTIVE_TC) { 1572a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, 1573a6dc60ffSKozlov Sergey "%s(): invalid state %d\n", __func__, priv->state); 1574a6dc60ffSKozlov Sergey return -EINVAL; 1575a6dc60ffSKozlov Sergey } 1576a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10); 1577a6dc60ffSKozlov Sergey cxd2841er_read_regs(priv, I2C_SLVT, 0x28, data, sizeof(data)); 1578a6dc60ffSKozlov Sergey reg = ((u32)data[0] << 8) | (u32)data[1]; 1579a6dc60ffSKozlov Sergey if (reg == 0) { 1580a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, 1581a6dc60ffSKozlov Sergey "%s(): reg value out of range\n", __func__); 1582a6dc60ffSKozlov Sergey return 0; 1583a6dc60ffSKozlov Sergey } 1584a6dc60ffSKozlov Sergey if (reg > 4996) 1585a6dc60ffSKozlov Sergey reg = 4996; 1586a6dc60ffSKozlov Sergey *snr = 10000 * ((intlog10(reg) - intlog10(5350 - reg)) >> 24) + 28500; 1587a6dc60ffSKozlov Sergey return 0; 1588a6dc60ffSKozlov Sergey } 1589a6dc60ffSKozlov Sergey 1590c8946c8dSMauro Carvalho Chehab static int cxd2841er_read_snr_t2(struct cxd2841er_priv *priv, u32 *snr) 1591a6dc60ffSKozlov Sergey { 1592a6dc60ffSKozlov Sergey u32 reg; 1593a6dc60ffSKozlov Sergey u8 data[2]; 1594a6dc60ffSKozlov Sergey 1595a6dc60ffSKozlov Sergey *snr = 0; 1596a6dc60ffSKozlov Sergey if (priv->state != STATE_ACTIVE_TC) { 1597a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, 1598a6dc60ffSKozlov Sergey "%s(): invalid state %d\n", __func__, priv->state); 1599a6dc60ffSKozlov Sergey return -EINVAL; 1600a6dc60ffSKozlov Sergey } 1601a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20); 1602a6dc60ffSKozlov Sergey cxd2841er_read_regs(priv, I2C_SLVT, 0x28, data, sizeof(data)); 1603a6dc60ffSKozlov Sergey reg = ((u32)data[0] << 8) | (u32)data[1]; 1604a6dc60ffSKozlov Sergey if (reg == 0) { 1605a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, 1606a6dc60ffSKozlov Sergey "%s(): reg value out of range\n", __func__); 1607a6dc60ffSKozlov Sergey return 0; 1608a6dc60ffSKozlov Sergey } 1609a6dc60ffSKozlov Sergey if (reg > 10876) 1610a6dc60ffSKozlov Sergey reg = 10876; 1611a6dc60ffSKozlov Sergey *snr = 10000 * ((intlog10(reg) - 1612a6dc60ffSKozlov Sergey intlog10(12600 - reg)) >> 24) + 32000; 1613a6dc60ffSKozlov Sergey return 0; 1614a6dc60ffSKozlov Sergey } 1615a6dc60ffSKozlov Sergey 161683808c23SAbylay Ospan static int cxd2841er_read_snr_i(struct cxd2841er_priv *priv, u32 *snr) 161783808c23SAbylay Ospan { 161883808c23SAbylay Ospan u32 reg; 161983808c23SAbylay Ospan u8 data[2]; 162083808c23SAbylay Ospan 162183808c23SAbylay Ospan *snr = 0; 162283808c23SAbylay Ospan if (priv->state != STATE_ACTIVE_TC) { 162383808c23SAbylay Ospan dev_dbg(&priv->i2c->dev, 162483808c23SAbylay Ospan "%s(): invalid state %d\n", __func__, 162583808c23SAbylay Ospan priv->state); 162683808c23SAbylay Ospan return -EINVAL; 162783808c23SAbylay Ospan } 162883808c23SAbylay Ospan 162983808c23SAbylay Ospan /* Freeze all registers */ 163083808c23SAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x01, 0x01); 163183808c23SAbylay Ospan 163283808c23SAbylay Ospan 163383808c23SAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60); 163483808c23SAbylay Ospan cxd2841er_read_regs(priv, I2C_SLVT, 0x28, data, sizeof(data)); 163583808c23SAbylay Ospan reg = ((u32)data[0] << 8) | (u32)data[1]; 163683808c23SAbylay Ospan if (reg == 0) { 163783808c23SAbylay Ospan dev_dbg(&priv->i2c->dev, 163883808c23SAbylay Ospan "%s(): reg value out of range\n", __func__); 163983808c23SAbylay Ospan return 0; 164083808c23SAbylay Ospan } 164183808c23SAbylay Ospan if (reg > 4996) 164283808c23SAbylay Ospan reg = 4996; 164383808c23SAbylay Ospan *snr = 100 * intlog10(reg) - 9031; 164483808c23SAbylay Ospan return 0; 164583808c23SAbylay Ospan } 164683808c23SAbylay Ospan 1647d0998ce7SAbylay Ospan static u16 cxd2841er_read_agc_gain_c(struct cxd2841er_priv *priv, 1648d0998ce7SAbylay Ospan u8 delsys) 1649d0998ce7SAbylay Ospan { 1650d0998ce7SAbylay Ospan u8 data[2]; 1651d0998ce7SAbylay Ospan 1652d0998ce7SAbylay Ospan cxd2841er_write_reg( 1653d0998ce7SAbylay Ospan priv, I2C_SLVT, 0x00, 0x40); 1654d0998ce7SAbylay Ospan cxd2841er_read_regs(priv, I2C_SLVT, 0x49, data, 2); 1655d0998ce7SAbylay Ospan dev_dbg(&priv->i2c->dev, 1656d0998ce7SAbylay Ospan "%s(): AGC value=%u\n", 1657d0998ce7SAbylay Ospan __func__, (((u16)data[0] & 0x0F) << 8) | 1658d0998ce7SAbylay Ospan (u16)(data[1] & 0xFF)); 1659d0998ce7SAbylay Ospan return ((((u16)data[0] & 0x0F) << 8) | (u16)(data[1] & 0xFF)) << 4; 1660d0998ce7SAbylay Ospan } 1661d0998ce7SAbylay Ospan 1662a6dc60ffSKozlov Sergey static u16 cxd2841er_read_agc_gain_t_t2(struct cxd2841er_priv *priv, 1663a6dc60ffSKozlov Sergey u8 delsys) 1664a6dc60ffSKozlov Sergey { 1665a6dc60ffSKozlov Sergey u8 data[2]; 1666a6dc60ffSKozlov Sergey 1667a6dc60ffSKozlov Sergey cxd2841er_write_reg( 1668a6dc60ffSKozlov Sergey priv, I2C_SLVT, 0x00, (delsys == SYS_DVBT ? 0x10 : 0x20)); 1669a6dc60ffSKozlov Sergey cxd2841er_read_regs(priv, I2C_SLVT, 0x26, data, 2); 1670c5ea46daSAbylay Ospan dev_dbg(&priv->i2c->dev, 1671c5ea46daSAbylay Ospan "%s(): AGC value=%u\n", 1672c5ea46daSAbylay Ospan __func__, (((u16)data[0] & 0x0F) << 8) | 1673c5ea46daSAbylay Ospan (u16)(data[1] & 0xFF)); 1674a6dc60ffSKozlov Sergey return ((((u16)data[0] & 0x0F) << 8) | (u16)(data[1] & 0xFF)) << 4; 1675a6dc60ffSKozlov Sergey } 1676a6dc60ffSKozlov Sergey 167783808c23SAbylay Ospan static u16 cxd2841er_read_agc_gain_i(struct cxd2841er_priv *priv, 167883808c23SAbylay Ospan u8 delsys) 167983808c23SAbylay Ospan { 168083808c23SAbylay Ospan u8 data[2]; 168183808c23SAbylay Ospan 168283808c23SAbylay Ospan cxd2841er_write_reg( 168383808c23SAbylay Ospan priv, I2C_SLVT, 0x00, 0x60); 168483808c23SAbylay Ospan cxd2841er_read_regs(priv, I2C_SLVT, 0x26, data, 2); 168583808c23SAbylay Ospan 168683808c23SAbylay Ospan dev_dbg(&priv->i2c->dev, 168783808c23SAbylay Ospan "%s(): AGC value=%u\n", 168883808c23SAbylay Ospan __func__, (((u16)data[0] & 0x0F) << 8) | 168983808c23SAbylay Ospan (u16)(data[1] & 0xFF)); 169083808c23SAbylay Ospan return ((((u16)data[0] & 0x0F) << 8) | (u16)(data[1] & 0xFF)) << 4; 169183808c23SAbylay Ospan } 169283808c23SAbylay Ospan 1693a6dc60ffSKozlov Sergey static u16 cxd2841er_read_agc_gain_s(struct cxd2841er_priv *priv) 1694a6dc60ffSKozlov Sergey { 1695a6dc60ffSKozlov Sergey u8 data[2]; 1696a6dc60ffSKozlov Sergey 1697a6dc60ffSKozlov Sergey /* Set SLV-T Bank : 0xA0 */ 1698a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0); 1699a6dc60ffSKozlov Sergey /* 1700a6dc60ffSKozlov Sergey * slave Bank Addr Bit Signal name 1701a6dc60ffSKozlov Sergey * <SLV-T> A0h 1Fh [4:0] IRFAGC_GAIN[12:8] 1702a6dc60ffSKozlov Sergey * <SLV-T> A0h 20h [7:0] IRFAGC_GAIN[7:0] 1703a6dc60ffSKozlov Sergey */ 1704a6dc60ffSKozlov Sergey cxd2841er_read_regs(priv, I2C_SLVT, 0x1f, data, 2); 1705a6dc60ffSKozlov Sergey return ((((u16)data[0] & 0x1F) << 8) | (u16)(data[1] & 0xFF)) << 3; 1706a6dc60ffSKozlov Sergey } 1707a6dc60ffSKozlov Sergey 1708f1b26622SMauro Carvalho Chehab static void cxd2841er_read_ber(struct dvb_frontend *fe) 1709a6dc60ffSKozlov Sergey { 1710a6dc60ffSKozlov Sergey struct dtv_frontend_properties *p = &fe->dtv_property_cache; 1711a6dc60ffSKozlov Sergey struct cxd2841er_priv *priv = fe->demodulator_priv; 17124216be14SMauro Carvalho Chehab u32 ret, bit_error = 0, bit_count = 0; 1713a6dc60ffSKozlov Sergey 1714a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s()\n", __func__); 1715a6dc60ffSKozlov Sergey switch (p->delivery_system) { 1716a6dc60ffSKozlov Sergey case SYS_DVBS: 17174216be14SMauro Carvalho Chehab ret = cxd2841er_mon_read_ber_s(priv, &bit_error, &bit_count); 1718a6dc60ffSKozlov Sergey break; 1719a6dc60ffSKozlov Sergey case SYS_DVBS2: 17204216be14SMauro Carvalho Chehab ret = cxd2841er_mon_read_ber_s2(priv, &bit_error, &bit_count); 1721a6dc60ffSKozlov Sergey break; 1722a6dc60ffSKozlov Sergey case SYS_DVBT: 17234216be14SMauro Carvalho Chehab ret = cxd2841er_read_ber_t(priv, &bit_error, &bit_count); 1724a6dc60ffSKozlov Sergey break; 1725f1b26622SMauro Carvalho Chehab case SYS_DVBT2: 17264216be14SMauro Carvalho Chehab ret = cxd2841er_read_ber_t2(priv, &bit_error, &bit_count); 1727f1b26622SMauro Carvalho Chehab break; 1728f1b26622SMauro Carvalho Chehab default: 1729f1b26622SMauro Carvalho Chehab p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 17304216be14SMauro Carvalho Chehab p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 1731f1b26622SMauro Carvalho Chehab return; 1732a6dc60ffSKozlov Sergey } 1733f1b26622SMauro Carvalho Chehab 1734f1b26622SMauro Carvalho Chehab if (!ret) { 1735f1b26622SMauro Carvalho Chehab p->post_bit_error.stat[0].scale = FE_SCALE_COUNTER; 17364216be14SMauro Carvalho Chehab p->post_bit_error.stat[0].uvalue = bit_error; 17374216be14SMauro Carvalho Chehab p->post_bit_count.stat[0].scale = FE_SCALE_COUNTER; 17384216be14SMauro Carvalho Chehab p->post_bit_count.stat[0].uvalue = bit_count; 1739f1b26622SMauro Carvalho Chehab } else { 1740f1b26622SMauro Carvalho Chehab p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 17414216be14SMauro Carvalho Chehab p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 1742f1b26622SMauro Carvalho Chehab } 1743a6dc60ffSKozlov Sergey } 1744a6dc60ffSKozlov Sergey 17455fda1b65SMauro Carvalho Chehab static void cxd2841er_read_signal_strength(struct dvb_frontend *fe) 1746a6dc60ffSKozlov Sergey { 1747a6dc60ffSKozlov Sergey struct dtv_frontend_properties *p = &fe->dtv_property_cache; 1748a6dc60ffSKozlov Sergey struct cxd2841er_priv *priv = fe->demodulator_priv; 1749313a7dfbSMauro Carvalho Chehab s32 strength; 1750a6dc60ffSKozlov Sergey 1751a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s()\n", __func__); 1752a6dc60ffSKozlov Sergey switch (p->delivery_system) { 1753a6dc60ffSKozlov Sergey case SYS_DVBT: 1754a6dc60ffSKozlov Sergey case SYS_DVBT2: 17555fda1b65SMauro Carvalho Chehab strength = cxd2841er_read_agc_gain_t_t2(priv, 17565fda1b65SMauro Carvalho Chehab p->delivery_system); 17575fda1b65SMauro Carvalho Chehab p->strength.stat[0].scale = FE_SCALE_DECIBEL; 17585fda1b65SMauro Carvalho Chehab /* Formula was empirically determinated @ 410 MHz */ 1759313a7dfbSMauro Carvalho Chehab p->strength.stat[0].uvalue = strength * 366 / 100 - 89520; 17605fda1b65SMauro Carvalho Chehab break; /* Code moved out of the function */ 1761988bd281SMauro Carvalho Chehab case SYS_DVBC_ANNEX_A: 1762997bdc0cSAbylay Ospan case SYS_DVBC_ANNEX_B: 1763997bdc0cSAbylay Ospan case SYS_DVBC_ANNEX_C: 1764997bdc0cSAbylay Ospan strength = cxd2841er_read_agc_gain_c(priv, 1765988bd281SMauro Carvalho Chehab p->delivery_system); 1766d12b791eSMauro Carvalho Chehab p->strength.stat[0].scale = FE_SCALE_DECIBEL; 1767d12b791eSMauro Carvalho Chehab /* 1768d12b791eSMauro Carvalho Chehab * Formula was empirically determinated via linear regression, 1769d12b791eSMauro Carvalho Chehab * using frequencies: 175 MHz, 410 MHz and 800 MHz, and a 1770d12b791eSMauro Carvalho Chehab * stream modulated with QAM64 1771d12b791eSMauro Carvalho Chehab */ 1772313a7dfbSMauro Carvalho Chehab p->strength.stat[0].uvalue = strength * 4045 / 1000 - 85224; 1773988bd281SMauro Carvalho Chehab break; 177483808c23SAbylay Ospan case SYS_ISDBT: 1775313a7dfbSMauro Carvalho Chehab strength = cxd2841er_read_agc_gain_i(priv, p->delivery_system); 1776313a7dfbSMauro Carvalho Chehab p->strength.stat[0].scale = FE_SCALE_DECIBEL; 1777313a7dfbSMauro Carvalho Chehab /* 1778313a7dfbSMauro Carvalho Chehab * Formula was empirically determinated via linear regression, 1779313a7dfbSMauro Carvalho Chehab * using frequencies: 175 MHz, 410 MHz and 800 MHz. 1780313a7dfbSMauro Carvalho Chehab */ 1781313a7dfbSMauro Carvalho Chehab p->strength.stat[0].uvalue = strength * 3775 / 1000 - 90185; 178283808c23SAbylay Ospan break; 1783a6dc60ffSKozlov Sergey case SYS_DVBS: 1784a6dc60ffSKozlov Sergey case SYS_DVBS2: 17855fda1b65SMauro Carvalho Chehab strength = 65535 - cxd2841er_read_agc_gain_s(priv); 17865fda1b65SMauro Carvalho Chehab p->strength.stat[0].scale = FE_SCALE_RELATIVE; 17875fda1b65SMauro Carvalho Chehab p->strength.stat[0].uvalue = strength; 1788a6dc60ffSKozlov Sergey break; 1789a6dc60ffSKozlov Sergey default: 1790f1b26622SMauro Carvalho Chehab p->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 1791a6dc60ffSKozlov Sergey break; 1792a6dc60ffSKozlov Sergey } 1793a6dc60ffSKozlov Sergey } 1794a6dc60ffSKozlov Sergey 1795f1b26622SMauro Carvalho Chehab static void cxd2841er_read_snr(struct dvb_frontend *fe) 1796a6dc60ffSKozlov Sergey { 1797a6dc60ffSKozlov Sergey u32 tmp = 0; 1798a6dc60ffSKozlov Sergey struct dtv_frontend_properties *p = &fe->dtv_property_cache; 1799a6dc60ffSKozlov Sergey struct cxd2841er_priv *priv = fe->demodulator_priv; 1800a6dc60ffSKozlov Sergey 1801a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s()\n", __func__); 1802a6dc60ffSKozlov Sergey switch (p->delivery_system) { 1803a6dc60ffSKozlov Sergey case SYS_DVBT: 1804a6dc60ffSKozlov Sergey cxd2841er_read_snr_t(priv, &tmp); 1805a6dc60ffSKozlov Sergey break; 1806a6dc60ffSKozlov Sergey case SYS_DVBT2: 1807a6dc60ffSKozlov Sergey cxd2841er_read_snr_t2(priv, &tmp); 1808a6dc60ffSKozlov Sergey break; 180983808c23SAbylay Ospan case SYS_ISDBT: 181083808c23SAbylay Ospan cxd2841er_read_snr_i(priv, &tmp); 181183808c23SAbylay Ospan break; 1812a6dc60ffSKozlov Sergey case SYS_DVBS: 1813a6dc60ffSKozlov Sergey case SYS_DVBS2: 1814a6dc60ffSKozlov Sergey tmp = cxd2841er_dvbs_read_snr(priv, p->delivery_system); 1815a6dc60ffSKozlov Sergey break; 1816a6dc60ffSKozlov Sergey default: 1817a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s(): unknown delivery system %d\n", 1818a6dc60ffSKozlov Sergey __func__, p->delivery_system); 1819f1b26622SMauro Carvalho Chehab p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 1820f1b26622SMauro Carvalho Chehab return; 1821a6dc60ffSKozlov Sergey } 1822a6dc60ffSKozlov Sergey 1823f1b26622SMauro Carvalho Chehab p->cnr.stat[0].scale = FE_SCALE_DECIBEL; 1824f1b26622SMauro Carvalho Chehab p->cnr.stat[0].svalue = tmp; 1825f1b26622SMauro Carvalho Chehab } 1826f1b26622SMauro Carvalho Chehab 1827f1b26622SMauro Carvalho Chehab static void cxd2841er_read_ucblocks(struct dvb_frontend *fe) 1828a6dc60ffSKozlov Sergey { 1829a6dc60ffSKozlov Sergey struct dtv_frontend_properties *p = &fe->dtv_property_cache; 1830a6dc60ffSKozlov Sergey struct cxd2841er_priv *priv = fe->demodulator_priv; 1831f1b26622SMauro Carvalho Chehab u32 ucblocks; 1832a6dc60ffSKozlov Sergey 1833a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s()\n", __func__); 1834a6dc60ffSKozlov Sergey switch (p->delivery_system) { 1835a6dc60ffSKozlov Sergey case SYS_DVBT: 1836f1b26622SMauro Carvalho Chehab cxd2841er_read_packet_errors_t(priv, &ucblocks); 1837a6dc60ffSKozlov Sergey break; 1838a6dc60ffSKozlov Sergey case SYS_DVBT2: 1839f1b26622SMauro Carvalho Chehab cxd2841er_read_packet_errors_t2(priv, &ucblocks); 1840a6dc60ffSKozlov Sergey break; 184183808c23SAbylay Ospan case SYS_ISDBT: 1842f1b26622SMauro Carvalho Chehab cxd2841er_read_packet_errors_i(priv, &ucblocks); 184383808c23SAbylay Ospan break; 1844a6dc60ffSKozlov Sergey default: 1845f1b26622SMauro Carvalho Chehab p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 1846f1b26622SMauro Carvalho Chehab return; 1847a6dc60ffSKozlov Sergey } 1848a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s()\n", __func__); 1849f1b26622SMauro Carvalho Chehab 1850f1b26622SMauro Carvalho Chehab p->block_error.stat[0].scale = FE_SCALE_COUNTER; 1851f1b26622SMauro Carvalho Chehab p->block_error.stat[0].uvalue = ucblocks; 1852a6dc60ffSKozlov Sergey } 1853a6dc60ffSKozlov Sergey 1854a6dc60ffSKozlov Sergey static int cxd2841er_dvbt2_set_profile( 1855a6dc60ffSKozlov Sergey struct cxd2841er_priv *priv, enum cxd2841er_dvbt2_profile_t profile) 1856a6dc60ffSKozlov Sergey { 1857a6dc60ffSKozlov Sergey u8 tune_mode; 1858a6dc60ffSKozlov Sergey u8 seq_not2d_time; 1859a6dc60ffSKozlov Sergey 1860a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s()\n", __func__); 1861a6dc60ffSKozlov Sergey switch (profile) { 1862a6dc60ffSKozlov Sergey case DVBT2_PROFILE_BASE: 1863a6dc60ffSKozlov Sergey tune_mode = 0x01; 18646c77161aSAbylay Ospan /* Set early unlock time */ 18656c77161aSAbylay Ospan seq_not2d_time = (priv->xtal == SONY_XTAL_24000)?0x0E:0x0C; 1866a6dc60ffSKozlov Sergey break; 1867a6dc60ffSKozlov Sergey case DVBT2_PROFILE_LITE: 1868a6dc60ffSKozlov Sergey tune_mode = 0x05; 18696c77161aSAbylay Ospan /* Set early unlock time */ 18706c77161aSAbylay Ospan seq_not2d_time = (priv->xtal == SONY_XTAL_24000)?0x2E:0x28; 1871a6dc60ffSKozlov Sergey break; 1872a6dc60ffSKozlov Sergey case DVBT2_PROFILE_ANY: 1873a6dc60ffSKozlov Sergey tune_mode = 0x00; 18746c77161aSAbylay Ospan /* Set early unlock time */ 18756c77161aSAbylay Ospan seq_not2d_time = (priv->xtal == SONY_XTAL_24000)?0x2E:0x28; 1876a6dc60ffSKozlov Sergey break; 1877a6dc60ffSKozlov Sergey default: 1878a6dc60ffSKozlov Sergey return -EINVAL; 1879a6dc60ffSKozlov Sergey } 1880a6dc60ffSKozlov Sergey /* Set SLV-T Bank : 0x2E */ 1881a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2e); 1882a6dc60ffSKozlov Sergey /* Set profile and tune mode */ 1883a6dc60ffSKozlov Sergey cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x10, tune_mode, 0x07); 1884a6dc60ffSKozlov Sergey /* Set SLV-T Bank : 0x2B */ 1885a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2b); 1886a6dc60ffSKozlov Sergey /* Set early unlock detection time */ 1887a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x9d, seq_not2d_time); 1888a6dc60ffSKozlov Sergey return 0; 1889a6dc60ffSKozlov Sergey } 1890a6dc60ffSKozlov Sergey 1891a6dc60ffSKozlov Sergey static int cxd2841er_dvbt2_set_plp_config(struct cxd2841er_priv *priv, 1892a6dc60ffSKozlov Sergey u8 is_auto, u8 plp_id) 1893a6dc60ffSKozlov Sergey { 1894a6dc60ffSKozlov Sergey if (is_auto) { 1895a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, 1896a6dc60ffSKozlov Sergey "%s() using auto PLP selection\n", __func__); 1897a6dc60ffSKozlov Sergey } else { 1898a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, 1899a6dc60ffSKozlov Sergey "%s() using manual PLP selection, ID %d\n", 1900a6dc60ffSKozlov Sergey __func__, plp_id); 1901a6dc60ffSKozlov Sergey } 1902a6dc60ffSKozlov Sergey /* Set SLV-T Bank : 0x23 */ 1903a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x23); 1904a6dc60ffSKozlov Sergey if (!is_auto) { 1905a6dc60ffSKozlov Sergey /* Manual PLP selection mode. Set the data PLP Id. */ 1906a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0xaf, plp_id); 1907a6dc60ffSKozlov Sergey } 1908a6dc60ffSKozlov Sergey /* Auto PLP select (Scanning mode = 0x00). Data PLP select = 0x01. */ 1909a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0xad, (is_auto ? 0x00 : 0x01)); 1910a6dc60ffSKozlov Sergey return 0; 1911a6dc60ffSKozlov Sergey } 1912a6dc60ffSKozlov Sergey 1913a6dc60ffSKozlov Sergey static int cxd2841er_sleep_tc_to_active_t2_band(struct cxd2841er_priv *priv, 1914a6dc60ffSKozlov Sergey u32 bandwidth) 1915a6dc60ffSKozlov Sergey { 1916a6dc60ffSKozlov Sergey u32 iffreq; 19176c77161aSAbylay Ospan u8 data[MAX_WRITE_REGSIZE]; 1918a6dc60ffSKozlov Sergey 19196c77161aSAbylay Ospan const uint8_t nominalRate8bw[3][5] = { 19206c77161aSAbylay Ospan /* TRCG Nominal Rate [37:0] */ 19216c77161aSAbylay Ospan {0x11, 0xF0, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */ 19226c77161aSAbylay Ospan {0x15, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */ 19236c77161aSAbylay Ospan {0x11, 0xF0, 0x00, 0x00, 0x00} /* 41MHz XTal */ 19246c77161aSAbylay Ospan }; 19256c77161aSAbylay Ospan 19266c77161aSAbylay Ospan const uint8_t nominalRate7bw[3][5] = { 19276c77161aSAbylay Ospan /* TRCG Nominal Rate [37:0] */ 19286c77161aSAbylay Ospan {0x14, 0x80, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */ 19296c77161aSAbylay Ospan {0x18, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */ 19306c77161aSAbylay Ospan {0x14, 0x80, 0x00, 0x00, 0x00} /* 41MHz XTal */ 19316c77161aSAbylay Ospan }; 19326c77161aSAbylay Ospan 19336c77161aSAbylay Ospan const uint8_t nominalRate6bw[3][5] = { 19346c77161aSAbylay Ospan /* TRCG Nominal Rate [37:0] */ 19356c77161aSAbylay Ospan {0x17, 0xEA, 0xAA, 0xAA, 0xAA}, /* 20.5MHz XTal */ 19366c77161aSAbylay Ospan {0x1C, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */ 19376c77161aSAbylay Ospan {0x17, 0xEA, 0xAA, 0xAA, 0xAA} /* 41MHz XTal */ 19386c77161aSAbylay Ospan }; 19396c77161aSAbylay Ospan 19406c77161aSAbylay Ospan const uint8_t nominalRate5bw[3][5] = { 19416c77161aSAbylay Ospan /* TRCG Nominal Rate [37:0] */ 19426c77161aSAbylay Ospan {0x1C, 0xB3, 0x33, 0x33, 0x33}, /* 20.5MHz XTal */ 19436c77161aSAbylay Ospan {0x21, 0x99, 0x99, 0x99, 0x99}, /* 24MHz XTal */ 19446c77161aSAbylay Ospan {0x1C, 0xB3, 0x33, 0x33, 0x33} /* 41MHz XTal */ 19456c77161aSAbylay Ospan }; 19466c77161aSAbylay Ospan 19476c77161aSAbylay Ospan const uint8_t nominalRate17bw[3][5] = { 19486c77161aSAbylay Ospan /* TRCG Nominal Rate [37:0] */ 19496c77161aSAbylay Ospan {0x58, 0xE2, 0xAF, 0xE0, 0xBC}, /* 20.5MHz XTal */ 19506c77161aSAbylay Ospan {0x68, 0x0F, 0xA2, 0x32, 0xD0}, /* 24MHz XTal */ 19516c77161aSAbylay Ospan {0x58, 0xE2, 0xAF, 0xE0, 0xBC} /* 41MHz XTal */ 19526c77161aSAbylay Ospan }; 19536c77161aSAbylay Ospan 19546c77161aSAbylay Ospan const uint8_t itbCoef8bw[3][14] = { 19556c77161aSAbylay Ospan {0x26, 0xAF, 0x06, 0xCD, 0x13, 0xBB, 0x28, 0xBA, 19566c77161aSAbylay Ospan 0x23, 0xA9, 0x1F, 0xA8, 0x2C, 0xC8}, /* 20.5MHz XTal */ 19576c77161aSAbylay Ospan {0x2F, 0xBA, 0x28, 0x9B, 0x28, 0x9D, 0x28, 0xA1, 19586c77161aSAbylay Ospan 0x29, 0xA5, 0x2A, 0xAC, 0x29, 0xB5}, /* 24MHz XTal */ 19596c77161aSAbylay Ospan {0x26, 0xAF, 0x06, 0xCD, 0x13, 0xBB, 0x28, 0xBA, 19606c77161aSAbylay Ospan 0x23, 0xA9, 0x1F, 0xA8, 0x2C, 0xC8} /* 41MHz XTal */ 19616c77161aSAbylay Ospan }; 19626c77161aSAbylay Ospan 19636c77161aSAbylay Ospan const uint8_t itbCoef7bw[3][14] = { 19646c77161aSAbylay Ospan {0x2C, 0xBD, 0x02, 0xCF, 0x04, 0xF8, 0x23, 0xA6, 19656c77161aSAbylay Ospan 0x29, 0xB0, 0x26, 0xA9, 0x21, 0xA5}, /* 20.5MHz XTal */ 19666c77161aSAbylay Ospan {0x30, 0xB1, 0x29, 0x9A, 0x28, 0x9C, 0x28, 0xA0, 19676c77161aSAbylay Ospan 0x29, 0xA2, 0x2B, 0xA6, 0x2B, 0xAD}, /* 24MHz XTal */ 19686c77161aSAbylay Ospan {0x2C, 0xBD, 0x02, 0xCF, 0x04, 0xF8, 0x23, 0xA6, 19696c77161aSAbylay Ospan 0x29, 0xB0, 0x26, 0xA9, 0x21, 0xA5} /* 41MHz XTal */ 19706c77161aSAbylay Ospan }; 19716c77161aSAbylay Ospan 19726c77161aSAbylay Ospan const uint8_t itbCoef6bw[3][14] = { 19736c77161aSAbylay Ospan {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 19746c77161aSAbylay Ospan 0x00, 0xCF, 0x00, 0xE6, 0x23, 0xA4}, /* 20.5MHz XTal */ 19756c77161aSAbylay Ospan {0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E, 19766c77161aSAbylay Ospan 0x29, 0xA4, 0x29, 0xA2, 0x29, 0xA8}, /* 24MHz XTal */ 19776c77161aSAbylay Ospan {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 19786c77161aSAbylay Ospan 0x00, 0xCF, 0x00, 0xE6, 0x23, 0xA4} /* 41MHz XTal */ 19796c77161aSAbylay Ospan }; 19806c77161aSAbylay Ospan 19816c77161aSAbylay Ospan const uint8_t itbCoef5bw[3][14] = { 19826c77161aSAbylay Ospan {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 19836c77161aSAbylay Ospan 0x00, 0xCF, 0x00, 0xE6, 0x23, 0xA4}, /* 20.5MHz XTal */ 19846c77161aSAbylay Ospan {0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E, 19856c77161aSAbylay Ospan 0x29, 0xA4, 0x29, 0xA2, 0x29, 0xA8}, /* 24MHz XTal */ 19866c77161aSAbylay Ospan {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 19876c77161aSAbylay Ospan 0x00, 0xCF, 0x00, 0xE6, 0x23, 0xA4} /* 41MHz XTal */ 19886c77161aSAbylay Ospan }; 19896c77161aSAbylay Ospan 19906c77161aSAbylay Ospan const uint8_t itbCoef17bw[3][14] = { 19916c77161aSAbylay Ospan {0x25, 0xA0, 0x36, 0x8D, 0x2E, 0x94, 0x28, 0x9B, 19926c77161aSAbylay Ospan 0x32, 0x90, 0x2C, 0x9D, 0x29, 0x99}, /* 20.5MHz XTal */ 19936c77161aSAbylay Ospan {0x33, 0x8E, 0x2B, 0x97, 0x2D, 0x95, 0x37, 0x8B, 19946c77161aSAbylay Ospan 0x30, 0x97, 0x2D, 0x9A, 0x21, 0xA4}, /* 24MHz XTal */ 19956c77161aSAbylay Ospan {0x25, 0xA0, 0x36, 0x8D, 0x2E, 0x94, 0x28, 0x9B, 19966c77161aSAbylay Ospan 0x32, 0x90, 0x2C, 0x9D, 0x29, 0x99} /* 41MHz XTal */ 19976c77161aSAbylay Ospan }; 19986c77161aSAbylay Ospan 19996c77161aSAbylay Ospan /* Set SLV-T Bank : 0x20 */ 20006c77161aSAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20); 20016c77161aSAbylay Ospan 2002a6dc60ffSKozlov Sergey switch (bandwidth) { 2003a6dc60ffSKozlov Sergey case 8000000: 20046c77161aSAbylay Ospan /* <Timing Recovery setting> */ 20056c77161aSAbylay Ospan cxd2841er_write_regs(priv, I2C_SLVT, 20066c77161aSAbylay Ospan 0x9F, nominalRate8bw[priv->xtal], 5); 20076c77161aSAbylay Ospan 20086c77161aSAbylay Ospan /* Set SLV-T Bank : 0x27 */ 20096c77161aSAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27); 20106c77161aSAbylay Ospan cxd2841er_set_reg_bits(priv, I2C_SLVT, 20116c77161aSAbylay Ospan 0x7a, 0x00, 0x0f); 20126c77161aSAbylay Ospan 20136c77161aSAbylay Ospan /* Set SLV-T Bank : 0x10 */ 20146c77161aSAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10); 20156c77161aSAbylay Ospan 20166c77161aSAbylay Ospan /* Group delay equaliser settings for 20176c77161aSAbylay Ospan * ASCOT2D, ASCOT2E and ASCOT3 tuners 20186c77161aSAbylay Ospan */ 20196c77161aSAbylay Ospan cxd2841er_write_regs(priv, I2C_SLVT, 20206c77161aSAbylay Ospan 0xA6, itbCoef8bw[priv->xtal], 14); 20216c77161aSAbylay Ospan /* <IF freq setting> */ 20226c77161aSAbylay Ospan iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 4.80); 20236c77161aSAbylay Ospan data[0] = (u8) ((iffreq >> 16) & 0xff); 20246c77161aSAbylay Ospan data[1] = (u8)((iffreq >> 8) & 0xff); 20256c77161aSAbylay Ospan data[2] = (u8)(iffreq & 0xff); 20266c77161aSAbylay Ospan cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3); 20276c77161aSAbylay Ospan /* System bandwidth setting */ 20286c77161aSAbylay Ospan cxd2841er_set_reg_bits( 20296c77161aSAbylay Ospan priv, I2C_SLVT, 0xD7, 0x00, 0x07); 2030a6dc60ffSKozlov Sergey break; 2031a6dc60ffSKozlov Sergey case 7000000: 20326c77161aSAbylay Ospan /* <Timing Recovery setting> */ 20336c77161aSAbylay Ospan cxd2841er_write_regs(priv, I2C_SLVT, 20346c77161aSAbylay Ospan 0x9F, nominalRate7bw[priv->xtal], 5); 20356c77161aSAbylay Ospan 20366c77161aSAbylay Ospan /* Set SLV-T Bank : 0x27 */ 20376c77161aSAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27); 20386c77161aSAbylay Ospan cxd2841er_set_reg_bits(priv, I2C_SLVT, 20396c77161aSAbylay Ospan 0x7a, 0x00, 0x0f); 20406c77161aSAbylay Ospan 20416c77161aSAbylay Ospan /* Set SLV-T Bank : 0x10 */ 20426c77161aSAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10); 20436c77161aSAbylay Ospan 20446c77161aSAbylay Ospan /* Group delay equaliser settings for 20456c77161aSAbylay Ospan * ASCOT2D, ASCOT2E and ASCOT3 tuners 20466c77161aSAbylay Ospan */ 20476c77161aSAbylay Ospan cxd2841er_write_regs(priv, I2C_SLVT, 20486c77161aSAbylay Ospan 0xA6, itbCoef7bw[priv->xtal], 14); 20496c77161aSAbylay Ospan /* <IF freq setting> */ 20506c77161aSAbylay Ospan iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 4.20); 20516c77161aSAbylay Ospan data[0] = (u8) ((iffreq >> 16) & 0xff); 20526c77161aSAbylay Ospan data[1] = (u8)((iffreq >> 8) & 0xff); 20536c77161aSAbylay Ospan data[2] = (u8)(iffreq & 0xff); 20546c77161aSAbylay Ospan cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3); 20556c77161aSAbylay Ospan /* System bandwidth setting */ 20566c77161aSAbylay Ospan cxd2841er_set_reg_bits( 20576c77161aSAbylay Ospan priv, I2C_SLVT, 0xD7, 0x02, 0x07); 2058a6dc60ffSKozlov Sergey break; 2059a6dc60ffSKozlov Sergey case 6000000: 20606c77161aSAbylay Ospan /* <Timing Recovery setting> */ 20616c77161aSAbylay Ospan cxd2841er_write_regs(priv, I2C_SLVT, 20626c77161aSAbylay Ospan 0x9F, nominalRate6bw[priv->xtal], 5); 20636c77161aSAbylay Ospan 20646c77161aSAbylay Ospan /* Set SLV-T Bank : 0x27 */ 20656c77161aSAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27); 20666c77161aSAbylay Ospan cxd2841er_set_reg_bits(priv, I2C_SLVT, 20676c77161aSAbylay Ospan 0x7a, 0x00, 0x0f); 20686c77161aSAbylay Ospan 20696c77161aSAbylay Ospan /* Set SLV-T Bank : 0x10 */ 20706c77161aSAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10); 20716c77161aSAbylay Ospan 20726c77161aSAbylay Ospan /* Group delay equaliser settings for 20736c77161aSAbylay Ospan * ASCOT2D, ASCOT2E and ASCOT3 tuners 20746c77161aSAbylay Ospan */ 20756c77161aSAbylay Ospan cxd2841er_write_regs(priv, I2C_SLVT, 20766c77161aSAbylay Ospan 0xA6, itbCoef6bw[priv->xtal], 14); 20776c77161aSAbylay Ospan /* <IF freq setting> */ 20786c77161aSAbylay Ospan iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 3.60); 20796c77161aSAbylay Ospan data[0] = (u8) ((iffreq >> 16) & 0xff); 20806c77161aSAbylay Ospan data[1] = (u8)((iffreq >> 8) & 0xff); 20816c77161aSAbylay Ospan data[2] = (u8)(iffreq & 0xff); 20826c77161aSAbylay Ospan cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3); 20836c77161aSAbylay Ospan /* System bandwidth setting */ 20846c77161aSAbylay Ospan cxd2841er_set_reg_bits( 20856c77161aSAbylay Ospan priv, I2C_SLVT, 0xD7, 0x04, 0x07); 2086a6dc60ffSKozlov Sergey break; 2087a6dc60ffSKozlov Sergey case 5000000: 20886c77161aSAbylay Ospan /* <Timing Recovery setting> */ 20896c77161aSAbylay Ospan cxd2841er_write_regs(priv, I2C_SLVT, 20906c77161aSAbylay Ospan 0x9F, nominalRate5bw[priv->xtal], 5); 20916c77161aSAbylay Ospan 20926c77161aSAbylay Ospan /* Set SLV-T Bank : 0x27 */ 20936c77161aSAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27); 20946c77161aSAbylay Ospan cxd2841er_set_reg_bits(priv, I2C_SLVT, 20956c77161aSAbylay Ospan 0x7a, 0x00, 0x0f); 20966c77161aSAbylay Ospan 20976c77161aSAbylay Ospan /* Set SLV-T Bank : 0x10 */ 20986c77161aSAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10); 20996c77161aSAbylay Ospan 21006c77161aSAbylay Ospan /* Group delay equaliser settings for 21016c77161aSAbylay Ospan * ASCOT2D, ASCOT2E and ASCOT3 tuners 21026c77161aSAbylay Ospan */ 21036c77161aSAbylay Ospan cxd2841er_write_regs(priv, I2C_SLVT, 21046c77161aSAbylay Ospan 0xA6, itbCoef5bw[priv->xtal], 14); 21056c77161aSAbylay Ospan /* <IF freq setting> */ 21066c77161aSAbylay Ospan iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 3.60); 21076c77161aSAbylay Ospan data[0] = (u8) ((iffreq >> 16) & 0xff); 21086c77161aSAbylay Ospan data[1] = (u8)((iffreq >> 8) & 0xff); 21096c77161aSAbylay Ospan data[2] = (u8)(iffreq & 0xff); 21106c77161aSAbylay Ospan cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3); 21116c77161aSAbylay Ospan /* System bandwidth setting */ 21126c77161aSAbylay Ospan cxd2841er_set_reg_bits( 21136c77161aSAbylay Ospan priv, I2C_SLVT, 0xD7, 0x06, 0x07); 2114a6dc60ffSKozlov Sergey break; 2115a6dc60ffSKozlov Sergey case 1712000: 21166c77161aSAbylay Ospan /* <Timing Recovery setting> */ 21176c77161aSAbylay Ospan cxd2841er_write_regs(priv, I2C_SLVT, 21186c77161aSAbylay Ospan 0x9F, nominalRate17bw[priv->xtal], 5); 21196c77161aSAbylay Ospan 21206c77161aSAbylay Ospan /* Set SLV-T Bank : 0x27 */ 21216c77161aSAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27); 21226c77161aSAbylay Ospan cxd2841er_set_reg_bits(priv, I2C_SLVT, 21236c77161aSAbylay Ospan 0x7a, 0x03, 0x0f); 21246c77161aSAbylay Ospan 21256c77161aSAbylay Ospan /* Set SLV-T Bank : 0x10 */ 21266c77161aSAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10); 21276c77161aSAbylay Ospan 21286c77161aSAbylay Ospan /* Group delay equaliser settings for 21296c77161aSAbylay Ospan * ASCOT2D, ASCOT2E and ASCOT3 tuners 21306c77161aSAbylay Ospan */ 21316c77161aSAbylay Ospan cxd2841er_write_regs(priv, I2C_SLVT, 21326c77161aSAbylay Ospan 0xA6, itbCoef17bw[priv->xtal], 14); 21336c77161aSAbylay Ospan /* <IF freq setting> */ 21346c77161aSAbylay Ospan iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 3.50); 21356c77161aSAbylay Ospan data[0] = (u8) ((iffreq >> 16) & 0xff); 21366c77161aSAbylay Ospan data[1] = (u8)((iffreq >> 8) & 0xff); 21376c77161aSAbylay Ospan data[2] = (u8)(iffreq & 0xff); 21386c77161aSAbylay Ospan cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3); 21396c77161aSAbylay Ospan /* System bandwidth setting */ 21406c77161aSAbylay Ospan cxd2841er_set_reg_bits( 21416c77161aSAbylay Ospan priv, I2C_SLVT, 0xD7, 0x03, 0x07); 2142a6dc60ffSKozlov Sergey break; 2143a6dc60ffSKozlov Sergey default: 2144a6dc60ffSKozlov Sergey return -EINVAL; 2145a6dc60ffSKozlov Sergey } 2146a6dc60ffSKozlov Sergey return 0; 2147a6dc60ffSKozlov Sergey } 2148a6dc60ffSKozlov Sergey 2149a6dc60ffSKozlov Sergey static int cxd2841er_sleep_tc_to_active_t_band( 2150a6dc60ffSKozlov Sergey struct cxd2841er_priv *priv, u32 bandwidth) 2151a6dc60ffSKozlov Sergey { 215283808c23SAbylay Ospan u8 data[MAX_WRITE_REGSIZE]; 2153a6dc60ffSKozlov Sergey u32 iffreq; 215483808c23SAbylay Ospan u8 nominalRate8bw[3][5] = { 215583808c23SAbylay Ospan /* TRCG Nominal Rate [37:0] */ 215683808c23SAbylay Ospan {0x11, 0xF0, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */ 215783808c23SAbylay Ospan {0x15, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */ 215883808c23SAbylay Ospan {0x11, 0xF0, 0x00, 0x00, 0x00} /* 41MHz XTal */ 215983808c23SAbylay Ospan }; 216083808c23SAbylay Ospan u8 nominalRate7bw[3][5] = { 216183808c23SAbylay Ospan /* TRCG Nominal Rate [37:0] */ 216283808c23SAbylay Ospan {0x14, 0x80, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */ 216383808c23SAbylay Ospan {0x18, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */ 216483808c23SAbylay Ospan {0x14, 0x80, 0x00, 0x00, 0x00} /* 41MHz XTal */ 216583808c23SAbylay Ospan }; 216683808c23SAbylay Ospan u8 nominalRate6bw[3][5] = { 216783808c23SAbylay Ospan /* TRCG Nominal Rate [37:0] */ 216883808c23SAbylay Ospan {0x17, 0xEA, 0xAA, 0xAA, 0xAA}, /* 20.5MHz XTal */ 216983808c23SAbylay Ospan {0x1C, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */ 217083808c23SAbylay Ospan {0x17, 0xEA, 0xAA, 0xAA, 0xAA} /* 41MHz XTal */ 217183808c23SAbylay Ospan }; 217283808c23SAbylay Ospan u8 nominalRate5bw[3][5] = { 217383808c23SAbylay Ospan /* TRCG Nominal Rate [37:0] */ 217483808c23SAbylay Ospan {0x1C, 0xB3, 0x33, 0x33, 0x33}, /* 20.5MHz XTal */ 217583808c23SAbylay Ospan {0x21, 0x99, 0x99, 0x99, 0x99}, /* 24MHz XTal */ 217683808c23SAbylay Ospan {0x1C, 0xB3, 0x33, 0x33, 0x33} /* 41MHz XTal */ 217783808c23SAbylay Ospan }; 2178a6dc60ffSKozlov Sergey 217983808c23SAbylay Ospan u8 itbCoef8bw[3][14] = { 218083808c23SAbylay Ospan {0x26, 0xAF, 0x06, 0xCD, 0x13, 0xBB, 0x28, 0xBA, 0x23, 0xA9, 218183808c23SAbylay Ospan 0x1F, 0xA8, 0x2C, 0xC8}, /* 20.5MHz XTal */ 218283808c23SAbylay Ospan {0x2F, 0xBA, 0x28, 0x9B, 0x28, 0x9D, 0x28, 0xA1, 0x29, 0xA5, 218383808c23SAbylay Ospan 0x2A, 0xAC, 0x29, 0xB5}, /* 24MHz XTal */ 218483808c23SAbylay Ospan {0x26, 0xAF, 0x06, 0xCD, 0x13, 0xBB, 0x28, 0xBA, 0x23, 0xA9, 218583808c23SAbylay Ospan 0x1F, 0xA8, 0x2C, 0xC8} /* 41MHz XTal */ 218683808c23SAbylay Ospan }; 218783808c23SAbylay Ospan u8 itbCoef7bw[3][14] = { 218883808c23SAbylay Ospan {0x2C, 0xBD, 0x02, 0xCF, 0x04, 0xF8, 0x23, 0xA6, 0x29, 0xB0, 218983808c23SAbylay Ospan 0x26, 0xA9, 0x21, 0xA5}, /* 20.5MHz XTal */ 219083808c23SAbylay Ospan {0x30, 0xB1, 0x29, 0x9A, 0x28, 0x9C, 0x28, 0xA0, 0x29, 0xA2, 219183808c23SAbylay Ospan 0x2B, 0xA6, 0x2B, 0xAD}, /* 24MHz XTal */ 219283808c23SAbylay Ospan {0x2C, 0xBD, 0x02, 0xCF, 0x04, 0xF8, 0x23, 0xA6, 0x29, 0xB0, 219383808c23SAbylay Ospan 0x26, 0xA9, 0x21, 0xA5} /* 41MHz XTal */ 219483808c23SAbylay Ospan }; 219583808c23SAbylay Ospan u8 itbCoef6bw[3][14] = { 219683808c23SAbylay Ospan {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00, 0xCF, 219783808c23SAbylay Ospan 0x00, 0xE6, 0x23, 0xA4}, /* 20.5MHz XTal */ 219883808c23SAbylay Ospan {0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E, 0x29, 0xA4, 219983808c23SAbylay Ospan 0x29, 0xA2, 0x29, 0xA8}, /* 24MHz XTal */ 220083808c23SAbylay Ospan {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00, 0xCF, 220183808c23SAbylay Ospan 0x00, 0xE6, 0x23, 0xA4} /* 41MHz XTal */ 220283808c23SAbylay Ospan }; 220383808c23SAbylay Ospan u8 itbCoef5bw[3][14] = { 220483808c23SAbylay Ospan {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00, 0xCF, 220583808c23SAbylay Ospan 0x00, 0xE6, 0x23, 0xA4}, /* 20.5MHz XTal */ 220683808c23SAbylay Ospan {0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E, 0x29, 0xA4, 220783808c23SAbylay Ospan 0x29, 0xA2, 0x29, 0xA8}, /* 24MHz XTal */ 220883808c23SAbylay Ospan {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00, 0xCF, 220983808c23SAbylay Ospan 0x00, 0xE6, 0x23, 0xA4} /* 41MHz XTal */ 221083808c23SAbylay Ospan }; 221183808c23SAbylay Ospan 221283808c23SAbylay Ospan /* Set SLV-T Bank : 0x13 */ 2213a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x13); 2214a6dc60ffSKozlov Sergey /* Echo performance optimization setting */ 221583808c23SAbylay Ospan data[0] = 0x01; 221683808c23SAbylay Ospan data[1] = 0x14; 221783808c23SAbylay Ospan cxd2841er_write_regs(priv, I2C_SLVT, 0x9C, data, 2); 221883808c23SAbylay Ospan 221983808c23SAbylay Ospan /* Set SLV-T Bank : 0x10 */ 2220a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10); 2221a6dc60ffSKozlov Sergey 2222a6dc60ffSKozlov Sergey switch (bandwidth) { 2223a6dc60ffSKozlov Sergey case 8000000: 222483808c23SAbylay Ospan /* <Timing Recovery setting> */ 222583808c23SAbylay Ospan cxd2841er_write_regs(priv, I2C_SLVT, 222683808c23SAbylay Ospan 0x9F, nominalRate8bw[priv->xtal], 5); 222783808c23SAbylay Ospan /* Group delay equaliser settings for 222883808c23SAbylay Ospan * ASCOT2D, ASCOT2E and ASCOT3 tuners 222983808c23SAbylay Ospan */ 223083808c23SAbylay Ospan cxd2841er_write_regs(priv, I2C_SLVT, 223183808c23SAbylay Ospan 0xA6, itbCoef8bw[priv->xtal], 14); 223283808c23SAbylay Ospan /* <IF freq setting> */ 223383808c23SAbylay Ospan iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 4.80); 223483808c23SAbylay Ospan data[0] = (u8) ((iffreq >> 16) & 0xff); 223583808c23SAbylay Ospan data[1] = (u8)((iffreq >> 8) & 0xff); 223683808c23SAbylay Ospan data[2] = (u8)(iffreq & 0xff); 223783808c23SAbylay Ospan cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3); 223883808c23SAbylay Ospan /* System bandwidth setting */ 223983808c23SAbylay Ospan cxd2841er_set_reg_bits( 224083808c23SAbylay Ospan priv, I2C_SLVT, 0xD7, 0x00, 0x07); 224183808c23SAbylay Ospan 224283808c23SAbylay Ospan /* Demod core latency setting */ 224383808c23SAbylay Ospan if (priv->xtal == SONY_XTAL_24000) { 224483808c23SAbylay Ospan data[0] = 0x15; 224583808c23SAbylay Ospan data[1] = 0x28; 224683808c23SAbylay Ospan } else { 224783808c23SAbylay Ospan data[0] = 0x01; 224883808c23SAbylay Ospan data[1] = 0xE0; 224983808c23SAbylay Ospan } 225083808c23SAbylay Ospan cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2); 225183808c23SAbylay Ospan 225283808c23SAbylay Ospan /* Notch filter setting */ 225383808c23SAbylay Ospan data[0] = 0x01; 225483808c23SAbylay Ospan data[1] = 0x02; 225583808c23SAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x17); 225683808c23SAbylay Ospan cxd2841er_write_regs(priv, I2C_SLVT, 0x38, data, 2); 2257a6dc60ffSKozlov Sergey break; 2258a6dc60ffSKozlov Sergey case 7000000: 225983808c23SAbylay Ospan /* <Timing Recovery setting> */ 226083808c23SAbylay Ospan cxd2841er_write_regs(priv, I2C_SLVT, 226183808c23SAbylay Ospan 0x9F, nominalRate7bw[priv->xtal], 5); 226283808c23SAbylay Ospan /* Group delay equaliser settings for 226383808c23SAbylay Ospan * ASCOT2D, ASCOT2E and ASCOT3 tuners 226483808c23SAbylay Ospan */ 226583808c23SAbylay Ospan cxd2841er_write_regs(priv, I2C_SLVT, 226683808c23SAbylay Ospan 0xA6, itbCoef7bw[priv->xtal], 14); 226783808c23SAbylay Ospan /* <IF freq setting> */ 226883808c23SAbylay Ospan iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 4.20); 226983808c23SAbylay Ospan data[0] = (u8) ((iffreq >> 16) & 0xff); 227083808c23SAbylay Ospan data[1] = (u8)((iffreq >> 8) & 0xff); 227183808c23SAbylay Ospan data[2] = (u8)(iffreq & 0xff); 227283808c23SAbylay Ospan cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3); 227383808c23SAbylay Ospan /* System bandwidth setting */ 227483808c23SAbylay Ospan cxd2841er_set_reg_bits( 227583808c23SAbylay Ospan priv, I2C_SLVT, 0xD7, 0x02, 0x07); 227683808c23SAbylay Ospan 227783808c23SAbylay Ospan /* Demod core latency setting */ 227883808c23SAbylay Ospan if (priv->xtal == SONY_XTAL_24000) { 227983808c23SAbylay Ospan data[0] = 0x1F; 228083808c23SAbylay Ospan data[1] = 0xF8; 228183808c23SAbylay Ospan } else { 228283808c23SAbylay Ospan data[0] = 0x12; 228383808c23SAbylay Ospan data[1] = 0xF8; 228483808c23SAbylay Ospan } 228583808c23SAbylay Ospan cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2); 228683808c23SAbylay Ospan 228783808c23SAbylay Ospan /* Notch filter setting */ 228883808c23SAbylay Ospan data[0] = 0x00; 228983808c23SAbylay Ospan data[1] = 0x03; 229083808c23SAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x17); 229183808c23SAbylay Ospan cxd2841er_write_regs(priv, I2C_SLVT, 0x38, data, 2); 2292a6dc60ffSKozlov Sergey break; 2293a6dc60ffSKozlov Sergey case 6000000: 229483808c23SAbylay Ospan /* <Timing Recovery setting> */ 229583808c23SAbylay Ospan cxd2841er_write_regs(priv, I2C_SLVT, 229683808c23SAbylay Ospan 0x9F, nominalRate6bw[priv->xtal], 5); 229783808c23SAbylay Ospan /* Group delay equaliser settings for 229883808c23SAbylay Ospan * ASCOT2D, ASCOT2E and ASCOT3 tuners 229983808c23SAbylay Ospan */ 230083808c23SAbylay Ospan cxd2841er_write_regs(priv, I2C_SLVT, 230183808c23SAbylay Ospan 0xA6, itbCoef6bw[priv->xtal], 14); 230283808c23SAbylay Ospan /* <IF freq setting> */ 230383808c23SAbylay Ospan iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 3.60); 230483808c23SAbylay Ospan data[0] = (u8) ((iffreq >> 16) & 0xff); 230583808c23SAbylay Ospan data[1] = (u8)((iffreq >> 8) & 0xff); 230683808c23SAbylay Ospan data[2] = (u8)(iffreq & 0xff); 230783808c23SAbylay Ospan cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3); 230883808c23SAbylay Ospan /* System bandwidth setting */ 230983808c23SAbylay Ospan cxd2841er_set_reg_bits( 231083808c23SAbylay Ospan priv, I2C_SLVT, 0xD7, 0x04, 0x07); 231183808c23SAbylay Ospan 231283808c23SAbylay Ospan /* Demod core latency setting */ 231383808c23SAbylay Ospan if (priv->xtal == SONY_XTAL_24000) { 231483808c23SAbylay Ospan data[0] = 0x25; 231583808c23SAbylay Ospan data[1] = 0x4C; 231683808c23SAbylay Ospan } else { 231783808c23SAbylay Ospan data[0] = 0x1F; 231883808c23SAbylay Ospan data[1] = 0xDC; 231983808c23SAbylay Ospan } 232083808c23SAbylay Ospan cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2); 232183808c23SAbylay Ospan 232283808c23SAbylay Ospan /* Notch filter setting */ 232383808c23SAbylay Ospan data[0] = 0x00; 232483808c23SAbylay Ospan data[1] = 0x03; 232583808c23SAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x17); 232683808c23SAbylay Ospan cxd2841er_write_regs(priv, I2C_SLVT, 0x38, data, 2); 2327a6dc60ffSKozlov Sergey break; 2328a6dc60ffSKozlov Sergey case 5000000: 232983808c23SAbylay Ospan /* <Timing Recovery setting> */ 233083808c23SAbylay Ospan cxd2841er_write_regs(priv, I2C_SLVT, 233183808c23SAbylay Ospan 0x9F, nominalRate5bw[priv->xtal], 5); 233283808c23SAbylay Ospan /* Group delay equaliser settings for 233383808c23SAbylay Ospan * ASCOT2D, ASCOT2E and ASCOT3 tuners 233483808c23SAbylay Ospan */ 233583808c23SAbylay Ospan cxd2841er_write_regs(priv, I2C_SLVT, 233683808c23SAbylay Ospan 0xA6, itbCoef5bw[priv->xtal], 14); 233783808c23SAbylay Ospan /* <IF freq setting> */ 233883808c23SAbylay Ospan iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 3.60); 233983808c23SAbylay Ospan data[0] = (u8) ((iffreq >> 16) & 0xff); 234083808c23SAbylay Ospan data[1] = (u8)((iffreq >> 8) & 0xff); 234183808c23SAbylay Ospan data[2] = (u8)(iffreq & 0xff); 234283808c23SAbylay Ospan cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3); 234383808c23SAbylay Ospan /* System bandwidth setting */ 234483808c23SAbylay Ospan cxd2841er_set_reg_bits( 234583808c23SAbylay Ospan priv, I2C_SLVT, 0xD7, 0x06, 0x07); 234683808c23SAbylay Ospan 234783808c23SAbylay Ospan /* Demod core latency setting */ 234883808c23SAbylay Ospan if (priv->xtal == SONY_XTAL_24000) { 234983808c23SAbylay Ospan data[0] = 0x2C; 235083808c23SAbylay Ospan data[1] = 0xC2; 235183808c23SAbylay Ospan } else { 235283808c23SAbylay Ospan data[0] = 0x26; 235383808c23SAbylay Ospan data[1] = 0x3C; 235483808c23SAbylay Ospan } 235583808c23SAbylay Ospan cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2); 235683808c23SAbylay Ospan 235783808c23SAbylay Ospan /* Notch filter setting */ 235883808c23SAbylay Ospan data[0] = 0x00; 235983808c23SAbylay Ospan data[1] = 0x03; 236083808c23SAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x17); 236183808c23SAbylay Ospan cxd2841er_write_regs(priv, I2C_SLVT, 0x38, data, 2); 236283808c23SAbylay Ospan break; 236383808c23SAbylay Ospan } 236483808c23SAbylay Ospan 236583808c23SAbylay Ospan return 0; 236683808c23SAbylay Ospan } 236783808c23SAbylay Ospan 236883808c23SAbylay Ospan static int cxd2841er_sleep_tc_to_active_i_band( 236983808c23SAbylay Ospan struct cxd2841er_priv *priv, u32 bandwidth) 237083808c23SAbylay Ospan { 237183808c23SAbylay Ospan u32 iffreq; 237283808c23SAbylay Ospan u8 data[3]; 237383808c23SAbylay Ospan 237483808c23SAbylay Ospan /* TRCG Nominal Rate */ 237583808c23SAbylay Ospan u8 nominalRate8bw[3][5] = { 237683808c23SAbylay Ospan {0x00, 0x00, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */ 237783808c23SAbylay Ospan {0x11, 0xB8, 0x00, 0x00, 0x00}, /* 24MHz XTal */ 237883808c23SAbylay Ospan {0x00, 0x00, 0x00, 0x00, 0x00} /* 41MHz XTal */ 237983808c23SAbylay Ospan }; 238083808c23SAbylay Ospan 238183808c23SAbylay Ospan u8 nominalRate7bw[3][5] = { 238283808c23SAbylay Ospan {0x00, 0x00, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */ 238383808c23SAbylay Ospan {0x14, 0x40, 0x00, 0x00, 0x00}, /* 24MHz XTal */ 238483808c23SAbylay Ospan {0x00, 0x00, 0x00, 0x00, 0x00} /* 41MHz XTal */ 238583808c23SAbylay Ospan }; 238683808c23SAbylay Ospan 238783808c23SAbylay Ospan u8 nominalRate6bw[3][5] = { 238883808c23SAbylay Ospan {0x14, 0x2E, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */ 238983808c23SAbylay Ospan {0x17, 0xA0, 0x00, 0x00, 0x00}, /* 24MHz XTal */ 239083808c23SAbylay Ospan {0x14, 0x2E, 0x00, 0x00, 0x00} /* 41MHz XTal */ 239183808c23SAbylay Ospan }; 239283808c23SAbylay Ospan 239383808c23SAbylay Ospan u8 itbCoef8bw[3][14] = { 239483808c23SAbylay Ospan {0x00}, /* 20.5MHz XTal */ 239583808c23SAbylay Ospan {0x2F, 0xBA, 0x28, 0x9B, 0x28, 0x9D, 0x28, 0xA1, 0x29, 239683808c23SAbylay Ospan 0xA5, 0x2A, 0xAC, 0x29, 0xB5}, /* 24MHz Xtal */ 239783808c23SAbylay Ospan {0x0}, /* 41MHz XTal */ 239883808c23SAbylay Ospan }; 239983808c23SAbylay Ospan 240083808c23SAbylay Ospan u8 itbCoef7bw[3][14] = { 240183808c23SAbylay Ospan {0x00}, /* 20.5MHz XTal */ 240283808c23SAbylay Ospan {0x30, 0xB1, 0x29, 0x9A, 0x28, 0x9C, 0x28, 0xA0, 0x29, 240383808c23SAbylay Ospan 0xA2, 0x2B, 0xA6, 0x2B, 0xAD}, /* 24MHz Xtal */ 240483808c23SAbylay Ospan {0x00}, /* 41MHz XTal */ 240583808c23SAbylay Ospan }; 240683808c23SAbylay Ospan 240783808c23SAbylay Ospan u8 itbCoef6bw[3][14] = { 240883808c23SAbylay Ospan {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00, 240983808c23SAbylay Ospan 0xCF, 0x00, 0xE6, 0x23, 0xA4}, /* 20.5MHz XTal */ 241083808c23SAbylay Ospan {0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E, 0x29, 241183808c23SAbylay Ospan 0xA4, 0x29, 0xA2, 0x29, 0xA8}, /* 24MHz Xtal */ 241283808c23SAbylay Ospan {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00, 241383808c23SAbylay Ospan 0xCF, 0x00, 0xE6, 0x23, 0xA4}, /* 41MHz XTal */ 241483808c23SAbylay Ospan }; 241583808c23SAbylay Ospan 241683808c23SAbylay Ospan dev_dbg(&priv->i2c->dev, "%s() bandwidth=%u\n", __func__, bandwidth); 241783808c23SAbylay Ospan /* Set SLV-T Bank : 0x10 */ 241883808c23SAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10); 241983808c23SAbylay Ospan 242083808c23SAbylay Ospan /* 20.5/41MHz Xtal support is not available 242183808c23SAbylay Ospan * on ISDB-T 7MHzBW and 8MHzBW 242283808c23SAbylay Ospan */ 242383808c23SAbylay Ospan if (priv->xtal != SONY_XTAL_24000 && bandwidth > 6000000) { 242483808c23SAbylay Ospan dev_err(&priv->i2c->dev, 242583808c23SAbylay Ospan "%s(): bandwidth %d supported only for 24MHz xtal\n", 242683808c23SAbylay Ospan __func__, bandwidth); 242783808c23SAbylay Ospan return -EINVAL; 242883808c23SAbylay Ospan } 242983808c23SAbylay Ospan 243083808c23SAbylay Ospan switch (bandwidth) { 243183808c23SAbylay Ospan case 8000000: 243283808c23SAbylay Ospan /* TRCG Nominal Rate */ 243383808c23SAbylay Ospan cxd2841er_write_regs(priv, I2C_SLVT, 243483808c23SAbylay Ospan 0x9F, nominalRate8bw[priv->xtal], 5); 243583808c23SAbylay Ospan /* Group delay equaliser settings for ASCOT tuners optimized */ 243683808c23SAbylay Ospan cxd2841er_write_regs(priv, I2C_SLVT, 243783808c23SAbylay Ospan 0xA6, itbCoef8bw[priv->xtal], 14); 243883808c23SAbylay Ospan 243983808c23SAbylay Ospan /* IF freq setting */ 244083808c23SAbylay Ospan iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 4.75); 244183808c23SAbylay Ospan data[0] = (u8) ((iffreq >> 16) & 0xff); 244283808c23SAbylay Ospan data[1] = (u8)((iffreq >> 8) & 0xff); 244383808c23SAbylay Ospan data[2] = (u8)(iffreq & 0xff); 244483808c23SAbylay Ospan cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3); 244583808c23SAbylay Ospan 244683808c23SAbylay Ospan /* System bandwidth setting */ 244783808c23SAbylay Ospan cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd7, 0x0, 0x7); 244883808c23SAbylay Ospan 244983808c23SAbylay Ospan /* Demod core latency setting */ 245083808c23SAbylay Ospan data[0] = 0x13; 245183808c23SAbylay Ospan data[1] = 0xFC; 245283808c23SAbylay Ospan cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2); 245383808c23SAbylay Ospan 245483808c23SAbylay Ospan /* Acquisition optimization setting */ 245583808c23SAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x12); 245683808c23SAbylay Ospan cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x71, 0x03, 0x07); 245783808c23SAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x15); 245883808c23SAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0xBE, 0x03); 245983808c23SAbylay Ospan break; 246083808c23SAbylay Ospan case 7000000: 246183808c23SAbylay Ospan /* TRCG Nominal Rate */ 246283808c23SAbylay Ospan cxd2841er_write_regs(priv, I2C_SLVT, 246383808c23SAbylay Ospan 0x9F, nominalRate7bw[priv->xtal], 5); 246483808c23SAbylay Ospan /* Group delay equaliser settings for ASCOT tuners optimized */ 246583808c23SAbylay Ospan cxd2841er_write_regs(priv, I2C_SLVT, 246683808c23SAbylay Ospan 0xA6, itbCoef7bw[priv->xtal], 14); 246783808c23SAbylay Ospan 246883808c23SAbylay Ospan /* IF freq setting */ 246983808c23SAbylay Ospan iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 4.15); 247083808c23SAbylay Ospan data[0] = (u8) ((iffreq >> 16) & 0xff); 247183808c23SAbylay Ospan data[1] = (u8)((iffreq >> 8) & 0xff); 247283808c23SAbylay Ospan data[2] = (u8)(iffreq & 0xff); 247383808c23SAbylay Ospan cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3); 247483808c23SAbylay Ospan 247583808c23SAbylay Ospan /* System bandwidth setting */ 247683808c23SAbylay Ospan cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd7, 0x02, 0x7); 247783808c23SAbylay Ospan 247883808c23SAbylay Ospan /* Demod core latency setting */ 247983808c23SAbylay Ospan data[0] = 0x1A; 248083808c23SAbylay Ospan data[1] = 0xFA; 248183808c23SAbylay Ospan cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2); 248283808c23SAbylay Ospan 248383808c23SAbylay Ospan /* Acquisition optimization setting */ 248483808c23SAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x12); 248583808c23SAbylay Ospan cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x71, 0x03, 0x07); 248683808c23SAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x15); 248783808c23SAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0xBE, 0x02); 248883808c23SAbylay Ospan break; 248983808c23SAbylay Ospan case 6000000: 249083808c23SAbylay Ospan /* TRCG Nominal Rate */ 249183808c23SAbylay Ospan cxd2841er_write_regs(priv, I2C_SLVT, 249283808c23SAbylay Ospan 0x9F, nominalRate6bw[priv->xtal], 5); 249383808c23SAbylay Ospan /* Group delay equaliser settings for ASCOT tuners optimized */ 249483808c23SAbylay Ospan cxd2841er_write_regs(priv, I2C_SLVT, 249583808c23SAbylay Ospan 0xA6, itbCoef6bw[priv->xtal], 14); 249683808c23SAbylay Ospan 249783808c23SAbylay Ospan /* IF freq setting */ 249883808c23SAbylay Ospan iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 3.55); 249983808c23SAbylay Ospan data[0] = (u8) ((iffreq >> 16) & 0xff); 250083808c23SAbylay Ospan data[1] = (u8)((iffreq >> 8) & 0xff); 250183808c23SAbylay Ospan data[2] = (u8)(iffreq & 0xff); 250283808c23SAbylay Ospan cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3); 250383808c23SAbylay Ospan 250483808c23SAbylay Ospan /* System bandwidth setting */ 250583808c23SAbylay Ospan cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd7, 0x04, 0x7); 250683808c23SAbylay Ospan 250783808c23SAbylay Ospan /* Demod core latency setting */ 250883808c23SAbylay Ospan if (priv->xtal == SONY_XTAL_24000) { 250983808c23SAbylay Ospan data[0] = 0x1F; 251083808c23SAbylay Ospan data[1] = 0x79; 251183808c23SAbylay Ospan } else { 251283808c23SAbylay Ospan data[0] = 0x1A; 251383808c23SAbylay Ospan data[1] = 0xE2; 251483808c23SAbylay Ospan } 251583808c23SAbylay Ospan cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2); 251683808c23SAbylay Ospan 251783808c23SAbylay Ospan /* Acquisition optimization setting */ 251883808c23SAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x12); 251983808c23SAbylay Ospan cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x71, 0x07, 0x07); 252083808c23SAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x15); 252183808c23SAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0xBE, 0x02); 2522a6dc60ffSKozlov Sergey break; 2523a6dc60ffSKozlov Sergey default: 2524a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s(): invalid bandwidth %d\n", 2525a6dc60ffSKozlov Sergey __func__, bandwidth); 2526a6dc60ffSKozlov Sergey return -EINVAL; 2527a6dc60ffSKozlov Sergey } 2528a6dc60ffSKozlov Sergey return 0; 2529a6dc60ffSKozlov Sergey } 2530a6dc60ffSKozlov Sergey 2531a6dc60ffSKozlov Sergey static int cxd2841er_sleep_tc_to_active_c_band(struct cxd2841er_priv *priv, 2532a6dc60ffSKozlov Sergey u32 bandwidth) 2533a6dc60ffSKozlov Sergey { 2534a6dc60ffSKozlov Sergey u8 bw7_8mhz_b10_a6[] = { 2535a6dc60ffSKozlov Sergey 0x2D, 0xC7, 0x04, 0xF4, 0x07, 0xC5, 0x2A, 0xB8, 2536a6dc60ffSKozlov Sergey 0x27, 0x9E, 0x27, 0xA4, 0x29, 0xAB }; 2537a6dc60ffSKozlov Sergey u8 bw6mhz_b10_a6[] = { 2538a6dc60ffSKozlov Sergey 0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 2539a6dc60ffSKozlov Sergey 0x00, 0xCF, 0x00, 0xE6, 0x23, 0xA4 }; 2540a6dc60ffSKozlov Sergey u8 b10_b6[3]; 2541a6dc60ffSKozlov Sergey u32 iffreq; 2542a6dc60ffSKozlov Sergey 25433f3b48a0SAbylay Ospan dev_dbg(&priv->i2c->dev, "%s() bw=%d\n", __func__, bandwidth); 2544a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10); 2545a6dc60ffSKozlov Sergey switch (bandwidth) { 2546a6dc60ffSKozlov Sergey case 8000000: 2547a6dc60ffSKozlov Sergey case 7000000: 2548a6dc60ffSKozlov Sergey cxd2841er_write_regs( 2549a6dc60ffSKozlov Sergey priv, I2C_SLVT, 0xa6, 2550a6dc60ffSKozlov Sergey bw7_8mhz_b10_a6, sizeof(bw7_8mhz_b10_a6)); 2551a6dc60ffSKozlov Sergey iffreq = MAKE_IFFREQ_CONFIG(4.9); 2552a6dc60ffSKozlov Sergey break; 2553a6dc60ffSKozlov Sergey case 6000000: 2554a6dc60ffSKozlov Sergey cxd2841er_write_regs( 2555a6dc60ffSKozlov Sergey priv, I2C_SLVT, 0xa6, 2556a6dc60ffSKozlov Sergey bw6mhz_b10_a6, sizeof(bw6mhz_b10_a6)); 2557a6dc60ffSKozlov Sergey iffreq = MAKE_IFFREQ_CONFIG(3.7); 2558a6dc60ffSKozlov Sergey break; 2559a6dc60ffSKozlov Sergey default: 25603f3b48a0SAbylay Ospan dev_err(&priv->i2c->dev, "%s(): unsupported bandwidth %d\n", 2561a6dc60ffSKozlov Sergey __func__, bandwidth); 2562a6dc60ffSKozlov Sergey return -EINVAL; 2563a6dc60ffSKozlov Sergey } 2564a6dc60ffSKozlov Sergey /* <IF freq setting> */ 2565a6dc60ffSKozlov Sergey b10_b6[0] = (u8) ((iffreq >> 16) & 0xff); 2566a6dc60ffSKozlov Sergey b10_b6[1] = (u8)((iffreq >> 8) & 0xff); 2567a6dc60ffSKozlov Sergey b10_b6[2] = (u8)(iffreq & 0xff); 2568a6dc60ffSKozlov Sergey cxd2841er_write_regs(priv, I2C_SLVT, 0xb6, b10_b6, sizeof(b10_b6)); 2569a6dc60ffSKozlov Sergey /* Set SLV-T Bank : 0x11 */ 2570a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11); 2571a6dc60ffSKozlov Sergey switch (bandwidth) { 2572a6dc60ffSKozlov Sergey case 8000000: 2573a6dc60ffSKozlov Sergey case 7000000: 2574a6dc60ffSKozlov Sergey cxd2841er_set_reg_bits( 2575a6dc60ffSKozlov Sergey priv, I2C_SLVT, 0xa3, 0x00, 0x1f); 2576a6dc60ffSKozlov Sergey break; 2577a6dc60ffSKozlov Sergey case 6000000: 2578a6dc60ffSKozlov Sergey cxd2841er_set_reg_bits( 2579a6dc60ffSKozlov Sergey priv, I2C_SLVT, 0xa3, 0x14, 0x1f); 2580a6dc60ffSKozlov Sergey break; 2581a6dc60ffSKozlov Sergey } 2582a6dc60ffSKozlov Sergey /* Set SLV-T Bank : 0x40 */ 2583a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40); 2584a6dc60ffSKozlov Sergey switch (bandwidth) { 2585a6dc60ffSKozlov Sergey case 8000000: 2586a6dc60ffSKozlov Sergey cxd2841er_set_reg_bits( 2587a6dc60ffSKozlov Sergey priv, I2C_SLVT, 0x26, 0x0b, 0x0f); 2588a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x27, 0x3e); 2589a6dc60ffSKozlov Sergey break; 2590a6dc60ffSKozlov Sergey case 7000000: 2591a6dc60ffSKozlov Sergey cxd2841er_set_reg_bits( 2592a6dc60ffSKozlov Sergey priv, I2C_SLVT, 0x26, 0x09, 0x0f); 2593a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x27, 0xd6); 2594a6dc60ffSKozlov Sergey break; 2595a6dc60ffSKozlov Sergey case 6000000: 2596a6dc60ffSKozlov Sergey cxd2841er_set_reg_bits( 2597a6dc60ffSKozlov Sergey priv, I2C_SLVT, 0x26, 0x08, 0x0f); 2598a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x27, 0x6e); 2599a6dc60ffSKozlov Sergey break; 2600a6dc60ffSKozlov Sergey } 2601a6dc60ffSKozlov Sergey return 0; 2602a6dc60ffSKozlov Sergey } 2603a6dc60ffSKozlov Sergey 2604a6dc60ffSKozlov Sergey static int cxd2841er_sleep_tc_to_active_t(struct cxd2841er_priv *priv, 2605a6dc60ffSKozlov Sergey u32 bandwidth) 2606a6dc60ffSKozlov Sergey { 2607a6dc60ffSKozlov Sergey u8 data[2] = { 0x09, 0x54 }; 260883808c23SAbylay Ospan u8 data24m[3] = {0xDC, 0x6C, 0x00}; 2609a6dc60ffSKozlov Sergey 2610a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s()\n", __func__); 2611a6dc60ffSKozlov Sergey cxd2841er_set_ts_clock_mode(priv, SYS_DVBT); 2612a6dc60ffSKozlov Sergey /* Set SLV-X Bank : 0x00 */ 2613a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00); 2614a6dc60ffSKozlov Sergey /* Set demod mode */ 2615a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x01); 2616a6dc60ffSKozlov Sergey /* Set SLV-T Bank : 0x00 */ 2617a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00); 2618a6dc60ffSKozlov Sergey /* Enable demod clock */ 2619a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01); 2620a6dc60ffSKozlov Sergey /* Disable RF level monitor */ 2621a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00); 2622a6dc60ffSKozlov Sergey /* Enable ADC clock */ 2623a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00); 2624a6dc60ffSKozlov Sergey /* Enable ADC 1 */ 2625a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x1a); 262683808c23SAbylay Ospan /* Enable ADC 2 & 3 */ 262783808c23SAbylay Ospan if (priv->xtal == SONY_XTAL_41000) { 262883808c23SAbylay Ospan data[0] = 0x0A; 262983808c23SAbylay Ospan data[1] = 0xD4; 263083808c23SAbylay Ospan } 2631a6dc60ffSKozlov Sergey cxd2841er_write_regs(priv, I2C_SLVT, 0x43, data, 2); 2632a6dc60ffSKozlov Sergey /* Enable ADC 4 */ 2633a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00); 2634a6dc60ffSKozlov Sergey /* Set SLV-T Bank : 0x10 */ 2635a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10); 2636a6dc60ffSKozlov Sergey /* IFAGC gain settings */ 2637a6dc60ffSKozlov Sergey cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd2, 0x0c, 0x1f); 2638a6dc60ffSKozlov Sergey /* Set SLV-T Bank : 0x11 */ 2639a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11); 2640a6dc60ffSKozlov Sergey /* BBAGC TARGET level setting */ 2641a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x6a, 0x50); 2642a6dc60ffSKozlov Sergey /* Set SLV-T Bank : 0x10 */ 2643a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10); 2644a6dc60ffSKozlov Sergey /* ASCOT setting ON */ 2645a6dc60ffSKozlov Sergey cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa5, 0x01, 0x01); 2646a6dc60ffSKozlov Sergey /* Set SLV-T Bank : 0x18 */ 2647a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x18); 2648a6dc60ffSKozlov Sergey /* Pre-RS BER moniter setting */ 2649a6dc60ffSKozlov Sergey cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x36, 0x40, 0x07); 2650a6dc60ffSKozlov Sergey /* FEC Auto Recovery setting */ 2651a6dc60ffSKozlov Sergey cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x30, 0x01, 0x01); 2652a6dc60ffSKozlov Sergey cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x31, 0x01, 0x01); 2653a6dc60ffSKozlov Sergey /* Set SLV-T Bank : 0x00 */ 2654a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00); 2655a6dc60ffSKozlov Sergey /* TSIF setting */ 2656a6dc60ffSKozlov Sergey cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xce, 0x01, 0x01); 2657a6dc60ffSKozlov Sergey cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcf, 0x01, 0x01); 265883808c23SAbylay Ospan 265983808c23SAbylay Ospan if (priv->xtal == SONY_XTAL_24000) { 266083808c23SAbylay Ospan /* Set SLV-T Bank : 0x10 */ 266183808c23SAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10); 266283808c23SAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0xBF, 0x60); 266383808c23SAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x18); 266483808c23SAbylay Ospan cxd2841er_write_regs(priv, I2C_SLVT, 0x24, data24m, 3); 266583808c23SAbylay Ospan } 266683808c23SAbylay Ospan 2667a6dc60ffSKozlov Sergey cxd2841er_sleep_tc_to_active_t_band(priv, bandwidth); 2668a6dc60ffSKozlov Sergey /* Set SLV-T Bank : 0x00 */ 2669a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00); 2670a6dc60ffSKozlov Sergey /* Disable HiZ Setting 1 */ 2671a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x28); 2672a6dc60ffSKozlov Sergey /* Disable HiZ Setting 2 */ 2673a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00); 2674a6dc60ffSKozlov Sergey priv->state = STATE_ACTIVE_TC; 2675a6dc60ffSKozlov Sergey return 0; 2676a6dc60ffSKozlov Sergey } 2677a6dc60ffSKozlov Sergey 2678a6dc60ffSKozlov Sergey static int cxd2841er_sleep_tc_to_active_t2(struct cxd2841er_priv *priv, 2679a6dc60ffSKozlov Sergey u32 bandwidth) 2680a6dc60ffSKozlov Sergey { 26816c77161aSAbylay Ospan u8 data[MAX_WRITE_REGSIZE]; 2682a6dc60ffSKozlov Sergey 2683a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s()\n", __func__); 2684a6dc60ffSKozlov Sergey cxd2841er_set_ts_clock_mode(priv, SYS_DVBT2); 2685a6dc60ffSKozlov Sergey /* Set SLV-X Bank : 0x00 */ 2686a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00); 2687a6dc60ffSKozlov Sergey /* Set demod mode */ 2688a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x02); 2689a6dc60ffSKozlov Sergey /* Set SLV-T Bank : 0x00 */ 2690a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00); 2691a6dc60ffSKozlov Sergey /* Enable demod clock */ 2692a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01); 2693a6dc60ffSKozlov Sergey /* Disable RF level monitor */ 26946c77161aSAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x59, 0x00); 2695a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00); 2696a6dc60ffSKozlov Sergey /* Enable ADC clock */ 2697a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00); 2698a6dc60ffSKozlov Sergey /* Enable ADC 1 */ 2699a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x1a); 27006c77161aSAbylay Ospan 27016c77161aSAbylay Ospan if (priv->xtal == SONY_XTAL_41000) { 27026c77161aSAbylay Ospan data[0] = 0x0A; 27036c77161aSAbylay Ospan data[1] = 0xD4; 27046c77161aSAbylay Ospan } else { 27056c77161aSAbylay Ospan data[0] = 0x09; 27066c77161aSAbylay Ospan data[1] = 0x54; 27076c77161aSAbylay Ospan } 27086c77161aSAbylay Ospan 2709a6dc60ffSKozlov Sergey cxd2841er_write_regs(priv, I2C_SLVT, 0x43, data, 2); 2710a6dc60ffSKozlov Sergey /* Enable ADC 4 */ 2711a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00); 2712a6dc60ffSKozlov Sergey /* Set SLV-T Bank : 0x10 */ 2713a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10); 2714a6dc60ffSKozlov Sergey /* IFAGC gain settings */ 2715a6dc60ffSKozlov Sergey cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd2, 0x0c, 0x1f); 2716a6dc60ffSKozlov Sergey /* Set SLV-T Bank : 0x11 */ 2717a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11); 2718a6dc60ffSKozlov Sergey /* BBAGC TARGET level setting */ 2719a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x6a, 0x50); 2720a6dc60ffSKozlov Sergey /* Set SLV-T Bank : 0x10 */ 2721a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10); 2722a6dc60ffSKozlov Sergey /* ASCOT setting ON */ 2723a6dc60ffSKozlov Sergey cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa5, 0x01, 0x01); 2724a6dc60ffSKozlov Sergey /* Set SLV-T Bank : 0x20 */ 2725a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20); 2726a6dc60ffSKozlov Sergey /* Acquisition optimization setting */ 2727a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x8b, 0x3c); 2728a6dc60ffSKozlov Sergey /* Set SLV-T Bank : 0x2b */ 2729a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2b); 2730a6dc60ffSKozlov Sergey cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x76, 0x20, 0x70); 27316c77161aSAbylay Ospan /* Set SLV-T Bank : 0x23 */ 27326c77161aSAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x23); 27336c77161aSAbylay Ospan /* L1 Control setting */ 27346c77161aSAbylay Ospan cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xE6, 0x00, 0x03); 2735a6dc60ffSKozlov Sergey /* Set SLV-T Bank : 0x00 */ 2736a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00); 2737a6dc60ffSKozlov Sergey /* TSIF setting */ 2738a6dc60ffSKozlov Sergey cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xce, 0x01, 0x01); 2739a6dc60ffSKozlov Sergey cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcf, 0x01, 0x01); 2740a6dc60ffSKozlov Sergey /* DVB-T2 initial setting */ 2741a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x13); 2742a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x83, 0x10); 2743a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x86, 0x34); 2744a6dc60ffSKozlov Sergey cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x9e, 0x09, 0x0f); 2745a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x9f, 0xd8); 2746a6dc60ffSKozlov Sergey /* Set SLV-T Bank : 0x2a */ 2747a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2a); 2748a6dc60ffSKozlov Sergey cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x38, 0x04, 0x0f); 2749a6dc60ffSKozlov Sergey /* Set SLV-T Bank : 0x2b */ 2750a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2b); 2751a6dc60ffSKozlov Sergey cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x11, 0x20, 0x3f); 2752a6dc60ffSKozlov Sergey 27536c77161aSAbylay Ospan /* 24MHz Xtal setting */ 27546c77161aSAbylay Ospan if (priv->xtal == SONY_XTAL_24000) { 27556c77161aSAbylay Ospan /* Set SLV-T Bank : 0x11 */ 27566c77161aSAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11); 27576c77161aSAbylay Ospan data[0] = 0xEB; 27586c77161aSAbylay Ospan data[1] = 0x03; 27596c77161aSAbylay Ospan data[2] = 0x3B; 27606c77161aSAbylay Ospan cxd2841er_write_regs(priv, I2C_SLVT, 0x33, data, 3); 27616c77161aSAbylay Ospan 27626c77161aSAbylay Ospan /* Set SLV-T Bank : 0x20 */ 27636c77161aSAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20); 27646c77161aSAbylay Ospan data[0] = 0x5E; 27656c77161aSAbylay Ospan data[1] = 0x5E; 27666c77161aSAbylay Ospan data[2] = 0x47; 27676c77161aSAbylay Ospan cxd2841er_write_regs(priv, I2C_SLVT, 0x95, data, 3); 27686c77161aSAbylay Ospan 27696c77161aSAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x99, 0x18); 27706c77161aSAbylay Ospan 27716c77161aSAbylay Ospan data[0] = 0x3F; 27726c77161aSAbylay Ospan data[1] = 0xFF; 27736c77161aSAbylay Ospan cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2); 27746c77161aSAbylay Ospan 27756c77161aSAbylay Ospan /* Set SLV-T Bank : 0x24 */ 27766c77161aSAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x24); 27776c77161aSAbylay Ospan data[0] = 0x0B; 27786c77161aSAbylay Ospan data[1] = 0x72; 27796c77161aSAbylay Ospan cxd2841er_write_regs(priv, I2C_SLVT, 0x34, data, 2); 27806c77161aSAbylay Ospan 27816c77161aSAbylay Ospan data[0] = 0x93; 27826c77161aSAbylay Ospan data[1] = 0xF3; 27836c77161aSAbylay Ospan data[2] = 0x00; 27846c77161aSAbylay Ospan cxd2841er_write_regs(priv, I2C_SLVT, 0xD2, data, 3); 27856c77161aSAbylay Ospan 27866c77161aSAbylay Ospan data[0] = 0x05; 27876c77161aSAbylay Ospan data[1] = 0xB8; 27886c77161aSAbylay Ospan data[2] = 0xD8; 27896c77161aSAbylay Ospan cxd2841er_write_regs(priv, I2C_SLVT, 0xDD, data, 3); 27906c77161aSAbylay Ospan 27916c77161aSAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0xE0, 0x00); 27926c77161aSAbylay Ospan 27936c77161aSAbylay Ospan /* Set SLV-T Bank : 0x25 */ 27946c77161aSAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x25); 27956c77161aSAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0xED, 0x60); 27966c77161aSAbylay Ospan 27976c77161aSAbylay Ospan /* Set SLV-T Bank : 0x27 */ 27986c77161aSAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27); 27996c77161aSAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0xFA, 0x34); 28006c77161aSAbylay Ospan 28016c77161aSAbylay Ospan /* Set SLV-T Bank : 0x2B */ 28026c77161aSAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2B); 28036c77161aSAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x4B, 0x2F); 28046c77161aSAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x9E, 0x0E); 28056c77161aSAbylay Ospan 28066c77161aSAbylay Ospan /* Set SLV-T Bank : 0x2D */ 28076c77161aSAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2D); 28086c77161aSAbylay Ospan data[0] = 0x89; 28096c77161aSAbylay Ospan data[1] = 0x89; 28106c77161aSAbylay Ospan cxd2841er_write_regs(priv, I2C_SLVT, 0x24, data, 2); 28116c77161aSAbylay Ospan 28126c77161aSAbylay Ospan /* Set SLV-T Bank : 0x5E */ 28136c77161aSAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x5E); 28146c77161aSAbylay Ospan data[0] = 0x24; 28156c77161aSAbylay Ospan data[1] = 0x95; 28166c77161aSAbylay Ospan cxd2841er_write_regs(priv, I2C_SLVT, 0x8C, data, 2); 28176c77161aSAbylay Ospan } 28186c77161aSAbylay Ospan 2819a6dc60ffSKozlov Sergey cxd2841er_sleep_tc_to_active_t2_band(priv, bandwidth); 2820a6dc60ffSKozlov Sergey 2821a6dc60ffSKozlov Sergey /* Set SLV-T Bank : 0x00 */ 2822a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00); 2823a6dc60ffSKozlov Sergey /* Disable HiZ Setting 1 */ 2824a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x28); 2825a6dc60ffSKozlov Sergey /* Disable HiZ Setting 2 */ 2826a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00); 2827a6dc60ffSKozlov Sergey priv->state = STATE_ACTIVE_TC; 2828a6dc60ffSKozlov Sergey return 0; 2829a6dc60ffSKozlov Sergey } 2830a6dc60ffSKozlov Sergey 283183808c23SAbylay Ospan /* ISDB-Tb part */ 283283808c23SAbylay Ospan static int cxd2841er_sleep_tc_to_active_i(struct cxd2841er_priv *priv, 283383808c23SAbylay Ospan u32 bandwidth) 283483808c23SAbylay Ospan { 283583808c23SAbylay Ospan u8 data[2] = { 0x09, 0x54 }; 283683808c23SAbylay Ospan u8 data24m[2] = {0x60, 0x00}; 283783808c23SAbylay Ospan u8 data24m2[3] = {0xB7, 0x1B, 0x00}; 283883808c23SAbylay Ospan 283983808c23SAbylay Ospan dev_dbg(&priv->i2c->dev, "%s()\n", __func__); 284083808c23SAbylay Ospan cxd2841er_set_ts_clock_mode(priv, SYS_DVBT); 284183808c23SAbylay Ospan /* Set SLV-X Bank : 0x00 */ 284283808c23SAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00); 284383808c23SAbylay Ospan /* Set demod mode */ 284483808c23SAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x06); 284583808c23SAbylay Ospan /* Set SLV-T Bank : 0x00 */ 284683808c23SAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00); 284783808c23SAbylay Ospan /* Enable demod clock */ 284883808c23SAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01); 284983808c23SAbylay Ospan /* Enable RF level monitor */ 285083808c23SAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x01); 285183808c23SAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x59, 0x01); 285283808c23SAbylay Ospan /* Enable ADC clock */ 285383808c23SAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00); 285483808c23SAbylay Ospan /* Enable ADC 1 */ 285583808c23SAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x1a); 285683808c23SAbylay Ospan /* xtal freq 20.5MHz or 24M */ 285783808c23SAbylay Ospan cxd2841er_write_regs(priv, I2C_SLVT, 0x43, data, 2); 285883808c23SAbylay Ospan /* Enable ADC 4 */ 285983808c23SAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00); 286083808c23SAbylay Ospan /* ASCOT setting ON */ 286183808c23SAbylay Ospan cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa5, 0x01, 0x01); 286283808c23SAbylay Ospan /* FEC Auto Recovery setting */ 286383808c23SAbylay Ospan cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x30, 0x01, 0x01); 286483808c23SAbylay Ospan cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x31, 0x00, 0x01); 286583808c23SAbylay Ospan /* ISDB-T initial setting */ 286683808c23SAbylay Ospan /* Set SLV-T Bank : 0x00 */ 286783808c23SAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00); 286883808c23SAbylay Ospan cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xce, 0x00, 0x01); 286983808c23SAbylay Ospan cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcf, 0x00, 0x01); 287083808c23SAbylay Ospan /* Set SLV-T Bank : 0x10 */ 287183808c23SAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10); 287283808c23SAbylay Ospan cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x69, 0x04, 0x07); 287383808c23SAbylay Ospan cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x6B, 0x03, 0x07); 287483808c23SAbylay Ospan cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x9D, 0x50, 0xFF); 287583808c23SAbylay Ospan cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xD3, 0x06, 0x1F); 287683808c23SAbylay Ospan cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xED, 0x00, 0x01); 287783808c23SAbylay Ospan cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xE2, 0xCE, 0x80); 287883808c23SAbylay Ospan cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xF2, 0x13, 0x10); 287983808c23SAbylay Ospan cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xDE, 0x2E, 0x3F); 288083808c23SAbylay Ospan /* Set SLV-T Bank : 0x15 */ 288183808c23SAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x15); 288283808c23SAbylay Ospan cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xDE, 0x02, 0x03); 288383808c23SAbylay Ospan /* Set SLV-T Bank : 0x1E */ 288483808c23SAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x1E); 288583808c23SAbylay Ospan cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x73, 0x68, 0xFF); 288683808c23SAbylay Ospan /* Set SLV-T Bank : 0x63 */ 288783808c23SAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x63); 288883808c23SAbylay Ospan cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x81, 0x00, 0x01); 288983808c23SAbylay Ospan 289083808c23SAbylay Ospan /* for xtal 24MHz */ 289183808c23SAbylay Ospan /* Set SLV-T Bank : 0x10 */ 289283808c23SAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10); 289383808c23SAbylay Ospan cxd2841er_write_regs(priv, I2C_SLVT, 0xBF, data24m, 2); 289483808c23SAbylay Ospan /* Set SLV-T Bank : 0x60 */ 289583808c23SAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60); 289683808c23SAbylay Ospan cxd2841er_write_regs(priv, I2C_SLVT, 0xA8, data24m2, 3); 289783808c23SAbylay Ospan 289883808c23SAbylay Ospan cxd2841er_sleep_tc_to_active_i_band(priv, bandwidth); 289983808c23SAbylay Ospan /* Set SLV-T Bank : 0x00 */ 290083808c23SAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00); 290183808c23SAbylay Ospan /* Disable HiZ Setting 1 */ 290283808c23SAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x28); 290383808c23SAbylay Ospan /* Disable HiZ Setting 2 */ 290483808c23SAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00); 290583808c23SAbylay Ospan priv->state = STATE_ACTIVE_TC; 290683808c23SAbylay Ospan return 0; 290783808c23SAbylay Ospan } 290883808c23SAbylay Ospan 2909a6dc60ffSKozlov Sergey static int cxd2841er_sleep_tc_to_active_c(struct cxd2841er_priv *priv, 2910a6dc60ffSKozlov Sergey u32 bandwidth) 2911a6dc60ffSKozlov Sergey { 2912a6dc60ffSKozlov Sergey u8 data[2] = { 0x09, 0x54 }; 2913a6dc60ffSKozlov Sergey 2914a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s()\n", __func__); 2915a6dc60ffSKozlov Sergey cxd2841er_set_ts_clock_mode(priv, SYS_DVBC_ANNEX_A); 2916a6dc60ffSKozlov Sergey /* Set SLV-X Bank : 0x00 */ 2917a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00); 2918a6dc60ffSKozlov Sergey /* Set demod mode */ 2919a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x04); 2920a6dc60ffSKozlov Sergey /* Set SLV-T Bank : 0x00 */ 2921a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00); 2922a6dc60ffSKozlov Sergey /* Enable demod clock */ 2923a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01); 2924a6dc60ffSKozlov Sergey /* Disable RF level monitor */ 2925a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00); 2926a6dc60ffSKozlov Sergey /* Enable ADC clock */ 2927a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00); 2928a6dc60ffSKozlov Sergey /* Enable ADC 1 */ 2929a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x1a); 2930a6dc60ffSKozlov Sergey /* xtal freq 20.5MHz */ 2931a6dc60ffSKozlov Sergey cxd2841er_write_regs(priv, I2C_SLVT, 0x43, data, 2); 2932a6dc60ffSKozlov Sergey /* Enable ADC 4 */ 2933a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00); 2934a6dc60ffSKozlov Sergey /* Set SLV-T Bank : 0x10 */ 2935a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10); 2936a6dc60ffSKozlov Sergey /* IFAGC gain settings */ 2937a6dc60ffSKozlov Sergey cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd2, 0x09, 0x1f); 2938a6dc60ffSKozlov Sergey /* Set SLV-T Bank : 0x11 */ 2939a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11); 2940a6dc60ffSKozlov Sergey /* BBAGC TARGET level setting */ 2941a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x6a, 0x48); 2942a6dc60ffSKozlov Sergey /* Set SLV-T Bank : 0x10 */ 2943a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10); 2944a6dc60ffSKozlov Sergey /* ASCOT setting ON */ 2945a6dc60ffSKozlov Sergey cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa5, 0x01, 0x01); 2946a6dc60ffSKozlov Sergey /* Set SLV-T Bank : 0x40 */ 2947a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40); 2948a6dc60ffSKozlov Sergey /* Demod setting */ 2949a6dc60ffSKozlov Sergey cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xc3, 0x00, 0x04); 2950a6dc60ffSKozlov Sergey /* Set SLV-T Bank : 0x00 */ 2951a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00); 2952a6dc60ffSKozlov Sergey /* TSIF setting */ 2953a6dc60ffSKozlov Sergey cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xce, 0x01, 0x01); 2954a6dc60ffSKozlov Sergey cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcf, 0x01, 0x01); 2955a6dc60ffSKozlov Sergey 29563f3b48a0SAbylay Ospan cxd2841er_sleep_tc_to_active_c_band(priv, bandwidth); 2957a6dc60ffSKozlov Sergey /* Set SLV-T Bank : 0x00 */ 2958a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00); 2959a6dc60ffSKozlov Sergey /* Disable HiZ Setting 1 */ 2960a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x28); 2961a6dc60ffSKozlov Sergey /* Disable HiZ Setting 2 */ 2962a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00); 2963a6dc60ffSKozlov Sergey priv->state = STATE_ACTIVE_TC; 2964a6dc60ffSKozlov Sergey return 0; 2965a6dc60ffSKozlov Sergey } 2966a6dc60ffSKozlov Sergey 29677e3e68bcSMauro Carvalho Chehab static int cxd2841er_get_frontend(struct dvb_frontend *fe, 29687e3e68bcSMauro Carvalho Chehab struct dtv_frontend_properties *p) 2969a6dc60ffSKozlov Sergey { 2970a6dc60ffSKozlov Sergey enum fe_status status = 0; 2971a6dc60ffSKozlov Sergey struct cxd2841er_priv *priv = fe->demodulator_priv; 2972a6dc60ffSKozlov Sergey 2973a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s()\n", __func__); 2974a6dc60ffSKozlov Sergey if (priv->state == STATE_ACTIVE_S) 2975a6dc60ffSKozlov Sergey cxd2841er_read_status_s(fe, &status); 2976a6dc60ffSKozlov Sergey else if (priv->state == STATE_ACTIVE_TC) 2977a6dc60ffSKozlov Sergey cxd2841er_read_status_tc(fe, &status); 2978a6dc60ffSKozlov Sergey 29795fda1b65SMauro Carvalho Chehab cxd2841er_read_signal_strength(fe); 2980d0e20e13SMauro Carvalho Chehab 2981d0e20e13SMauro Carvalho Chehab if (status & FE_HAS_LOCK) { 2982f1b26622SMauro Carvalho Chehab cxd2841er_read_snr(fe); 2983f1b26622SMauro Carvalho Chehab cxd2841er_read_ucblocks(fe); 2984d0e20e13SMauro Carvalho Chehab 2985f1b26622SMauro Carvalho Chehab cxd2841er_read_ber(fe); 2986a6dc60ffSKozlov Sergey } else { 2987a6dc60ffSKozlov Sergey p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 2988a6dc60ffSKozlov Sergey p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 2989a6dc60ffSKozlov Sergey p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 29904216be14SMauro Carvalho Chehab p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 2991a6dc60ffSKozlov Sergey } 2992a6dc60ffSKozlov Sergey return 0; 2993a6dc60ffSKozlov Sergey } 2994a6dc60ffSKozlov Sergey 2995a6dc60ffSKozlov Sergey static int cxd2841er_set_frontend_s(struct dvb_frontend *fe) 2996a6dc60ffSKozlov Sergey { 2997a6dc60ffSKozlov Sergey int ret = 0, i, timeout, carr_offset; 2998a6dc60ffSKozlov Sergey enum fe_status status; 2999a6dc60ffSKozlov Sergey struct cxd2841er_priv *priv = fe->demodulator_priv; 3000a6dc60ffSKozlov Sergey struct dtv_frontend_properties *p = &fe->dtv_property_cache; 3001a6dc60ffSKozlov Sergey u32 symbol_rate = p->symbol_rate/1000; 3002a6dc60ffSKozlov Sergey 300383808c23SAbylay Ospan dev_dbg(&priv->i2c->dev, "%s(): %s frequency=%d symbol_rate=%d xtal=%d\n", 3004a6dc60ffSKozlov Sergey __func__, 3005a6dc60ffSKozlov Sergey (p->delivery_system == SYS_DVBS ? "DVB-S" : "DVB-S2"), 300683808c23SAbylay Ospan p->frequency, symbol_rate, priv->xtal); 3007a6dc60ffSKozlov Sergey switch (priv->state) { 3008a6dc60ffSKozlov Sergey case STATE_SLEEP_S: 3009a6dc60ffSKozlov Sergey ret = cxd2841er_sleep_s_to_active_s( 3010a6dc60ffSKozlov Sergey priv, p->delivery_system, symbol_rate); 3011a6dc60ffSKozlov Sergey break; 3012a6dc60ffSKozlov Sergey case STATE_ACTIVE_S: 3013a6dc60ffSKozlov Sergey ret = cxd2841er_retune_active(priv, p); 3014a6dc60ffSKozlov Sergey break; 3015a6dc60ffSKozlov Sergey default: 3016a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n", 3017a6dc60ffSKozlov Sergey __func__, priv->state); 3018a6dc60ffSKozlov Sergey ret = -EINVAL; 3019a6dc60ffSKozlov Sergey goto done; 3020a6dc60ffSKozlov Sergey } 3021a6dc60ffSKozlov Sergey if (ret) { 3022a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s(): tune failed\n", __func__); 3023a6dc60ffSKozlov Sergey goto done; 3024a6dc60ffSKozlov Sergey } 3025a6dc60ffSKozlov Sergey if (fe->ops.i2c_gate_ctrl) 3026a6dc60ffSKozlov Sergey fe->ops.i2c_gate_ctrl(fe, 1); 3027a6dc60ffSKozlov Sergey if (fe->ops.tuner_ops.set_params) 3028a6dc60ffSKozlov Sergey fe->ops.tuner_ops.set_params(fe); 3029a6dc60ffSKozlov Sergey if (fe->ops.i2c_gate_ctrl) 3030a6dc60ffSKozlov Sergey fe->ops.i2c_gate_ctrl(fe, 0); 3031a6dc60ffSKozlov Sergey cxd2841er_tune_done(priv); 3032a6dc60ffSKozlov Sergey timeout = ((3000000 + (symbol_rate - 1)) / symbol_rate) + 150; 3033a6dc60ffSKozlov Sergey for (i = 0; i < timeout / CXD2841ER_DVBS_POLLING_INVL; i++) { 3034a6dc60ffSKozlov Sergey usleep_range(CXD2841ER_DVBS_POLLING_INVL*1000, 3035a6dc60ffSKozlov Sergey (CXD2841ER_DVBS_POLLING_INVL + 2) * 1000); 3036a6dc60ffSKozlov Sergey cxd2841er_read_status_s(fe, &status); 3037a6dc60ffSKozlov Sergey if (status & FE_HAS_LOCK) 3038a6dc60ffSKozlov Sergey break; 3039a6dc60ffSKozlov Sergey } 3040a6dc60ffSKozlov Sergey if (status & FE_HAS_LOCK) { 3041a6dc60ffSKozlov Sergey if (cxd2841er_get_carrier_offset_s_s2( 3042a6dc60ffSKozlov Sergey priv, &carr_offset)) { 3043a6dc60ffSKozlov Sergey ret = -EINVAL; 3044a6dc60ffSKozlov Sergey goto done; 3045a6dc60ffSKozlov Sergey } 3046a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s(): carrier_offset=%d\n", 3047a6dc60ffSKozlov Sergey __func__, carr_offset); 3048a6dc60ffSKozlov Sergey } 3049a6dc60ffSKozlov Sergey done: 3050d0e20e13SMauro Carvalho Chehab /* Reset stats */ 3051d0e20e13SMauro Carvalho Chehab p->strength.stat[0].scale = FE_SCALE_RELATIVE; 3052d0e20e13SMauro Carvalho Chehab p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 3053d0e20e13SMauro Carvalho Chehab p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 3054d0e20e13SMauro Carvalho Chehab p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 30554216be14SMauro Carvalho Chehab p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 3056d0e20e13SMauro Carvalho Chehab 3057a6dc60ffSKozlov Sergey return ret; 3058a6dc60ffSKozlov Sergey } 3059a6dc60ffSKozlov Sergey 3060a6dc60ffSKozlov Sergey static int cxd2841er_set_frontend_tc(struct dvb_frontend *fe) 3061a6dc60ffSKozlov Sergey { 3062a6dc60ffSKozlov Sergey int ret = 0, timeout; 3063a6dc60ffSKozlov Sergey enum fe_status status; 3064a6dc60ffSKozlov Sergey struct cxd2841er_priv *priv = fe->demodulator_priv; 3065a6dc60ffSKozlov Sergey struct dtv_frontend_properties *p = &fe->dtv_property_cache; 3066a6dc60ffSKozlov Sergey 30673f3b48a0SAbylay Ospan dev_dbg(&priv->i2c->dev, "%s() delivery_system=%d bandwidth_hz=%d\n", 30683f3b48a0SAbylay Ospan __func__, p->delivery_system, p->bandwidth_hz); 3069a6dc60ffSKozlov Sergey if (p->delivery_system == SYS_DVBT) { 3070a6dc60ffSKozlov Sergey priv->system = SYS_DVBT; 3071a6dc60ffSKozlov Sergey switch (priv->state) { 3072a6dc60ffSKozlov Sergey case STATE_SLEEP_TC: 3073a6dc60ffSKozlov Sergey ret = cxd2841er_sleep_tc_to_active_t( 3074a6dc60ffSKozlov Sergey priv, p->bandwidth_hz); 3075a6dc60ffSKozlov Sergey break; 3076a6dc60ffSKozlov Sergey case STATE_ACTIVE_TC: 3077a6dc60ffSKozlov Sergey ret = cxd2841er_retune_active(priv, p); 3078a6dc60ffSKozlov Sergey break; 3079a6dc60ffSKozlov Sergey default: 3080a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n", 3081a6dc60ffSKozlov Sergey __func__, priv->state); 3082a6dc60ffSKozlov Sergey ret = -EINVAL; 3083a6dc60ffSKozlov Sergey } 3084a6dc60ffSKozlov Sergey } else if (p->delivery_system == SYS_DVBT2) { 3085a6dc60ffSKozlov Sergey priv->system = SYS_DVBT2; 3086a6dc60ffSKozlov Sergey cxd2841er_dvbt2_set_plp_config(priv, 3087a6dc60ffSKozlov Sergey (int)(p->stream_id > 255), p->stream_id); 3088a6dc60ffSKozlov Sergey cxd2841er_dvbt2_set_profile(priv, DVBT2_PROFILE_BASE); 3089a6dc60ffSKozlov Sergey switch (priv->state) { 3090a6dc60ffSKozlov Sergey case STATE_SLEEP_TC: 3091a6dc60ffSKozlov Sergey ret = cxd2841er_sleep_tc_to_active_t2(priv, 3092a6dc60ffSKozlov Sergey p->bandwidth_hz); 3093a6dc60ffSKozlov Sergey break; 3094a6dc60ffSKozlov Sergey case STATE_ACTIVE_TC: 3095a6dc60ffSKozlov Sergey ret = cxd2841er_retune_active(priv, p); 3096a6dc60ffSKozlov Sergey break; 3097a6dc60ffSKozlov Sergey default: 3098a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n", 3099a6dc60ffSKozlov Sergey __func__, priv->state); 3100a6dc60ffSKozlov Sergey ret = -EINVAL; 3101a6dc60ffSKozlov Sergey } 310283808c23SAbylay Ospan } else if (p->delivery_system == SYS_ISDBT) { 310383808c23SAbylay Ospan priv->system = SYS_ISDBT; 310483808c23SAbylay Ospan switch (priv->state) { 310583808c23SAbylay Ospan case STATE_SLEEP_TC: 310683808c23SAbylay Ospan ret = cxd2841er_sleep_tc_to_active_i( 310783808c23SAbylay Ospan priv, p->bandwidth_hz); 310883808c23SAbylay Ospan break; 310983808c23SAbylay Ospan case STATE_ACTIVE_TC: 311083808c23SAbylay Ospan ret = cxd2841er_retune_active(priv, p); 311183808c23SAbylay Ospan break; 311283808c23SAbylay Ospan default: 311383808c23SAbylay Ospan dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n", 311483808c23SAbylay Ospan __func__, priv->state); 311583808c23SAbylay Ospan ret = -EINVAL; 311683808c23SAbylay Ospan } 3117a6dc60ffSKozlov Sergey } else if (p->delivery_system == SYS_DVBC_ANNEX_A || 3118a6dc60ffSKozlov Sergey p->delivery_system == SYS_DVBC_ANNEX_C) { 3119a6dc60ffSKozlov Sergey priv->system = SYS_DVBC_ANNEX_A; 31203f3b48a0SAbylay Ospan /* correct bandwidth */ 31213f3b48a0SAbylay Ospan if (p->bandwidth_hz != 6000000 && 31223f3b48a0SAbylay Ospan p->bandwidth_hz != 7000000 && 31233f3b48a0SAbylay Ospan p->bandwidth_hz != 8000000) { 31243f3b48a0SAbylay Ospan p->bandwidth_hz = 8000000; 31253f3b48a0SAbylay Ospan dev_dbg(&priv->i2c->dev, "%s(): forcing bandwidth to %d\n", 31263f3b48a0SAbylay Ospan __func__, p->bandwidth_hz); 31273f3b48a0SAbylay Ospan } 31283f3b48a0SAbylay Ospan 3129a6dc60ffSKozlov Sergey switch (priv->state) { 3130a6dc60ffSKozlov Sergey case STATE_SLEEP_TC: 3131a6dc60ffSKozlov Sergey ret = cxd2841er_sleep_tc_to_active_c( 3132a6dc60ffSKozlov Sergey priv, p->bandwidth_hz); 3133a6dc60ffSKozlov Sergey break; 3134a6dc60ffSKozlov Sergey case STATE_ACTIVE_TC: 3135a6dc60ffSKozlov Sergey ret = cxd2841er_retune_active(priv, p); 3136a6dc60ffSKozlov Sergey break; 3137a6dc60ffSKozlov Sergey default: 3138a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n", 3139a6dc60ffSKozlov Sergey __func__, priv->state); 3140a6dc60ffSKozlov Sergey ret = -EINVAL; 3141a6dc60ffSKozlov Sergey } 3142a6dc60ffSKozlov Sergey } else { 3143a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, 3144a6dc60ffSKozlov Sergey "%s(): invalid delivery system %d\n", 3145a6dc60ffSKozlov Sergey __func__, p->delivery_system); 3146a6dc60ffSKozlov Sergey ret = -EINVAL; 3147a6dc60ffSKozlov Sergey } 3148a6dc60ffSKozlov Sergey if (ret) 3149a6dc60ffSKozlov Sergey goto done; 3150a6dc60ffSKozlov Sergey if (fe->ops.i2c_gate_ctrl) 3151a6dc60ffSKozlov Sergey fe->ops.i2c_gate_ctrl(fe, 1); 3152a6dc60ffSKozlov Sergey if (fe->ops.tuner_ops.set_params) 3153a6dc60ffSKozlov Sergey fe->ops.tuner_ops.set_params(fe); 3154a6dc60ffSKozlov Sergey if (fe->ops.i2c_gate_ctrl) 3155a6dc60ffSKozlov Sergey fe->ops.i2c_gate_ctrl(fe, 0); 3156a6dc60ffSKozlov Sergey cxd2841er_tune_done(priv); 3157a6dc60ffSKozlov Sergey timeout = 2500; 3158a6dc60ffSKozlov Sergey while (timeout > 0) { 3159a6dc60ffSKozlov Sergey ret = cxd2841er_read_status_tc(fe, &status); 3160a6dc60ffSKozlov Sergey if (ret) 3161a6dc60ffSKozlov Sergey goto done; 3162a6dc60ffSKozlov Sergey if (status & FE_HAS_LOCK) 3163a6dc60ffSKozlov Sergey break; 3164a6dc60ffSKozlov Sergey msleep(20); 3165a6dc60ffSKozlov Sergey timeout -= 20; 3166a6dc60ffSKozlov Sergey } 3167a6dc60ffSKozlov Sergey if (timeout < 0) 3168a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, 3169a6dc60ffSKozlov Sergey "%s(): LOCK wait timeout\n", __func__); 3170a6dc60ffSKozlov Sergey done: 3171a6dc60ffSKozlov Sergey return ret; 3172a6dc60ffSKozlov Sergey } 3173a6dc60ffSKozlov Sergey 3174a6dc60ffSKozlov Sergey static int cxd2841er_tune_s(struct dvb_frontend *fe, 3175a6dc60ffSKozlov Sergey bool re_tune, 3176a6dc60ffSKozlov Sergey unsigned int mode_flags, 3177a6dc60ffSKozlov Sergey unsigned int *delay, 3178a6dc60ffSKozlov Sergey enum fe_status *status) 3179a6dc60ffSKozlov Sergey { 3180a6dc60ffSKozlov Sergey int ret, carrier_offset; 3181a6dc60ffSKozlov Sergey struct cxd2841er_priv *priv = fe->demodulator_priv; 3182a6dc60ffSKozlov Sergey struct dtv_frontend_properties *p = &fe->dtv_property_cache; 3183a6dc60ffSKozlov Sergey 3184a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s() re_tune=%d\n", __func__, re_tune); 3185a6dc60ffSKozlov Sergey if (re_tune) { 3186a6dc60ffSKozlov Sergey ret = cxd2841er_set_frontend_s(fe); 3187a6dc60ffSKozlov Sergey if (ret) 3188a6dc60ffSKozlov Sergey return ret; 3189a6dc60ffSKozlov Sergey cxd2841er_read_status_s(fe, status); 3190a6dc60ffSKozlov Sergey if (*status & FE_HAS_LOCK) { 3191a6dc60ffSKozlov Sergey if (cxd2841er_get_carrier_offset_s_s2( 3192a6dc60ffSKozlov Sergey priv, &carrier_offset)) 3193a6dc60ffSKozlov Sergey return -EINVAL; 3194a6dc60ffSKozlov Sergey p->frequency += carrier_offset; 3195a6dc60ffSKozlov Sergey ret = cxd2841er_set_frontend_s(fe); 3196a6dc60ffSKozlov Sergey if (ret) 3197a6dc60ffSKozlov Sergey return ret; 3198a6dc60ffSKozlov Sergey } 3199a6dc60ffSKozlov Sergey } 3200a6dc60ffSKozlov Sergey *delay = HZ / 5; 3201a6dc60ffSKozlov Sergey return cxd2841er_read_status_s(fe, status); 3202a6dc60ffSKozlov Sergey } 3203a6dc60ffSKozlov Sergey 3204a6dc60ffSKozlov Sergey static int cxd2841er_tune_tc(struct dvb_frontend *fe, 3205a6dc60ffSKozlov Sergey bool re_tune, 3206a6dc60ffSKozlov Sergey unsigned int mode_flags, 3207a6dc60ffSKozlov Sergey unsigned int *delay, 3208a6dc60ffSKozlov Sergey enum fe_status *status) 3209a6dc60ffSKozlov Sergey { 3210a6dc60ffSKozlov Sergey int ret, carrier_offset; 3211a6dc60ffSKozlov Sergey struct cxd2841er_priv *priv = fe->demodulator_priv; 3212a6dc60ffSKozlov Sergey struct dtv_frontend_properties *p = &fe->dtv_property_cache; 3213a6dc60ffSKozlov Sergey 32143f3b48a0SAbylay Ospan dev_dbg(&priv->i2c->dev, "%s(): re_tune %d bandwidth=%d\n", __func__, 32153f3b48a0SAbylay Ospan re_tune, p->bandwidth_hz); 3216a6dc60ffSKozlov Sergey if (re_tune) { 3217a6dc60ffSKozlov Sergey ret = cxd2841er_set_frontend_tc(fe); 3218a6dc60ffSKozlov Sergey if (ret) 3219a6dc60ffSKozlov Sergey return ret; 3220a6dc60ffSKozlov Sergey cxd2841er_read_status_tc(fe, status); 3221a6dc60ffSKozlov Sergey if (*status & FE_HAS_LOCK) { 3222a6dc60ffSKozlov Sergey switch (priv->system) { 322376344a3fSMauro Carvalho Chehab case SYS_ISDBT: 322476344a3fSMauro Carvalho Chehab ret = cxd2841er_get_carrier_offset_i( 322576344a3fSMauro Carvalho Chehab priv, p->bandwidth_hz, 322676344a3fSMauro Carvalho Chehab &carrier_offset); 322776344a3fSMauro Carvalho Chehab break; 3228a6dc60ffSKozlov Sergey case SYS_DVBT: 3229c5ea46daSAbylay Ospan ret = cxd2841er_get_carrier_offset_t( 3230c5ea46daSAbylay Ospan priv, p->bandwidth_hz, 3231c5ea46daSAbylay Ospan &carrier_offset); 3232c5ea46daSAbylay Ospan break; 3233a6dc60ffSKozlov Sergey case SYS_DVBT2: 3234a6dc60ffSKozlov Sergey ret = cxd2841er_get_carrier_offset_t2( 3235a6dc60ffSKozlov Sergey priv, p->bandwidth_hz, 3236a6dc60ffSKozlov Sergey &carrier_offset); 3237a6dc60ffSKozlov Sergey break; 3238a6dc60ffSKozlov Sergey case SYS_DVBC_ANNEX_A: 3239a6dc60ffSKozlov Sergey ret = cxd2841er_get_carrier_offset_c( 3240a6dc60ffSKozlov Sergey priv, &carrier_offset); 3241a6dc60ffSKozlov Sergey break; 3242a6dc60ffSKozlov Sergey default: 3243a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, 3244a6dc60ffSKozlov Sergey "%s(): invalid delivery system %d\n", 3245a6dc60ffSKozlov Sergey __func__, priv->system); 3246a6dc60ffSKozlov Sergey return -EINVAL; 3247a6dc60ffSKozlov Sergey } 3248a6dc60ffSKozlov Sergey if (ret) 3249a6dc60ffSKozlov Sergey return ret; 3250a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s(): carrier offset %d\n", 3251a6dc60ffSKozlov Sergey __func__, carrier_offset); 3252a6dc60ffSKozlov Sergey p->frequency += carrier_offset; 3253a6dc60ffSKozlov Sergey ret = cxd2841er_set_frontend_tc(fe); 3254a6dc60ffSKozlov Sergey if (ret) 3255a6dc60ffSKozlov Sergey return ret; 3256a6dc60ffSKozlov Sergey } 3257a6dc60ffSKozlov Sergey } 3258a6dc60ffSKozlov Sergey *delay = HZ / 5; 3259a6dc60ffSKozlov Sergey return cxd2841er_read_status_tc(fe, status); 3260a6dc60ffSKozlov Sergey } 3261a6dc60ffSKozlov Sergey 3262a6dc60ffSKozlov Sergey static int cxd2841er_sleep_s(struct dvb_frontend *fe) 3263a6dc60ffSKozlov Sergey { 3264a6dc60ffSKozlov Sergey struct cxd2841er_priv *priv = fe->demodulator_priv; 3265a6dc60ffSKozlov Sergey 3266a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s()\n", __func__); 3267a6dc60ffSKozlov Sergey cxd2841er_active_s_to_sleep_s(fe->demodulator_priv); 3268a6dc60ffSKozlov Sergey cxd2841er_sleep_s_to_shutdown(fe->demodulator_priv); 3269a6dc60ffSKozlov Sergey return 0; 3270a6dc60ffSKozlov Sergey } 3271a6dc60ffSKozlov Sergey 3272a6dc60ffSKozlov Sergey static int cxd2841er_sleep_tc(struct dvb_frontend *fe) 3273a6dc60ffSKozlov Sergey { 3274a6dc60ffSKozlov Sergey struct cxd2841er_priv *priv = fe->demodulator_priv; 3275a6dc60ffSKozlov Sergey 3276a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s()\n", __func__); 3277a6dc60ffSKozlov Sergey if (priv->state == STATE_ACTIVE_TC) { 3278a6dc60ffSKozlov Sergey switch (priv->system) { 3279a6dc60ffSKozlov Sergey case SYS_DVBT: 3280a6dc60ffSKozlov Sergey cxd2841er_active_t_to_sleep_tc(priv); 3281a6dc60ffSKozlov Sergey break; 3282a6dc60ffSKozlov Sergey case SYS_DVBT2: 3283a6dc60ffSKozlov Sergey cxd2841er_active_t2_to_sleep_tc(priv); 3284a6dc60ffSKozlov Sergey break; 328583808c23SAbylay Ospan case SYS_ISDBT: 328683808c23SAbylay Ospan cxd2841er_active_i_to_sleep_tc(priv); 328783808c23SAbylay Ospan break; 3288a6dc60ffSKozlov Sergey case SYS_DVBC_ANNEX_A: 3289a6dc60ffSKozlov Sergey cxd2841er_active_c_to_sleep_tc(priv); 3290a6dc60ffSKozlov Sergey break; 3291a6dc60ffSKozlov Sergey default: 3292a6dc60ffSKozlov Sergey dev_warn(&priv->i2c->dev, 3293a6dc60ffSKozlov Sergey "%s(): unknown delivery system %d\n", 3294a6dc60ffSKozlov Sergey __func__, priv->system); 3295a6dc60ffSKozlov Sergey } 3296a6dc60ffSKozlov Sergey } 3297a6dc60ffSKozlov Sergey if (priv->state != STATE_SLEEP_TC) { 3298a6dc60ffSKozlov Sergey dev_err(&priv->i2c->dev, "%s(): invalid state %d\n", 3299a6dc60ffSKozlov Sergey __func__, priv->state); 3300a6dc60ffSKozlov Sergey return -EINVAL; 3301a6dc60ffSKozlov Sergey } 3302a6dc60ffSKozlov Sergey cxd2841er_sleep_tc_to_shutdown(priv); 3303a6dc60ffSKozlov Sergey return 0; 3304a6dc60ffSKozlov Sergey } 3305a6dc60ffSKozlov Sergey 3306a6dc60ffSKozlov Sergey static int cxd2841er_send_burst(struct dvb_frontend *fe, 3307a6dc60ffSKozlov Sergey enum fe_sec_mini_cmd burst) 3308a6dc60ffSKozlov Sergey { 3309a6dc60ffSKozlov Sergey u8 data; 3310a6dc60ffSKozlov Sergey struct cxd2841er_priv *priv = fe->demodulator_priv; 3311a6dc60ffSKozlov Sergey 3312a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s(): burst mode %s\n", __func__, 3313a6dc60ffSKozlov Sergey (burst == SEC_MINI_A ? "A" : "B")); 3314a6dc60ffSKozlov Sergey if (priv->state != STATE_SLEEP_S && 3315a6dc60ffSKozlov Sergey priv->state != STATE_ACTIVE_S) { 3316a6dc60ffSKozlov Sergey dev_err(&priv->i2c->dev, "%s(): invalid demod state %d\n", 3317a6dc60ffSKozlov Sergey __func__, priv->state); 3318a6dc60ffSKozlov Sergey return -EINVAL; 3319a6dc60ffSKozlov Sergey } 3320a6dc60ffSKozlov Sergey data = (burst == SEC_MINI_A ? 0 : 1); 3321a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xbb); 3322a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x34, 0x01); 3323a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x35, data); 3324a6dc60ffSKozlov Sergey return 0; 3325a6dc60ffSKozlov Sergey } 3326a6dc60ffSKozlov Sergey 3327a6dc60ffSKozlov Sergey static int cxd2841er_set_tone(struct dvb_frontend *fe, 3328a6dc60ffSKozlov Sergey enum fe_sec_tone_mode tone) 3329a6dc60ffSKozlov Sergey { 3330a6dc60ffSKozlov Sergey u8 data; 3331a6dc60ffSKozlov Sergey struct cxd2841er_priv *priv = fe->demodulator_priv; 3332a6dc60ffSKozlov Sergey 3333a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s(): tone %s\n", __func__, 3334a6dc60ffSKozlov Sergey (tone == SEC_TONE_ON ? "On" : "Off")); 3335a6dc60ffSKozlov Sergey if (priv->state != STATE_SLEEP_S && 3336a6dc60ffSKozlov Sergey priv->state != STATE_ACTIVE_S) { 3337a6dc60ffSKozlov Sergey dev_err(&priv->i2c->dev, "%s(): invalid demod state %d\n", 3338a6dc60ffSKozlov Sergey __func__, priv->state); 3339a6dc60ffSKozlov Sergey return -EINVAL; 3340a6dc60ffSKozlov Sergey } 3341a6dc60ffSKozlov Sergey data = (tone == SEC_TONE_ON ? 1 : 0); 3342a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xbb); 3343a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x36, data); 3344a6dc60ffSKozlov Sergey return 0; 3345a6dc60ffSKozlov Sergey } 3346a6dc60ffSKozlov Sergey 3347a6dc60ffSKozlov Sergey static int cxd2841er_send_diseqc_msg(struct dvb_frontend *fe, 3348a6dc60ffSKozlov Sergey struct dvb_diseqc_master_cmd *cmd) 3349a6dc60ffSKozlov Sergey { 3350a6dc60ffSKozlov Sergey int i; 3351a6dc60ffSKozlov Sergey u8 data[12]; 3352a6dc60ffSKozlov Sergey struct cxd2841er_priv *priv = fe->demodulator_priv; 3353a6dc60ffSKozlov Sergey 3354a6dc60ffSKozlov Sergey if (priv->state != STATE_SLEEP_S && 3355a6dc60ffSKozlov Sergey priv->state != STATE_ACTIVE_S) { 3356a6dc60ffSKozlov Sergey dev_err(&priv->i2c->dev, "%s(): invalid demod state %d\n", 3357a6dc60ffSKozlov Sergey __func__, priv->state); 3358a6dc60ffSKozlov Sergey return -EINVAL; 3359a6dc60ffSKozlov Sergey } 3360a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, 3361a6dc60ffSKozlov Sergey "%s(): cmd->len %d\n", __func__, cmd->msg_len); 3362a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xbb); 3363a6dc60ffSKozlov Sergey /* DiDEqC enable */ 3364a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x33, 0x01); 3365a6dc60ffSKozlov Sergey /* cmd1 length & data */ 3366a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x3d, cmd->msg_len); 3367a6dc60ffSKozlov Sergey memset(data, 0, sizeof(data)); 3368a6dc60ffSKozlov Sergey for (i = 0; i < cmd->msg_len && i < sizeof(data); i++) 3369a6dc60ffSKozlov Sergey data[i] = cmd->msg[i]; 3370a6dc60ffSKozlov Sergey cxd2841er_write_regs(priv, I2C_SLVT, 0x3e, data, sizeof(data)); 3371a6dc60ffSKozlov Sergey /* repeat count for cmd1 */ 3372a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x37, 1); 3373a6dc60ffSKozlov Sergey /* repeat count for cmd2: always 0 */ 3374a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x38, 0); 3375a6dc60ffSKozlov Sergey /* start transmit */ 3376a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x32, 0x01); 3377a6dc60ffSKozlov Sergey /* wait for 1 sec timeout */ 3378a6dc60ffSKozlov Sergey for (i = 0; i < 50; i++) { 3379a6dc60ffSKozlov Sergey cxd2841er_read_reg(priv, I2C_SLVT, 0x10, data); 3380a6dc60ffSKozlov Sergey if (!data[0]) { 3381a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, 3382a6dc60ffSKozlov Sergey "%s(): DiSEqC cmd has been sent\n", __func__); 3383a6dc60ffSKozlov Sergey return 0; 3384a6dc60ffSKozlov Sergey } 3385a6dc60ffSKozlov Sergey msleep(20); 3386a6dc60ffSKozlov Sergey } 3387a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, 3388a6dc60ffSKozlov Sergey "%s(): DiSEqC cmd transmit timeout\n", __func__); 3389a6dc60ffSKozlov Sergey return -ETIMEDOUT; 3390a6dc60ffSKozlov Sergey } 3391a6dc60ffSKozlov Sergey 3392a6dc60ffSKozlov Sergey static void cxd2841er_release(struct dvb_frontend *fe) 3393a6dc60ffSKozlov Sergey { 3394a6dc60ffSKozlov Sergey struct cxd2841er_priv *priv = fe->demodulator_priv; 3395a6dc60ffSKozlov Sergey 3396a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s()\n", __func__); 3397a6dc60ffSKozlov Sergey kfree(priv); 3398a6dc60ffSKozlov Sergey } 3399a6dc60ffSKozlov Sergey 3400a6dc60ffSKozlov Sergey static int cxd2841er_i2c_gate_ctrl(struct dvb_frontend *fe, int enable) 3401a6dc60ffSKozlov Sergey { 3402a6dc60ffSKozlov Sergey struct cxd2841er_priv *priv = fe->demodulator_priv; 3403a6dc60ffSKozlov Sergey 3404a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s(): enable=%d\n", __func__, enable); 3405a6dc60ffSKozlov Sergey cxd2841er_set_reg_bits( 3406a6dc60ffSKozlov Sergey priv, I2C_SLVX, 0x8, (enable ? 0x01 : 0x00), 0x01); 3407a6dc60ffSKozlov Sergey return 0; 3408a6dc60ffSKozlov Sergey } 3409a6dc60ffSKozlov Sergey 3410a6dc60ffSKozlov Sergey static enum dvbfe_algo cxd2841er_get_algo(struct dvb_frontend *fe) 3411a6dc60ffSKozlov Sergey { 3412a6dc60ffSKozlov Sergey struct cxd2841er_priv *priv = fe->demodulator_priv; 3413a6dc60ffSKozlov Sergey 3414a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s()\n", __func__); 3415a6dc60ffSKozlov Sergey return DVBFE_ALGO_HW; 3416a6dc60ffSKozlov Sergey } 3417a6dc60ffSKozlov Sergey 3418d0e20e13SMauro Carvalho Chehab static void cxd2841er_init_stats(struct dvb_frontend *fe) 3419d0e20e13SMauro Carvalho Chehab { 3420d0e20e13SMauro Carvalho Chehab struct dtv_frontend_properties *p = &fe->dtv_property_cache; 3421d0e20e13SMauro Carvalho Chehab 3422d0e20e13SMauro Carvalho Chehab p->strength.len = 1; 3423d0e20e13SMauro Carvalho Chehab p->strength.stat[0].scale = FE_SCALE_RELATIVE; 3424d0e20e13SMauro Carvalho Chehab p->cnr.len = 1; 3425d0e20e13SMauro Carvalho Chehab p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 3426d0e20e13SMauro Carvalho Chehab p->block_error.len = 1; 3427d0e20e13SMauro Carvalho Chehab p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 3428d0e20e13SMauro Carvalho Chehab p->post_bit_error.len = 1; 3429d0e20e13SMauro Carvalho Chehab p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 34304216be14SMauro Carvalho Chehab p->post_bit_count.len = 1; 34314216be14SMauro Carvalho Chehab p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 3432d0e20e13SMauro Carvalho Chehab } 3433d0e20e13SMauro Carvalho Chehab 3434d0e20e13SMauro Carvalho Chehab 3435a6dc60ffSKozlov Sergey static int cxd2841er_init_s(struct dvb_frontend *fe) 3436a6dc60ffSKozlov Sergey { 3437a6dc60ffSKozlov Sergey struct cxd2841er_priv *priv = fe->demodulator_priv; 3438a6dc60ffSKozlov Sergey 343930ae3307SAbylay Ospan /* sanity. force demod to SHUTDOWN state */ 344030ae3307SAbylay Ospan if (priv->state == STATE_SLEEP_S) { 344130ae3307SAbylay Ospan dev_dbg(&priv->i2c->dev, "%s() forcing sleep->shutdown\n", 344230ae3307SAbylay Ospan __func__); 344330ae3307SAbylay Ospan cxd2841er_sleep_s_to_shutdown(priv); 344430ae3307SAbylay Ospan } else if (priv->state == STATE_ACTIVE_S) { 344530ae3307SAbylay Ospan dev_dbg(&priv->i2c->dev, "%s() forcing active->sleep->shutdown\n", 344630ae3307SAbylay Ospan __func__); 344730ae3307SAbylay Ospan cxd2841er_active_s_to_sleep_s(priv); 344830ae3307SAbylay Ospan cxd2841er_sleep_s_to_shutdown(priv); 344930ae3307SAbylay Ospan } 345030ae3307SAbylay Ospan 3451a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s()\n", __func__); 3452a6dc60ffSKozlov Sergey cxd2841er_shutdown_to_sleep_s(priv); 3453a6dc60ffSKozlov Sergey /* SONY_DEMOD_CONFIG_SAT_IFAGCNEG set to 1 */ 3454a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0); 3455a6dc60ffSKozlov Sergey cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xb9, 0x01, 0x01); 3456d0e20e13SMauro Carvalho Chehab 3457d0e20e13SMauro Carvalho Chehab cxd2841er_init_stats(fe); 3458d0e20e13SMauro Carvalho Chehab 3459a6dc60ffSKozlov Sergey return 0; 3460a6dc60ffSKozlov Sergey } 3461a6dc60ffSKozlov Sergey 3462a6dc60ffSKozlov Sergey static int cxd2841er_init_tc(struct dvb_frontend *fe) 3463a6dc60ffSKozlov Sergey { 3464a6dc60ffSKozlov Sergey struct cxd2841er_priv *priv = fe->demodulator_priv; 34653f3b48a0SAbylay Ospan struct dtv_frontend_properties *p = &fe->dtv_property_cache; 3466a6dc60ffSKozlov Sergey 34673f3b48a0SAbylay Ospan dev_dbg(&priv->i2c->dev, "%s() bandwidth_hz=%d\n", 34683f3b48a0SAbylay Ospan __func__, p->bandwidth_hz); 3469a6dc60ffSKozlov Sergey cxd2841er_shutdown_to_sleep_tc(priv); 3470a6dc60ffSKozlov Sergey /* SONY_DEMOD_CONFIG_IFAGCNEG = 1 */ 3471a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10); 3472a6dc60ffSKozlov Sergey cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcb, 0x40, 0x40); 3473a6dc60ffSKozlov Sergey /* SONY_DEMOD_CONFIG_IFAGC_ADC_FS = 0 */ 3474a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0xcd, 0x50); 3475a6dc60ffSKozlov Sergey /* SONY_DEMOD_CONFIG_PARALLEL_SEL = 1 */ 3476a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00); 3477a6dc60ffSKozlov Sergey cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xc4, 0x00, 0x80); 3478d0e20e13SMauro Carvalho Chehab 3479d0e20e13SMauro Carvalho Chehab cxd2841er_init_stats(fe); 3480d0e20e13SMauro Carvalho Chehab 3481a6dc60ffSKozlov Sergey return 0; 3482a6dc60ffSKozlov Sergey } 3483a6dc60ffSKozlov Sergey 3484a6dc60ffSKozlov Sergey static struct dvb_frontend_ops cxd2841er_dvbs_s2_ops; 34853f3b48a0SAbylay Ospan static struct dvb_frontend_ops cxd2841er_t_c_ops; 3486a6dc60ffSKozlov Sergey 3487a6dc60ffSKozlov Sergey static struct dvb_frontend *cxd2841er_attach(struct cxd2841er_config *cfg, 3488a6dc60ffSKozlov Sergey struct i2c_adapter *i2c, 3489a6dc60ffSKozlov Sergey u8 system) 3490a6dc60ffSKozlov Sergey { 3491a6dc60ffSKozlov Sergey u8 chip_id = 0; 3492a6dc60ffSKozlov Sergey const char *type; 34933f3b48a0SAbylay Ospan const char *name; 3494a6dc60ffSKozlov Sergey struct cxd2841er_priv *priv = NULL; 3495a6dc60ffSKozlov Sergey 3496a6dc60ffSKozlov Sergey /* allocate memory for the internal state */ 3497a6dc60ffSKozlov Sergey priv = kzalloc(sizeof(struct cxd2841er_priv), GFP_KERNEL); 3498a6dc60ffSKozlov Sergey if (!priv) 3499a6dc60ffSKozlov Sergey return NULL; 3500a6dc60ffSKozlov Sergey priv->i2c = i2c; 3501a6dc60ffSKozlov Sergey priv->config = cfg; 3502a6dc60ffSKozlov Sergey priv->i2c_addr_slvx = (cfg->i2c_addr + 4) >> 1; 3503a6dc60ffSKozlov Sergey priv->i2c_addr_slvt = (cfg->i2c_addr) >> 1; 350483808c23SAbylay Ospan priv->xtal = cfg->xtal; 3505a6dc60ffSKozlov Sergey priv->frontend.demodulator_priv = priv; 3506a6dc60ffSKozlov Sergey dev_info(&priv->i2c->dev, 3507a6dc60ffSKozlov Sergey "%s(): I2C adapter %p SLVX addr %x SLVT addr %x\n", 3508a6dc60ffSKozlov Sergey __func__, priv->i2c, 3509a6dc60ffSKozlov Sergey priv->i2c_addr_slvx, priv->i2c_addr_slvt); 3510a6dc60ffSKozlov Sergey chip_id = cxd2841er_chip_id(priv); 35113f3b48a0SAbylay Ospan switch (chip_id) { 35123f3b48a0SAbylay Ospan case CXD2841ER_CHIP_ID: 35133f3b48a0SAbylay Ospan snprintf(cxd2841er_t_c_ops.info.name, 128, 35143f3b48a0SAbylay Ospan "Sony CXD2841ER DVB-T/T2/C demodulator"); 35153f3b48a0SAbylay Ospan name = "CXD2841ER"; 35163f3b48a0SAbylay Ospan break; 35173f3b48a0SAbylay Ospan case CXD2854ER_CHIP_ID: 35183f3b48a0SAbylay Ospan snprintf(cxd2841er_t_c_ops.info.name, 128, 35193f3b48a0SAbylay Ospan "Sony CXD2854ER DVB-T/T2/C and ISDB-T demodulator"); 35203f3b48a0SAbylay Ospan cxd2841er_t_c_ops.delsys[3] = SYS_ISDBT; 35213f3b48a0SAbylay Ospan name = "CXD2854ER"; 35223f3b48a0SAbylay Ospan break; 35233f3b48a0SAbylay Ospan default: 3524a6dc60ffSKozlov Sergey dev_err(&priv->i2c->dev, "%s(): invalid chip ID 0x%02x\n", 3525a6dc60ffSKozlov Sergey __func__, chip_id); 3526a6dc60ffSKozlov Sergey priv->frontend.demodulator_priv = NULL; 3527a6dc60ffSKozlov Sergey kfree(priv); 3528a6dc60ffSKozlov Sergey return NULL; 3529a6dc60ffSKozlov Sergey } 35303f3b48a0SAbylay Ospan 35313f3b48a0SAbylay Ospan /* create dvb_frontend */ 35323f3b48a0SAbylay Ospan if (system == SYS_DVBS) { 35333f3b48a0SAbylay Ospan memcpy(&priv->frontend.ops, 35343f3b48a0SAbylay Ospan &cxd2841er_dvbs_s2_ops, 35353f3b48a0SAbylay Ospan sizeof(struct dvb_frontend_ops)); 35363f3b48a0SAbylay Ospan type = "S/S2"; 35373f3b48a0SAbylay Ospan } else { 35383f3b48a0SAbylay Ospan memcpy(&priv->frontend.ops, 35393f3b48a0SAbylay Ospan &cxd2841er_t_c_ops, 35403f3b48a0SAbylay Ospan sizeof(struct dvb_frontend_ops)); 35413f3b48a0SAbylay Ospan type = "T/T2/C/ISDB-T"; 35423f3b48a0SAbylay Ospan } 35433f3b48a0SAbylay Ospan 35443f3b48a0SAbylay Ospan dev_info(&priv->i2c->dev, 35453f3b48a0SAbylay Ospan "%s(): attaching %s DVB-%s frontend\n", 35463f3b48a0SAbylay Ospan __func__, name, type); 3547a6dc60ffSKozlov Sergey dev_info(&priv->i2c->dev, "%s(): chip ID 0x%02x OK.\n", 3548a6dc60ffSKozlov Sergey __func__, chip_id); 3549a6dc60ffSKozlov Sergey return &priv->frontend; 3550a6dc60ffSKozlov Sergey } 3551a6dc60ffSKozlov Sergey 3552a6dc60ffSKozlov Sergey struct dvb_frontend *cxd2841er_attach_s(struct cxd2841er_config *cfg, 3553a6dc60ffSKozlov Sergey struct i2c_adapter *i2c) 3554a6dc60ffSKozlov Sergey { 3555a6dc60ffSKozlov Sergey return cxd2841er_attach(cfg, i2c, SYS_DVBS); 3556a6dc60ffSKozlov Sergey } 3557a6dc60ffSKozlov Sergey EXPORT_SYMBOL(cxd2841er_attach_s); 3558a6dc60ffSKozlov Sergey 35593f3b48a0SAbylay Ospan struct dvb_frontend *cxd2841er_attach_t_c(struct cxd2841er_config *cfg, 3560a6dc60ffSKozlov Sergey struct i2c_adapter *i2c) 3561a6dc60ffSKozlov Sergey { 35623f3b48a0SAbylay Ospan return cxd2841er_attach(cfg, i2c, 0); 3563a6dc60ffSKozlov Sergey } 35643f3b48a0SAbylay Ospan EXPORT_SYMBOL(cxd2841er_attach_t_c); 3565a6dc60ffSKozlov Sergey 3566a6dc60ffSKozlov Sergey static struct dvb_frontend_ops cxd2841er_dvbs_s2_ops = { 3567a6dc60ffSKozlov Sergey .delsys = { SYS_DVBS, SYS_DVBS2 }, 3568a6dc60ffSKozlov Sergey .info = { 3569a6dc60ffSKozlov Sergey .name = "Sony CXD2841ER DVB-S/S2 demodulator", 3570a6dc60ffSKozlov Sergey .frequency_min = 500000, 3571a6dc60ffSKozlov Sergey .frequency_max = 2500000, 3572a6dc60ffSKozlov Sergey .frequency_stepsize = 0, 3573a6dc60ffSKozlov Sergey .symbol_rate_min = 1000000, 3574a6dc60ffSKozlov Sergey .symbol_rate_max = 45000000, 3575a6dc60ffSKozlov Sergey .symbol_rate_tolerance = 500, 3576a6dc60ffSKozlov Sergey .caps = FE_CAN_INVERSION_AUTO | 3577a6dc60ffSKozlov Sergey FE_CAN_FEC_AUTO | 3578a6dc60ffSKozlov Sergey FE_CAN_QPSK, 3579a6dc60ffSKozlov Sergey }, 3580a6dc60ffSKozlov Sergey .init = cxd2841er_init_s, 3581a6dc60ffSKozlov Sergey .sleep = cxd2841er_sleep_s, 3582a6dc60ffSKozlov Sergey .release = cxd2841er_release, 3583a6dc60ffSKozlov Sergey .set_frontend = cxd2841er_set_frontend_s, 3584a6dc60ffSKozlov Sergey .get_frontend = cxd2841er_get_frontend, 3585a6dc60ffSKozlov Sergey .read_status = cxd2841er_read_status_s, 3586a6dc60ffSKozlov Sergey .i2c_gate_ctrl = cxd2841er_i2c_gate_ctrl, 3587a6dc60ffSKozlov Sergey .get_frontend_algo = cxd2841er_get_algo, 3588a6dc60ffSKozlov Sergey .set_tone = cxd2841er_set_tone, 3589a6dc60ffSKozlov Sergey .diseqc_send_burst = cxd2841er_send_burst, 3590a6dc60ffSKozlov Sergey .diseqc_send_master_cmd = cxd2841er_send_diseqc_msg, 3591a6dc60ffSKozlov Sergey .tune = cxd2841er_tune_s 3592a6dc60ffSKozlov Sergey }; 3593a6dc60ffSKozlov Sergey 35943f3b48a0SAbylay Ospan static struct dvb_frontend_ops cxd2841er_t_c_ops = { 35953f3b48a0SAbylay Ospan .delsys = { SYS_DVBT, SYS_DVBT2, SYS_DVBC_ANNEX_A }, 3596a6dc60ffSKozlov Sergey .info = { 35973f3b48a0SAbylay Ospan .name = "", /* will set in attach function */ 3598a6dc60ffSKozlov Sergey .caps = FE_CAN_FEC_1_2 | 3599a6dc60ffSKozlov Sergey FE_CAN_FEC_2_3 | 3600a6dc60ffSKozlov Sergey FE_CAN_FEC_3_4 | 3601a6dc60ffSKozlov Sergey FE_CAN_FEC_5_6 | 3602a6dc60ffSKozlov Sergey FE_CAN_FEC_7_8 | 3603a6dc60ffSKozlov Sergey FE_CAN_FEC_AUTO | 3604a6dc60ffSKozlov Sergey FE_CAN_QPSK | 3605a6dc60ffSKozlov Sergey FE_CAN_QAM_16 | 3606a6dc60ffSKozlov Sergey FE_CAN_QAM_32 | 3607a6dc60ffSKozlov Sergey FE_CAN_QAM_64 | 3608a6dc60ffSKozlov Sergey FE_CAN_QAM_128 | 3609a6dc60ffSKozlov Sergey FE_CAN_QAM_256 | 3610a6dc60ffSKozlov Sergey FE_CAN_QAM_AUTO | 3611a6dc60ffSKozlov Sergey FE_CAN_TRANSMISSION_MODE_AUTO | 3612a6dc60ffSKozlov Sergey FE_CAN_GUARD_INTERVAL_AUTO | 3613a6dc60ffSKozlov Sergey FE_CAN_HIERARCHY_AUTO | 3614a6dc60ffSKozlov Sergey FE_CAN_MUTE_TS | 3615a6dc60ffSKozlov Sergey FE_CAN_2G_MODULATION, 3616a6dc60ffSKozlov Sergey .frequency_min = 42000000, 3617a6dc60ffSKozlov Sergey .frequency_max = 1002000000 3618a6dc60ffSKozlov Sergey }, 3619a6dc60ffSKozlov Sergey .init = cxd2841er_init_tc, 3620a6dc60ffSKozlov Sergey .sleep = cxd2841er_sleep_tc, 3621a6dc60ffSKozlov Sergey .release = cxd2841er_release, 3622a6dc60ffSKozlov Sergey .set_frontend = cxd2841er_set_frontend_tc, 3623a6dc60ffSKozlov Sergey .get_frontend = cxd2841er_get_frontend, 3624a6dc60ffSKozlov Sergey .read_status = cxd2841er_read_status_tc, 3625a6dc60ffSKozlov Sergey .tune = cxd2841er_tune_tc, 3626a6dc60ffSKozlov Sergey .i2c_gate_ctrl = cxd2841er_i2c_gate_ctrl, 3627a6dc60ffSKozlov Sergey .get_frontend_algo = cxd2841er_get_algo 3628a6dc60ffSKozlov Sergey }; 3629a6dc60ffSKozlov Sergey 363083808c23SAbylay Ospan MODULE_DESCRIPTION("Sony CXD2841ER/CXD2854ER DVB-C/C2/T/T2/S/S2 demodulator driver"); 363183808c23SAbylay Ospan MODULE_AUTHOR("Sergey Kozlov <serjk@netup.ru>, Abylay Ospan <aospan@netup.ru>"); 3632a6dc60ffSKozlov Sergey MODULE_LICENSE("GPL"); 3633