1c942fddfSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later
2a6dc60ffSKozlov Sergey /*
3a6dc60ffSKozlov Sergey * cxd2841er.c
4a6dc60ffSKozlov Sergey *
583808c23SAbylay Ospan * Sony digital demodulator driver for
69ca1736fSAbylay Ospan * CXD2841ER - DVB-S/S2/T/T2/C/C2
79ca1736fSAbylay Ospan * CXD2854ER - DVB-S/S2/T/T2/C/C2, ISDB-T/S
8a6dc60ffSKozlov Sergey *
9a6dc60ffSKozlov Sergey * Copyright 2012 Sony Corporation
10a6dc60ffSKozlov Sergey * Copyright (C) 2014 NetUP Inc.
11a6dc60ffSKozlov Sergey * Copyright (C) 2014 Sergey Kozlov <serjk@netup.ru>
12a6dc60ffSKozlov Sergey * Copyright (C) 2014 Abylay Ospan <aospan@netup.ru>
13a6dc60ffSKozlov Sergey */
14a6dc60ffSKozlov Sergey
15a6dc60ffSKozlov Sergey #include <linux/module.h>
16a6dc60ffSKozlov Sergey #include <linux/init.h>
17a6dc60ffSKozlov Sergey #include <linux/string.h>
18a6dc60ffSKozlov Sergey #include <linux/slab.h>
19a6dc60ffSKozlov Sergey #include <linux/bitops.h>
20a6dc60ffSKozlov Sergey #include <linux/math64.h>
21a6dc60ffSKozlov Sergey #include <linux/log2.h>
22a6dc60ffSKozlov Sergey #include <linux/dynamic_debug.h>
23e40d14a8SJérémy Lefaure #include <linux/kernel.h>
24a6dc60ffSKozlov Sergey
25f97fa3dcSAndy Shevchenko #include <linux/int_log.h>
26fada1935SMauro Carvalho Chehab #include <media/dvb_frontend.h>
27a6dc60ffSKozlov Sergey #include "cxd2841er.h"
28a6dc60ffSKozlov Sergey #include "cxd2841er_priv.h"
29a6dc60ffSKozlov Sergey
30d13a7b67SMauro Carvalho Chehab #define MAX_WRITE_REGSIZE 16
31a6f330cbSAbylay Ospan #define LOG2_E_100X 144
32a6f330cbSAbylay Ospan
33df61f828SDaniel Scheller #define INTLOG10X100(x) ((u32) (((u64) intlog10(x) * 100) >> 24))
34df61f828SDaniel Scheller
35a6f330cbSAbylay Ospan /* DVB-C constellation */
36a6f330cbSAbylay Ospan enum sony_dvbc_constellation_t {
37a6f330cbSAbylay Ospan SONY_DVBC_CONSTELLATION_16QAM,
38a6f330cbSAbylay Ospan SONY_DVBC_CONSTELLATION_32QAM,
39a6f330cbSAbylay Ospan SONY_DVBC_CONSTELLATION_64QAM,
40a6f330cbSAbylay Ospan SONY_DVBC_CONSTELLATION_128QAM,
41a6f330cbSAbylay Ospan SONY_DVBC_CONSTELLATION_256QAM
42a6f330cbSAbylay Ospan };
43d13a7b67SMauro Carvalho Chehab
44a6dc60ffSKozlov Sergey enum cxd2841er_state {
45a6dc60ffSKozlov Sergey STATE_SHUTDOWN = 0,
46a6dc60ffSKozlov Sergey STATE_SLEEP_S,
47a6dc60ffSKozlov Sergey STATE_ACTIVE_S,
48a6dc60ffSKozlov Sergey STATE_SLEEP_TC,
49a6dc60ffSKozlov Sergey STATE_ACTIVE_TC
50a6dc60ffSKozlov Sergey };
51a6dc60ffSKozlov Sergey
52a6dc60ffSKozlov Sergey struct cxd2841er_priv {
53a6dc60ffSKozlov Sergey struct dvb_frontend frontend;
54a6dc60ffSKozlov Sergey struct i2c_adapter *i2c;
55a6dc60ffSKozlov Sergey u8 i2c_addr_slvx;
56a6dc60ffSKozlov Sergey u8 i2c_addr_slvt;
57a6dc60ffSKozlov Sergey const struct cxd2841er_config *config;
58a6dc60ffSKozlov Sergey enum cxd2841er_state state;
59a6dc60ffSKozlov Sergey u8 system;
6083808c23SAbylay Ospan enum cxd2841er_xtal xtal;
613f3b48a0SAbylay Ospan enum fe_caps caps;
62050863aaSDaniel Scheller u32 flags;
63d9aeaa6dSMauro Carvalho Chehab unsigned long stats_time;
64a6dc60ffSKozlov Sergey };
65a6dc60ffSKozlov Sergey
66a6dc60ffSKozlov Sergey static const struct cxd2841er_cnr_data s_cn_data[] = {
67a6dc60ffSKozlov Sergey { 0x033e, 0 }, { 0x0339, 100 }, { 0x0333, 200 },
68a6dc60ffSKozlov Sergey { 0x032e, 300 }, { 0x0329, 400 }, { 0x0324, 500 },
69a6dc60ffSKozlov Sergey { 0x031e, 600 }, { 0x0319, 700 }, { 0x0314, 800 },
70a6dc60ffSKozlov Sergey { 0x030f, 900 }, { 0x030a, 1000 }, { 0x02ff, 1100 },
71a6dc60ffSKozlov Sergey { 0x02f4, 1200 }, { 0x02e9, 1300 }, { 0x02de, 1400 },
72a6dc60ffSKozlov Sergey { 0x02d4, 1500 }, { 0x02c9, 1600 }, { 0x02bf, 1700 },
73a6dc60ffSKozlov Sergey { 0x02b5, 1800 }, { 0x02ab, 1900 }, { 0x02a1, 2000 },
74a6dc60ffSKozlov Sergey { 0x029b, 2100 }, { 0x0295, 2200 }, { 0x0290, 2300 },
75a6dc60ffSKozlov Sergey { 0x028a, 2400 }, { 0x0284, 2500 }, { 0x027f, 2600 },
76a6dc60ffSKozlov Sergey { 0x0279, 2700 }, { 0x0274, 2800 }, { 0x026e, 2900 },
77a6dc60ffSKozlov Sergey { 0x0269, 3000 }, { 0x0262, 3100 }, { 0x025c, 3200 },
78a6dc60ffSKozlov Sergey { 0x0255, 3300 }, { 0x024f, 3400 }, { 0x0249, 3500 },
79a6dc60ffSKozlov Sergey { 0x0242, 3600 }, { 0x023c, 3700 }, { 0x0236, 3800 },
80a6dc60ffSKozlov Sergey { 0x0230, 3900 }, { 0x022a, 4000 }, { 0x0223, 4100 },
81a6dc60ffSKozlov Sergey { 0x021c, 4200 }, { 0x0215, 4300 }, { 0x020e, 4400 },
82a6dc60ffSKozlov Sergey { 0x0207, 4500 }, { 0x0201, 4600 }, { 0x01fa, 4700 },
83a6dc60ffSKozlov Sergey { 0x01f4, 4800 }, { 0x01ed, 4900 }, { 0x01e7, 5000 },
84a6dc60ffSKozlov Sergey { 0x01e0, 5100 }, { 0x01d9, 5200 }, { 0x01d2, 5300 },
85a6dc60ffSKozlov Sergey { 0x01cb, 5400 }, { 0x01c4, 5500 }, { 0x01be, 5600 },
86a6dc60ffSKozlov Sergey { 0x01b7, 5700 }, { 0x01b1, 5800 }, { 0x01aa, 5900 },
87a6dc60ffSKozlov Sergey { 0x01a4, 6000 }, { 0x019d, 6100 }, { 0x0196, 6200 },
88a6dc60ffSKozlov Sergey { 0x018f, 6300 }, { 0x0189, 6400 }, { 0x0182, 6500 },
89a6dc60ffSKozlov Sergey { 0x017c, 6600 }, { 0x0175, 6700 }, { 0x016f, 6800 },
90a6dc60ffSKozlov Sergey { 0x0169, 6900 }, { 0x0163, 7000 }, { 0x015c, 7100 },
91a6dc60ffSKozlov Sergey { 0x0156, 7200 }, { 0x0150, 7300 }, { 0x014a, 7400 },
92a6dc60ffSKozlov Sergey { 0x0144, 7500 }, { 0x013e, 7600 }, { 0x0138, 7700 },
93a6dc60ffSKozlov Sergey { 0x0132, 7800 }, { 0x012d, 7900 }, { 0x0127, 8000 },
94a6dc60ffSKozlov Sergey { 0x0121, 8100 }, { 0x011c, 8200 }, { 0x0116, 8300 },
95a6dc60ffSKozlov Sergey { 0x0111, 8400 }, { 0x010b, 8500 }, { 0x0106, 8600 },
96a6dc60ffSKozlov Sergey { 0x0101, 8700 }, { 0x00fc, 8800 }, { 0x00f7, 8900 },
97a6dc60ffSKozlov Sergey { 0x00f2, 9000 }, { 0x00ee, 9100 }, { 0x00ea, 9200 },
98a6dc60ffSKozlov Sergey { 0x00e6, 9300 }, { 0x00e2, 9400 }, { 0x00de, 9500 },
99a6dc60ffSKozlov Sergey { 0x00da, 9600 }, { 0x00d7, 9700 }, { 0x00d3, 9800 },
100a6dc60ffSKozlov Sergey { 0x00d0, 9900 }, { 0x00cc, 10000 }, { 0x00c7, 10100 },
101a6dc60ffSKozlov Sergey { 0x00c3, 10200 }, { 0x00bf, 10300 }, { 0x00ba, 10400 },
102a6dc60ffSKozlov Sergey { 0x00b6, 10500 }, { 0x00b2, 10600 }, { 0x00ae, 10700 },
103a6dc60ffSKozlov Sergey { 0x00aa, 10800 }, { 0x00a7, 10900 }, { 0x00a3, 11000 },
104a6dc60ffSKozlov Sergey { 0x009f, 11100 }, { 0x009c, 11200 }, { 0x0098, 11300 },
105a6dc60ffSKozlov Sergey { 0x0094, 11400 }, { 0x0091, 11500 }, { 0x008e, 11600 },
106a6dc60ffSKozlov Sergey { 0x008a, 11700 }, { 0x0087, 11800 }, { 0x0084, 11900 },
107a6dc60ffSKozlov Sergey { 0x0081, 12000 }, { 0x007e, 12100 }, { 0x007b, 12200 },
108a6dc60ffSKozlov Sergey { 0x0079, 12300 }, { 0x0076, 12400 }, { 0x0073, 12500 },
109a6dc60ffSKozlov Sergey { 0x0071, 12600 }, { 0x006e, 12700 }, { 0x006c, 12800 },
110a6dc60ffSKozlov Sergey { 0x0069, 12900 }, { 0x0067, 13000 }, { 0x0065, 13100 },
111a6dc60ffSKozlov Sergey { 0x0062, 13200 }, { 0x0060, 13300 }, { 0x005e, 13400 },
112a6dc60ffSKozlov Sergey { 0x005c, 13500 }, { 0x005a, 13600 }, { 0x0058, 13700 },
113a6dc60ffSKozlov Sergey { 0x0056, 13800 }, { 0x0054, 13900 }, { 0x0052, 14000 },
114a6dc60ffSKozlov Sergey { 0x0050, 14100 }, { 0x004e, 14200 }, { 0x004c, 14300 },
115a6dc60ffSKozlov Sergey { 0x004b, 14400 }, { 0x0049, 14500 }, { 0x0047, 14600 },
116a6dc60ffSKozlov Sergey { 0x0046, 14700 }, { 0x0044, 14800 }, { 0x0043, 14900 },
117a6dc60ffSKozlov Sergey { 0x0041, 15000 }, { 0x003f, 15100 }, { 0x003e, 15200 },
118a6dc60ffSKozlov Sergey { 0x003c, 15300 }, { 0x003b, 15400 }, { 0x003a, 15500 },
119a6dc60ffSKozlov Sergey { 0x0037, 15700 }, { 0x0036, 15800 }, { 0x0034, 15900 },
120a6dc60ffSKozlov Sergey { 0x0033, 16000 }, { 0x0032, 16100 }, { 0x0031, 16200 },
121a6dc60ffSKozlov Sergey { 0x0030, 16300 }, { 0x002f, 16400 }, { 0x002e, 16500 },
122a6dc60ffSKozlov Sergey { 0x002d, 16600 }, { 0x002c, 16700 }, { 0x002b, 16800 },
123a6dc60ffSKozlov Sergey { 0x002a, 16900 }, { 0x0029, 17000 }, { 0x0028, 17100 },
124a6dc60ffSKozlov Sergey { 0x0027, 17200 }, { 0x0026, 17300 }, { 0x0025, 17400 },
125a6dc60ffSKozlov Sergey { 0x0024, 17500 }, { 0x0023, 17600 }, { 0x0022, 17800 },
126a6dc60ffSKozlov Sergey { 0x0021, 17900 }, { 0x0020, 18000 }, { 0x001f, 18200 },
127a6dc60ffSKozlov Sergey { 0x001e, 18300 }, { 0x001d, 18500 }, { 0x001c, 18700 },
128a6dc60ffSKozlov Sergey { 0x001b, 18900 }, { 0x001a, 19000 }, { 0x0019, 19200 },
129a6dc60ffSKozlov Sergey { 0x0018, 19300 }, { 0x0017, 19500 }, { 0x0016, 19700 },
130a6dc60ffSKozlov Sergey { 0x0015, 19900 }, { 0x0014, 20000 },
131a6dc60ffSKozlov Sergey };
132a6dc60ffSKozlov Sergey
133a6dc60ffSKozlov Sergey static const struct cxd2841er_cnr_data s2_cn_data[] = {
134a6dc60ffSKozlov Sergey { 0x05af, 0 }, { 0x0597, 100 }, { 0x057e, 200 },
135a6dc60ffSKozlov Sergey { 0x0567, 300 }, { 0x0550, 400 }, { 0x0539, 500 },
136a6dc60ffSKozlov Sergey { 0x0522, 600 }, { 0x050c, 700 }, { 0x04f6, 800 },
137a6dc60ffSKozlov Sergey { 0x04e1, 900 }, { 0x04cc, 1000 }, { 0x04b6, 1100 },
138a6dc60ffSKozlov Sergey { 0x04a1, 1200 }, { 0x048c, 1300 }, { 0x0477, 1400 },
139a6dc60ffSKozlov Sergey { 0x0463, 1500 }, { 0x044f, 1600 }, { 0x043c, 1700 },
140a6dc60ffSKozlov Sergey { 0x0428, 1800 }, { 0x0416, 1900 }, { 0x0403, 2000 },
141a6dc60ffSKozlov Sergey { 0x03ef, 2100 }, { 0x03dc, 2200 }, { 0x03c9, 2300 },
142a6dc60ffSKozlov Sergey { 0x03b6, 2400 }, { 0x03a4, 2500 }, { 0x0392, 2600 },
143a6dc60ffSKozlov Sergey { 0x0381, 2700 }, { 0x036f, 2800 }, { 0x035f, 2900 },
144a6dc60ffSKozlov Sergey { 0x034e, 3000 }, { 0x033d, 3100 }, { 0x032d, 3200 },
145a6dc60ffSKozlov Sergey { 0x031d, 3300 }, { 0x030d, 3400 }, { 0x02fd, 3500 },
146a6dc60ffSKozlov Sergey { 0x02ee, 3600 }, { 0x02df, 3700 }, { 0x02d0, 3800 },
147a6dc60ffSKozlov Sergey { 0x02c2, 3900 }, { 0x02b4, 4000 }, { 0x02a6, 4100 },
148a6dc60ffSKozlov Sergey { 0x0299, 4200 }, { 0x028c, 4300 }, { 0x027f, 4400 },
149a6dc60ffSKozlov Sergey { 0x0272, 4500 }, { 0x0265, 4600 }, { 0x0259, 4700 },
150a6dc60ffSKozlov Sergey { 0x024d, 4800 }, { 0x0241, 4900 }, { 0x0236, 5000 },
151a6dc60ffSKozlov Sergey { 0x022b, 5100 }, { 0x0220, 5200 }, { 0x0215, 5300 },
152a6dc60ffSKozlov Sergey { 0x020a, 5400 }, { 0x0200, 5500 }, { 0x01f6, 5600 },
153a6dc60ffSKozlov Sergey { 0x01ec, 5700 }, { 0x01e2, 5800 }, { 0x01d8, 5900 },
154a6dc60ffSKozlov Sergey { 0x01cf, 6000 }, { 0x01c6, 6100 }, { 0x01bc, 6200 },
155a6dc60ffSKozlov Sergey { 0x01b3, 6300 }, { 0x01aa, 6400 }, { 0x01a2, 6500 },
156a6dc60ffSKozlov Sergey { 0x0199, 6600 }, { 0x0191, 6700 }, { 0x0189, 6800 },
157a6dc60ffSKozlov Sergey { 0x0181, 6900 }, { 0x0179, 7000 }, { 0x0171, 7100 },
158a6dc60ffSKozlov Sergey { 0x0169, 7200 }, { 0x0161, 7300 }, { 0x015a, 7400 },
159a6dc60ffSKozlov Sergey { 0x0153, 7500 }, { 0x014b, 7600 }, { 0x0144, 7700 },
160a6dc60ffSKozlov Sergey { 0x013d, 7800 }, { 0x0137, 7900 }, { 0x0130, 8000 },
161a6dc60ffSKozlov Sergey { 0x012a, 8100 }, { 0x0124, 8200 }, { 0x011e, 8300 },
162a6dc60ffSKozlov Sergey { 0x0118, 8400 }, { 0x0112, 8500 }, { 0x010c, 8600 },
163a6dc60ffSKozlov Sergey { 0x0107, 8700 }, { 0x0101, 8800 }, { 0x00fc, 8900 },
164a6dc60ffSKozlov Sergey { 0x00f7, 9000 }, { 0x00f2, 9100 }, { 0x00ec, 9200 },
165a6dc60ffSKozlov Sergey { 0x00e7, 9300 }, { 0x00e2, 9400 }, { 0x00dd, 9500 },
166a6dc60ffSKozlov Sergey { 0x00d8, 9600 }, { 0x00d4, 9700 }, { 0x00cf, 9800 },
167a6dc60ffSKozlov Sergey { 0x00ca, 9900 }, { 0x00c6, 10000 }, { 0x00c2, 10100 },
168a6dc60ffSKozlov Sergey { 0x00be, 10200 }, { 0x00b9, 10300 }, { 0x00b5, 10400 },
169a6dc60ffSKozlov Sergey { 0x00b1, 10500 }, { 0x00ae, 10600 }, { 0x00aa, 10700 },
170a6dc60ffSKozlov Sergey { 0x00a6, 10800 }, { 0x00a3, 10900 }, { 0x009f, 11000 },
171a6dc60ffSKozlov Sergey { 0x009b, 11100 }, { 0x0098, 11200 }, { 0x0095, 11300 },
172a6dc60ffSKozlov Sergey { 0x0091, 11400 }, { 0x008e, 11500 }, { 0x008b, 11600 },
173a6dc60ffSKozlov Sergey { 0x0088, 11700 }, { 0x0085, 11800 }, { 0x0082, 11900 },
174a6dc60ffSKozlov Sergey { 0x007f, 12000 }, { 0x007c, 12100 }, { 0x007a, 12200 },
175a6dc60ffSKozlov Sergey { 0x0077, 12300 }, { 0x0074, 12400 }, { 0x0072, 12500 },
176a6dc60ffSKozlov Sergey { 0x006f, 12600 }, { 0x006d, 12700 }, { 0x006b, 12800 },
177a6dc60ffSKozlov Sergey { 0x0068, 12900 }, { 0x0066, 13000 }, { 0x0064, 13100 },
178a6dc60ffSKozlov Sergey { 0x0061, 13200 }, { 0x005f, 13300 }, { 0x005d, 13400 },
179a6dc60ffSKozlov Sergey { 0x005b, 13500 }, { 0x0059, 13600 }, { 0x0057, 13700 },
180a6dc60ffSKozlov Sergey { 0x0055, 13800 }, { 0x0053, 13900 }, { 0x0051, 14000 },
181a6dc60ffSKozlov Sergey { 0x004f, 14100 }, { 0x004e, 14200 }, { 0x004c, 14300 },
182a6dc60ffSKozlov Sergey { 0x004a, 14400 }, { 0x0049, 14500 }, { 0x0047, 14600 },
183a6dc60ffSKozlov Sergey { 0x0045, 14700 }, { 0x0044, 14800 }, { 0x0042, 14900 },
184a6dc60ffSKozlov Sergey { 0x0041, 15000 }, { 0x003f, 15100 }, { 0x003e, 15200 },
185a6dc60ffSKozlov Sergey { 0x003c, 15300 }, { 0x003b, 15400 }, { 0x003a, 15500 },
186a6dc60ffSKozlov Sergey { 0x0038, 15600 }, { 0x0037, 15700 }, { 0x0036, 15800 },
187a6dc60ffSKozlov Sergey { 0x0034, 15900 }, { 0x0033, 16000 }, { 0x0032, 16100 },
188a6dc60ffSKozlov Sergey { 0x0031, 16200 }, { 0x0030, 16300 }, { 0x002f, 16400 },
189a6dc60ffSKozlov Sergey { 0x002e, 16500 }, { 0x002d, 16600 }, { 0x002c, 16700 },
190a6dc60ffSKozlov Sergey { 0x002b, 16800 }, { 0x002a, 16900 }, { 0x0029, 17000 },
191a6dc60ffSKozlov Sergey { 0x0028, 17100 }, { 0x0027, 17200 }, { 0x0026, 17300 },
192a6dc60ffSKozlov Sergey { 0x0025, 17400 }, { 0x0024, 17500 }, { 0x0023, 17600 },
193a6dc60ffSKozlov Sergey { 0x0022, 17800 }, { 0x0021, 17900 }, { 0x0020, 18000 },
194a6dc60ffSKozlov Sergey { 0x001f, 18200 }, { 0x001e, 18300 }, { 0x001d, 18500 },
195a6dc60ffSKozlov Sergey { 0x001c, 18700 }, { 0x001b, 18900 }, { 0x001a, 19000 },
196a6dc60ffSKozlov Sergey { 0x0019, 19200 }, { 0x0018, 19300 }, { 0x0017, 19500 },
197a6dc60ffSKozlov Sergey { 0x0016, 19700 }, { 0x0015, 19900 }, { 0x0014, 20000 },
198a6dc60ffSKozlov Sergey };
199a6dc60ffSKozlov Sergey
2000854df79SAbylay Ospan static int cxd2841er_freeze_regs(struct cxd2841er_priv *priv);
2010854df79SAbylay Ospan static int cxd2841er_unfreeze_regs(struct cxd2841er_priv *priv);
2020854df79SAbylay Ospan
cxd2841er_i2c_debug(struct cxd2841er_priv * priv,u8 addr,u8 reg,u8 write,const u8 * data,u32 len)203a6dc60ffSKozlov Sergey static void cxd2841er_i2c_debug(struct cxd2841er_priv *priv,
204a6dc60ffSKozlov Sergey u8 addr, u8 reg, u8 write,
205a6dc60ffSKozlov Sergey const u8 *data, u32 len)
206a6dc60ffSKozlov Sergey {
207a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev,
2085d6d93a1SDaniel Scheller "cxd2841er: I2C %s addr %02x reg 0x%02x size %d data %*ph\n",
2095d6d93a1SDaniel Scheller (write == 0 ? "read" : "write"), addr, reg, len, len, data);
210a6dc60ffSKozlov Sergey }
211a6dc60ffSKozlov Sergey
cxd2841er_write_regs(struct cxd2841er_priv * priv,u8 addr,u8 reg,const u8 * data,u32 len)212a6dc60ffSKozlov Sergey static int cxd2841er_write_regs(struct cxd2841er_priv *priv,
213a6dc60ffSKozlov Sergey u8 addr, u8 reg, const u8 *data, u32 len)
214a6dc60ffSKozlov Sergey {
215a6dc60ffSKozlov Sergey int ret;
216d13a7b67SMauro Carvalho Chehab u8 buf[MAX_WRITE_REGSIZE + 1];
217a6dc60ffSKozlov Sergey u8 i2c_addr = (addr == I2C_SLVX ?
218a6dc60ffSKozlov Sergey priv->i2c_addr_slvx : priv->i2c_addr_slvt);
219a6dc60ffSKozlov Sergey struct i2c_msg msg[1] = {
220a6dc60ffSKozlov Sergey {
221a6dc60ffSKozlov Sergey .addr = i2c_addr,
222a6dc60ffSKozlov Sergey .flags = 0,
223d13a7b67SMauro Carvalho Chehab .len = len + 1,
224a6dc60ffSKozlov Sergey .buf = buf,
225a6dc60ffSKozlov Sergey }
226a6dc60ffSKozlov Sergey };
227a6dc60ffSKozlov Sergey
228d13a7b67SMauro Carvalho Chehab if (len + 1 >= sizeof(buf)) {
229d13a7b67SMauro Carvalho Chehab dev_warn(&priv->i2c->dev, "wr reg=%04x: len=%d is too big!\n",
230d13a7b67SMauro Carvalho Chehab reg, len + 1);
231d13a7b67SMauro Carvalho Chehab return -E2BIG;
232d13a7b67SMauro Carvalho Chehab }
233d13a7b67SMauro Carvalho Chehab
234a6dc60ffSKozlov Sergey cxd2841er_i2c_debug(priv, i2c_addr, reg, 1, data, len);
235a6dc60ffSKozlov Sergey buf[0] = reg;
236a6dc60ffSKozlov Sergey memcpy(&buf[1], data, len);
237a6dc60ffSKozlov Sergey
238a6dc60ffSKozlov Sergey ret = i2c_transfer(priv->i2c, msg, 1);
239a6dc60ffSKozlov Sergey if (ret >= 0 && ret != 1)
240a6dc60ffSKozlov Sergey ret = -EIO;
241a6dc60ffSKozlov Sergey if (ret < 0) {
242a6dc60ffSKozlov Sergey dev_warn(&priv->i2c->dev,
243a6dc60ffSKozlov Sergey "%s: i2c wr failed=%d addr=%02x reg=%02x len=%d\n",
244a6dc60ffSKozlov Sergey KBUILD_MODNAME, ret, i2c_addr, reg, len);
245a6dc60ffSKozlov Sergey return ret;
246a6dc60ffSKozlov Sergey }
247a6dc60ffSKozlov Sergey return 0;
248a6dc60ffSKozlov Sergey }
249a6dc60ffSKozlov Sergey
cxd2841er_write_reg(struct cxd2841er_priv * priv,u8 addr,u8 reg,u8 val)250a6dc60ffSKozlov Sergey static int cxd2841er_write_reg(struct cxd2841er_priv *priv,
251a6dc60ffSKozlov Sergey u8 addr, u8 reg, u8 val)
252a6dc60ffSKozlov Sergey {
2533cd890dbSArnd Bergmann u8 tmp = val; /* see gcc.gnu.org/bugzilla/show_bug.cgi?id=81715 */
2543cd890dbSArnd Bergmann
2553cd890dbSArnd Bergmann return cxd2841er_write_regs(priv, addr, reg, &tmp, 1);
256a6dc60ffSKozlov Sergey }
257a6dc60ffSKozlov Sergey
cxd2841er_read_regs(struct cxd2841er_priv * priv,u8 addr,u8 reg,u8 * val,u32 len)258a6dc60ffSKozlov Sergey static int cxd2841er_read_regs(struct cxd2841er_priv *priv,
259a6dc60ffSKozlov Sergey u8 addr, u8 reg, u8 *val, u32 len)
260a6dc60ffSKozlov Sergey {
261a6dc60ffSKozlov Sergey int ret;
262a6dc60ffSKozlov Sergey u8 i2c_addr = (addr == I2C_SLVX ?
263a6dc60ffSKozlov Sergey priv->i2c_addr_slvx : priv->i2c_addr_slvt);
264a6dc60ffSKozlov Sergey struct i2c_msg msg[2] = {
265a6dc60ffSKozlov Sergey {
266a6dc60ffSKozlov Sergey .addr = i2c_addr,
267a6dc60ffSKozlov Sergey .flags = 0,
268a6dc60ffSKozlov Sergey .len = 1,
269a6dc60ffSKozlov Sergey .buf = ®,
270a6dc60ffSKozlov Sergey }, {
271a6dc60ffSKozlov Sergey .addr = i2c_addr,
272a6dc60ffSKozlov Sergey .flags = I2C_M_RD,
273a6dc60ffSKozlov Sergey .len = len,
274a6dc60ffSKozlov Sergey .buf = val,
275a6dc60ffSKozlov Sergey }
276a6dc60ffSKozlov Sergey };
277a6dc60ffSKozlov Sergey
278725e93ebSDaniel Scheller ret = i2c_transfer(priv->i2c, msg, 2);
279725e93ebSDaniel Scheller if (ret >= 0 && ret != 2)
280a6dc60ffSKozlov Sergey ret = -EIO;
281a6dc60ffSKozlov Sergey if (ret < 0) {
282a6dc60ffSKozlov Sergey dev_warn(&priv->i2c->dev,
283a6dc60ffSKozlov Sergey "%s: i2c rd failed=%d addr=%02x reg=%02x\n",
284a6dc60ffSKozlov Sergey KBUILD_MODNAME, ret, i2c_addr, reg);
285a6dc60ffSKozlov Sergey return ret;
286a6dc60ffSKozlov Sergey }
2876c77161aSAbylay Ospan cxd2841er_i2c_debug(priv, i2c_addr, reg, 0, val, len);
288a6dc60ffSKozlov Sergey return 0;
289a6dc60ffSKozlov Sergey }
290a6dc60ffSKozlov Sergey
cxd2841er_read_reg(struct cxd2841er_priv * priv,u8 addr,u8 reg,u8 * val)291a6dc60ffSKozlov Sergey static int cxd2841er_read_reg(struct cxd2841er_priv *priv,
292a6dc60ffSKozlov Sergey u8 addr, u8 reg, u8 *val)
293a6dc60ffSKozlov Sergey {
294a6dc60ffSKozlov Sergey return cxd2841er_read_regs(priv, addr, reg, val, 1);
295a6dc60ffSKozlov Sergey }
296a6dc60ffSKozlov Sergey
cxd2841er_set_reg_bits(struct cxd2841er_priv * priv,u8 addr,u8 reg,u8 data,u8 mask)297a6dc60ffSKozlov Sergey static int cxd2841er_set_reg_bits(struct cxd2841er_priv *priv,
298a6dc60ffSKozlov Sergey u8 addr, u8 reg, u8 data, u8 mask)
299a6dc60ffSKozlov Sergey {
300a6dc60ffSKozlov Sergey int res;
301a6dc60ffSKozlov Sergey u8 rdata;
302a6dc60ffSKozlov Sergey
303a6dc60ffSKozlov Sergey if (mask != 0xff) {
304a6dc60ffSKozlov Sergey res = cxd2841er_read_reg(priv, addr, reg, &rdata);
305a6dc60ffSKozlov Sergey if (res)
306a6dc60ffSKozlov Sergey return res;
307a6dc60ffSKozlov Sergey data = ((data & mask) | (rdata & (mask ^ 0xFF)));
308a6dc60ffSKozlov Sergey }
309a6dc60ffSKozlov Sergey return cxd2841er_write_reg(priv, addr, reg, data);
310a6dc60ffSKozlov Sergey }
311a6dc60ffSKozlov Sergey
cxd2841er_calc_iffreq_xtal(enum cxd2841er_xtal xtal,u32 ifhz)312cbc85a47SDaniel Scheller static u32 cxd2841er_calc_iffreq_xtal(enum cxd2841er_xtal xtal, u32 ifhz)
313cbc85a47SDaniel Scheller {
314cbc85a47SDaniel Scheller u64 tmp;
315cbc85a47SDaniel Scheller
316cbc85a47SDaniel Scheller tmp = (u64) ifhz * 16777216;
317cbc85a47SDaniel Scheller do_div(tmp, ((xtal == SONY_XTAL_24000) ? 48000000 : 41000000));
318cbc85a47SDaniel Scheller
319cbc85a47SDaniel Scheller return (u32) tmp;
320cbc85a47SDaniel Scheller }
321cbc85a47SDaniel Scheller
cxd2841er_calc_iffreq(u32 ifhz)322cbc85a47SDaniel Scheller static u32 cxd2841er_calc_iffreq(u32 ifhz)
323cbc85a47SDaniel Scheller {
324cbc85a47SDaniel Scheller return cxd2841er_calc_iffreq_xtal(SONY_XTAL_20500, ifhz);
325cbc85a47SDaniel Scheller }
326cbc85a47SDaniel Scheller
cxd2841er_get_if_hz(struct cxd2841er_priv * priv,u32 def_hz)3274b866c4eSDaniel Scheller static int cxd2841er_get_if_hz(struct cxd2841er_priv *priv, u32 def_hz)
3284b866c4eSDaniel Scheller {
3294b866c4eSDaniel Scheller u32 hz;
3304b866c4eSDaniel Scheller
3314b866c4eSDaniel Scheller if (priv->frontend.ops.tuner_ops.get_if_frequency
3324b866c4eSDaniel Scheller && (priv->flags & CXD2841ER_AUTO_IFHZ))
3334b866c4eSDaniel Scheller priv->frontend.ops.tuner_ops.get_if_frequency(
3344b866c4eSDaniel Scheller &priv->frontend, &hz);
3354b866c4eSDaniel Scheller else
3364b866c4eSDaniel Scheller hz = def_hz;
3374b866c4eSDaniel Scheller
3384b866c4eSDaniel Scheller return hz;
3394b866c4eSDaniel Scheller }
3404b866c4eSDaniel Scheller
cxd2841er_tuner_set(struct dvb_frontend * fe)341c7518d13SDaniel Scheller static int cxd2841er_tuner_set(struct dvb_frontend *fe)
342c7518d13SDaniel Scheller {
343c7518d13SDaniel Scheller struct cxd2841er_priv *priv = fe->demodulator_priv;
344c7518d13SDaniel Scheller
345c7518d13SDaniel Scheller if ((priv->flags & CXD2841ER_USE_GATECTRL) && fe->ops.i2c_gate_ctrl)
346c7518d13SDaniel Scheller fe->ops.i2c_gate_ctrl(fe, 1);
347c7518d13SDaniel Scheller if (fe->ops.tuner_ops.set_params)
348c7518d13SDaniel Scheller fe->ops.tuner_ops.set_params(fe);
349c7518d13SDaniel Scheller if ((priv->flags & CXD2841ER_USE_GATECTRL) && fe->ops.i2c_gate_ctrl)
350c7518d13SDaniel Scheller fe->ops.i2c_gate_ctrl(fe, 0);
351c7518d13SDaniel Scheller
352c7518d13SDaniel Scheller return 0;
353c7518d13SDaniel Scheller }
354c7518d13SDaniel Scheller
cxd2841er_dvbs2_set_symbol_rate(struct cxd2841er_priv * priv,u32 symbol_rate)355a6dc60ffSKozlov Sergey static int cxd2841er_dvbs2_set_symbol_rate(struct cxd2841er_priv *priv,
356a6dc60ffSKozlov Sergey u32 symbol_rate)
357a6dc60ffSKozlov Sergey {
358a6dc60ffSKozlov Sergey u32 reg_value = 0;
359a6dc60ffSKozlov Sergey u8 data[3] = {0, 0, 0};
360a6dc60ffSKozlov Sergey
361a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
362a6dc60ffSKozlov Sergey /*
363a6dc60ffSKozlov Sergey * regValue = (symbolRateKSps * 2^14 / 1000) + 0.5
364a6dc60ffSKozlov Sergey * = ((symbolRateKSps * 2^14) + 500) / 1000
365a6dc60ffSKozlov Sergey * = ((symbolRateKSps * 16384) + 500) / 1000
366a6dc60ffSKozlov Sergey */
367a6dc60ffSKozlov Sergey reg_value = DIV_ROUND_CLOSEST(symbol_rate * 16384, 1000);
368a6dc60ffSKozlov Sergey if ((reg_value == 0) || (reg_value > 0xFFFFF)) {
369a6dc60ffSKozlov Sergey dev_err(&priv->i2c->dev,
370a6dc60ffSKozlov Sergey "%s(): reg_value is out of range\n", __func__);
371a6dc60ffSKozlov Sergey return -EINVAL;
372a6dc60ffSKozlov Sergey }
373a6dc60ffSKozlov Sergey data[0] = (u8)((reg_value >> 16) & 0x0F);
374a6dc60ffSKozlov Sergey data[1] = (u8)((reg_value >> 8) & 0xFF);
375a6dc60ffSKozlov Sergey data[2] = (u8)(reg_value & 0xFF);
376a6dc60ffSKozlov Sergey /* Set SLV-T Bank : 0xAE */
377a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xae);
378a6dc60ffSKozlov Sergey cxd2841er_write_regs(priv, I2C_SLVT, 0x20, data, 3);
379a6dc60ffSKozlov Sergey return 0;
380a6dc60ffSKozlov Sergey }
381a6dc60ffSKozlov Sergey
382a6dc60ffSKozlov Sergey static void cxd2841er_set_ts_clock_mode(struct cxd2841er_priv *priv,
383a6dc60ffSKozlov Sergey u8 system);
384a6dc60ffSKozlov Sergey
cxd2841er_sleep_s_to_active_s(struct cxd2841er_priv * priv,u8 system,u32 symbol_rate)385a6dc60ffSKozlov Sergey static int cxd2841er_sleep_s_to_active_s(struct cxd2841er_priv *priv,
386a6dc60ffSKozlov Sergey u8 system, u32 symbol_rate)
387a6dc60ffSKozlov Sergey {
388a6dc60ffSKozlov Sergey int ret;
389a6dc60ffSKozlov Sergey u8 data[4] = { 0, 0, 0, 0 };
390a6dc60ffSKozlov Sergey
391a6dc60ffSKozlov Sergey if (priv->state != STATE_SLEEP_S) {
392a6dc60ffSKozlov Sergey dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
393a6dc60ffSKozlov Sergey __func__, (int)priv->state);
394a6dc60ffSKozlov Sergey return -EINVAL;
395a6dc60ffSKozlov Sergey }
396a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
397a6dc60ffSKozlov Sergey cxd2841er_set_ts_clock_mode(priv, SYS_DVBS);
398a6dc60ffSKozlov Sergey /* Set demod mode */
399a6dc60ffSKozlov Sergey if (system == SYS_DVBS) {
400a6dc60ffSKozlov Sergey data[0] = 0x0A;
401a6dc60ffSKozlov Sergey } else if (system == SYS_DVBS2) {
402a6dc60ffSKozlov Sergey data[0] = 0x0B;
403a6dc60ffSKozlov Sergey } else {
404a6dc60ffSKozlov Sergey dev_err(&priv->i2c->dev, "%s(): invalid delsys %d\n",
405a6dc60ffSKozlov Sergey __func__, system);
406a6dc60ffSKozlov Sergey return -EINVAL;
407a6dc60ffSKozlov Sergey }
408a6dc60ffSKozlov Sergey /* Set SLV-X Bank : 0x00 */
409a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
410a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVX, 0x17, data[0]);
411a6dc60ffSKozlov Sergey /* DVB-S/S2 */
412a6dc60ffSKozlov Sergey data[0] = 0x00;
413a6dc60ffSKozlov Sergey /* Set SLV-T Bank : 0x00 */
414a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
415a6dc60ffSKozlov Sergey /* Enable S/S2 auto detection 1 */
416a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x2d, data[0]);
417a6dc60ffSKozlov Sergey /* Set SLV-T Bank : 0xAE */
418a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xae);
419a6dc60ffSKozlov Sergey /* Enable S/S2 auto detection 2 */
420a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x30, data[0]);
421a6dc60ffSKozlov Sergey /* Set SLV-T Bank : 0x00 */
422a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
423a6dc60ffSKozlov Sergey /* Enable demod clock */
424a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
425a6dc60ffSKozlov Sergey /* Enable ADC clock */
426a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x31, 0x01);
427a6dc60ffSKozlov Sergey /* Enable ADC 1 */
428a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x63, 0x16);
429a6dc60ffSKozlov Sergey /* Enable ADC 2 */
430a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x65, 0x3f);
431a6dc60ffSKozlov Sergey /* Set SLV-X Bank : 0x00 */
432a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
433a6dc60ffSKozlov Sergey /* Enable ADC 3 */
434a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
435a6dc60ffSKozlov Sergey /* Set SLV-T Bank : 0xA3 */
436a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa3);
437a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0xac, 0x00);
438a6dc60ffSKozlov Sergey data[0] = 0x07;
439a6dc60ffSKozlov Sergey data[1] = 0x3B;
440a6dc60ffSKozlov Sergey data[2] = 0x08;
441a6dc60ffSKozlov Sergey data[3] = 0xC5;
442a6dc60ffSKozlov Sergey /* Set SLV-T Bank : 0xAB */
443a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xab);
444a6dc60ffSKozlov Sergey cxd2841er_write_regs(priv, I2C_SLVT, 0x98, data, 4);
445a6dc60ffSKozlov Sergey data[0] = 0x05;
446a6dc60ffSKozlov Sergey data[1] = 0x80;
447a6dc60ffSKozlov Sergey data[2] = 0x0A;
448a6dc60ffSKozlov Sergey data[3] = 0x80;
449a6dc60ffSKozlov Sergey cxd2841er_write_regs(priv, I2C_SLVT, 0xa8, data, 4);
450a6dc60ffSKozlov Sergey data[0] = 0x0C;
451a6dc60ffSKozlov Sergey data[1] = 0xCC;
452a6dc60ffSKozlov Sergey cxd2841er_write_regs(priv, I2C_SLVT, 0xc3, data, 2);
453a6dc60ffSKozlov Sergey /* Set demod parameter */
454a6dc60ffSKozlov Sergey ret = cxd2841er_dvbs2_set_symbol_rate(priv, symbol_rate);
455a6dc60ffSKozlov Sergey if (ret != 0)
456a6dc60ffSKozlov Sergey return ret;
457a6dc60ffSKozlov Sergey /* Set SLV-T Bank : 0x00 */
458a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
459a6dc60ffSKozlov Sergey /* disable Hi-Z setting 1 */
460a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x10);
461a6dc60ffSKozlov Sergey /* disable Hi-Z setting 2 */
462a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
463a6dc60ffSKozlov Sergey priv->state = STATE_ACTIVE_S;
464a6dc60ffSKozlov Sergey return 0;
465a6dc60ffSKozlov Sergey }
466a6dc60ffSKozlov Sergey
467a6dc60ffSKozlov Sergey static int cxd2841er_sleep_tc_to_active_t_band(struct cxd2841er_priv *priv,
468a6dc60ffSKozlov Sergey u32 bandwidth);
469a6dc60ffSKozlov Sergey
470a6dc60ffSKozlov Sergey static int cxd2841er_sleep_tc_to_active_t2_band(struct cxd2841er_priv *priv,
471a6dc60ffSKozlov Sergey u32 bandwidth);
472a6dc60ffSKozlov Sergey
473a6dc60ffSKozlov Sergey static int cxd2841er_sleep_tc_to_active_c_band(struct cxd2841er_priv *priv,
474a6dc60ffSKozlov Sergey u32 bandwidth);
475a6dc60ffSKozlov Sergey
47676344a3fSMauro Carvalho Chehab static int cxd2841er_sleep_tc_to_active_i(struct cxd2841er_priv *priv,
47776344a3fSMauro Carvalho Chehab u32 bandwidth);
47876344a3fSMauro Carvalho Chehab
47976344a3fSMauro Carvalho Chehab static int cxd2841er_active_i_to_sleep_tc(struct cxd2841er_priv *priv);
48076344a3fSMauro Carvalho Chehab
48176344a3fSMauro Carvalho Chehab static int cxd2841er_sleep_tc_to_shutdown(struct cxd2841er_priv *priv);
48276344a3fSMauro Carvalho Chehab
48376344a3fSMauro Carvalho Chehab static int cxd2841er_shutdown_to_sleep_tc(struct cxd2841er_priv *priv);
48476344a3fSMauro Carvalho Chehab
485bd2355b8SDaniel Scheller static int cxd2841er_sleep_tc(struct dvb_frontend *fe);
486bd2355b8SDaniel Scheller
cxd2841er_retune_active(struct cxd2841er_priv * priv,struct dtv_frontend_properties * p)487a6dc60ffSKozlov Sergey static int cxd2841er_retune_active(struct cxd2841er_priv *priv,
488a6dc60ffSKozlov Sergey struct dtv_frontend_properties *p)
489a6dc60ffSKozlov Sergey {
490a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
491a6dc60ffSKozlov Sergey if (priv->state != STATE_ACTIVE_S &&
492a6dc60ffSKozlov Sergey priv->state != STATE_ACTIVE_TC) {
493a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
494a6dc60ffSKozlov Sergey __func__, priv->state);
495a6dc60ffSKozlov Sergey return -EINVAL;
496a6dc60ffSKozlov Sergey }
497a6dc60ffSKozlov Sergey /* Set SLV-T Bank : 0x00 */
498a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
499a6dc60ffSKozlov Sergey /* disable TS output */
500a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
501a6dc60ffSKozlov Sergey if (priv->state == STATE_ACTIVE_S)
502a6dc60ffSKozlov Sergey return cxd2841er_dvbs2_set_symbol_rate(
503a6dc60ffSKozlov Sergey priv, p->symbol_rate / 1000);
504a6dc60ffSKozlov Sergey else if (priv->state == STATE_ACTIVE_TC) {
505a6dc60ffSKozlov Sergey switch (priv->system) {
506a6dc60ffSKozlov Sergey case SYS_DVBT:
507a6dc60ffSKozlov Sergey return cxd2841er_sleep_tc_to_active_t_band(
508a6dc60ffSKozlov Sergey priv, p->bandwidth_hz);
509a6dc60ffSKozlov Sergey case SYS_DVBT2:
510a6dc60ffSKozlov Sergey return cxd2841er_sleep_tc_to_active_t2_band(
511a6dc60ffSKozlov Sergey priv, p->bandwidth_hz);
512a6dc60ffSKozlov Sergey case SYS_DVBC_ANNEX_A:
513a6dc60ffSKozlov Sergey return cxd2841er_sleep_tc_to_active_c_band(
51476344a3fSMauro Carvalho Chehab priv, p->bandwidth_hz);
51576344a3fSMauro Carvalho Chehab case SYS_ISDBT:
51676344a3fSMauro Carvalho Chehab cxd2841er_active_i_to_sleep_tc(priv);
51776344a3fSMauro Carvalho Chehab cxd2841er_sleep_tc_to_shutdown(priv);
51876344a3fSMauro Carvalho Chehab cxd2841er_shutdown_to_sleep_tc(priv);
51976344a3fSMauro Carvalho Chehab return cxd2841er_sleep_tc_to_active_i(
52076344a3fSMauro Carvalho Chehab priv, p->bandwidth_hz);
521a6dc60ffSKozlov Sergey }
522a6dc60ffSKozlov Sergey }
523a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
524a6dc60ffSKozlov Sergey __func__, priv->system);
525a6dc60ffSKozlov Sergey return -EINVAL;
526a6dc60ffSKozlov Sergey }
527a6dc60ffSKozlov Sergey
cxd2841er_active_s_to_sleep_s(struct cxd2841er_priv * priv)528a6dc60ffSKozlov Sergey static int cxd2841er_active_s_to_sleep_s(struct cxd2841er_priv *priv)
529a6dc60ffSKozlov Sergey {
530a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
531a6dc60ffSKozlov Sergey if (priv->state != STATE_ACTIVE_S) {
532a6dc60ffSKozlov Sergey dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
533a6dc60ffSKozlov Sergey __func__, priv->state);
534a6dc60ffSKozlov Sergey return -EINVAL;
535a6dc60ffSKozlov Sergey }
536a6dc60ffSKozlov Sergey /* Set SLV-T Bank : 0x00 */
537a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
538a6dc60ffSKozlov Sergey /* disable TS output */
539a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
540a6dc60ffSKozlov Sergey /* enable Hi-Z setting 1 */
541a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x1f);
542a6dc60ffSKozlov Sergey /* enable Hi-Z setting 2 */
543a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
544a6dc60ffSKozlov Sergey /* Set SLV-X Bank : 0x00 */
545a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
546a6dc60ffSKozlov Sergey /* disable ADC 1 */
547a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
548a6dc60ffSKozlov Sergey /* Set SLV-T Bank : 0x00 */
549a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
550a6dc60ffSKozlov Sergey /* disable ADC clock */
551a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x31, 0x00);
552a6dc60ffSKozlov Sergey /* disable ADC 2 */
553a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x63, 0x16);
554a6dc60ffSKozlov Sergey /* disable ADC 3 */
555a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x65, 0x27);
556a6dc60ffSKozlov Sergey /* SADC Bias ON */
557a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x69, 0x06);
558a6dc60ffSKozlov Sergey /* disable demod clock */
559a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
560a6dc60ffSKozlov Sergey /* Set SLV-T Bank : 0xAE */
561a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xae);
562a6dc60ffSKozlov Sergey /* disable S/S2 auto detection1 */
563a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
564a6dc60ffSKozlov Sergey /* Set SLV-T Bank : 0x00 */
565a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
566a6dc60ffSKozlov Sergey /* disable S/S2 auto detection2 */
567a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x2d, 0x00);
568a6dc60ffSKozlov Sergey priv->state = STATE_SLEEP_S;
569a6dc60ffSKozlov Sergey return 0;
570a6dc60ffSKozlov Sergey }
571a6dc60ffSKozlov Sergey
cxd2841er_sleep_s_to_shutdown(struct cxd2841er_priv * priv)572a6dc60ffSKozlov Sergey static int cxd2841er_sleep_s_to_shutdown(struct cxd2841er_priv *priv)
573a6dc60ffSKozlov Sergey {
574a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
575a6dc60ffSKozlov Sergey if (priv->state != STATE_SLEEP_S) {
576a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s(): invalid demod state %d\n",
577a6dc60ffSKozlov Sergey __func__, priv->state);
578a6dc60ffSKozlov Sergey return -EINVAL;
579a6dc60ffSKozlov Sergey }
580a6dc60ffSKozlov Sergey /* Set SLV-T Bank : 0x00 */
581a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
582a6dc60ffSKozlov Sergey /* Disable DSQOUT */
583a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
584a6dc60ffSKozlov Sergey /* Disable DSQIN */
585a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x9c, 0x00);
586a6dc60ffSKozlov Sergey /* Set SLV-X Bank : 0x00 */
587a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
588a6dc60ffSKozlov Sergey /* Disable oscillator */
589a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVX, 0x15, 0x01);
590a6dc60ffSKozlov Sergey /* Set demod mode */
591a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x01);
592a6dc60ffSKozlov Sergey priv->state = STATE_SHUTDOWN;
593a6dc60ffSKozlov Sergey return 0;
594a6dc60ffSKozlov Sergey }
595a6dc60ffSKozlov Sergey
cxd2841er_sleep_tc_to_shutdown(struct cxd2841er_priv * priv)596a6dc60ffSKozlov Sergey static int cxd2841er_sleep_tc_to_shutdown(struct cxd2841er_priv *priv)
597a6dc60ffSKozlov Sergey {
598a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
599a6dc60ffSKozlov Sergey if (priv->state != STATE_SLEEP_TC) {
600a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s(): invalid demod state %d\n",
601a6dc60ffSKozlov Sergey __func__, priv->state);
602a6dc60ffSKozlov Sergey return -EINVAL;
603a6dc60ffSKozlov Sergey }
604a6dc60ffSKozlov Sergey /* Set SLV-X Bank : 0x00 */
605a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
606a6dc60ffSKozlov Sergey /* Disable oscillator */
607a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVX, 0x15, 0x01);
608a6dc60ffSKozlov Sergey /* Set demod mode */
609a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x01);
610a6dc60ffSKozlov Sergey priv->state = STATE_SHUTDOWN;
611a6dc60ffSKozlov Sergey return 0;
612a6dc60ffSKozlov Sergey }
613a6dc60ffSKozlov Sergey
cxd2841er_active_t_to_sleep_tc(struct cxd2841er_priv * priv)614a6dc60ffSKozlov Sergey static int cxd2841er_active_t_to_sleep_tc(struct cxd2841er_priv *priv)
615a6dc60ffSKozlov Sergey {
616a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
617a6dc60ffSKozlov Sergey if (priv->state != STATE_ACTIVE_TC) {
618a6dc60ffSKozlov Sergey dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
619a6dc60ffSKozlov Sergey __func__, priv->state);
620a6dc60ffSKozlov Sergey return -EINVAL;
621a6dc60ffSKozlov Sergey }
622a6dc60ffSKozlov Sergey /* Set SLV-T Bank : 0x00 */
623a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
624a6dc60ffSKozlov Sergey /* disable TS output */
625a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
626a6dc60ffSKozlov Sergey /* enable Hi-Z setting 1 */
627a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
628a6dc60ffSKozlov Sergey /* enable Hi-Z setting 2 */
629a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
630a6dc60ffSKozlov Sergey /* Set SLV-X Bank : 0x00 */
631a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
632a6dc60ffSKozlov Sergey /* disable ADC 1 */
633a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
634a6dc60ffSKozlov Sergey /* Set SLV-T Bank : 0x00 */
635a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
636a6dc60ffSKozlov Sergey /* Disable ADC 2 */
637a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
638a6dc60ffSKozlov Sergey /* Disable ADC 3 */
639a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
640a6dc60ffSKozlov Sergey /* Disable ADC clock */
641a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
642a6dc60ffSKozlov Sergey /* Disable RF level monitor */
643a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
644a6dc60ffSKozlov Sergey /* Disable demod clock */
645a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
646a6dc60ffSKozlov Sergey priv->state = STATE_SLEEP_TC;
647a6dc60ffSKozlov Sergey return 0;
648a6dc60ffSKozlov Sergey }
649a6dc60ffSKozlov Sergey
cxd2841er_active_t2_to_sleep_tc(struct cxd2841er_priv * priv)650a6dc60ffSKozlov Sergey static int cxd2841er_active_t2_to_sleep_tc(struct cxd2841er_priv *priv)
651a6dc60ffSKozlov Sergey {
652a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
653a6dc60ffSKozlov Sergey if (priv->state != STATE_ACTIVE_TC) {
654a6dc60ffSKozlov Sergey dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
655a6dc60ffSKozlov Sergey __func__, priv->state);
656a6dc60ffSKozlov Sergey return -EINVAL;
657a6dc60ffSKozlov Sergey }
658a6dc60ffSKozlov Sergey /* Set SLV-T Bank : 0x00 */
659a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
660a6dc60ffSKozlov Sergey /* disable TS output */
661a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
662a6dc60ffSKozlov Sergey /* enable Hi-Z setting 1 */
663a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
664a6dc60ffSKozlov Sergey /* enable Hi-Z setting 2 */
665a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
666a6dc60ffSKozlov Sergey /* Cancel DVB-T2 setting */
667a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x13);
668a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x83, 0x40);
669a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x86, 0x21);
670a6dc60ffSKozlov Sergey cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x9e, 0x09, 0x0f);
671a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x9f, 0xfb);
672a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2a);
673a6dc60ffSKozlov Sergey cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x38, 0x00, 0x0f);
674a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2b);
675a6dc60ffSKozlov Sergey cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x11, 0x00, 0x3f);
676a6dc60ffSKozlov Sergey /* Set SLV-X Bank : 0x00 */
677a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
678a6dc60ffSKozlov Sergey /* disable ADC 1 */
679a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
680a6dc60ffSKozlov Sergey /* Set SLV-T Bank : 0x00 */
681a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
682a6dc60ffSKozlov Sergey /* Disable ADC 2 */
683a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
684a6dc60ffSKozlov Sergey /* Disable ADC 3 */
685a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
686a6dc60ffSKozlov Sergey /* Disable ADC clock */
687a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
688a6dc60ffSKozlov Sergey /* Disable RF level monitor */
689a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
690a6dc60ffSKozlov Sergey /* Disable demod clock */
691a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
692a6dc60ffSKozlov Sergey priv->state = STATE_SLEEP_TC;
693a6dc60ffSKozlov Sergey return 0;
694a6dc60ffSKozlov Sergey }
695a6dc60ffSKozlov Sergey
cxd2841er_active_c_to_sleep_tc(struct cxd2841er_priv * priv)696a6dc60ffSKozlov Sergey static int cxd2841er_active_c_to_sleep_tc(struct cxd2841er_priv *priv)
697a6dc60ffSKozlov Sergey {
698a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
699a6dc60ffSKozlov Sergey if (priv->state != STATE_ACTIVE_TC) {
700a6dc60ffSKozlov Sergey dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
701a6dc60ffSKozlov Sergey __func__, priv->state);
702a6dc60ffSKozlov Sergey return -EINVAL;
703a6dc60ffSKozlov Sergey }
704a6dc60ffSKozlov Sergey /* Set SLV-T Bank : 0x00 */
705a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
706a6dc60ffSKozlov Sergey /* disable TS output */
707a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
708a6dc60ffSKozlov Sergey /* enable Hi-Z setting 1 */
709a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
710a6dc60ffSKozlov Sergey /* enable Hi-Z setting 2 */
711a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
712a6dc60ffSKozlov Sergey /* Cancel DVB-C setting */
713a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
714a6dc60ffSKozlov Sergey cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa3, 0x00, 0x1f);
715a6dc60ffSKozlov Sergey /* Set SLV-X Bank : 0x00 */
716a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
717a6dc60ffSKozlov Sergey /* disable ADC 1 */
718a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
719a6dc60ffSKozlov Sergey /* Set SLV-T Bank : 0x00 */
720a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
721a6dc60ffSKozlov Sergey /* Disable ADC 2 */
722a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
723a6dc60ffSKozlov Sergey /* Disable ADC 3 */
724a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
725a6dc60ffSKozlov Sergey /* Disable ADC clock */
726a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
727a6dc60ffSKozlov Sergey /* Disable RF level monitor */
728a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
729a6dc60ffSKozlov Sergey /* Disable demod clock */
730a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
731a6dc60ffSKozlov Sergey priv->state = STATE_SLEEP_TC;
732a6dc60ffSKozlov Sergey return 0;
733a6dc60ffSKozlov Sergey }
734a6dc60ffSKozlov Sergey
cxd2841er_active_i_to_sleep_tc(struct cxd2841er_priv * priv)73583808c23SAbylay Ospan static int cxd2841er_active_i_to_sleep_tc(struct cxd2841er_priv *priv)
73683808c23SAbylay Ospan {
73783808c23SAbylay Ospan dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
73883808c23SAbylay Ospan if (priv->state != STATE_ACTIVE_TC) {
73983808c23SAbylay Ospan dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
74083808c23SAbylay Ospan __func__, priv->state);
74183808c23SAbylay Ospan return -EINVAL;
74283808c23SAbylay Ospan }
74383808c23SAbylay Ospan /* Set SLV-T Bank : 0x00 */
74483808c23SAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
74583808c23SAbylay Ospan /* disable TS output */
74683808c23SAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
74783808c23SAbylay Ospan /* enable Hi-Z setting 1 */
74883808c23SAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
74983808c23SAbylay Ospan /* enable Hi-Z setting 2 */
75083808c23SAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
75183808c23SAbylay Ospan
75283808c23SAbylay Ospan /* TODO: Cancel demod parameter */
75383808c23SAbylay Ospan
75483808c23SAbylay Ospan /* Set SLV-X Bank : 0x00 */
75583808c23SAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
75683808c23SAbylay Ospan /* disable ADC 1 */
75783808c23SAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
75883808c23SAbylay Ospan /* Set SLV-T Bank : 0x00 */
75983808c23SAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
76083808c23SAbylay Ospan /* Disable ADC 2 */
76183808c23SAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
76283808c23SAbylay Ospan /* Disable ADC 3 */
76383808c23SAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
76483808c23SAbylay Ospan /* Disable ADC clock */
76583808c23SAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
76683808c23SAbylay Ospan /* Disable RF level monitor */
76783808c23SAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
76883808c23SAbylay Ospan /* Disable demod clock */
76983808c23SAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
77083808c23SAbylay Ospan priv->state = STATE_SLEEP_TC;
77183808c23SAbylay Ospan return 0;
77283808c23SAbylay Ospan }
77383808c23SAbylay Ospan
cxd2841er_shutdown_to_sleep_s(struct cxd2841er_priv * priv)774a6dc60ffSKozlov Sergey static int cxd2841er_shutdown_to_sleep_s(struct cxd2841er_priv *priv)
775a6dc60ffSKozlov Sergey {
776a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
777a6dc60ffSKozlov Sergey if (priv->state != STATE_SHUTDOWN) {
778a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s(): invalid demod state %d\n",
779a6dc60ffSKozlov Sergey __func__, priv->state);
780a6dc60ffSKozlov Sergey return -EINVAL;
781a6dc60ffSKozlov Sergey }
782a6dc60ffSKozlov Sergey /* Set SLV-X Bank : 0x00 */
783a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
784a6dc60ffSKozlov Sergey /* Clear all demodulator registers */
785a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVX, 0x02, 0x00);
786a6dc60ffSKozlov Sergey usleep_range(3000, 5000);
787a6dc60ffSKozlov Sergey /* Set SLV-X Bank : 0x00 */
788a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
789a6dc60ffSKozlov Sergey /* Set demod SW reset */
790a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVX, 0x10, 0x01);
79183808c23SAbylay Ospan
79283808c23SAbylay Ospan switch (priv->xtal) {
79383808c23SAbylay Ospan case SONY_XTAL_20500:
794a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVX, 0x14, 0x00);
79583808c23SAbylay Ospan break;
79683808c23SAbylay Ospan case SONY_XTAL_24000:
79783808c23SAbylay Ospan /* Select demod frequency */
79883808c23SAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVX, 0x12, 0x00);
79983808c23SAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVX, 0x14, 0x03);
80083808c23SAbylay Ospan break;
80183808c23SAbylay Ospan case SONY_XTAL_41000:
80283808c23SAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVX, 0x14, 0x01);
80383808c23SAbylay Ospan break;
80483808c23SAbylay Ospan default:
80583808c23SAbylay Ospan dev_dbg(&priv->i2c->dev, "%s(): invalid demod xtal %d\n",
80683808c23SAbylay Ospan __func__, priv->xtal);
80783808c23SAbylay Ospan return -EINVAL;
80883808c23SAbylay Ospan }
80983808c23SAbylay Ospan
810a6dc60ffSKozlov Sergey /* Set demod mode */
811a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x0a);
812a6dc60ffSKozlov Sergey /* Clear demod SW reset */
813a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVX, 0x10, 0x00);
814a6dc60ffSKozlov Sergey usleep_range(1000, 2000);
815a6dc60ffSKozlov Sergey /* Set SLV-T Bank : 0x00 */
816a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
817a6dc60ffSKozlov Sergey /* enable DSQOUT */
818a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x1F);
819a6dc60ffSKozlov Sergey /* enable DSQIN */
820a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x9C, 0x40);
821a6dc60ffSKozlov Sergey /* TADC Bias On */
822a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
823a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
824a6dc60ffSKozlov Sergey /* SADC Bias On */
825a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x63, 0x16);
826a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x65, 0x27);
827a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x69, 0x06);
828a6dc60ffSKozlov Sergey priv->state = STATE_SLEEP_S;
829a6dc60ffSKozlov Sergey return 0;
830a6dc60ffSKozlov Sergey }
831a6dc60ffSKozlov Sergey
cxd2841er_shutdown_to_sleep_tc(struct cxd2841er_priv * priv)832a6dc60ffSKozlov Sergey static int cxd2841er_shutdown_to_sleep_tc(struct cxd2841er_priv *priv)
833a6dc60ffSKozlov Sergey {
8346c77161aSAbylay Ospan u8 data = 0;
8353f3b48a0SAbylay Ospan
836a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
837a6dc60ffSKozlov Sergey if (priv->state != STATE_SHUTDOWN) {
838a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s(): invalid demod state %d\n",
839a6dc60ffSKozlov Sergey __func__, priv->state);
840a6dc60ffSKozlov Sergey return -EINVAL;
841a6dc60ffSKozlov Sergey }
842a6dc60ffSKozlov Sergey /* Set SLV-X Bank : 0x00 */
843a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
844a6dc60ffSKozlov Sergey /* Clear all demodulator registers */
845a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVX, 0x02, 0x00);
846a6dc60ffSKozlov Sergey usleep_range(3000, 5000);
847a6dc60ffSKozlov Sergey /* Set SLV-X Bank : 0x00 */
848a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
849a6dc60ffSKozlov Sergey /* Set demod SW reset */
850a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVX, 0x10, 0x01);
8516c77161aSAbylay Ospan /* Select ADC clock mode */
852a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVX, 0x13, 0x00);
8536c77161aSAbylay Ospan
8546c77161aSAbylay Ospan switch (priv->xtal) {
8556c77161aSAbylay Ospan case SONY_XTAL_20500:
8566c77161aSAbylay Ospan data = 0x0;
8576c77161aSAbylay Ospan break;
8586c77161aSAbylay Ospan case SONY_XTAL_24000:
8596c77161aSAbylay Ospan /* Select demod frequency */
8606c77161aSAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVX, 0x12, 0x00);
8616c77161aSAbylay Ospan data = 0x3;
8626c77161aSAbylay Ospan break;
8636c77161aSAbylay Ospan case SONY_XTAL_41000:
8646c77161aSAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVX, 0x12, 0x00);
8656c77161aSAbylay Ospan data = 0x1;
8666c77161aSAbylay Ospan break;
8676c77161aSAbylay Ospan }
8686c77161aSAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVX, 0x14, data);
869a6dc60ffSKozlov Sergey /* Clear demod SW reset */
870a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVX, 0x10, 0x00);
871a6dc60ffSKozlov Sergey usleep_range(1000, 2000);
872a6dc60ffSKozlov Sergey /* Set SLV-T Bank : 0x00 */
873a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
874a6dc60ffSKozlov Sergey /* TADC Bias On */
875a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
876a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
877a6dc60ffSKozlov Sergey /* SADC Bias On */
878a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x63, 0x16);
879a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x65, 0x27);
880a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x69, 0x06);
881a6dc60ffSKozlov Sergey priv->state = STATE_SLEEP_TC;
882a6dc60ffSKozlov Sergey return 0;
883a6dc60ffSKozlov Sergey }
884a6dc60ffSKozlov Sergey
cxd2841er_tune_done(struct cxd2841er_priv * priv)885a6dc60ffSKozlov Sergey static int cxd2841er_tune_done(struct cxd2841er_priv *priv)
886a6dc60ffSKozlov Sergey {
887a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
888a6dc60ffSKozlov Sergey /* Set SLV-T Bank : 0x00 */
889a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0, 0);
890a6dc60ffSKozlov Sergey /* SW Reset */
891a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0xfe, 0x01);
892a6dc60ffSKozlov Sergey /* Enable TS output */
893a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x00);
894a6dc60ffSKozlov Sergey return 0;
895a6dc60ffSKozlov Sergey }
896a6dc60ffSKozlov Sergey
897a6dc60ffSKozlov Sergey /* Set TS parallel mode */
cxd2841er_set_ts_clock_mode(struct cxd2841er_priv * priv,u8 system)898a6dc60ffSKozlov Sergey static void cxd2841er_set_ts_clock_mode(struct cxd2841er_priv *priv,
899a6dc60ffSKozlov Sergey u8 system)
900a6dc60ffSKozlov Sergey {
901a6dc60ffSKozlov Sergey u8 serial_ts, ts_rate_ctrl_off, ts_in_off;
902a6dc60ffSKozlov Sergey
903a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
904a6dc60ffSKozlov Sergey /* Set SLV-T Bank : 0x00 */
905a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
906a6dc60ffSKozlov Sergey cxd2841er_read_reg(priv, I2C_SLVT, 0xc4, &serial_ts);
907a6dc60ffSKozlov Sergey cxd2841er_read_reg(priv, I2C_SLVT, 0xd3, &ts_rate_ctrl_off);
908a6dc60ffSKozlov Sergey cxd2841er_read_reg(priv, I2C_SLVT, 0xde, &ts_in_off);
909a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s(): ser_ts=0x%02x rate_ctrl_off=0x%02x in_off=0x%02x\n",
910a6dc60ffSKozlov Sergey __func__, serial_ts, ts_rate_ctrl_off, ts_in_off);
911a6dc60ffSKozlov Sergey
912a6dc60ffSKozlov Sergey /*
913a6dc60ffSKozlov Sergey * slave Bank Addr Bit default Name
91403ab1bd5SDaniel Scheller * <SLV-T> 00h C4h [1:0] 2'b?? OSERCKMODE
91503ab1bd5SDaniel Scheller */
91603ab1bd5SDaniel Scheller cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xc4,
91703ab1bd5SDaniel Scheller ((priv->flags & CXD2841ER_TS_SERIAL) ? 0x01 : 0x00), 0x03);
91803ab1bd5SDaniel Scheller /*
91903ab1bd5SDaniel Scheller * slave Bank Addr Bit default Name
92003ab1bd5SDaniel Scheller * <SLV-T> 00h D1h [1:0] 2'b?? OSERDUTYMODE
92103ab1bd5SDaniel Scheller */
92203ab1bd5SDaniel Scheller cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd1,
92303ab1bd5SDaniel Scheller ((priv->flags & CXD2841ER_TS_SERIAL) ? 0x01 : 0x00), 0x03);
92403ab1bd5SDaniel Scheller /*
92503ab1bd5SDaniel Scheller * slave Bank Addr Bit default Name
926a6dc60ffSKozlov Sergey * <SLV-T> 00h D9h [7:0] 8'h08 OTSCKPERIOD
927a6dc60ffSKozlov Sergey */
928a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0xd9, 0x08);
929a6dc60ffSKozlov Sergey /*
930a6dc60ffSKozlov Sergey * Disable TS IF Clock
931a6dc60ffSKozlov Sergey * slave Bank Addr Bit default Name
932a6dc60ffSKozlov Sergey * <SLV-T> 00h 32h [0] 1'b1 OREG_CK_TSIF_EN
933a6dc60ffSKozlov Sergey */
934a6dc60ffSKozlov Sergey cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x32, 0x00, 0x01);
935a6dc60ffSKozlov Sergey /*
936a6dc60ffSKozlov Sergey * slave Bank Addr Bit default Name
937a6dc60ffSKozlov Sergey * <SLV-T> 00h 33h [1:0] 2'b01 OREG_CKSEL_TSIF
938a6dc60ffSKozlov Sergey */
93903ab1bd5SDaniel Scheller cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x33,
94003ab1bd5SDaniel Scheller ((priv->flags & CXD2841ER_TS_SERIAL) ? 0x01 : 0x00), 0x03);
941a6dc60ffSKozlov Sergey /*
942a6dc60ffSKozlov Sergey * Enable TS IF Clock
943a6dc60ffSKozlov Sergey * slave Bank Addr Bit default Name
944a6dc60ffSKozlov Sergey * <SLV-T> 00h 32h [0] 1'b1 OREG_CK_TSIF_EN
945a6dc60ffSKozlov Sergey */
946a6dc60ffSKozlov Sergey cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x32, 0x01, 0x01);
947a6dc60ffSKozlov Sergey
948a6dc60ffSKozlov Sergey if (system == SYS_DVBT) {
949a6dc60ffSKozlov Sergey /* Enable parity period for DVB-T */
950a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
951a6dc60ffSKozlov Sergey cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x66, 0x01, 0x01);
952a6dc60ffSKozlov Sergey } else if (system == SYS_DVBC_ANNEX_A) {
953a6dc60ffSKozlov Sergey /* Enable parity period for DVB-C */
954a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
955a6dc60ffSKozlov Sergey cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x66, 0x01, 0x01);
956a6dc60ffSKozlov Sergey }
957a6dc60ffSKozlov Sergey }
958a6dc60ffSKozlov Sergey
cxd2841er_chip_id(struct cxd2841er_priv * priv)959a6dc60ffSKozlov Sergey static u8 cxd2841er_chip_id(struct cxd2841er_priv *priv)
960a6dc60ffSKozlov Sergey {
96183808c23SAbylay Ospan u8 chip_id = 0;
962a6dc60ffSKozlov Sergey
963a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
96483808c23SAbylay Ospan if (cxd2841er_write_reg(priv, I2C_SLVT, 0, 0) == 0)
965a6dc60ffSKozlov Sergey cxd2841er_read_reg(priv, I2C_SLVT, 0xfd, &chip_id);
96683808c23SAbylay Ospan else if (cxd2841er_write_reg(priv, I2C_SLVX, 0, 0) == 0)
96783808c23SAbylay Ospan cxd2841er_read_reg(priv, I2C_SLVX, 0xfd, &chip_id);
96883808c23SAbylay Ospan
969a6dc60ffSKozlov Sergey return chip_id;
970a6dc60ffSKozlov Sergey }
971a6dc60ffSKozlov Sergey
cxd2841er_read_status_s(struct dvb_frontend * fe,enum fe_status * status)972a6dc60ffSKozlov Sergey static int cxd2841er_read_status_s(struct dvb_frontend *fe,
973a6dc60ffSKozlov Sergey enum fe_status *status)
974a6dc60ffSKozlov Sergey {
975a6dc60ffSKozlov Sergey u8 reg = 0;
976a6dc60ffSKozlov Sergey struct cxd2841er_priv *priv = fe->demodulator_priv;
977a6dc60ffSKozlov Sergey
978a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
979a6dc60ffSKozlov Sergey *status = 0;
980a6dc60ffSKozlov Sergey if (priv->state != STATE_ACTIVE_S) {
981a6dc60ffSKozlov Sergey dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
982a6dc60ffSKozlov Sergey __func__, priv->state);
983a6dc60ffSKozlov Sergey return -EINVAL;
984a6dc60ffSKozlov Sergey }
985a6dc60ffSKozlov Sergey /* Set SLV-T Bank : 0xA0 */
986a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
987a6dc60ffSKozlov Sergey /*
988a6dc60ffSKozlov Sergey * slave Bank Addr Bit Signal name
989a6dc60ffSKozlov Sergey * <SLV-T> A0h 11h [2] ITSLOCK
990a6dc60ffSKozlov Sergey */
991a6dc60ffSKozlov Sergey cxd2841er_read_reg(priv, I2C_SLVT, 0x11, ®);
992a6dc60ffSKozlov Sergey if (reg & 0x04) {
993a6dc60ffSKozlov Sergey *status = FE_HAS_SIGNAL
994a6dc60ffSKozlov Sergey | FE_HAS_CARRIER
995a6dc60ffSKozlov Sergey | FE_HAS_VITERBI
996a6dc60ffSKozlov Sergey | FE_HAS_SYNC
997a6dc60ffSKozlov Sergey | FE_HAS_LOCK;
998a6dc60ffSKozlov Sergey }
999a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s(): result 0x%x\n", __func__, *status);
1000a6dc60ffSKozlov Sergey return 0;
1001a6dc60ffSKozlov Sergey }
1002a6dc60ffSKozlov Sergey
cxd2841er_read_status_t_t2(struct cxd2841er_priv * priv,u8 * sync,u8 * tslock,u8 * unlock)1003a6dc60ffSKozlov Sergey static int cxd2841er_read_status_t_t2(struct cxd2841er_priv *priv,
1004a6dc60ffSKozlov Sergey u8 *sync, u8 *tslock, u8 *unlock)
1005a6dc60ffSKozlov Sergey {
1006a6dc60ffSKozlov Sergey u8 data = 0;
1007a6dc60ffSKozlov Sergey
1008a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1009a6dc60ffSKozlov Sergey if (priv->state != STATE_ACTIVE_TC)
1010a6dc60ffSKozlov Sergey return -EINVAL;
1011a6dc60ffSKozlov Sergey if (priv->system == SYS_DVBT) {
1012a6dc60ffSKozlov Sergey /* Set SLV-T Bank : 0x10 */
1013a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1014a6dc60ffSKozlov Sergey } else {
1015a6dc60ffSKozlov Sergey /* Set SLV-T Bank : 0x20 */
1016a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
1017a6dc60ffSKozlov Sergey }
1018a6dc60ffSKozlov Sergey cxd2841er_read_reg(priv, I2C_SLVT, 0x10, &data);
1019a6dc60ffSKozlov Sergey if ((data & 0x07) == 0x07) {
1020a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev,
1021a6dc60ffSKozlov Sergey "%s(): invalid hardware state detected\n", __func__);
1022a6dc60ffSKozlov Sergey *sync = 0;
1023a6dc60ffSKozlov Sergey *tslock = 0;
1024a6dc60ffSKozlov Sergey *unlock = 0;
1025a6dc60ffSKozlov Sergey } else {
1026a6dc60ffSKozlov Sergey *sync = ((data & 0x07) == 0x6 ? 1 : 0);
1027a6dc60ffSKozlov Sergey *tslock = ((data & 0x20) ? 1 : 0);
1028a6dc60ffSKozlov Sergey *unlock = ((data & 0x10) ? 1 : 0);
1029a6dc60ffSKozlov Sergey }
1030a6dc60ffSKozlov Sergey return 0;
1031a6dc60ffSKozlov Sergey }
1032a6dc60ffSKozlov Sergey
cxd2841er_read_status_c(struct cxd2841er_priv * priv,u8 * tslock)1033a6dc60ffSKozlov Sergey static int cxd2841er_read_status_c(struct cxd2841er_priv *priv, u8 *tslock)
1034a6dc60ffSKozlov Sergey {
1035a6dc60ffSKozlov Sergey u8 data;
1036a6dc60ffSKozlov Sergey
1037a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1038a6dc60ffSKozlov Sergey if (priv->state != STATE_ACTIVE_TC)
1039a6dc60ffSKozlov Sergey return -EINVAL;
1040a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
1041a6dc60ffSKozlov Sergey cxd2841er_read_reg(priv, I2C_SLVT, 0x88, &data);
1042a6dc60ffSKozlov Sergey if ((data & 0x01) == 0) {
1043a6dc60ffSKozlov Sergey *tslock = 0;
1044a6dc60ffSKozlov Sergey } else {
1045a6dc60ffSKozlov Sergey cxd2841er_read_reg(priv, I2C_SLVT, 0x10, &data);
1046a6dc60ffSKozlov Sergey *tslock = ((data & 0x20) ? 1 : 0);
1047a6dc60ffSKozlov Sergey }
1048a6dc60ffSKozlov Sergey return 0;
1049a6dc60ffSKozlov Sergey }
1050a6dc60ffSKozlov Sergey
cxd2841er_read_status_i(struct cxd2841er_priv * priv,u8 * sync,u8 * tslock,u8 * unlock)105183808c23SAbylay Ospan static int cxd2841er_read_status_i(struct cxd2841er_priv *priv,
105283808c23SAbylay Ospan u8 *sync, u8 *tslock, u8 *unlock)
105383808c23SAbylay Ospan {
105483808c23SAbylay Ospan u8 data = 0;
105583808c23SAbylay Ospan
105683808c23SAbylay Ospan dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
105783808c23SAbylay Ospan if (priv->state != STATE_ACTIVE_TC)
105883808c23SAbylay Ospan return -EINVAL;
105983808c23SAbylay Ospan /* Set SLV-T Bank : 0x60 */
106083808c23SAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
106183808c23SAbylay Ospan cxd2841er_read_reg(priv, I2C_SLVT, 0x10, &data);
106283808c23SAbylay Ospan dev_dbg(&priv->i2c->dev,
106383808c23SAbylay Ospan "%s(): lock=0x%x\n", __func__, data);
106483808c23SAbylay Ospan *sync = ((data & 0x02) ? 1 : 0);
106583808c23SAbylay Ospan *tslock = ((data & 0x01) ? 1 : 0);
106683808c23SAbylay Ospan *unlock = ((data & 0x10) ? 1 : 0);
106783808c23SAbylay Ospan return 0;
106883808c23SAbylay Ospan }
106983808c23SAbylay Ospan
cxd2841er_read_status_tc(struct dvb_frontend * fe,enum fe_status * status)1070a6dc60ffSKozlov Sergey static int cxd2841er_read_status_tc(struct dvb_frontend *fe,
1071a6dc60ffSKozlov Sergey enum fe_status *status)
1072a6dc60ffSKozlov Sergey {
1073a6dc60ffSKozlov Sergey int ret = 0;
1074a6dc60ffSKozlov Sergey u8 sync = 0;
1075a6dc60ffSKozlov Sergey u8 tslock = 0;
1076a6dc60ffSKozlov Sergey u8 unlock = 0;
1077a6dc60ffSKozlov Sergey struct cxd2841er_priv *priv = fe->demodulator_priv;
1078a6dc60ffSKozlov Sergey
1079a6dc60ffSKozlov Sergey *status = 0;
1080a6dc60ffSKozlov Sergey if (priv->state == STATE_ACTIVE_TC) {
1081a6dc60ffSKozlov Sergey if (priv->system == SYS_DVBT || priv->system == SYS_DVBT2) {
1082a6dc60ffSKozlov Sergey ret = cxd2841er_read_status_t_t2(
1083a6dc60ffSKozlov Sergey priv, &sync, &tslock, &unlock);
1084a6dc60ffSKozlov Sergey if (ret)
1085a6dc60ffSKozlov Sergey goto done;
1086a6dc60ffSKozlov Sergey if (unlock)
1087a6dc60ffSKozlov Sergey goto done;
1088a6dc60ffSKozlov Sergey if (sync)
1089a6dc60ffSKozlov Sergey *status = FE_HAS_SIGNAL |
1090a6dc60ffSKozlov Sergey FE_HAS_CARRIER |
1091a6dc60ffSKozlov Sergey FE_HAS_VITERBI |
1092a6dc60ffSKozlov Sergey FE_HAS_SYNC;
1093a6dc60ffSKozlov Sergey if (tslock)
1094a6dc60ffSKozlov Sergey *status |= FE_HAS_LOCK;
109583808c23SAbylay Ospan } else if (priv->system == SYS_ISDBT) {
109683808c23SAbylay Ospan ret = cxd2841er_read_status_i(
109783808c23SAbylay Ospan priv, &sync, &tslock, &unlock);
109883808c23SAbylay Ospan if (ret)
109983808c23SAbylay Ospan goto done;
110083808c23SAbylay Ospan if (unlock)
110183808c23SAbylay Ospan goto done;
110283808c23SAbylay Ospan if (sync)
110383808c23SAbylay Ospan *status = FE_HAS_SIGNAL |
110483808c23SAbylay Ospan FE_HAS_CARRIER |
110583808c23SAbylay Ospan FE_HAS_VITERBI |
110683808c23SAbylay Ospan FE_HAS_SYNC;
110783808c23SAbylay Ospan if (tslock)
110883808c23SAbylay Ospan *status |= FE_HAS_LOCK;
1109a6dc60ffSKozlov Sergey } else if (priv->system == SYS_DVBC_ANNEX_A) {
1110a6dc60ffSKozlov Sergey ret = cxd2841er_read_status_c(priv, &tslock);
1111a6dc60ffSKozlov Sergey if (ret)
1112a6dc60ffSKozlov Sergey goto done;
1113a6dc60ffSKozlov Sergey if (tslock)
1114a6dc60ffSKozlov Sergey *status = FE_HAS_SIGNAL |
1115a6dc60ffSKozlov Sergey FE_HAS_CARRIER |
1116a6dc60ffSKozlov Sergey FE_HAS_VITERBI |
1117a6dc60ffSKozlov Sergey FE_HAS_SYNC |
1118a6dc60ffSKozlov Sergey FE_HAS_LOCK;
1119a6dc60ffSKozlov Sergey }
1120a6dc60ffSKozlov Sergey }
1121a6dc60ffSKozlov Sergey done:
1122a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s(): status 0x%x\n", __func__, *status);
1123a6dc60ffSKozlov Sergey return ret;
1124a6dc60ffSKozlov Sergey }
1125a6dc60ffSKozlov Sergey
cxd2841er_get_carrier_offset_s_s2(struct cxd2841er_priv * priv,int * offset)1126a6dc60ffSKozlov Sergey static int cxd2841er_get_carrier_offset_s_s2(struct cxd2841er_priv *priv,
1127a6dc60ffSKozlov Sergey int *offset)
1128a6dc60ffSKozlov Sergey {
1129a6dc60ffSKozlov Sergey u8 data[3];
1130a6dc60ffSKozlov Sergey u8 is_hs_mode;
1131a6dc60ffSKozlov Sergey s32 cfrl_ctrlval;
1132a6dc60ffSKozlov Sergey s32 temp_div, temp_q, temp_r;
1133a6dc60ffSKozlov Sergey
1134a6dc60ffSKozlov Sergey if (priv->state != STATE_ACTIVE_S) {
1135a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1136a6dc60ffSKozlov Sergey __func__, priv->state);
1137a6dc60ffSKozlov Sergey return -EINVAL;
1138a6dc60ffSKozlov Sergey }
1139a6dc60ffSKozlov Sergey /*
1140a6dc60ffSKozlov Sergey * Get High Sampling Rate mode
1141a6dc60ffSKozlov Sergey * slave Bank Addr Bit Signal name
1142a6dc60ffSKozlov Sergey * <SLV-T> A0h 10h [0] ITRL_LOCK
1143a6dc60ffSKozlov Sergey */
1144a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
1145a6dc60ffSKozlov Sergey cxd2841er_read_reg(priv, I2C_SLVT, 0x10, &data[0]);
1146a6dc60ffSKozlov Sergey if (data[0] & 0x01) {
1147a6dc60ffSKozlov Sergey /*
1148a6dc60ffSKozlov Sergey * slave Bank Addr Bit Signal name
1149a6dc60ffSKozlov Sergey * <SLV-T> A0h 50h [4] IHSMODE
1150a6dc60ffSKozlov Sergey */
1151a6dc60ffSKozlov Sergey cxd2841er_read_reg(priv, I2C_SLVT, 0x50, &data[0]);
1152a6dc60ffSKozlov Sergey is_hs_mode = (data[0] & 0x10 ? 1 : 0);
1153a6dc60ffSKozlov Sergey } else {
1154a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev,
1155a6dc60ffSKozlov Sergey "%s(): unable to detect sampling rate mode\n",
1156a6dc60ffSKozlov Sergey __func__);
1157a6dc60ffSKozlov Sergey return -EINVAL;
1158a6dc60ffSKozlov Sergey }
1159a6dc60ffSKozlov Sergey /*
1160a6dc60ffSKozlov Sergey * slave Bank Addr Bit Signal name
1161a6dc60ffSKozlov Sergey * <SLV-T> A0h 45h [4:0] ICFRL_CTRLVAL[20:16]
1162a6dc60ffSKozlov Sergey * <SLV-T> A0h 46h [7:0] ICFRL_CTRLVAL[15:8]
1163a6dc60ffSKozlov Sergey * <SLV-T> A0h 47h [7:0] ICFRL_CTRLVAL[7:0]
1164a6dc60ffSKozlov Sergey */
1165a6dc60ffSKozlov Sergey cxd2841er_read_regs(priv, I2C_SLVT, 0x45, data, 3);
1166a6dc60ffSKozlov Sergey cfrl_ctrlval = sign_extend32((((u32)data[0] & 0x1F) << 16) |
1167a6dc60ffSKozlov Sergey (((u32)data[1] & 0xFF) << 8) |
1168a6dc60ffSKozlov Sergey ((u32)data[2] & 0xFF), 20);
1169a6dc60ffSKozlov Sergey temp_div = (is_hs_mode ? 1048576 : 1572864);
1170a6dc60ffSKozlov Sergey if (cfrl_ctrlval > 0) {
1171a6dc60ffSKozlov Sergey temp_q = div_s64_rem(97375LL * cfrl_ctrlval,
1172a6dc60ffSKozlov Sergey temp_div, &temp_r);
1173a6dc60ffSKozlov Sergey } else {
1174a6dc60ffSKozlov Sergey temp_q = div_s64_rem(-97375LL * cfrl_ctrlval,
1175a6dc60ffSKozlov Sergey temp_div, &temp_r);
1176a6dc60ffSKozlov Sergey }
1177a6dc60ffSKozlov Sergey if (temp_r >= temp_div / 2)
1178a6dc60ffSKozlov Sergey temp_q++;
1179a6dc60ffSKozlov Sergey if (cfrl_ctrlval > 0)
1180a6dc60ffSKozlov Sergey temp_q *= -1;
1181a6dc60ffSKozlov Sergey *offset = temp_q;
1182a6dc60ffSKozlov Sergey return 0;
1183a6dc60ffSKozlov Sergey }
1184a6dc60ffSKozlov Sergey
cxd2841er_get_carrier_offset_i(struct cxd2841er_priv * priv,u32 bandwidth,int * offset)118576344a3fSMauro Carvalho Chehab static int cxd2841er_get_carrier_offset_i(struct cxd2841er_priv *priv,
118676344a3fSMauro Carvalho Chehab u32 bandwidth, int *offset)
118776344a3fSMauro Carvalho Chehab {
118876344a3fSMauro Carvalho Chehab u8 data[4];
118976344a3fSMauro Carvalho Chehab
119076344a3fSMauro Carvalho Chehab dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
119176344a3fSMauro Carvalho Chehab if (priv->state != STATE_ACTIVE_TC) {
119276344a3fSMauro Carvalho Chehab dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
119376344a3fSMauro Carvalho Chehab __func__, priv->state);
119476344a3fSMauro Carvalho Chehab return -EINVAL;
119576344a3fSMauro Carvalho Chehab }
119676344a3fSMauro Carvalho Chehab if (priv->system != SYS_ISDBT) {
119776344a3fSMauro Carvalho Chehab dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
119876344a3fSMauro Carvalho Chehab __func__, priv->system);
119976344a3fSMauro Carvalho Chehab return -EINVAL;
120076344a3fSMauro Carvalho Chehab }
120176344a3fSMauro Carvalho Chehab cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
120276344a3fSMauro Carvalho Chehab cxd2841er_read_regs(priv, I2C_SLVT, 0x4c, data, sizeof(data));
120376344a3fSMauro Carvalho Chehab *offset = -1 * sign_extend32(
120476344a3fSMauro Carvalho Chehab ((u32)(data[0] & 0x1F) << 24) | ((u32)data[1] << 16) |
120576344a3fSMauro Carvalho Chehab ((u32)data[2] << 8) | (u32)data[3], 29);
120676344a3fSMauro Carvalho Chehab
120776344a3fSMauro Carvalho Chehab switch (bandwidth) {
120876344a3fSMauro Carvalho Chehab case 6000000:
120976344a3fSMauro Carvalho Chehab *offset = -1 * ((*offset) * 8/264);
121076344a3fSMauro Carvalho Chehab break;
121176344a3fSMauro Carvalho Chehab case 7000000:
121276344a3fSMauro Carvalho Chehab *offset = -1 * ((*offset) * 8/231);
121376344a3fSMauro Carvalho Chehab break;
121476344a3fSMauro Carvalho Chehab case 8000000:
121576344a3fSMauro Carvalho Chehab *offset = -1 * ((*offset) * 8/198);
121676344a3fSMauro Carvalho Chehab break;
121776344a3fSMauro Carvalho Chehab default:
121876344a3fSMauro Carvalho Chehab dev_dbg(&priv->i2c->dev, "%s(): invalid bandwidth %d\n",
121976344a3fSMauro Carvalho Chehab __func__, bandwidth);
122076344a3fSMauro Carvalho Chehab return -EINVAL;
122176344a3fSMauro Carvalho Chehab }
122276344a3fSMauro Carvalho Chehab
122376344a3fSMauro Carvalho Chehab dev_dbg(&priv->i2c->dev, "%s(): bandwidth %d offset %d\n",
122476344a3fSMauro Carvalho Chehab __func__, bandwidth, *offset);
122576344a3fSMauro Carvalho Chehab
122676344a3fSMauro Carvalho Chehab return 0;
122776344a3fSMauro Carvalho Chehab }
122876344a3fSMauro Carvalho Chehab
cxd2841er_get_carrier_offset_t(struct cxd2841er_priv * priv,u32 bandwidth,int * offset)1229c5ea46daSAbylay Ospan static int cxd2841er_get_carrier_offset_t(struct cxd2841er_priv *priv,
1230c5ea46daSAbylay Ospan u32 bandwidth, int *offset)
1231c5ea46daSAbylay Ospan {
1232c5ea46daSAbylay Ospan u8 data[4];
1233c5ea46daSAbylay Ospan
1234c5ea46daSAbylay Ospan dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1235c5ea46daSAbylay Ospan if (priv->state != STATE_ACTIVE_TC) {
1236c5ea46daSAbylay Ospan dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1237c5ea46daSAbylay Ospan __func__, priv->state);
1238c5ea46daSAbylay Ospan return -EINVAL;
1239c5ea46daSAbylay Ospan }
1240c5ea46daSAbylay Ospan if (priv->system != SYS_DVBT) {
1241c5ea46daSAbylay Ospan dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
1242c5ea46daSAbylay Ospan __func__, priv->system);
1243c5ea46daSAbylay Ospan return -EINVAL;
1244c5ea46daSAbylay Ospan }
1245c5ea46daSAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1246c5ea46daSAbylay Ospan cxd2841er_read_regs(priv, I2C_SLVT, 0x4c, data, sizeof(data));
1247c5ea46daSAbylay Ospan *offset = -1 * sign_extend32(
1248c5ea46daSAbylay Ospan ((u32)(data[0] & 0x1F) << 24) | ((u32)data[1] << 16) |
1249c5ea46daSAbylay Ospan ((u32)data[2] << 8) | (u32)data[3], 29);
12504da093ceSAbylay Ospan *offset *= (bandwidth / 1000000);
12514da093ceSAbylay Ospan *offset /= 235;
1252c5ea46daSAbylay Ospan return 0;
1253c5ea46daSAbylay Ospan }
1254c5ea46daSAbylay Ospan
cxd2841er_get_carrier_offset_t2(struct cxd2841er_priv * priv,u32 bandwidth,int * offset)1255c8946c8dSMauro Carvalho Chehab static int cxd2841er_get_carrier_offset_t2(struct cxd2841er_priv *priv,
1256c8946c8dSMauro Carvalho Chehab u32 bandwidth, int *offset)
1257a6dc60ffSKozlov Sergey {
1258a6dc60ffSKozlov Sergey u8 data[4];
1259a6dc60ffSKozlov Sergey
1260a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1261a6dc60ffSKozlov Sergey if (priv->state != STATE_ACTIVE_TC) {
1262a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1263a6dc60ffSKozlov Sergey __func__, priv->state);
1264a6dc60ffSKozlov Sergey return -EINVAL;
1265a6dc60ffSKozlov Sergey }
1266a6dc60ffSKozlov Sergey if (priv->system != SYS_DVBT2) {
1267a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
1268a6dc60ffSKozlov Sergey __func__, priv->system);
1269a6dc60ffSKozlov Sergey return -EINVAL;
1270a6dc60ffSKozlov Sergey }
1271a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
1272a6dc60ffSKozlov Sergey cxd2841er_read_regs(priv, I2C_SLVT, 0x4c, data, sizeof(data));
1273a6dc60ffSKozlov Sergey *offset = -1 * sign_extend32(
1274a6dc60ffSKozlov Sergey ((u32)(data[0] & 0x0F) << 24) | ((u32)data[1] << 16) |
1275a6dc60ffSKozlov Sergey ((u32)data[2] << 8) | (u32)data[3], 27);
1276a6dc60ffSKozlov Sergey switch (bandwidth) {
1277a6dc60ffSKozlov Sergey case 1712000:
1278a6dc60ffSKozlov Sergey *offset /= 582;
1279a6dc60ffSKozlov Sergey break;
1280a6dc60ffSKozlov Sergey case 5000000:
1281a6dc60ffSKozlov Sergey case 6000000:
1282a6dc60ffSKozlov Sergey case 7000000:
1283a6dc60ffSKozlov Sergey case 8000000:
1284a6dc60ffSKozlov Sergey *offset *= (bandwidth / 1000000);
1285a6dc60ffSKozlov Sergey *offset /= 940;
1286a6dc60ffSKozlov Sergey break;
1287a6dc60ffSKozlov Sergey default:
1288a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s(): invalid bandwidth %d\n",
1289a6dc60ffSKozlov Sergey __func__, bandwidth);
1290a6dc60ffSKozlov Sergey return -EINVAL;
1291a6dc60ffSKozlov Sergey }
1292a6dc60ffSKozlov Sergey return 0;
1293a6dc60ffSKozlov Sergey }
1294a6dc60ffSKozlov Sergey
cxd2841er_get_carrier_offset_c(struct cxd2841er_priv * priv,int * offset)1295c8946c8dSMauro Carvalho Chehab static int cxd2841er_get_carrier_offset_c(struct cxd2841er_priv *priv,
1296c8946c8dSMauro Carvalho Chehab int *offset)
1297a6dc60ffSKozlov Sergey {
1298a6dc60ffSKozlov Sergey u8 data[2];
1299a6dc60ffSKozlov Sergey
1300a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1301a6dc60ffSKozlov Sergey if (priv->state != STATE_ACTIVE_TC) {
1302a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1303a6dc60ffSKozlov Sergey __func__, priv->state);
1304a6dc60ffSKozlov Sergey return -EINVAL;
1305a6dc60ffSKozlov Sergey }
1306a6dc60ffSKozlov Sergey if (priv->system != SYS_DVBC_ANNEX_A) {
1307a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
1308a6dc60ffSKozlov Sergey __func__, priv->system);
1309a6dc60ffSKozlov Sergey return -EINVAL;
1310a6dc60ffSKozlov Sergey }
1311a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
1312a6dc60ffSKozlov Sergey cxd2841er_read_regs(priv, I2C_SLVT, 0x15, data, sizeof(data));
1313a6dc60ffSKozlov Sergey *offset = div_s64(41000LL * sign_extend32((((u32)data[0] & 0x3f) << 8)
1314a6dc60ffSKozlov Sergey | (u32)data[1], 13), 16384);
1315a6dc60ffSKozlov Sergey return 0;
1316a6dc60ffSKozlov Sergey }
1317a6dc60ffSKozlov Sergey
cxd2841er_read_packet_errors_c(struct cxd2841er_priv * priv,u32 * penum)1318a6f330cbSAbylay Ospan static int cxd2841er_read_packet_errors_c(
1319a6f330cbSAbylay Ospan struct cxd2841er_priv *priv, u32 *penum)
1320a6f330cbSAbylay Ospan {
1321a6f330cbSAbylay Ospan u8 data[3];
1322a6f330cbSAbylay Ospan
1323a6f330cbSAbylay Ospan *penum = 0;
1324a6f330cbSAbylay Ospan if (priv->state != STATE_ACTIVE_TC) {
1325a6f330cbSAbylay Ospan dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1326a6f330cbSAbylay Ospan __func__, priv->state);
1327a6f330cbSAbylay Ospan return -EINVAL;
1328a6f330cbSAbylay Ospan }
1329a6f330cbSAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
1330a6f330cbSAbylay Ospan cxd2841er_read_regs(priv, I2C_SLVT, 0xea, data, sizeof(data));
1331a6f330cbSAbylay Ospan if (data[2] & 0x01)
1332a6f330cbSAbylay Ospan *penum = ((u32)data[0] << 8) | (u32)data[1];
1333a6f330cbSAbylay Ospan return 0;
1334a6f330cbSAbylay Ospan }
1335a6f330cbSAbylay Ospan
cxd2841er_read_packet_errors_t(struct cxd2841er_priv * priv,u32 * penum)1336a6dc60ffSKozlov Sergey static int cxd2841er_read_packet_errors_t(
1337a6dc60ffSKozlov Sergey struct cxd2841er_priv *priv, u32 *penum)
1338a6dc60ffSKozlov Sergey {
1339a6dc60ffSKozlov Sergey u8 data[3];
1340a6dc60ffSKozlov Sergey
1341a6dc60ffSKozlov Sergey *penum = 0;
1342a6dc60ffSKozlov Sergey if (priv->state != STATE_ACTIVE_TC) {
1343a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1344a6dc60ffSKozlov Sergey __func__, priv->state);
1345a6dc60ffSKozlov Sergey return -EINVAL;
1346a6dc60ffSKozlov Sergey }
1347a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1348a6dc60ffSKozlov Sergey cxd2841er_read_regs(priv, I2C_SLVT, 0xea, data, sizeof(data));
1349a6dc60ffSKozlov Sergey if (data[2] & 0x01)
1350a6dc60ffSKozlov Sergey *penum = ((u32)data[0] << 8) | (u32)data[1];
1351a6dc60ffSKozlov Sergey return 0;
1352a6dc60ffSKozlov Sergey }
1353a6dc60ffSKozlov Sergey
cxd2841er_read_packet_errors_t2(struct cxd2841er_priv * priv,u32 * penum)1354a6dc60ffSKozlov Sergey static int cxd2841er_read_packet_errors_t2(
1355a6dc60ffSKozlov Sergey struct cxd2841er_priv *priv, u32 *penum)
1356a6dc60ffSKozlov Sergey {
1357a6dc60ffSKozlov Sergey u8 data[3];
1358a6dc60ffSKozlov Sergey
1359a6dc60ffSKozlov Sergey *penum = 0;
1360a6dc60ffSKozlov Sergey if (priv->state != STATE_ACTIVE_TC) {
1361a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1362a6dc60ffSKozlov Sergey __func__, priv->state);
1363a6dc60ffSKozlov Sergey return -EINVAL;
1364a6dc60ffSKozlov Sergey }
1365a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x24);
1366a6dc60ffSKozlov Sergey cxd2841er_read_regs(priv, I2C_SLVT, 0xfd, data, sizeof(data));
1367a6dc60ffSKozlov Sergey if (data[0] & 0x01)
1368a6dc60ffSKozlov Sergey *penum = ((u32)data[1] << 8) | (u32)data[2];
1369a6dc60ffSKozlov Sergey return 0;
1370a6dc60ffSKozlov Sergey }
1371a6dc60ffSKozlov Sergey
cxd2841er_read_packet_errors_i(struct cxd2841er_priv * priv,u32 * penum)137283808c23SAbylay Ospan static int cxd2841er_read_packet_errors_i(
137383808c23SAbylay Ospan struct cxd2841er_priv *priv, u32 *penum)
137483808c23SAbylay Ospan {
137583808c23SAbylay Ospan u8 data[2];
137683808c23SAbylay Ospan
137783808c23SAbylay Ospan *penum = 0;
137883808c23SAbylay Ospan if (priv->state != STATE_ACTIVE_TC) {
137983808c23SAbylay Ospan dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
138083808c23SAbylay Ospan __func__, priv->state);
138183808c23SAbylay Ospan return -EINVAL;
138283808c23SAbylay Ospan }
138383808c23SAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
138483808c23SAbylay Ospan cxd2841er_read_regs(priv, I2C_SLVT, 0xA1, data, 1);
138583808c23SAbylay Ospan
138683808c23SAbylay Ospan if (!(data[0] & 0x01))
138783808c23SAbylay Ospan return 0;
138883808c23SAbylay Ospan
138983808c23SAbylay Ospan /* Layer A */
139083808c23SAbylay Ospan cxd2841er_read_regs(priv, I2C_SLVT, 0xA2, data, sizeof(data));
139183808c23SAbylay Ospan *penum = ((u32)data[0] << 8) | (u32)data[1];
139283808c23SAbylay Ospan
139383808c23SAbylay Ospan /* Layer B */
139483808c23SAbylay Ospan cxd2841er_read_regs(priv, I2C_SLVT, 0xA4, data, sizeof(data));
139583808c23SAbylay Ospan *penum += ((u32)data[0] << 8) | (u32)data[1];
139683808c23SAbylay Ospan
139783808c23SAbylay Ospan /* Layer C */
139883808c23SAbylay Ospan cxd2841er_read_regs(priv, I2C_SLVT, 0xA6, data, sizeof(data));
139983808c23SAbylay Ospan *penum += ((u32)data[0] << 8) | (u32)data[1];
140083808c23SAbylay Ospan
140183808c23SAbylay Ospan return 0;
140283808c23SAbylay Ospan }
140383808c23SAbylay Ospan
cxd2841er_read_ber_c(struct cxd2841er_priv * priv,u32 * bit_error,u32 * bit_count)1404a6f330cbSAbylay Ospan static int cxd2841er_read_ber_c(struct cxd2841er_priv *priv,
1405a6f330cbSAbylay Ospan u32 *bit_error, u32 *bit_count)
1406a6f330cbSAbylay Ospan {
1407a6f330cbSAbylay Ospan u8 data[3];
1408a6f330cbSAbylay Ospan u32 bit_err, period_exp;
1409a6f330cbSAbylay Ospan
1410a6f330cbSAbylay Ospan dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1411a6f330cbSAbylay Ospan if (priv->state != STATE_ACTIVE_TC) {
1412a6f330cbSAbylay Ospan dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1413a6f330cbSAbylay Ospan __func__, priv->state);
1414a6f330cbSAbylay Ospan return -EINVAL;
1415a6f330cbSAbylay Ospan }
1416a6f330cbSAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
1417a6f330cbSAbylay Ospan cxd2841er_read_regs(priv, I2C_SLVT, 0x62, data, sizeof(data));
1418a6f330cbSAbylay Ospan if (!(data[0] & 0x80)) {
1419a6f330cbSAbylay Ospan dev_dbg(&priv->i2c->dev,
1420a6f330cbSAbylay Ospan "%s(): no valid BER data\n", __func__);
1421a6f330cbSAbylay Ospan return -EINVAL;
1422a6f330cbSAbylay Ospan }
1423a6f330cbSAbylay Ospan bit_err = ((u32)(data[0] & 0x3f) << 16) |
1424a6f330cbSAbylay Ospan ((u32)data[1] << 8) |
1425a6f330cbSAbylay Ospan (u32)data[2];
1426a6f330cbSAbylay Ospan cxd2841er_read_reg(priv, I2C_SLVT, 0x60, data);
1427a6f330cbSAbylay Ospan period_exp = data[0] & 0x1f;
1428a6f330cbSAbylay Ospan
1429a6f330cbSAbylay Ospan if ((period_exp <= 11) && (bit_err > (1 << period_exp) * 204 * 8)) {
1430a6f330cbSAbylay Ospan dev_dbg(&priv->i2c->dev,
1431a6f330cbSAbylay Ospan "%s(): period_exp(%u) or bit_err(%u) not in range. no valid BER data\n",
1432a6f330cbSAbylay Ospan __func__, period_exp, bit_err);
1433a6f330cbSAbylay Ospan return -EINVAL;
1434a6f330cbSAbylay Ospan }
1435a6f330cbSAbylay Ospan
1436a6f330cbSAbylay Ospan dev_dbg(&priv->i2c->dev,
1437a6f330cbSAbylay Ospan "%s(): period_exp(%u) or bit_err(%u) count=%d\n",
1438a6f330cbSAbylay Ospan __func__, period_exp, bit_err,
1439a6f330cbSAbylay Ospan ((1 << period_exp) * 204 * 8));
1440a6f330cbSAbylay Ospan
1441a6f330cbSAbylay Ospan *bit_error = bit_err;
1442a6f330cbSAbylay Ospan *bit_count = ((1 << period_exp) * 204 * 8);
1443a6f330cbSAbylay Ospan
1444a6f330cbSAbylay Ospan return 0;
1445a6f330cbSAbylay Ospan }
1446a6f330cbSAbylay Ospan
cxd2841er_read_ber_i(struct cxd2841er_priv * priv,u32 * bit_error,u32 * bit_count)14470854df79SAbylay Ospan static int cxd2841er_read_ber_i(struct cxd2841er_priv *priv,
14480854df79SAbylay Ospan u32 *bit_error, u32 *bit_count)
14490854df79SAbylay Ospan {
14500854df79SAbylay Ospan u8 data[3];
14510854df79SAbylay Ospan u8 pktnum[2];
14520854df79SAbylay Ospan
14530854df79SAbylay Ospan dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
14540854df79SAbylay Ospan if (priv->state != STATE_ACTIVE_TC) {
14550854df79SAbylay Ospan dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
14560854df79SAbylay Ospan __func__, priv->state);
14570854df79SAbylay Ospan return -EINVAL;
14580854df79SAbylay Ospan }
14590854df79SAbylay Ospan
14600854df79SAbylay Ospan cxd2841er_freeze_regs(priv);
14610854df79SAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
14620854df79SAbylay Ospan cxd2841er_read_regs(priv, I2C_SLVT, 0x5B, pktnum, sizeof(pktnum));
14630854df79SAbylay Ospan cxd2841er_read_regs(priv, I2C_SLVT, 0x16, data, sizeof(data));
14646ccf821cSDaniel Scheller cxd2841er_unfreeze_regs(priv);
14650854df79SAbylay Ospan
14660854df79SAbylay Ospan if (!pktnum[0] && !pktnum[1]) {
14670854df79SAbylay Ospan dev_dbg(&priv->i2c->dev,
14680854df79SAbylay Ospan "%s(): no valid BER data\n", __func__);
14690854df79SAbylay Ospan return -EINVAL;
14700854df79SAbylay Ospan }
14710854df79SAbylay Ospan
14720854df79SAbylay Ospan *bit_error = ((u32)(data[0] & 0x7F) << 16) |
14730854df79SAbylay Ospan ((u32)data[1] << 8) | data[2];
14740854df79SAbylay Ospan *bit_count = ((((u32)pktnum[0] << 8) | pktnum[1]) * 204 * 8);
14750854df79SAbylay Ospan dev_dbg(&priv->i2c->dev, "%s(): bit_error=%u bit_count=%u\n",
14760854df79SAbylay Ospan __func__, *bit_error, *bit_count);
14770854df79SAbylay Ospan
14780854df79SAbylay Ospan return 0;
14790854df79SAbylay Ospan }
14800854df79SAbylay Ospan
cxd2841er_mon_read_ber_s(struct cxd2841er_priv * priv,u32 * bit_error,u32 * bit_count)14814216be14SMauro Carvalho Chehab static int cxd2841er_mon_read_ber_s(struct cxd2841er_priv *priv,
14824216be14SMauro Carvalho Chehab u32 *bit_error, u32 *bit_count)
1483a6dc60ffSKozlov Sergey {
1484a6dc60ffSKozlov Sergey u8 data[11];
1485a6dc60ffSKozlov Sergey
1486a6dc60ffSKozlov Sergey /* Set SLV-T Bank : 0xA0 */
1487a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
1488a6dc60ffSKozlov Sergey /*
1489a6dc60ffSKozlov Sergey * slave Bank Addr Bit Signal name
1490a6dc60ffSKozlov Sergey * <SLV-T> A0h 35h [0] IFVBER_VALID
1491a6dc60ffSKozlov Sergey * <SLV-T> A0h 36h [5:0] IFVBER_BITERR[21:16]
1492a6dc60ffSKozlov Sergey * <SLV-T> A0h 37h [7:0] IFVBER_BITERR[15:8]
1493a6dc60ffSKozlov Sergey * <SLV-T> A0h 38h [7:0] IFVBER_BITERR[7:0]
1494a6dc60ffSKozlov Sergey * <SLV-T> A0h 3Dh [5:0] IFVBER_BITNUM[21:16]
1495a6dc60ffSKozlov Sergey * <SLV-T> A0h 3Eh [7:0] IFVBER_BITNUM[15:8]
1496a6dc60ffSKozlov Sergey * <SLV-T> A0h 3Fh [7:0] IFVBER_BITNUM[7:0]
1497a6dc60ffSKozlov Sergey */
1498a6dc60ffSKozlov Sergey cxd2841er_read_regs(priv, I2C_SLVT, 0x35, data, 11);
1499a6dc60ffSKozlov Sergey if (data[0] & 0x01) {
15004216be14SMauro Carvalho Chehab *bit_error = ((u32)(data[1] & 0x3F) << 16) |
1501a6dc60ffSKozlov Sergey ((u32)(data[2] & 0xFF) << 8) |
1502a6dc60ffSKozlov Sergey (u32)(data[3] & 0xFF);
15034216be14SMauro Carvalho Chehab *bit_count = ((u32)(data[8] & 0x3F) << 16) |
1504a6dc60ffSKozlov Sergey ((u32)(data[9] & 0xFF) << 8) |
1505a6dc60ffSKozlov Sergey (u32)(data[10] & 0xFF);
15064216be14SMauro Carvalho Chehab if ((*bit_count == 0) || (*bit_error > *bit_count)) {
1507a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev,
1508a6dc60ffSKozlov Sergey "%s(): invalid bit_error %d, bit_count %d\n",
15094216be14SMauro Carvalho Chehab __func__, *bit_error, *bit_count);
1510f1b26622SMauro Carvalho Chehab return -EINVAL;
1511a6dc60ffSKozlov Sergey }
1512a6dc60ffSKozlov Sergey return 0;
1513a6dc60ffSKozlov Sergey }
1514f1b26622SMauro Carvalho Chehab dev_dbg(&priv->i2c->dev, "%s(): no data available\n", __func__);
1515f1b26622SMauro Carvalho Chehab return -EINVAL;
1516f1b26622SMauro Carvalho Chehab }
1517a6dc60ffSKozlov Sergey
1518a6dc60ffSKozlov Sergey
cxd2841er_mon_read_ber_s2(struct cxd2841er_priv * priv,u32 * bit_error,u32 * bit_count)15194216be14SMauro Carvalho Chehab static int cxd2841er_mon_read_ber_s2(struct cxd2841er_priv *priv,
15204216be14SMauro Carvalho Chehab u32 *bit_error, u32 *bit_count)
1521a6dc60ffSKozlov Sergey {
1522a6dc60ffSKozlov Sergey u8 data[5];
15234216be14SMauro Carvalho Chehab u32 period;
1524a6dc60ffSKozlov Sergey
1525a6dc60ffSKozlov Sergey /* Set SLV-T Bank : 0xB2 */
1526a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xb2);
1527a6dc60ffSKozlov Sergey /*
1528a6dc60ffSKozlov Sergey * slave Bank Addr Bit Signal name
1529a6dc60ffSKozlov Sergey * <SLV-T> B2h 30h [0] IFLBER_VALID
1530a6dc60ffSKozlov Sergey * <SLV-T> B2h 31h [3:0] IFLBER_BITERR[27:24]
1531a6dc60ffSKozlov Sergey * <SLV-T> B2h 32h [7:0] IFLBER_BITERR[23:16]
1532a6dc60ffSKozlov Sergey * <SLV-T> B2h 33h [7:0] IFLBER_BITERR[15:8]
1533a6dc60ffSKozlov Sergey * <SLV-T> B2h 34h [7:0] IFLBER_BITERR[7:0]
1534a6dc60ffSKozlov Sergey */
1535a6dc60ffSKozlov Sergey cxd2841er_read_regs(priv, I2C_SLVT, 0x30, data, 5);
1536a6dc60ffSKozlov Sergey if (data[0] & 0x01) {
1537a6dc60ffSKozlov Sergey /* Bit error count */
15384216be14SMauro Carvalho Chehab *bit_error = ((u32)(data[1] & 0x0F) << 24) |
1539a6dc60ffSKozlov Sergey ((u32)(data[2] & 0xFF) << 16) |
1540a6dc60ffSKozlov Sergey ((u32)(data[3] & 0xFF) << 8) |
1541a6dc60ffSKozlov Sergey (u32)(data[4] & 0xFF);
1542a6dc60ffSKozlov Sergey
1543a6dc60ffSKozlov Sergey /* Set SLV-T Bank : 0xA0 */
1544a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
1545a6dc60ffSKozlov Sergey cxd2841er_read_reg(priv, I2C_SLVT, 0x7a, data);
1546a6dc60ffSKozlov Sergey /* Measurement period */
1547a6dc60ffSKozlov Sergey period = (u32)(1 << (data[0] & 0x0F));
1548a6dc60ffSKozlov Sergey if (period == 0) {
1549a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev,
1550a6dc60ffSKozlov Sergey "%s(): period is 0\n", __func__);
1551f1b26622SMauro Carvalho Chehab return -EINVAL;
1552a6dc60ffSKozlov Sergey }
15534216be14SMauro Carvalho Chehab if (*bit_error > (period * 64800)) {
1554a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev,
1555a6dc60ffSKozlov Sergey "%s(): invalid bit_err 0x%x period 0x%x\n",
15564216be14SMauro Carvalho Chehab __func__, *bit_error, period);
1557f1b26622SMauro Carvalho Chehab return -EINVAL;
1558a6dc60ffSKozlov Sergey }
15594216be14SMauro Carvalho Chehab *bit_count = period * 64800;
15604216be14SMauro Carvalho Chehab
1561f1b26622SMauro Carvalho Chehab return 0;
1562a6dc60ffSKozlov Sergey } else {
1563a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev,
1564a6dc60ffSKozlov Sergey "%s(): no data available\n", __func__);
1565a6dc60ffSKozlov Sergey }
1566f1b26622SMauro Carvalho Chehab return -EINVAL;
1567a6dc60ffSKozlov Sergey }
1568a6dc60ffSKozlov Sergey
cxd2841er_read_ber_t2(struct cxd2841er_priv * priv,u32 * bit_error,u32 * bit_count)15694216be14SMauro Carvalho Chehab static int cxd2841er_read_ber_t2(struct cxd2841er_priv *priv,
15704216be14SMauro Carvalho Chehab u32 *bit_error, u32 *bit_count)
1571a6dc60ffSKozlov Sergey {
1572a6dc60ffSKozlov Sergey u8 data[4];
15734216be14SMauro Carvalho Chehab u32 period_exp, n_ldpc;
1574a6dc60ffSKozlov Sergey
1575a6dc60ffSKozlov Sergey if (priv->state != STATE_ACTIVE_TC) {
1576a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev,
1577a6dc60ffSKozlov Sergey "%s(): invalid state %d\n", __func__, priv->state);
1578a6dc60ffSKozlov Sergey return -EINVAL;
1579a6dc60ffSKozlov Sergey }
1580a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
1581a6dc60ffSKozlov Sergey cxd2841er_read_regs(priv, I2C_SLVT, 0x39, data, sizeof(data));
1582a6dc60ffSKozlov Sergey if (!(data[0] & 0x10)) {
1583a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev,
1584a6dc60ffSKozlov Sergey "%s(): no valid BER data\n", __func__);
15854216be14SMauro Carvalho Chehab return -EINVAL;
1586a6dc60ffSKozlov Sergey }
15874216be14SMauro Carvalho Chehab *bit_error = ((u32)(data[0] & 0x0f) << 24) |
1588a6dc60ffSKozlov Sergey ((u32)data[1] << 16) |
1589a6dc60ffSKozlov Sergey ((u32)data[2] << 8) |
1590a6dc60ffSKozlov Sergey (u32)data[3];
1591a6dc60ffSKozlov Sergey cxd2841er_read_reg(priv, I2C_SLVT, 0x6f, data);
1592a6dc60ffSKozlov Sergey period_exp = data[0] & 0x0f;
1593a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x22);
1594a6dc60ffSKozlov Sergey cxd2841er_read_reg(priv, I2C_SLVT, 0x5e, data);
1595a6dc60ffSKozlov Sergey n_ldpc = ((data[0] & 0x03) == 0 ? 16200 : 64800);
15964216be14SMauro Carvalho Chehab if (*bit_error > ((1U << period_exp) * n_ldpc)) {
1597a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev,
1598a6dc60ffSKozlov Sergey "%s(): invalid BER value\n", __func__);
1599a6dc60ffSKozlov Sergey return -EINVAL;
1600a6dc60ffSKozlov Sergey }
16014216be14SMauro Carvalho Chehab
16024216be14SMauro Carvalho Chehab /*
16034216be14SMauro Carvalho Chehab * FIXME: the right thing would be to return bit_error untouched,
16044216be14SMauro Carvalho Chehab * but, as we don't know the scale returned by the counters, let's
16054216be14SMauro Carvalho Chehab * at least preserver BER = bit_error/bit_count.
16064216be14SMauro Carvalho Chehab */
1607a6dc60ffSKozlov Sergey if (period_exp >= 4) {
16084216be14SMauro Carvalho Chehab *bit_count = (1U << (period_exp - 4)) * (n_ldpc / 200);
16094216be14SMauro Carvalho Chehab *bit_error *= 3125ULL;
1610a6dc60ffSKozlov Sergey } else {
16114216be14SMauro Carvalho Chehab *bit_count = (1U << period_exp) * (n_ldpc / 200);
1612a6f330cbSAbylay Ospan *bit_error *= 50000ULL;
1613a6dc60ffSKozlov Sergey }
1614a6dc60ffSKozlov Sergey return 0;
1615a6dc60ffSKozlov Sergey }
1616a6dc60ffSKozlov Sergey
cxd2841er_read_ber_t(struct cxd2841er_priv * priv,u32 * bit_error,u32 * bit_count)16174216be14SMauro Carvalho Chehab static int cxd2841er_read_ber_t(struct cxd2841er_priv *priv,
16184216be14SMauro Carvalho Chehab u32 *bit_error, u32 *bit_count)
1619a6dc60ffSKozlov Sergey {
1620a6dc60ffSKozlov Sergey u8 data[2];
16214216be14SMauro Carvalho Chehab u32 period;
1622a6dc60ffSKozlov Sergey
1623a6dc60ffSKozlov Sergey if (priv->state != STATE_ACTIVE_TC) {
1624a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev,
1625a6dc60ffSKozlov Sergey "%s(): invalid state %d\n", __func__, priv->state);
1626a6dc60ffSKozlov Sergey return -EINVAL;
1627a6dc60ffSKozlov Sergey }
1628a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1629a6dc60ffSKozlov Sergey cxd2841er_read_reg(priv, I2C_SLVT, 0x39, data);
1630a6dc60ffSKozlov Sergey if (!(data[0] & 0x01)) {
1631a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev,
1632a6dc60ffSKozlov Sergey "%s(): no valid BER data\n", __func__);
1633a6dc60ffSKozlov Sergey return 0;
1634a6dc60ffSKozlov Sergey }
1635a6dc60ffSKozlov Sergey cxd2841er_read_regs(priv, I2C_SLVT, 0x22, data, sizeof(data));
16364216be14SMauro Carvalho Chehab *bit_error = ((u32)data[0] << 8) | (u32)data[1];
1637a6dc60ffSKozlov Sergey cxd2841er_read_reg(priv, I2C_SLVT, 0x6f, data);
1638a6dc60ffSKozlov Sergey period = ((data[0] & 0x07) == 0) ? 256 : (4096 << (data[0] & 0x07));
16394216be14SMauro Carvalho Chehab
16404216be14SMauro Carvalho Chehab /*
16414216be14SMauro Carvalho Chehab * FIXME: the right thing would be to return bit_error untouched,
16424216be14SMauro Carvalho Chehab * but, as we don't know the scale returned by the counters, let's
16434216be14SMauro Carvalho Chehab * at least preserver BER = bit_error/bit_count.
16444216be14SMauro Carvalho Chehab */
16454216be14SMauro Carvalho Chehab *bit_count = period / 128;
16464216be14SMauro Carvalho Chehab *bit_error *= 78125ULL;
1647a6dc60ffSKozlov Sergey return 0;
1648a6dc60ffSKozlov Sergey }
1649a6dc60ffSKozlov Sergey
cxd2841er_freeze_regs(struct cxd2841er_priv * priv)16504a86bc10SAbylay Ospan static int cxd2841er_freeze_regs(struct cxd2841er_priv *priv)
16514a86bc10SAbylay Ospan {
16524a86bc10SAbylay Ospan /*
16534a86bc10SAbylay Ospan * Freeze registers: ensure multiple separate register reads
16544a86bc10SAbylay Ospan * are from the same snapshot
16554a86bc10SAbylay Ospan */
16564a86bc10SAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x01, 0x01);
16574a86bc10SAbylay Ospan return 0;
16584a86bc10SAbylay Ospan }
16594a86bc10SAbylay Ospan
cxd2841er_unfreeze_regs(struct cxd2841er_priv * priv)16604a86bc10SAbylay Ospan static int cxd2841er_unfreeze_regs(struct cxd2841er_priv *priv)
16614a86bc10SAbylay Ospan {
16624a86bc10SAbylay Ospan /*
16634a86bc10SAbylay Ospan * un-freeze registers
16644a86bc10SAbylay Ospan */
16654a86bc10SAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x01, 0x00);
16664a86bc10SAbylay Ospan return 0;
16674a86bc10SAbylay Ospan }
16684a86bc10SAbylay Ospan
cxd2841er_dvbs_read_snr(struct cxd2841er_priv * priv,u8 delsys,u32 * snr)1669e05b1872SAbylay Ospan static u32 cxd2841er_dvbs_read_snr(struct cxd2841er_priv *priv,
1670e05b1872SAbylay Ospan u8 delsys, u32 *snr)
1671a6dc60ffSKozlov Sergey {
1672a6dc60ffSKozlov Sergey u8 data[3];
1673a6dc60ffSKozlov Sergey u32 res = 0, value;
1674a6dc60ffSKozlov Sergey int min_index, max_index, index;
1675a6dc60ffSKozlov Sergey static const struct cxd2841er_cnr_data *cn_data;
1676a6dc60ffSKozlov Sergey
16774a86bc10SAbylay Ospan cxd2841er_freeze_regs(priv);
1678a6dc60ffSKozlov Sergey /* Set SLV-T Bank : 0xA1 */
1679a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa1);
1680a6dc60ffSKozlov Sergey /*
1681a6dc60ffSKozlov Sergey * slave Bank Addr Bit Signal name
1682a6dc60ffSKozlov Sergey * <SLV-T> A1h 10h [0] ICPM_QUICKRDY
1683a6dc60ffSKozlov Sergey * <SLV-T> A1h 11h [4:0] ICPM_QUICKCNDT[12:8]
1684a6dc60ffSKozlov Sergey * <SLV-T> A1h 12h [7:0] ICPM_QUICKCNDT[7:0]
1685a6dc60ffSKozlov Sergey */
1686a6dc60ffSKozlov Sergey cxd2841er_read_regs(priv, I2C_SLVT, 0x10, data, 3);
16876ccf821cSDaniel Scheller cxd2841er_unfreeze_regs(priv);
16886ccf821cSDaniel Scheller
1689a6dc60ffSKozlov Sergey if (data[0] & 0x01) {
1690a6dc60ffSKozlov Sergey value = ((u32)(data[1] & 0x1F) << 8) | (u32)(data[2] & 0xFF);
1691a6dc60ffSKozlov Sergey min_index = 0;
1692a6dc60ffSKozlov Sergey if (delsys == SYS_DVBS) {
1693a6dc60ffSKozlov Sergey cn_data = s_cn_data;
1694e40d14a8SJérémy Lefaure max_index = ARRAY_SIZE(s_cn_data) - 1;
1695a6dc60ffSKozlov Sergey } else {
1696a6dc60ffSKozlov Sergey cn_data = s2_cn_data;
1697e40d14a8SJérémy Lefaure max_index = ARRAY_SIZE(s2_cn_data) - 1;
1698a6dc60ffSKozlov Sergey }
1699a6dc60ffSKozlov Sergey if (value >= cn_data[min_index].value) {
1700a6dc60ffSKozlov Sergey res = cn_data[min_index].cnr_x1000;
1701a6dc60ffSKozlov Sergey goto done;
1702a6dc60ffSKozlov Sergey }
1703a6dc60ffSKozlov Sergey if (value <= cn_data[max_index].value) {
1704a6dc60ffSKozlov Sergey res = cn_data[max_index].cnr_x1000;
1705a6dc60ffSKozlov Sergey goto done;
1706a6dc60ffSKozlov Sergey }
1707a6dc60ffSKozlov Sergey while ((max_index - min_index) > 1) {
1708a6dc60ffSKozlov Sergey index = (max_index + min_index) / 2;
1709a6dc60ffSKozlov Sergey if (value == cn_data[index].value) {
1710a6dc60ffSKozlov Sergey res = cn_data[index].cnr_x1000;
1711a6dc60ffSKozlov Sergey goto done;
1712a6dc60ffSKozlov Sergey } else if (value > cn_data[index].value)
1713a6dc60ffSKozlov Sergey max_index = index;
1714a6dc60ffSKozlov Sergey else
1715a6dc60ffSKozlov Sergey min_index = index;
1716a6dc60ffSKozlov Sergey if ((max_index - min_index) <= 1) {
1717a6dc60ffSKozlov Sergey if (value == cn_data[max_index].value) {
1718a6dc60ffSKozlov Sergey res = cn_data[max_index].cnr_x1000;
1719a6dc60ffSKozlov Sergey goto done;
1720a6dc60ffSKozlov Sergey } else {
1721a6dc60ffSKozlov Sergey res = cn_data[min_index].cnr_x1000;
1722a6dc60ffSKozlov Sergey goto done;
1723a6dc60ffSKozlov Sergey }
1724a6dc60ffSKozlov Sergey }
1725a6dc60ffSKozlov Sergey }
1726a6dc60ffSKozlov Sergey } else {
1727a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev,
1728a6dc60ffSKozlov Sergey "%s(): no data available\n", __func__);
1729e05b1872SAbylay Ospan return -EINVAL;
1730a6dc60ffSKozlov Sergey }
1731a6dc60ffSKozlov Sergey done:
1732e05b1872SAbylay Ospan *snr = res;
1733e05b1872SAbylay Ospan return 0;
1734e05b1872SAbylay Ospan }
1735e05b1872SAbylay Ospan
sony_log(uint32_t x)1736e05b1872SAbylay Ospan static uint32_t sony_log(uint32_t x)
1737e05b1872SAbylay Ospan {
1738e05b1872SAbylay Ospan return (((10000>>8)*(intlog2(x)>>16) + LOG2_E_100X/2)/LOG2_E_100X);
1739e05b1872SAbylay Ospan }
1740e05b1872SAbylay Ospan
cxd2841er_read_snr_c(struct cxd2841er_priv * priv,u32 * snr)1741e05b1872SAbylay Ospan static int cxd2841er_read_snr_c(struct cxd2841er_priv *priv, u32 *snr)
1742e05b1872SAbylay Ospan {
1743e05b1872SAbylay Ospan u32 reg;
1744e05b1872SAbylay Ospan u8 data[2];
1745e05b1872SAbylay Ospan enum sony_dvbc_constellation_t qam = SONY_DVBC_CONSTELLATION_16QAM;
1746e05b1872SAbylay Ospan
1747e05b1872SAbylay Ospan *snr = 0;
1748e05b1872SAbylay Ospan if (priv->state != STATE_ACTIVE_TC) {
1749e05b1872SAbylay Ospan dev_dbg(&priv->i2c->dev,
1750e05b1872SAbylay Ospan "%s(): invalid state %d\n",
1751e05b1872SAbylay Ospan __func__, priv->state);
1752e05b1872SAbylay Ospan return -EINVAL;
1753e05b1872SAbylay Ospan }
1754e05b1872SAbylay Ospan
17554a86bc10SAbylay Ospan cxd2841er_freeze_regs(priv);
1756e05b1872SAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
1757e05b1872SAbylay Ospan cxd2841er_read_regs(priv, I2C_SLVT, 0x19, data, 1);
1758e05b1872SAbylay Ospan qam = (enum sony_dvbc_constellation_t) (data[0] & 0x07);
1759e05b1872SAbylay Ospan cxd2841er_read_regs(priv, I2C_SLVT, 0x4C, data, 2);
17606ccf821cSDaniel Scheller cxd2841er_unfreeze_regs(priv);
1761e05b1872SAbylay Ospan
1762e05b1872SAbylay Ospan reg = ((u32)(data[0]&0x1f) << 8) | (u32)data[1];
1763e05b1872SAbylay Ospan if (reg == 0) {
1764e05b1872SAbylay Ospan dev_dbg(&priv->i2c->dev,
1765e05b1872SAbylay Ospan "%s(): reg value out of range\n", __func__);
1766e05b1872SAbylay Ospan return 0;
1767e05b1872SAbylay Ospan }
1768e05b1872SAbylay Ospan
1769e05b1872SAbylay Ospan switch (qam) {
1770e05b1872SAbylay Ospan case SONY_DVBC_CONSTELLATION_16QAM:
1771e05b1872SAbylay Ospan case SONY_DVBC_CONSTELLATION_64QAM:
1772e05b1872SAbylay Ospan case SONY_DVBC_CONSTELLATION_256QAM:
1773e05b1872SAbylay Ospan /* SNR(dB) = -9.50 * ln(IREG_SNR_ESTIMATE / (24320)) */
1774e05b1872SAbylay Ospan if (reg < 126)
1775e05b1872SAbylay Ospan reg = 126;
1776e05b1872SAbylay Ospan *snr = -95 * (int32_t)sony_log(reg) + 95941;
1777e05b1872SAbylay Ospan break;
1778e05b1872SAbylay Ospan case SONY_DVBC_CONSTELLATION_32QAM:
1779e05b1872SAbylay Ospan case SONY_DVBC_CONSTELLATION_128QAM:
1780e05b1872SAbylay Ospan /* SNR(dB) = -8.75 * ln(IREG_SNR_ESTIMATE / (20800)) */
1781e05b1872SAbylay Ospan if (reg < 69)
1782e05b1872SAbylay Ospan reg = 69;
1783e05b1872SAbylay Ospan *snr = -88 * (int32_t)sony_log(reg) + 86999;
1784e05b1872SAbylay Ospan break;
1785e05b1872SAbylay Ospan default:
1786e05b1872SAbylay Ospan return -EINVAL;
1787e05b1872SAbylay Ospan }
1788e05b1872SAbylay Ospan
1789e05b1872SAbylay Ospan return 0;
1790a6dc60ffSKozlov Sergey }
1791a6dc60ffSKozlov Sergey
cxd2841er_read_snr_t(struct cxd2841er_priv * priv,u32 * snr)1792a6dc60ffSKozlov Sergey static int cxd2841er_read_snr_t(struct cxd2841er_priv *priv, u32 *snr)
1793a6dc60ffSKozlov Sergey {
1794a6dc60ffSKozlov Sergey u32 reg;
1795a6dc60ffSKozlov Sergey u8 data[2];
1796a6dc60ffSKozlov Sergey
1797a6dc60ffSKozlov Sergey *snr = 0;
1798a6dc60ffSKozlov Sergey if (priv->state != STATE_ACTIVE_TC) {
1799a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev,
1800a6dc60ffSKozlov Sergey "%s(): invalid state %d\n", __func__, priv->state);
1801a6dc60ffSKozlov Sergey return -EINVAL;
1802a6dc60ffSKozlov Sergey }
18034a86bc10SAbylay Ospan
18044a86bc10SAbylay Ospan cxd2841er_freeze_regs(priv);
1805a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1806a6dc60ffSKozlov Sergey cxd2841er_read_regs(priv, I2C_SLVT, 0x28, data, sizeof(data));
18076ccf821cSDaniel Scheller cxd2841er_unfreeze_regs(priv);
18086ccf821cSDaniel Scheller
1809a6dc60ffSKozlov Sergey reg = ((u32)data[0] << 8) | (u32)data[1];
1810a6dc60ffSKozlov Sergey if (reg == 0) {
1811a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev,
1812a6dc60ffSKozlov Sergey "%s(): reg value out of range\n", __func__);
1813a6dc60ffSKozlov Sergey return 0;
1814a6dc60ffSKozlov Sergey }
1815a6dc60ffSKozlov Sergey if (reg > 4996)
1816a6dc60ffSKozlov Sergey reg = 4996;
1817df61f828SDaniel Scheller *snr = 100 * ((INTLOG10X100(reg) - INTLOG10X100(5350 - reg)) + 285);
1818a6dc60ffSKozlov Sergey return 0;
1819a6dc60ffSKozlov Sergey }
1820a6dc60ffSKozlov Sergey
cxd2841er_read_snr_t2(struct cxd2841er_priv * priv,u32 * snr)1821c8946c8dSMauro Carvalho Chehab static int cxd2841er_read_snr_t2(struct cxd2841er_priv *priv, u32 *snr)
1822a6dc60ffSKozlov Sergey {
1823a6dc60ffSKozlov Sergey u32 reg;
1824a6dc60ffSKozlov Sergey u8 data[2];
1825a6dc60ffSKozlov Sergey
1826a6dc60ffSKozlov Sergey *snr = 0;
1827a6dc60ffSKozlov Sergey if (priv->state != STATE_ACTIVE_TC) {
1828a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev,
1829a6dc60ffSKozlov Sergey "%s(): invalid state %d\n", __func__, priv->state);
1830a6dc60ffSKozlov Sergey return -EINVAL;
1831a6dc60ffSKozlov Sergey }
18324a86bc10SAbylay Ospan
18334a86bc10SAbylay Ospan cxd2841er_freeze_regs(priv);
1834a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
1835a6dc60ffSKozlov Sergey cxd2841er_read_regs(priv, I2C_SLVT, 0x28, data, sizeof(data));
18366ccf821cSDaniel Scheller cxd2841er_unfreeze_regs(priv);
18376ccf821cSDaniel Scheller
1838a6dc60ffSKozlov Sergey reg = ((u32)data[0] << 8) | (u32)data[1];
1839a6dc60ffSKozlov Sergey if (reg == 0) {
1840a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev,
1841a6dc60ffSKozlov Sergey "%s(): reg value out of range\n", __func__);
1842a6dc60ffSKozlov Sergey return 0;
1843a6dc60ffSKozlov Sergey }
1844a6dc60ffSKozlov Sergey if (reg > 10876)
1845a6dc60ffSKozlov Sergey reg = 10876;
1846df61f828SDaniel Scheller *snr = 100 * ((INTLOG10X100(reg) - INTLOG10X100(12600 - reg)) + 320);
1847a6dc60ffSKozlov Sergey return 0;
1848a6dc60ffSKozlov Sergey }
1849a6dc60ffSKozlov Sergey
cxd2841er_read_snr_i(struct cxd2841er_priv * priv,u32 * snr)185083808c23SAbylay Ospan static int cxd2841er_read_snr_i(struct cxd2841er_priv *priv, u32 *snr)
185183808c23SAbylay Ospan {
185283808c23SAbylay Ospan u32 reg;
185383808c23SAbylay Ospan u8 data[2];
185483808c23SAbylay Ospan
185583808c23SAbylay Ospan *snr = 0;
185683808c23SAbylay Ospan if (priv->state != STATE_ACTIVE_TC) {
185783808c23SAbylay Ospan dev_dbg(&priv->i2c->dev,
185883808c23SAbylay Ospan "%s(): invalid state %d\n", __func__,
185983808c23SAbylay Ospan priv->state);
186083808c23SAbylay Ospan return -EINVAL;
186183808c23SAbylay Ospan }
186283808c23SAbylay Ospan
18634a86bc10SAbylay Ospan cxd2841er_freeze_regs(priv);
186483808c23SAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
186583808c23SAbylay Ospan cxd2841er_read_regs(priv, I2C_SLVT, 0x28, data, sizeof(data));
18666ccf821cSDaniel Scheller cxd2841er_unfreeze_regs(priv);
18676ccf821cSDaniel Scheller
186883808c23SAbylay Ospan reg = ((u32)data[0] << 8) | (u32)data[1];
186983808c23SAbylay Ospan if (reg == 0) {
187083808c23SAbylay Ospan dev_dbg(&priv->i2c->dev,
187183808c23SAbylay Ospan "%s(): reg value out of range\n", __func__);
187283808c23SAbylay Ospan return 0;
187383808c23SAbylay Ospan }
18740854df79SAbylay Ospan *snr = 10000 * (intlog10(reg) >> 24) - 9031;
187583808c23SAbylay Ospan return 0;
187683808c23SAbylay Ospan }
187783808c23SAbylay Ospan
cxd2841er_read_agc_gain_c(struct cxd2841er_priv * priv,u8 delsys)1878d0998ce7SAbylay Ospan static u16 cxd2841er_read_agc_gain_c(struct cxd2841er_priv *priv,
1879d0998ce7SAbylay Ospan u8 delsys)
1880d0998ce7SAbylay Ospan {
1881d0998ce7SAbylay Ospan u8 data[2];
1882d0998ce7SAbylay Ospan
1883d0998ce7SAbylay Ospan cxd2841er_write_reg(
1884d0998ce7SAbylay Ospan priv, I2C_SLVT, 0x00, 0x40);
1885d0998ce7SAbylay Ospan cxd2841er_read_regs(priv, I2C_SLVT, 0x49, data, 2);
1886d0998ce7SAbylay Ospan dev_dbg(&priv->i2c->dev,
1887d0998ce7SAbylay Ospan "%s(): AGC value=%u\n",
1888d0998ce7SAbylay Ospan __func__, (((u16)data[0] & 0x0F) << 8) |
1889d0998ce7SAbylay Ospan (u16)(data[1] & 0xFF));
1890d0998ce7SAbylay Ospan return ((((u16)data[0] & 0x0F) << 8) | (u16)(data[1] & 0xFF)) << 4;
1891d0998ce7SAbylay Ospan }
1892d0998ce7SAbylay Ospan
cxd2841er_read_agc_gain_t_t2(struct cxd2841er_priv * priv,u8 delsys)1893a6dc60ffSKozlov Sergey static u16 cxd2841er_read_agc_gain_t_t2(struct cxd2841er_priv *priv,
1894a6dc60ffSKozlov Sergey u8 delsys)
1895a6dc60ffSKozlov Sergey {
1896a6dc60ffSKozlov Sergey u8 data[2];
1897a6dc60ffSKozlov Sergey
1898a6dc60ffSKozlov Sergey cxd2841er_write_reg(
1899a6dc60ffSKozlov Sergey priv, I2C_SLVT, 0x00, (delsys == SYS_DVBT ? 0x10 : 0x20));
1900a6dc60ffSKozlov Sergey cxd2841er_read_regs(priv, I2C_SLVT, 0x26, data, 2);
1901c5ea46daSAbylay Ospan dev_dbg(&priv->i2c->dev,
1902c5ea46daSAbylay Ospan "%s(): AGC value=%u\n",
1903c5ea46daSAbylay Ospan __func__, (((u16)data[0] & 0x0F) << 8) |
1904c5ea46daSAbylay Ospan (u16)(data[1] & 0xFF));
1905a6dc60ffSKozlov Sergey return ((((u16)data[0] & 0x0F) << 8) | (u16)(data[1] & 0xFF)) << 4;
1906a6dc60ffSKozlov Sergey }
1907a6dc60ffSKozlov Sergey
cxd2841er_read_agc_gain_i(struct cxd2841er_priv * priv,u8 delsys)190883808c23SAbylay Ospan static u16 cxd2841er_read_agc_gain_i(struct cxd2841er_priv *priv,
190983808c23SAbylay Ospan u8 delsys)
191083808c23SAbylay Ospan {
191183808c23SAbylay Ospan u8 data[2];
191283808c23SAbylay Ospan
191383808c23SAbylay Ospan cxd2841er_write_reg(
191483808c23SAbylay Ospan priv, I2C_SLVT, 0x00, 0x60);
191583808c23SAbylay Ospan cxd2841er_read_regs(priv, I2C_SLVT, 0x26, data, 2);
191683808c23SAbylay Ospan
191783808c23SAbylay Ospan dev_dbg(&priv->i2c->dev,
191883808c23SAbylay Ospan "%s(): AGC value=%u\n",
191983808c23SAbylay Ospan __func__, (((u16)data[0] & 0x0F) << 8) |
192083808c23SAbylay Ospan (u16)(data[1] & 0xFF));
192183808c23SAbylay Ospan return ((((u16)data[0] & 0x0F) << 8) | (u16)(data[1] & 0xFF)) << 4;
192283808c23SAbylay Ospan }
192383808c23SAbylay Ospan
cxd2841er_read_agc_gain_s(struct cxd2841er_priv * priv)1924a6dc60ffSKozlov Sergey static u16 cxd2841er_read_agc_gain_s(struct cxd2841er_priv *priv)
1925a6dc60ffSKozlov Sergey {
1926a6dc60ffSKozlov Sergey u8 data[2];
1927a6dc60ffSKozlov Sergey
1928a6dc60ffSKozlov Sergey /* Set SLV-T Bank : 0xA0 */
1929a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
1930a6dc60ffSKozlov Sergey /*
1931a6dc60ffSKozlov Sergey * slave Bank Addr Bit Signal name
1932a6dc60ffSKozlov Sergey * <SLV-T> A0h 1Fh [4:0] IRFAGC_GAIN[12:8]
1933a6dc60ffSKozlov Sergey * <SLV-T> A0h 20h [7:0] IRFAGC_GAIN[7:0]
1934a6dc60ffSKozlov Sergey */
1935a6dc60ffSKozlov Sergey cxd2841er_read_regs(priv, I2C_SLVT, 0x1f, data, 2);
1936a6dc60ffSKozlov Sergey return ((((u16)data[0] & 0x1F) << 8) | (u16)(data[1] & 0xFF)) << 3;
1937a6dc60ffSKozlov Sergey }
1938a6dc60ffSKozlov Sergey
cxd2841er_read_ber(struct dvb_frontend * fe)1939f1b26622SMauro Carvalho Chehab static void cxd2841er_read_ber(struct dvb_frontend *fe)
1940a6dc60ffSKozlov Sergey {
1941a6dc60ffSKozlov Sergey struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1942a6dc60ffSKozlov Sergey struct cxd2841er_priv *priv = fe->demodulator_priv;
19434216be14SMauro Carvalho Chehab u32 ret, bit_error = 0, bit_count = 0;
1944a6dc60ffSKozlov Sergey
1945a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1946a6dc60ffSKozlov Sergey switch (p->delivery_system) {
1947a6f330cbSAbylay Ospan case SYS_DVBC_ANNEX_A:
1948a6f330cbSAbylay Ospan case SYS_DVBC_ANNEX_B:
1949a6f330cbSAbylay Ospan case SYS_DVBC_ANNEX_C:
1950a6f330cbSAbylay Ospan ret = cxd2841er_read_ber_c(priv, &bit_error, &bit_count);
1951a6f330cbSAbylay Ospan break;
19520854df79SAbylay Ospan case SYS_ISDBT:
19530854df79SAbylay Ospan ret = cxd2841er_read_ber_i(priv, &bit_error, &bit_count);
19540854df79SAbylay Ospan break;
1955a6dc60ffSKozlov Sergey case SYS_DVBS:
19564216be14SMauro Carvalho Chehab ret = cxd2841er_mon_read_ber_s(priv, &bit_error, &bit_count);
1957a6dc60ffSKozlov Sergey break;
1958a6dc60ffSKozlov Sergey case SYS_DVBS2:
19594216be14SMauro Carvalho Chehab ret = cxd2841er_mon_read_ber_s2(priv, &bit_error, &bit_count);
1960a6dc60ffSKozlov Sergey break;
1961a6dc60ffSKozlov Sergey case SYS_DVBT:
19624216be14SMauro Carvalho Chehab ret = cxd2841er_read_ber_t(priv, &bit_error, &bit_count);
1963a6dc60ffSKozlov Sergey break;
1964f1b26622SMauro Carvalho Chehab case SYS_DVBT2:
19654216be14SMauro Carvalho Chehab ret = cxd2841er_read_ber_t2(priv, &bit_error, &bit_count);
1966f1b26622SMauro Carvalho Chehab break;
1967f1b26622SMauro Carvalho Chehab default:
1968f1b26622SMauro Carvalho Chehab p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
19694216be14SMauro Carvalho Chehab p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1970f1b26622SMauro Carvalho Chehab return;
1971a6dc60ffSKozlov Sergey }
1972f1b26622SMauro Carvalho Chehab
1973f1b26622SMauro Carvalho Chehab if (!ret) {
1974f1b26622SMauro Carvalho Chehab p->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
1975a6f330cbSAbylay Ospan p->post_bit_error.stat[0].uvalue += bit_error;
19764216be14SMauro Carvalho Chehab p->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
1977a6f330cbSAbylay Ospan p->post_bit_count.stat[0].uvalue += bit_count;
1978f1b26622SMauro Carvalho Chehab } else {
1979f1b26622SMauro Carvalho Chehab p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
19804216be14SMauro Carvalho Chehab p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1981f1b26622SMauro Carvalho Chehab }
1982a6dc60ffSKozlov Sergey }
1983a6dc60ffSKozlov Sergey
cxd2841er_read_signal_strength(struct dvb_frontend * fe)19845fda1b65SMauro Carvalho Chehab static void cxd2841er_read_signal_strength(struct dvb_frontend *fe)
1985a6dc60ffSKozlov Sergey {
1986a6dc60ffSKozlov Sergey struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1987a6dc60ffSKozlov Sergey struct cxd2841er_priv *priv = fe->demodulator_priv;
1988313a7dfbSMauro Carvalho Chehab s32 strength;
1989a6dc60ffSKozlov Sergey
1990a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1991a6dc60ffSKozlov Sergey switch (p->delivery_system) {
1992a6dc60ffSKozlov Sergey case SYS_DVBT:
1993a6dc60ffSKozlov Sergey case SYS_DVBT2:
19945fda1b65SMauro Carvalho Chehab strength = cxd2841er_read_agc_gain_t_t2(priv,
19955fda1b65SMauro Carvalho Chehab p->delivery_system);
19965fda1b65SMauro Carvalho Chehab p->strength.stat[0].scale = FE_SCALE_DECIBEL;
19975fda1b65SMauro Carvalho Chehab /* Formula was empirically determinated @ 410 MHz */
1998313a7dfbSMauro Carvalho Chehab p->strength.stat[0].uvalue = strength * 366 / 100 - 89520;
19995fda1b65SMauro Carvalho Chehab break; /* Code moved out of the function */
2000988bd281SMauro Carvalho Chehab case SYS_DVBC_ANNEX_A:
2001997bdc0cSAbylay Ospan case SYS_DVBC_ANNEX_B:
2002997bdc0cSAbylay Ospan case SYS_DVBC_ANNEX_C:
2003997bdc0cSAbylay Ospan strength = cxd2841er_read_agc_gain_c(priv,
2004988bd281SMauro Carvalho Chehab p->delivery_system);
2005d12b791eSMauro Carvalho Chehab p->strength.stat[0].scale = FE_SCALE_DECIBEL;
2006d12b791eSMauro Carvalho Chehab /*
2007d12b791eSMauro Carvalho Chehab * Formula was empirically determinated via linear regression,
2008d12b791eSMauro Carvalho Chehab * using frequencies: 175 MHz, 410 MHz and 800 MHz, and a
2009d12b791eSMauro Carvalho Chehab * stream modulated with QAM64
2010d12b791eSMauro Carvalho Chehab */
2011313a7dfbSMauro Carvalho Chehab p->strength.stat[0].uvalue = strength * 4045 / 1000 - 85224;
2012988bd281SMauro Carvalho Chehab break;
201383808c23SAbylay Ospan case SYS_ISDBT:
2014313a7dfbSMauro Carvalho Chehab strength = cxd2841er_read_agc_gain_i(priv, p->delivery_system);
2015313a7dfbSMauro Carvalho Chehab p->strength.stat[0].scale = FE_SCALE_DECIBEL;
2016313a7dfbSMauro Carvalho Chehab /*
2017313a7dfbSMauro Carvalho Chehab * Formula was empirically determinated via linear regression,
2018313a7dfbSMauro Carvalho Chehab * using frequencies: 175 MHz, 410 MHz and 800 MHz.
2019313a7dfbSMauro Carvalho Chehab */
2020313a7dfbSMauro Carvalho Chehab p->strength.stat[0].uvalue = strength * 3775 / 1000 - 90185;
202183808c23SAbylay Ospan break;
2022a6dc60ffSKozlov Sergey case SYS_DVBS:
2023a6dc60ffSKozlov Sergey case SYS_DVBS2:
20245fda1b65SMauro Carvalho Chehab strength = 65535 - cxd2841er_read_agc_gain_s(priv);
20255fda1b65SMauro Carvalho Chehab p->strength.stat[0].scale = FE_SCALE_RELATIVE;
20265fda1b65SMauro Carvalho Chehab p->strength.stat[0].uvalue = strength;
2027a6dc60ffSKozlov Sergey break;
2028a6dc60ffSKozlov Sergey default:
2029f1b26622SMauro Carvalho Chehab p->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
2030a6dc60ffSKozlov Sergey break;
2031a6dc60ffSKozlov Sergey }
2032a6dc60ffSKozlov Sergey }
2033a6dc60ffSKozlov Sergey
cxd2841er_read_snr(struct dvb_frontend * fe)2034f1b26622SMauro Carvalho Chehab static void cxd2841er_read_snr(struct dvb_frontend *fe)
2035a6dc60ffSKozlov Sergey {
2036a6dc60ffSKozlov Sergey u32 tmp = 0;
2037e05b1872SAbylay Ospan int ret = 0;
2038a6dc60ffSKozlov Sergey struct dtv_frontend_properties *p = &fe->dtv_property_cache;
2039a6dc60ffSKozlov Sergey struct cxd2841er_priv *priv = fe->demodulator_priv;
2040a6dc60ffSKozlov Sergey
2041a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2042a6dc60ffSKozlov Sergey switch (p->delivery_system) {
2043e05b1872SAbylay Ospan case SYS_DVBC_ANNEX_A:
2044e05b1872SAbylay Ospan case SYS_DVBC_ANNEX_B:
2045e05b1872SAbylay Ospan case SYS_DVBC_ANNEX_C:
2046e05b1872SAbylay Ospan ret = cxd2841er_read_snr_c(priv, &tmp);
2047e05b1872SAbylay Ospan break;
2048a6dc60ffSKozlov Sergey case SYS_DVBT:
2049e05b1872SAbylay Ospan ret = cxd2841er_read_snr_t(priv, &tmp);
2050a6dc60ffSKozlov Sergey break;
2051a6dc60ffSKozlov Sergey case SYS_DVBT2:
2052e05b1872SAbylay Ospan ret = cxd2841er_read_snr_t2(priv, &tmp);
2053a6dc60ffSKozlov Sergey break;
205483808c23SAbylay Ospan case SYS_ISDBT:
2055e05b1872SAbylay Ospan ret = cxd2841er_read_snr_i(priv, &tmp);
205683808c23SAbylay Ospan break;
2057a6dc60ffSKozlov Sergey case SYS_DVBS:
2058a6dc60ffSKozlov Sergey case SYS_DVBS2:
2059e05b1872SAbylay Ospan ret = cxd2841er_dvbs_read_snr(priv, p->delivery_system, &tmp);
2060a6dc60ffSKozlov Sergey break;
2061a6dc60ffSKozlov Sergey default:
2062a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s(): unknown delivery system %d\n",
2063a6dc60ffSKozlov Sergey __func__, p->delivery_system);
2064f1b26622SMauro Carvalho Chehab p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
2065f1b26622SMauro Carvalho Chehab return;
2066a6dc60ffSKozlov Sergey }
2067a6dc60ffSKozlov Sergey
20680854df79SAbylay Ospan dev_dbg(&priv->i2c->dev, "%s(): snr=%d\n",
20690854df79SAbylay Ospan __func__, (int32_t)tmp);
20700854df79SAbylay Ospan
2071e05b1872SAbylay Ospan if (!ret) {
2072f1b26622SMauro Carvalho Chehab p->cnr.stat[0].scale = FE_SCALE_DECIBEL;
2073f1b26622SMauro Carvalho Chehab p->cnr.stat[0].svalue = tmp;
2074e05b1872SAbylay Ospan } else {
2075e05b1872SAbylay Ospan p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
2076e05b1872SAbylay Ospan }
2077f1b26622SMauro Carvalho Chehab }
2078f1b26622SMauro Carvalho Chehab
cxd2841er_read_ucblocks(struct dvb_frontend * fe)2079f1b26622SMauro Carvalho Chehab static void cxd2841er_read_ucblocks(struct dvb_frontend *fe)
2080a6dc60ffSKozlov Sergey {
2081a6dc60ffSKozlov Sergey struct dtv_frontend_properties *p = &fe->dtv_property_cache;
2082a6dc60ffSKozlov Sergey struct cxd2841er_priv *priv = fe->demodulator_priv;
20834a86bc10SAbylay Ospan u32 ucblocks = 0;
2084a6dc60ffSKozlov Sergey
2085a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2086a6dc60ffSKozlov Sergey switch (p->delivery_system) {
2087a6f330cbSAbylay Ospan case SYS_DVBC_ANNEX_A:
2088a6f330cbSAbylay Ospan case SYS_DVBC_ANNEX_B:
2089a6f330cbSAbylay Ospan case SYS_DVBC_ANNEX_C:
2090a6f330cbSAbylay Ospan cxd2841er_read_packet_errors_c(priv, &ucblocks);
2091a6f330cbSAbylay Ospan break;
2092a6dc60ffSKozlov Sergey case SYS_DVBT:
2093f1b26622SMauro Carvalho Chehab cxd2841er_read_packet_errors_t(priv, &ucblocks);
2094a6dc60ffSKozlov Sergey break;
2095a6dc60ffSKozlov Sergey case SYS_DVBT2:
2096f1b26622SMauro Carvalho Chehab cxd2841er_read_packet_errors_t2(priv, &ucblocks);
2097a6dc60ffSKozlov Sergey break;
209883808c23SAbylay Ospan case SYS_ISDBT:
2099f1b26622SMauro Carvalho Chehab cxd2841er_read_packet_errors_i(priv, &ucblocks);
210083808c23SAbylay Ospan break;
2101a6dc60ffSKozlov Sergey default:
2102f1b26622SMauro Carvalho Chehab p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
2103f1b26622SMauro Carvalho Chehab return;
2104a6dc60ffSKozlov Sergey }
21054a86bc10SAbylay Ospan dev_dbg(&priv->i2c->dev, "%s() ucblocks=%u\n", __func__, ucblocks);
2106f1b26622SMauro Carvalho Chehab
2107f1b26622SMauro Carvalho Chehab p->block_error.stat[0].scale = FE_SCALE_COUNTER;
2108f1b26622SMauro Carvalho Chehab p->block_error.stat[0].uvalue = ucblocks;
2109a6dc60ffSKozlov Sergey }
2110a6dc60ffSKozlov Sergey
cxd2841er_dvbt2_set_profile(struct cxd2841er_priv * priv,enum cxd2841er_dvbt2_profile_t profile)2111a6dc60ffSKozlov Sergey static int cxd2841er_dvbt2_set_profile(
2112a6dc60ffSKozlov Sergey struct cxd2841er_priv *priv, enum cxd2841er_dvbt2_profile_t profile)
2113a6dc60ffSKozlov Sergey {
2114a6dc60ffSKozlov Sergey u8 tune_mode;
2115a6dc60ffSKozlov Sergey u8 seq_not2d_time;
2116a6dc60ffSKozlov Sergey
2117a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2118a6dc60ffSKozlov Sergey switch (profile) {
2119a6dc60ffSKozlov Sergey case DVBT2_PROFILE_BASE:
2120a6dc60ffSKozlov Sergey tune_mode = 0x01;
21216c77161aSAbylay Ospan /* Set early unlock time */
21226c77161aSAbylay Ospan seq_not2d_time = (priv->xtal == SONY_XTAL_24000)?0x0E:0x0C;
2123a6dc60ffSKozlov Sergey break;
2124a6dc60ffSKozlov Sergey case DVBT2_PROFILE_LITE:
2125a6dc60ffSKozlov Sergey tune_mode = 0x05;
21266c77161aSAbylay Ospan /* Set early unlock time */
21276c77161aSAbylay Ospan seq_not2d_time = (priv->xtal == SONY_XTAL_24000)?0x2E:0x28;
2128a6dc60ffSKozlov Sergey break;
2129a6dc60ffSKozlov Sergey case DVBT2_PROFILE_ANY:
2130a6dc60ffSKozlov Sergey tune_mode = 0x00;
21316c77161aSAbylay Ospan /* Set early unlock time */
21326c77161aSAbylay Ospan seq_not2d_time = (priv->xtal == SONY_XTAL_24000)?0x2E:0x28;
2133a6dc60ffSKozlov Sergey break;
2134a6dc60ffSKozlov Sergey default:
2135a6dc60ffSKozlov Sergey return -EINVAL;
2136a6dc60ffSKozlov Sergey }
2137a6dc60ffSKozlov Sergey /* Set SLV-T Bank : 0x2E */
2138a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2e);
2139a6dc60ffSKozlov Sergey /* Set profile and tune mode */
2140a6dc60ffSKozlov Sergey cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x10, tune_mode, 0x07);
2141a6dc60ffSKozlov Sergey /* Set SLV-T Bank : 0x2B */
2142a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2b);
2143a6dc60ffSKozlov Sergey /* Set early unlock detection time */
2144a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x9d, seq_not2d_time);
2145a6dc60ffSKozlov Sergey return 0;
2146a6dc60ffSKozlov Sergey }
2147a6dc60ffSKozlov Sergey
cxd2841er_dvbt2_set_plp_config(struct cxd2841er_priv * priv,u8 is_auto,u8 plp_id)2148a6dc60ffSKozlov Sergey static int cxd2841er_dvbt2_set_plp_config(struct cxd2841er_priv *priv,
2149a6dc60ffSKozlov Sergey u8 is_auto, u8 plp_id)
2150a6dc60ffSKozlov Sergey {
2151a6dc60ffSKozlov Sergey if (is_auto) {
2152a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev,
2153a6dc60ffSKozlov Sergey "%s() using auto PLP selection\n", __func__);
2154a6dc60ffSKozlov Sergey } else {
2155a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev,
2156a6dc60ffSKozlov Sergey "%s() using manual PLP selection, ID %d\n",
2157a6dc60ffSKozlov Sergey __func__, plp_id);
2158a6dc60ffSKozlov Sergey }
2159a6dc60ffSKozlov Sergey /* Set SLV-T Bank : 0x23 */
2160a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x23);
2161a6dc60ffSKozlov Sergey if (!is_auto) {
2162a6dc60ffSKozlov Sergey /* Manual PLP selection mode. Set the data PLP Id. */
2163a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0xaf, plp_id);
2164a6dc60ffSKozlov Sergey }
2165a6dc60ffSKozlov Sergey /* Auto PLP select (Scanning mode = 0x00). Data PLP select = 0x01. */
2166a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0xad, (is_auto ? 0x00 : 0x01));
2167a6dc60ffSKozlov Sergey return 0;
2168a6dc60ffSKozlov Sergey }
2169a6dc60ffSKozlov Sergey
cxd2841er_sleep_tc_to_active_t2_band(struct cxd2841er_priv * priv,u32 bandwidth)2170a6dc60ffSKozlov Sergey static int cxd2841er_sleep_tc_to_active_t2_band(struct cxd2841er_priv *priv,
2171a6dc60ffSKozlov Sergey u32 bandwidth)
2172a6dc60ffSKozlov Sergey {
21734b866c4eSDaniel Scheller u32 iffreq, ifhz;
21746c77161aSAbylay Ospan u8 data[MAX_WRITE_REGSIZE];
2175a6dc60ffSKozlov Sergey
21763802c1bcSColin Ian King static const uint8_t nominalRate8bw[3][5] = {
21776c77161aSAbylay Ospan /* TRCG Nominal Rate [37:0] */
21786c77161aSAbylay Ospan {0x11, 0xF0, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
21796c77161aSAbylay Ospan {0x15, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
21806c77161aSAbylay Ospan {0x11, 0xF0, 0x00, 0x00, 0x00} /* 41MHz XTal */
21816c77161aSAbylay Ospan };
21826c77161aSAbylay Ospan
21833802c1bcSColin Ian King static const uint8_t nominalRate7bw[3][5] = {
21846c77161aSAbylay Ospan /* TRCG Nominal Rate [37:0] */
21856c77161aSAbylay Ospan {0x14, 0x80, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
21866c77161aSAbylay Ospan {0x18, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
21876c77161aSAbylay Ospan {0x14, 0x80, 0x00, 0x00, 0x00} /* 41MHz XTal */
21886c77161aSAbylay Ospan };
21896c77161aSAbylay Ospan
21903802c1bcSColin Ian King static const uint8_t nominalRate6bw[3][5] = {
21916c77161aSAbylay Ospan /* TRCG Nominal Rate [37:0] */
21926c77161aSAbylay Ospan {0x17, 0xEA, 0xAA, 0xAA, 0xAA}, /* 20.5MHz XTal */
21936c77161aSAbylay Ospan {0x1C, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
21946c77161aSAbylay Ospan {0x17, 0xEA, 0xAA, 0xAA, 0xAA} /* 41MHz XTal */
21956c77161aSAbylay Ospan };
21966c77161aSAbylay Ospan
21973802c1bcSColin Ian King static const uint8_t nominalRate5bw[3][5] = {
21986c77161aSAbylay Ospan /* TRCG Nominal Rate [37:0] */
21996c77161aSAbylay Ospan {0x1C, 0xB3, 0x33, 0x33, 0x33}, /* 20.5MHz XTal */
22006c77161aSAbylay Ospan {0x21, 0x99, 0x99, 0x99, 0x99}, /* 24MHz XTal */
22016c77161aSAbylay Ospan {0x1C, 0xB3, 0x33, 0x33, 0x33} /* 41MHz XTal */
22026c77161aSAbylay Ospan };
22036c77161aSAbylay Ospan
22043802c1bcSColin Ian King static const uint8_t nominalRate17bw[3][5] = {
22056c77161aSAbylay Ospan /* TRCG Nominal Rate [37:0] */
22066c77161aSAbylay Ospan {0x58, 0xE2, 0xAF, 0xE0, 0xBC}, /* 20.5MHz XTal */
22076c77161aSAbylay Ospan {0x68, 0x0F, 0xA2, 0x32, 0xD0}, /* 24MHz XTal */
22086c77161aSAbylay Ospan {0x58, 0xE2, 0xAF, 0xE0, 0xBC} /* 41MHz XTal */
22096c77161aSAbylay Ospan };
22106c77161aSAbylay Ospan
22113802c1bcSColin Ian King static const uint8_t itbCoef8bw[3][14] = {
22126c77161aSAbylay Ospan {0x26, 0xAF, 0x06, 0xCD, 0x13, 0xBB, 0x28, 0xBA,
22136c77161aSAbylay Ospan 0x23, 0xA9, 0x1F, 0xA8, 0x2C, 0xC8}, /* 20.5MHz XTal */
22146c77161aSAbylay Ospan {0x2F, 0xBA, 0x28, 0x9B, 0x28, 0x9D, 0x28, 0xA1,
22156c77161aSAbylay Ospan 0x29, 0xA5, 0x2A, 0xAC, 0x29, 0xB5}, /* 24MHz XTal */
22166c77161aSAbylay Ospan {0x26, 0xAF, 0x06, 0xCD, 0x13, 0xBB, 0x28, 0xBA,
22176c77161aSAbylay Ospan 0x23, 0xA9, 0x1F, 0xA8, 0x2C, 0xC8} /* 41MHz XTal */
22186c77161aSAbylay Ospan };
22196c77161aSAbylay Ospan
22203802c1bcSColin Ian King static const uint8_t itbCoef7bw[3][14] = {
22216c77161aSAbylay Ospan {0x2C, 0xBD, 0x02, 0xCF, 0x04, 0xF8, 0x23, 0xA6,
22226c77161aSAbylay Ospan 0x29, 0xB0, 0x26, 0xA9, 0x21, 0xA5}, /* 20.5MHz XTal */
22236c77161aSAbylay Ospan {0x30, 0xB1, 0x29, 0x9A, 0x28, 0x9C, 0x28, 0xA0,
22246c77161aSAbylay Ospan 0x29, 0xA2, 0x2B, 0xA6, 0x2B, 0xAD}, /* 24MHz XTal */
22256c77161aSAbylay Ospan {0x2C, 0xBD, 0x02, 0xCF, 0x04, 0xF8, 0x23, 0xA6,
22266c77161aSAbylay Ospan 0x29, 0xB0, 0x26, 0xA9, 0x21, 0xA5} /* 41MHz XTal */
22276c77161aSAbylay Ospan };
22286c77161aSAbylay Ospan
22293802c1bcSColin Ian King static const uint8_t itbCoef6bw[3][14] = {
22306c77161aSAbylay Ospan {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8,
22316c77161aSAbylay Ospan 0x00, 0xCF, 0x00, 0xE6, 0x23, 0xA4}, /* 20.5MHz XTal */
22326c77161aSAbylay Ospan {0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E,
22336c77161aSAbylay Ospan 0x29, 0xA4, 0x29, 0xA2, 0x29, 0xA8}, /* 24MHz XTal */
22346c77161aSAbylay Ospan {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8,
22356c77161aSAbylay Ospan 0x00, 0xCF, 0x00, 0xE6, 0x23, 0xA4} /* 41MHz XTal */
22366c77161aSAbylay Ospan };
22376c77161aSAbylay Ospan
22383802c1bcSColin Ian King static const uint8_t itbCoef5bw[3][14] = {
22396c77161aSAbylay Ospan {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8,
22406c77161aSAbylay Ospan 0x00, 0xCF, 0x00, 0xE6, 0x23, 0xA4}, /* 20.5MHz XTal */
22416c77161aSAbylay Ospan {0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E,
22426c77161aSAbylay Ospan 0x29, 0xA4, 0x29, 0xA2, 0x29, 0xA8}, /* 24MHz XTal */
22436c77161aSAbylay Ospan {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8,
22446c77161aSAbylay Ospan 0x00, 0xCF, 0x00, 0xE6, 0x23, 0xA4} /* 41MHz XTal */
22456c77161aSAbylay Ospan };
22466c77161aSAbylay Ospan
22473802c1bcSColin Ian King static const uint8_t itbCoef17bw[3][14] = {
22486c77161aSAbylay Ospan {0x25, 0xA0, 0x36, 0x8D, 0x2E, 0x94, 0x28, 0x9B,
22496c77161aSAbylay Ospan 0x32, 0x90, 0x2C, 0x9D, 0x29, 0x99}, /* 20.5MHz XTal */
22506c77161aSAbylay Ospan {0x33, 0x8E, 0x2B, 0x97, 0x2D, 0x95, 0x37, 0x8B,
22516c77161aSAbylay Ospan 0x30, 0x97, 0x2D, 0x9A, 0x21, 0xA4}, /* 24MHz XTal */
22526c77161aSAbylay Ospan {0x25, 0xA0, 0x36, 0x8D, 0x2E, 0x94, 0x28, 0x9B,
22536c77161aSAbylay Ospan 0x32, 0x90, 0x2C, 0x9D, 0x29, 0x99} /* 41MHz XTal */
22546c77161aSAbylay Ospan };
22556c77161aSAbylay Ospan
22566c77161aSAbylay Ospan /* Set SLV-T Bank : 0x20 */
22576c77161aSAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
22586c77161aSAbylay Ospan
2259a6dc60ffSKozlov Sergey switch (bandwidth) {
2260a6dc60ffSKozlov Sergey case 8000000:
22616c77161aSAbylay Ospan /* <Timing Recovery setting> */
22626c77161aSAbylay Ospan cxd2841er_write_regs(priv, I2C_SLVT,
22636c77161aSAbylay Ospan 0x9F, nominalRate8bw[priv->xtal], 5);
22646c77161aSAbylay Ospan
22656c77161aSAbylay Ospan /* Set SLV-T Bank : 0x27 */
22666c77161aSAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
22676c77161aSAbylay Ospan cxd2841er_set_reg_bits(priv, I2C_SLVT,
22686c77161aSAbylay Ospan 0x7a, 0x00, 0x0f);
22696c77161aSAbylay Ospan
22706c77161aSAbylay Ospan /* Set SLV-T Bank : 0x10 */
22716c77161aSAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
22726c77161aSAbylay Ospan
22736c77161aSAbylay Ospan /* Group delay equaliser settings for
22746c77161aSAbylay Ospan * ASCOT2D, ASCOT2E and ASCOT3 tuners
22756c77161aSAbylay Ospan */
22767afe510aSDaniel Scheller if (priv->flags & CXD2841ER_ASCOT)
22776c77161aSAbylay Ospan cxd2841er_write_regs(priv, I2C_SLVT,
22786c77161aSAbylay Ospan 0xA6, itbCoef8bw[priv->xtal], 14);
22796c77161aSAbylay Ospan /* <IF freq setting> */
22804b866c4eSDaniel Scheller ifhz = cxd2841er_get_if_hz(priv, 4800000);
22814b866c4eSDaniel Scheller iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
22826c77161aSAbylay Ospan data[0] = (u8) ((iffreq >> 16) & 0xff);
22836c77161aSAbylay Ospan data[1] = (u8)((iffreq >> 8) & 0xff);
22846c77161aSAbylay Ospan data[2] = (u8)(iffreq & 0xff);
22856c77161aSAbylay Ospan cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
22866c77161aSAbylay Ospan /* System bandwidth setting */
22876c77161aSAbylay Ospan cxd2841er_set_reg_bits(
22886c77161aSAbylay Ospan priv, I2C_SLVT, 0xD7, 0x00, 0x07);
2289a6dc60ffSKozlov Sergey break;
2290a6dc60ffSKozlov Sergey case 7000000:
22916c77161aSAbylay Ospan /* <Timing Recovery setting> */
22926c77161aSAbylay Ospan cxd2841er_write_regs(priv, I2C_SLVT,
22936c77161aSAbylay Ospan 0x9F, nominalRate7bw[priv->xtal], 5);
22946c77161aSAbylay Ospan
22956c77161aSAbylay Ospan /* Set SLV-T Bank : 0x27 */
22966c77161aSAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
22976c77161aSAbylay Ospan cxd2841er_set_reg_bits(priv, I2C_SLVT,
22986c77161aSAbylay Ospan 0x7a, 0x00, 0x0f);
22996c77161aSAbylay Ospan
23006c77161aSAbylay Ospan /* Set SLV-T Bank : 0x10 */
23016c77161aSAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
23026c77161aSAbylay Ospan
23036c77161aSAbylay Ospan /* Group delay equaliser settings for
23046c77161aSAbylay Ospan * ASCOT2D, ASCOT2E and ASCOT3 tuners
23056c77161aSAbylay Ospan */
23067afe510aSDaniel Scheller if (priv->flags & CXD2841ER_ASCOT)
23076c77161aSAbylay Ospan cxd2841er_write_regs(priv, I2C_SLVT,
23086c77161aSAbylay Ospan 0xA6, itbCoef7bw[priv->xtal], 14);
23096c77161aSAbylay Ospan /* <IF freq setting> */
23104b866c4eSDaniel Scheller ifhz = cxd2841er_get_if_hz(priv, 4200000);
23114b866c4eSDaniel Scheller iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
23126c77161aSAbylay Ospan data[0] = (u8) ((iffreq >> 16) & 0xff);
23136c77161aSAbylay Ospan data[1] = (u8)((iffreq >> 8) & 0xff);
23146c77161aSAbylay Ospan data[2] = (u8)(iffreq & 0xff);
23156c77161aSAbylay Ospan cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
23166c77161aSAbylay Ospan /* System bandwidth setting */
23176c77161aSAbylay Ospan cxd2841er_set_reg_bits(
23186c77161aSAbylay Ospan priv, I2C_SLVT, 0xD7, 0x02, 0x07);
2319a6dc60ffSKozlov Sergey break;
2320a6dc60ffSKozlov Sergey case 6000000:
23216c77161aSAbylay Ospan /* <Timing Recovery setting> */
23226c77161aSAbylay Ospan cxd2841er_write_regs(priv, I2C_SLVT,
23236c77161aSAbylay Ospan 0x9F, nominalRate6bw[priv->xtal], 5);
23246c77161aSAbylay Ospan
23256c77161aSAbylay Ospan /* Set SLV-T Bank : 0x27 */
23266c77161aSAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
23276c77161aSAbylay Ospan cxd2841er_set_reg_bits(priv, I2C_SLVT,
23286c77161aSAbylay Ospan 0x7a, 0x00, 0x0f);
23296c77161aSAbylay Ospan
23306c77161aSAbylay Ospan /* Set SLV-T Bank : 0x10 */
23316c77161aSAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
23326c77161aSAbylay Ospan
23336c77161aSAbylay Ospan /* Group delay equaliser settings for
23346c77161aSAbylay Ospan * ASCOT2D, ASCOT2E and ASCOT3 tuners
23356c77161aSAbylay Ospan */
23367afe510aSDaniel Scheller if (priv->flags & CXD2841ER_ASCOT)
23376c77161aSAbylay Ospan cxd2841er_write_regs(priv, I2C_SLVT,
23386c77161aSAbylay Ospan 0xA6, itbCoef6bw[priv->xtal], 14);
23396c77161aSAbylay Ospan /* <IF freq setting> */
23404b866c4eSDaniel Scheller ifhz = cxd2841er_get_if_hz(priv, 3600000);
23414b866c4eSDaniel Scheller iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
23426c77161aSAbylay Ospan data[0] = (u8) ((iffreq >> 16) & 0xff);
23436c77161aSAbylay Ospan data[1] = (u8)((iffreq >> 8) & 0xff);
23446c77161aSAbylay Ospan data[2] = (u8)(iffreq & 0xff);
23456c77161aSAbylay Ospan cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
23466c77161aSAbylay Ospan /* System bandwidth setting */
23476c77161aSAbylay Ospan cxd2841er_set_reg_bits(
23486c77161aSAbylay Ospan priv, I2C_SLVT, 0xD7, 0x04, 0x07);
2349a6dc60ffSKozlov Sergey break;
2350a6dc60ffSKozlov Sergey case 5000000:
23516c77161aSAbylay Ospan /* <Timing Recovery setting> */
23526c77161aSAbylay Ospan cxd2841er_write_regs(priv, I2C_SLVT,
23536c77161aSAbylay Ospan 0x9F, nominalRate5bw[priv->xtal], 5);
23546c77161aSAbylay Ospan
23556c77161aSAbylay Ospan /* Set SLV-T Bank : 0x27 */
23566c77161aSAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
23576c77161aSAbylay Ospan cxd2841er_set_reg_bits(priv, I2C_SLVT,
23586c77161aSAbylay Ospan 0x7a, 0x00, 0x0f);
23596c77161aSAbylay Ospan
23606c77161aSAbylay Ospan /* Set SLV-T Bank : 0x10 */
23616c77161aSAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
23626c77161aSAbylay Ospan
23636c77161aSAbylay Ospan /* Group delay equaliser settings for
23646c77161aSAbylay Ospan * ASCOT2D, ASCOT2E and ASCOT3 tuners
23656c77161aSAbylay Ospan */
23667afe510aSDaniel Scheller if (priv->flags & CXD2841ER_ASCOT)
23676c77161aSAbylay Ospan cxd2841er_write_regs(priv, I2C_SLVT,
23686c77161aSAbylay Ospan 0xA6, itbCoef5bw[priv->xtal], 14);
23696c77161aSAbylay Ospan /* <IF freq setting> */
23704b866c4eSDaniel Scheller ifhz = cxd2841er_get_if_hz(priv, 3600000);
23714b866c4eSDaniel Scheller iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
23726c77161aSAbylay Ospan data[0] = (u8) ((iffreq >> 16) & 0xff);
23736c77161aSAbylay Ospan data[1] = (u8)((iffreq >> 8) & 0xff);
23746c77161aSAbylay Ospan data[2] = (u8)(iffreq & 0xff);
23756c77161aSAbylay Ospan cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
23766c77161aSAbylay Ospan /* System bandwidth setting */
23776c77161aSAbylay Ospan cxd2841er_set_reg_bits(
23786c77161aSAbylay Ospan priv, I2C_SLVT, 0xD7, 0x06, 0x07);
2379a6dc60ffSKozlov Sergey break;
2380a6dc60ffSKozlov Sergey case 1712000:
23816c77161aSAbylay Ospan /* <Timing Recovery setting> */
23826c77161aSAbylay Ospan cxd2841er_write_regs(priv, I2C_SLVT,
23836c77161aSAbylay Ospan 0x9F, nominalRate17bw[priv->xtal], 5);
23846c77161aSAbylay Ospan
23856c77161aSAbylay Ospan /* Set SLV-T Bank : 0x27 */
23866c77161aSAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
23876c77161aSAbylay Ospan cxd2841er_set_reg_bits(priv, I2C_SLVT,
23886c77161aSAbylay Ospan 0x7a, 0x03, 0x0f);
23896c77161aSAbylay Ospan
23906c77161aSAbylay Ospan /* Set SLV-T Bank : 0x10 */
23916c77161aSAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
23926c77161aSAbylay Ospan
23936c77161aSAbylay Ospan /* Group delay equaliser settings for
23946c77161aSAbylay Ospan * ASCOT2D, ASCOT2E and ASCOT3 tuners
23956c77161aSAbylay Ospan */
23967afe510aSDaniel Scheller if (priv->flags & CXD2841ER_ASCOT)
23976c77161aSAbylay Ospan cxd2841er_write_regs(priv, I2C_SLVT,
23986c77161aSAbylay Ospan 0xA6, itbCoef17bw[priv->xtal], 14);
23996c77161aSAbylay Ospan /* <IF freq setting> */
24004b866c4eSDaniel Scheller ifhz = cxd2841er_get_if_hz(priv, 3500000);
24014b866c4eSDaniel Scheller iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
24026c77161aSAbylay Ospan data[0] = (u8) ((iffreq >> 16) & 0xff);
24036c77161aSAbylay Ospan data[1] = (u8)((iffreq >> 8) & 0xff);
24046c77161aSAbylay Ospan data[2] = (u8)(iffreq & 0xff);
24056c77161aSAbylay Ospan cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
24066c77161aSAbylay Ospan /* System bandwidth setting */
24076c77161aSAbylay Ospan cxd2841er_set_reg_bits(
24086c77161aSAbylay Ospan priv, I2C_SLVT, 0xD7, 0x03, 0x07);
2409a6dc60ffSKozlov Sergey break;
2410a6dc60ffSKozlov Sergey default:
2411a6dc60ffSKozlov Sergey return -EINVAL;
2412a6dc60ffSKozlov Sergey }
2413a6dc60ffSKozlov Sergey return 0;
2414a6dc60ffSKozlov Sergey }
2415a6dc60ffSKozlov Sergey
cxd2841er_sleep_tc_to_active_t_band(struct cxd2841er_priv * priv,u32 bandwidth)2416a6dc60ffSKozlov Sergey static int cxd2841er_sleep_tc_to_active_t_band(
2417a6dc60ffSKozlov Sergey struct cxd2841er_priv *priv, u32 bandwidth)
2418a6dc60ffSKozlov Sergey {
241983808c23SAbylay Ospan u8 data[MAX_WRITE_REGSIZE];
24204b866c4eSDaniel Scheller u32 iffreq, ifhz;
24213802c1bcSColin Ian King static const u8 nominalRate8bw[3][5] = {
242283808c23SAbylay Ospan /* TRCG Nominal Rate [37:0] */
242383808c23SAbylay Ospan {0x11, 0xF0, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
242483808c23SAbylay Ospan {0x15, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
242583808c23SAbylay Ospan {0x11, 0xF0, 0x00, 0x00, 0x00} /* 41MHz XTal */
242683808c23SAbylay Ospan };
24273802c1bcSColin Ian King static const u8 nominalRate7bw[3][5] = {
242883808c23SAbylay Ospan /* TRCG Nominal Rate [37:0] */
242983808c23SAbylay Ospan {0x14, 0x80, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
243083808c23SAbylay Ospan {0x18, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
243183808c23SAbylay Ospan {0x14, 0x80, 0x00, 0x00, 0x00} /* 41MHz XTal */
243283808c23SAbylay Ospan };
24333802c1bcSColin Ian King static const u8 nominalRate6bw[3][5] = {
243483808c23SAbylay Ospan /* TRCG Nominal Rate [37:0] */
243583808c23SAbylay Ospan {0x17, 0xEA, 0xAA, 0xAA, 0xAA}, /* 20.5MHz XTal */
243683808c23SAbylay Ospan {0x1C, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
243783808c23SAbylay Ospan {0x17, 0xEA, 0xAA, 0xAA, 0xAA} /* 41MHz XTal */
243883808c23SAbylay Ospan };
24393802c1bcSColin Ian King static const u8 nominalRate5bw[3][5] = {
244083808c23SAbylay Ospan /* TRCG Nominal Rate [37:0] */
244183808c23SAbylay Ospan {0x1C, 0xB3, 0x33, 0x33, 0x33}, /* 20.5MHz XTal */
244283808c23SAbylay Ospan {0x21, 0x99, 0x99, 0x99, 0x99}, /* 24MHz XTal */
244383808c23SAbylay Ospan {0x1C, 0xB3, 0x33, 0x33, 0x33} /* 41MHz XTal */
244483808c23SAbylay Ospan };
2445a6dc60ffSKozlov Sergey
24463802c1bcSColin Ian King static const u8 itbCoef8bw[3][14] = {
244783808c23SAbylay Ospan {0x26, 0xAF, 0x06, 0xCD, 0x13, 0xBB, 0x28, 0xBA, 0x23, 0xA9,
244883808c23SAbylay Ospan 0x1F, 0xA8, 0x2C, 0xC8}, /* 20.5MHz XTal */
244983808c23SAbylay Ospan {0x2F, 0xBA, 0x28, 0x9B, 0x28, 0x9D, 0x28, 0xA1, 0x29, 0xA5,
245083808c23SAbylay Ospan 0x2A, 0xAC, 0x29, 0xB5}, /* 24MHz XTal */
245183808c23SAbylay Ospan {0x26, 0xAF, 0x06, 0xCD, 0x13, 0xBB, 0x28, 0xBA, 0x23, 0xA9,
245283808c23SAbylay Ospan 0x1F, 0xA8, 0x2C, 0xC8} /* 41MHz XTal */
245383808c23SAbylay Ospan };
24543802c1bcSColin Ian King static const u8 itbCoef7bw[3][14] = {
245583808c23SAbylay Ospan {0x2C, 0xBD, 0x02, 0xCF, 0x04, 0xF8, 0x23, 0xA6, 0x29, 0xB0,
245683808c23SAbylay Ospan 0x26, 0xA9, 0x21, 0xA5}, /* 20.5MHz XTal */
245783808c23SAbylay Ospan {0x30, 0xB1, 0x29, 0x9A, 0x28, 0x9C, 0x28, 0xA0, 0x29, 0xA2,
245883808c23SAbylay Ospan 0x2B, 0xA6, 0x2B, 0xAD}, /* 24MHz XTal */
245983808c23SAbylay Ospan {0x2C, 0xBD, 0x02, 0xCF, 0x04, 0xF8, 0x23, 0xA6, 0x29, 0xB0,
246083808c23SAbylay Ospan 0x26, 0xA9, 0x21, 0xA5} /* 41MHz XTal */
246183808c23SAbylay Ospan };
24623802c1bcSColin Ian King static const u8 itbCoef6bw[3][14] = {
246383808c23SAbylay Ospan {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00, 0xCF,
246483808c23SAbylay Ospan 0x00, 0xE6, 0x23, 0xA4}, /* 20.5MHz XTal */
246583808c23SAbylay Ospan {0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E, 0x29, 0xA4,
246683808c23SAbylay Ospan 0x29, 0xA2, 0x29, 0xA8}, /* 24MHz XTal */
246783808c23SAbylay Ospan {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00, 0xCF,
246883808c23SAbylay Ospan 0x00, 0xE6, 0x23, 0xA4} /* 41MHz XTal */
246983808c23SAbylay Ospan };
24703802c1bcSColin Ian King static const u8 itbCoef5bw[3][14] = {
247183808c23SAbylay Ospan {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00, 0xCF,
247283808c23SAbylay Ospan 0x00, 0xE6, 0x23, 0xA4}, /* 20.5MHz XTal */
247383808c23SAbylay Ospan {0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E, 0x29, 0xA4,
247483808c23SAbylay Ospan 0x29, 0xA2, 0x29, 0xA8}, /* 24MHz XTal */
247583808c23SAbylay Ospan {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00, 0xCF,
247683808c23SAbylay Ospan 0x00, 0xE6, 0x23, 0xA4} /* 41MHz XTal */
247783808c23SAbylay Ospan };
247883808c23SAbylay Ospan
247983808c23SAbylay Ospan /* Set SLV-T Bank : 0x13 */
2480a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x13);
2481a6dc60ffSKozlov Sergey /* Echo performance optimization setting */
248283808c23SAbylay Ospan data[0] = 0x01;
248383808c23SAbylay Ospan data[1] = 0x14;
248483808c23SAbylay Ospan cxd2841er_write_regs(priv, I2C_SLVT, 0x9C, data, 2);
248583808c23SAbylay Ospan
248683808c23SAbylay Ospan /* Set SLV-T Bank : 0x10 */
2487a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2488a6dc60ffSKozlov Sergey
2489a6dc60ffSKozlov Sergey switch (bandwidth) {
2490a6dc60ffSKozlov Sergey case 8000000:
249183808c23SAbylay Ospan /* <Timing Recovery setting> */
249283808c23SAbylay Ospan cxd2841er_write_regs(priv, I2C_SLVT,
249383808c23SAbylay Ospan 0x9F, nominalRate8bw[priv->xtal], 5);
249483808c23SAbylay Ospan /* Group delay equaliser settings for
249583808c23SAbylay Ospan * ASCOT2D, ASCOT2E and ASCOT3 tuners
249683808c23SAbylay Ospan */
24977afe510aSDaniel Scheller if (priv->flags & CXD2841ER_ASCOT)
249883808c23SAbylay Ospan cxd2841er_write_regs(priv, I2C_SLVT,
249983808c23SAbylay Ospan 0xA6, itbCoef8bw[priv->xtal], 14);
250083808c23SAbylay Ospan /* <IF freq setting> */
25014b866c4eSDaniel Scheller ifhz = cxd2841er_get_if_hz(priv, 4800000);
25024b866c4eSDaniel Scheller iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
250383808c23SAbylay Ospan data[0] = (u8) ((iffreq >> 16) & 0xff);
250483808c23SAbylay Ospan data[1] = (u8)((iffreq >> 8) & 0xff);
250583808c23SAbylay Ospan data[2] = (u8)(iffreq & 0xff);
250683808c23SAbylay Ospan cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
250783808c23SAbylay Ospan /* System bandwidth setting */
250883808c23SAbylay Ospan cxd2841er_set_reg_bits(
250983808c23SAbylay Ospan priv, I2C_SLVT, 0xD7, 0x00, 0x07);
251083808c23SAbylay Ospan
251183808c23SAbylay Ospan /* Demod core latency setting */
251283808c23SAbylay Ospan if (priv->xtal == SONY_XTAL_24000) {
251383808c23SAbylay Ospan data[0] = 0x15;
251483808c23SAbylay Ospan data[1] = 0x28;
251583808c23SAbylay Ospan } else {
251683808c23SAbylay Ospan data[0] = 0x01;
251783808c23SAbylay Ospan data[1] = 0xE0;
251883808c23SAbylay Ospan }
251983808c23SAbylay Ospan cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
252083808c23SAbylay Ospan
252183808c23SAbylay Ospan /* Notch filter setting */
252283808c23SAbylay Ospan data[0] = 0x01;
252383808c23SAbylay Ospan data[1] = 0x02;
252483808c23SAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x17);
252583808c23SAbylay Ospan cxd2841er_write_regs(priv, I2C_SLVT, 0x38, data, 2);
2526a6dc60ffSKozlov Sergey break;
2527a6dc60ffSKozlov Sergey case 7000000:
252883808c23SAbylay Ospan /* <Timing Recovery setting> */
252983808c23SAbylay Ospan cxd2841er_write_regs(priv, I2C_SLVT,
253083808c23SAbylay Ospan 0x9F, nominalRate7bw[priv->xtal], 5);
253183808c23SAbylay Ospan /* Group delay equaliser settings for
253283808c23SAbylay Ospan * ASCOT2D, ASCOT2E and ASCOT3 tuners
253383808c23SAbylay Ospan */
25347afe510aSDaniel Scheller if (priv->flags & CXD2841ER_ASCOT)
253583808c23SAbylay Ospan cxd2841er_write_regs(priv, I2C_SLVT,
253683808c23SAbylay Ospan 0xA6, itbCoef7bw[priv->xtal], 14);
253783808c23SAbylay Ospan /* <IF freq setting> */
25384b866c4eSDaniel Scheller ifhz = cxd2841er_get_if_hz(priv, 4200000);
25394b866c4eSDaniel Scheller iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
254083808c23SAbylay Ospan data[0] = (u8) ((iffreq >> 16) & 0xff);
254183808c23SAbylay Ospan data[1] = (u8)((iffreq >> 8) & 0xff);
254283808c23SAbylay Ospan data[2] = (u8)(iffreq & 0xff);
254383808c23SAbylay Ospan cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
254483808c23SAbylay Ospan /* System bandwidth setting */
254583808c23SAbylay Ospan cxd2841er_set_reg_bits(
254683808c23SAbylay Ospan priv, I2C_SLVT, 0xD7, 0x02, 0x07);
254783808c23SAbylay Ospan
254883808c23SAbylay Ospan /* Demod core latency setting */
254983808c23SAbylay Ospan if (priv->xtal == SONY_XTAL_24000) {
255083808c23SAbylay Ospan data[0] = 0x1F;
255183808c23SAbylay Ospan data[1] = 0xF8;
255283808c23SAbylay Ospan } else {
255383808c23SAbylay Ospan data[0] = 0x12;
255483808c23SAbylay Ospan data[1] = 0xF8;
255583808c23SAbylay Ospan }
255683808c23SAbylay Ospan cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
255783808c23SAbylay Ospan
255883808c23SAbylay Ospan /* Notch filter setting */
255983808c23SAbylay Ospan data[0] = 0x00;
256083808c23SAbylay Ospan data[1] = 0x03;
256183808c23SAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x17);
256283808c23SAbylay Ospan cxd2841er_write_regs(priv, I2C_SLVT, 0x38, data, 2);
2563a6dc60ffSKozlov Sergey break;
2564a6dc60ffSKozlov Sergey case 6000000:
256583808c23SAbylay Ospan /* <Timing Recovery setting> */
256683808c23SAbylay Ospan cxd2841er_write_regs(priv, I2C_SLVT,
256783808c23SAbylay Ospan 0x9F, nominalRate6bw[priv->xtal], 5);
256883808c23SAbylay Ospan /* Group delay equaliser settings for
256983808c23SAbylay Ospan * ASCOT2D, ASCOT2E and ASCOT3 tuners
257083808c23SAbylay Ospan */
25717afe510aSDaniel Scheller if (priv->flags & CXD2841ER_ASCOT)
257283808c23SAbylay Ospan cxd2841er_write_regs(priv, I2C_SLVT,
257383808c23SAbylay Ospan 0xA6, itbCoef6bw[priv->xtal], 14);
257483808c23SAbylay Ospan /* <IF freq setting> */
25754b866c4eSDaniel Scheller ifhz = cxd2841er_get_if_hz(priv, 3600000);
25764b866c4eSDaniel Scheller iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
257783808c23SAbylay Ospan data[0] = (u8) ((iffreq >> 16) & 0xff);
257883808c23SAbylay Ospan data[1] = (u8)((iffreq >> 8) & 0xff);
257983808c23SAbylay Ospan data[2] = (u8)(iffreq & 0xff);
258083808c23SAbylay Ospan cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
258183808c23SAbylay Ospan /* System bandwidth setting */
258283808c23SAbylay Ospan cxd2841er_set_reg_bits(
258383808c23SAbylay Ospan priv, I2C_SLVT, 0xD7, 0x04, 0x07);
258483808c23SAbylay Ospan
258583808c23SAbylay Ospan /* Demod core latency setting */
258683808c23SAbylay Ospan if (priv->xtal == SONY_XTAL_24000) {
258783808c23SAbylay Ospan data[0] = 0x25;
258883808c23SAbylay Ospan data[1] = 0x4C;
258983808c23SAbylay Ospan } else {
259083808c23SAbylay Ospan data[0] = 0x1F;
259183808c23SAbylay Ospan data[1] = 0xDC;
259283808c23SAbylay Ospan }
259383808c23SAbylay Ospan cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
259483808c23SAbylay Ospan
259583808c23SAbylay Ospan /* Notch filter setting */
259683808c23SAbylay Ospan data[0] = 0x00;
259783808c23SAbylay Ospan data[1] = 0x03;
259883808c23SAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x17);
259983808c23SAbylay Ospan cxd2841er_write_regs(priv, I2C_SLVT, 0x38, data, 2);
2600a6dc60ffSKozlov Sergey break;
2601a6dc60ffSKozlov Sergey case 5000000:
260283808c23SAbylay Ospan /* <Timing Recovery setting> */
260383808c23SAbylay Ospan cxd2841er_write_regs(priv, I2C_SLVT,
260483808c23SAbylay Ospan 0x9F, nominalRate5bw[priv->xtal], 5);
260583808c23SAbylay Ospan /* Group delay equaliser settings for
260683808c23SAbylay Ospan * ASCOT2D, ASCOT2E and ASCOT3 tuners
260783808c23SAbylay Ospan */
26087afe510aSDaniel Scheller if (priv->flags & CXD2841ER_ASCOT)
260983808c23SAbylay Ospan cxd2841er_write_regs(priv, I2C_SLVT,
261083808c23SAbylay Ospan 0xA6, itbCoef5bw[priv->xtal], 14);
261183808c23SAbylay Ospan /* <IF freq setting> */
26124b866c4eSDaniel Scheller ifhz = cxd2841er_get_if_hz(priv, 3600000);
26134b866c4eSDaniel Scheller iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
261483808c23SAbylay Ospan data[0] = (u8) ((iffreq >> 16) & 0xff);
261583808c23SAbylay Ospan data[1] = (u8)((iffreq >> 8) & 0xff);
261683808c23SAbylay Ospan data[2] = (u8)(iffreq & 0xff);
261783808c23SAbylay Ospan cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
261883808c23SAbylay Ospan /* System bandwidth setting */
261983808c23SAbylay Ospan cxd2841er_set_reg_bits(
262083808c23SAbylay Ospan priv, I2C_SLVT, 0xD7, 0x06, 0x07);
262183808c23SAbylay Ospan
262283808c23SAbylay Ospan /* Demod core latency setting */
262383808c23SAbylay Ospan if (priv->xtal == SONY_XTAL_24000) {
262483808c23SAbylay Ospan data[0] = 0x2C;
262583808c23SAbylay Ospan data[1] = 0xC2;
262683808c23SAbylay Ospan } else {
262783808c23SAbylay Ospan data[0] = 0x26;
262883808c23SAbylay Ospan data[1] = 0x3C;
262983808c23SAbylay Ospan }
263083808c23SAbylay Ospan cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
263183808c23SAbylay Ospan
263283808c23SAbylay Ospan /* Notch filter setting */
263383808c23SAbylay Ospan data[0] = 0x00;
263483808c23SAbylay Ospan data[1] = 0x03;
263583808c23SAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x17);
263683808c23SAbylay Ospan cxd2841er_write_regs(priv, I2C_SLVT, 0x38, data, 2);
263783808c23SAbylay Ospan break;
263883808c23SAbylay Ospan }
263983808c23SAbylay Ospan
264083808c23SAbylay Ospan return 0;
264183808c23SAbylay Ospan }
264283808c23SAbylay Ospan
cxd2841er_sleep_tc_to_active_i_band(struct cxd2841er_priv * priv,u32 bandwidth)264383808c23SAbylay Ospan static int cxd2841er_sleep_tc_to_active_i_band(
264483808c23SAbylay Ospan struct cxd2841er_priv *priv, u32 bandwidth)
264583808c23SAbylay Ospan {
26464b866c4eSDaniel Scheller u32 iffreq, ifhz;
264783808c23SAbylay Ospan u8 data[3];
264883808c23SAbylay Ospan
264983808c23SAbylay Ospan /* TRCG Nominal Rate */
26503802c1bcSColin Ian King static const u8 nominalRate8bw[3][5] = {
265183808c23SAbylay Ospan {0x00, 0x00, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
265283808c23SAbylay Ospan {0x11, 0xB8, 0x00, 0x00, 0x00}, /* 24MHz XTal */
265383808c23SAbylay Ospan {0x00, 0x00, 0x00, 0x00, 0x00} /* 41MHz XTal */
265483808c23SAbylay Ospan };
265583808c23SAbylay Ospan
26563802c1bcSColin Ian King static const u8 nominalRate7bw[3][5] = {
265783808c23SAbylay Ospan {0x00, 0x00, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
265883808c23SAbylay Ospan {0x14, 0x40, 0x00, 0x00, 0x00}, /* 24MHz XTal */
265983808c23SAbylay Ospan {0x00, 0x00, 0x00, 0x00, 0x00} /* 41MHz XTal */
266083808c23SAbylay Ospan };
266183808c23SAbylay Ospan
26623802c1bcSColin Ian King static const u8 nominalRate6bw[3][5] = {
266383808c23SAbylay Ospan {0x14, 0x2E, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
266483808c23SAbylay Ospan {0x17, 0xA0, 0x00, 0x00, 0x00}, /* 24MHz XTal */
266583808c23SAbylay Ospan {0x14, 0x2E, 0x00, 0x00, 0x00} /* 41MHz XTal */
266683808c23SAbylay Ospan };
266783808c23SAbylay Ospan
26683802c1bcSColin Ian King static const u8 itbCoef8bw[3][14] = {
266983808c23SAbylay Ospan {0x00}, /* 20.5MHz XTal */
267083808c23SAbylay Ospan {0x2F, 0xBA, 0x28, 0x9B, 0x28, 0x9D, 0x28, 0xA1, 0x29,
267183808c23SAbylay Ospan 0xA5, 0x2A, 0xAC, 0x29, 0xB5}, /* 24MHz Xtal */
267283808c23SAbylay Ospan {0x0}, /* 41MHz XTal */
267383808c23SAbylay Ospan };
267483808c23SAbylay Ospan
26753802c1bcSColin Ian King static const u8 itbCoef7bw[3][14] = {
267683808c23SAbylay Ospan {0x00}, /* 20.5MHz XTal */
267783808c23SAbylay Ospan {0x30, 0xB1, 0x29, 0x9A, 0x28, 0x9C, 0x28, 0xA0, 0x29,
267883808c23SAbylay Ospan 0xA2, 0x2B, 0xA6, 0x2B, 0xAD}, /* 24MHz Xtal */
267983808c23SAbylay Ospan {0x00}, /* 41MHz XTal */
268083808c23SAbylay Ospan };
268183808c23SAbylay Ospan
26823802c1bcSColin Ian King static const u8 itbCoef6bw[3][14] = {
268383808c23SAbylay Ospan {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00,
268483808c23SAbylay Ospan 0xCF, 0x00, 0xE6, 0x23, 0xA4}, /* 20.5MHz XTal */
268583808c23SAbylay Ospan {0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E, 0x29,
268683808c23SAbylay Ospan 0xA4, 0x29, 0xA2, 0x29, 0xA8}, /* 24MHz Xtal */
268783808c23SAbylay Ospan {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00,
268883808c23SAbylay Ospan 0xCF, 0x00, 0xE6, 0x23, 0xA4}, /* 41MHz XTal */
268983808c23SAbylay Ospan };
269083808c23SAbylay Ospan
269183808c23SAbylay Ospan dev_dbg(&priv->i2c->dev, "%s() bandwidth=%u\n", __func__, bandwidth);
269283808c23SAbylay Ospan /* Set SLV-T Bank : 0x10 */
269383808c23SAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
269483808c23SAbylay Ospan
269583808c23SAbylay Ospan /* 20.5/41MHz Xtal support is not available
269683808c23SAbylay Ospan * on ISDB-T 7MHzBW and 8MHzBW
269783808c23SAbylay Ospan */
269883808c23SAbylay Ospan if (priv->xtal != SONY_XTAL_24000 && bandwidth > 6000000) {
269983808c23SAbylay Ospan dev_err(&priv->i2c->dev,
270083808c23SAbylay Ospan "%s(): bandwidth %d supported only for 24MHz xtal\n",
270183808c23SAbylay Ospan __func__, bandwidth);
270283808c23SAbylay Ospan return -EINVAL;
270383808c23SAbylay Ospan }
270483808c23SAbylay Ospan
270583808c23SAbylay Ospan switch (bandwidth) {
270683808c23SAbylay Ospan case 8000000:
270783808c23SAbylay Ospan /* TRCG Nominal Rate */
270883808c23SAbylay Ospan cxd2841er_write_regs(priv, I2C_SLVT,
270983808c23SAbylay Ospan 0x9F, nominalRate8bw[priv->xtal], 5);
271083808c23SAbylay Ospan /* Group delay equaliser settings for ASCOT tuners optimized */
27117afe510aSDaniel Scheller if (priv->flags & CXD2841ER_ASCOT)
271283808c23SAbylay Ospan cxd2841er_write_regs(priv, I2C_SLVT,
271383808c23SAbylay Ospan 0xA6, itbCoef8bw[priv->xtal], 14);
271483808c23SAbylay Ospan
271583808c23SAbylay Ospan /* IF freq setting */
27164b866c4eSDaniel Scheller ifhz = cxd2841er_get_if_hz(priv, 4750000);
27174b866c4eSDaniel Scheller iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
271883808c23SAbylay Ospan data[0] = (u8) ((iffreq >> 16) & 0xff);
271983808c23SAbylay Ospan data[1] = (u8)((iffreq >> 8) & 0xff);
272083808c23SAbylay Ospan data[2] = (u8)(iffreq & 0xff);
272183808c23SAbylay Ospan cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
272283808c23SAbylay Ospan
272383808c23SAbylay Ospan /* System bandwidth setting */
272483808c23SAbylay Ospan cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd7, 0x0, 0x7);
272583808c23SAbylay Ospan
272683808c23SAbylay Ospan /* Demod core latency setting */
272783808c23SAbylay Ospan data[0] = 0x13;
272883808c23SAbylay Ospan data[1] = 0xFC;
272983808c23SAbylay Ospan cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
273083808c23SAbylay Ospan
273183808c23SAbylay Ospan /* Acquisition optimization setting */
273283808c23SAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x12);
273383808c23SAbylay Ospan cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x71, 0x03, 0x07);
273483808c23SAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x15);
273583808c23SAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0xBE, 0x03);
273683808c23SAbylay Ospan break;
273783808c23SAbylay Ospan case 7000000:
273883808c23SAbylay Ospan /* TRCG Nominal Rate */
273983808c23SAbylay Ospan cxd2841er_write_regs(priv, I2C_SLVT,
274083808c23SAbylay Ospan 0x9F, nominalRate7bw[priv->xtal], 5);
274183808c23SAbylay Ospan /* Group delay equaliser settings for ASCOT tuners optimized */
27427afe510aSDaniel Scheller if (priv->flags & CXD2841ER_ASCOT)
274383808c23SAbylay Ospan cxd2841er_write_regs(priv, I2C_SLVT,
274483808c23SAbylay Ospan 0xA6, itbCoef7bw[priv->xtal], 14);
274583808c23SAbylay Ospan
274683808c23SAbylay Ospan /* IF freq setting */
27474b866c4eSDaniel Scheller ifhz = cxd2841er_get_if_hz(priv, 4150000);
27484b866c4eSDaniel Scheller iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
274983808c23SAbylay Ospan data[0] = (u8) ((iffreq >> 16) & 0xff);
275083808c23SAbylay Ospan data[1] = (u8)((iffreq >> 8) & 0xff);
275183808c23SAbylay Ospan data[2] = (u8)(iffreq & 0xff);
275283808c23SAbylay Ospan cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
275383808c23SAbylay Ospan
275483808c23SAbylay Ospan /* System bandwidth setting */
275583808c23SAbylay Ospan cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd7, 0x02, 0x7);
275683808c23SAbylay Ospan
275783808c23SAbylay Ospan /* Demod core latency setting */
275883808c23SAbylay Ospan data[0] = 0x1A;
275983808c23SAbylay Ospan data[1] = 0xFA;
276083808c23SAbylay Ospan cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
276183808c23SAbylay Ospan
276283808c23SAbylay Ospan /* Acquisition optimization setting */
276383808c23SAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x12);
276483808c23SAbylay Ospan cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x71, 0x03, 0x07);
276583808c23SAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x15);
276683808c23SAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0xBE, 0x02);
276783808c23SAbylay Ospan break;
276883808c23SAbylay Ospan case 6000000:
276983808c23SAbylay Ospan /* TRCG Nominal Rate */
277083808c23SAbylay Ospan cxd2841er_write_regs(priv, I2C_SLVT,
277183808c23SAbylay Ospan 0x9F, nominalRate6bw[priv->xtal], 5);
277283808c23SAbylay Ospan /* Group delay equaliser settings for ASCOT tuners optimized */
27737afe510aSDaniel Scheller if (priv->flags & CXD2841ER_ASCOT)
277483808c23SAbylay Ospan cxd2841er_write_regs(priv, I2C_SLVT,
277583808c23SAbylay Ospan 0xA6, itbCoef6bw[priv->xtal], 14);
277683808c23SAbylay Ospan
277783808c23SAbylay Ospan /* IF freq setting */
27784b866c4eSDaniel Scheller ifhz = cxd2841er_get_if_hz(priv, 3550000);
27794b866c4eSDaniel Scheller iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
278083808c23SAbylay Ospan data[0] = (u8) ((iffreq >> 16) & 0xff);
278183808c23SAbylay Ospan data[1] = (u8)((iffreq >> 8) & 0xff);
278283808c23SAbylay Ospan data[2] = (u8)(iffreq & 0xff);
278383808c23SAbylay Ospan cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
278483808c23SAbylay Ospan
278583808c23SAbylay Ospan /* System bandwidth setting */
278683808c23SAbylay Ospan cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd7, 0x04, 0x7);
278783808c23SAbylay Ospan
278883808c23SAbylay Ospan /* Demod core latency setting */
278983808c23SAbylay Ospan if (priv->xtal == SONY_XTAL_24000) {
279083808c23SAbylay Ospan data[0] = 0x1F;
279183808c23SAbylay Ospan data[1] = 0x79;
279283808c23SAbylay Ospan } else {
279383808c23SAbylay Ospan data[0] = 0x1A;
279483808c23SAbylay Ospan data[1] = 0xE2;
279583808c23SAbylay Ospan }
279683808c23SAbylay Ospan cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
279783808c23SAbylay Ospan
279883808c23SAbylay Ospan /* Acquisition optimization setting */
279983808c23SAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x12);
280083808c23SAbylay Ospan cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x71, 0x07, 0x07);
280183808c23SAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x15);
280283808c23SAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0xBE, 0x02);
2803a6dc60ffSKozlov Sergey break;
2804a6dc60ffSKozlov Sergey default:
2805a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s(): invalid bandwidth %d\n",
2806a6dc60ffSKozlov Sergey __func__, bandwidth);
2807a6dc60ffSKozlov Sergey return -EINVAL;
2808a6dc60ffSKozlov Sergey }
2809a6dc60ffSKozlov Sergey return 0;
2810a6dc60ffSKozlov Sergey }
2811a6dc60ffSKozlov Sergey
cxd2841er_sleep_tc_to_active_c_band(struct cxd2841er_priv * priv,u32 bandwidth)2812a6dc60ffSKozlov Sergey static int cxd2841er_sleep_tc_to_active_c_band(struct cxd2841er_priv *priv,
2813a6dc60ffSKozlov Sergey u32 bandwidth)
2814a6dc60ffSKozlov Sergey {
2815a6dc60ffSKozlov Sergey u8 bw7_8mhz_b10_a6[] = {
2816a6dc60ffSKozlov Sergey 0x2D, 0xC7, 0x04, 0xF4, 0x07, 0xC5, 0x2A, 0xB8,
2817a6dc60ffSKozlov Sergey 0x27, 0x9E, 0x27, 0xA4, 0x29, 0xAB };
2818a6dc60ffSKozlov Sergey u8 bw6mhz_b10_a6[] = {
2819a6dc60ffSKozlov Sergey 0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8,
2820a6dc60ffSKozlov Sergey 0x00, 0xCF, 0x00, 0xE6, 0x23, 0xA4 };
2821a6dc60ffSKozlov Sergey u8 b10_b6[3];
28224b866c4eSDaniel Scheller u32 iffreq, ifhz;
2823a6dc60ffSKozlov Sergey
2824af4cc462SAbylay Ospan if (bandwidth != 6000000 &&
2825af4cc462SAbylay Ospan bandwidth != 7000000 &&
2826af4cc462SAbylay Ospan bandwidth != 8000000) {
2827af4cc462SAbylay Ospan dev_info(&priv->i2c->dev, "%s(): unsupported bandwidth %d. Forcing 8Mhz!\n",
2828af4cc462SAbylay Ospan __func__, bandwidth);
2829af4cc462SAbylay Ospan bandwidth = 8000000;
2830af4cc462SAbylay Ospan }
2831af4cc462SAbylay Ospan
28323f3b48a0SAbylay Ospan dev_dbg(&priv->i2c->dev, "%s() bw=%d\n", __func__, bandwidth);
2833a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2834a6dc60ffSKozlov Sergey switch (bandwidth) {
2835a6dc60ffSKozlov Sergey case 8000000:
2836a6dc60ffSKozlov Sergey case 7000000:
28377afe510aSDaniel Scheller if (priv->flags & CXD2841ER_ASCOT)
2838a6dc60ffSKozlov Sergey cxd2841er_write_regs(
2839a6dc60ffSKozlov Sergey priv, I2C_SLVT, 0xa6,
2840a6dc60ffSKozlov Sergey bw7_8mhz_b10_a6, sizeof(bw7_8mhz_b10_a6));
28414b866c4eSDaniel Scheller ifhz = cxd2841er_get_if_hz(priv, 4900000);
28424b866c4eSDaniel Scheller iffreq = cxd2841er_calc_iffreq(ifhz);
2843a6dc60ffSKozlov Sergey break;
2844a6dc60ffSKozlov Sergey case 6000000:
28457afe510aSDaniel Scheller if (priv->flags & CXD2841ER_ASCOT)
2846a6dc60ffSKozlov Sergey cxd2841er_write_regs(
2847a6dc60ffSKozlov Sergey priv, I2C_SLVT, 0xa6,
2848a6dc60ffSKozlov Sergey bw6mhz_b10_a6, sizeof(bw6mhz_b10_a6));
28494b866c4eSDaniel Scheller ifhz = cxd2841er_get_if_hz(priv, 3700000);
28504b866c4eSDaniel Scheller iffreq = cxd2841er_calc_iffreq(ifhz);
2851a6dc60ffSKozlov Sergey break;
2852a6dc60ffSKozlov Sergey default:
28533f3b48a0SAbylay Ospan dev_err(&priv->i2c->dev, "%s(): unsupported bandwidth %d\n",
2854a6dc60ffSKozlov Sergey __func__, bandwidth);
2855a6dc60ffSKozlov Sergey return -EINVAL;
2856a6dc60ffSKozlov Sergey }
2857a6dc60ffSKozlov Sergey /* <IF freq setting> */
2858a6dc60ffSKozlov Sergey b10_b6[0] = (u8) ((iffreq >> 16) & 0xff);
2859a6dc60ffSKozlov Sergey b10_b6[1] = (u8)((iffreq >> 8) & 0xff);
2860a6dc60ffSKozlov Sergey b10_b6[2] = (u8)(iffreq & 0xff);
2861a6dc60ffSKozlov Sergey cxd2841er_write_regs(priv, I2C_SLVT, 0xb6, b10_b6, sizeof(b10_b6));
2862a6dc60ffSKozlov Sergey /* Set SLV-T Bank : 0x11 */
2863a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
2864a6dc60ffSKozlov Sergey switch (bandwidth) {
2865a6dc60ffSKozlov Sergey case 8000000:
2866a6dc60ffSKozlov Sergey case 7000000:
2867a6dc60ffSKozlov Sergey cxd2841er_set_reg_bits(
2868a6dc60ffSKozlov Sergey priv, I2C_SLVT, 0xa3, 0x00, 0x1f);
2869a6dc60ffSKozlov Sergey break;
2870a6dc60ffSKozlov Sergey case 6000000:
2871a6dc60ffSKozlov Sergey cxd2841er_set_reg_bits(
2872a6dc60ffSKozlov Sergey priv, I2C_SLVT, 0xa3, 0x14, 0x1f);
2873a6dc60ffSKozlov Sergey break;
2874a6dc60ffSKozlov Sergey }
2875a6dc60ffSKozlov Sergey /* Set SLV-T Bank : 0x40 */
2876a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
2877a6dc60ffSKozlov Sergey switch (bandwidth) {
2878a6dc60ffSKozlov Sergey case 8000000:
2879a6dc60ffSKozlov Sergey cxd2841er_set_reg_bits(
2880a6dc60ffSKozlov Sergey priv, I2C_SLVT, 0x26, 0x0b, 0x0f);
2881a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x27, 0x3e);
2882a6dc60ffSKozlov Sergey break;
2883a6dc60ffSKozlov Sergey case 7000000:
2884a6dc60ffSKozlov Sergey cxd2841er_set_reg_bits(
2885a6dc60ffSKozlov Sergey priv, I2C_SLVT, 0x26, 0x09, 0x0f);
2886a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x27, 0xd6);
2887a6dc60ffSKozlov Sergey break;
2888a6dc60ffSKozlov Sergey case 6000000:
2889a6dc60ffSKozlov Sergey cxd2841er_set_reg_bits(
2890a6dc60ffSKozlov Sergey priv, I2C_SLVT, 0x26, 0x08, 0x0f);
2891a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x27, 0x6e);
2892a6dc60ffSKozlov Sergey break;
2893a6dc60ffSKozlov Sergey }
2894a6dc60ffSKozlov Sergey return 0;
2895a6dc60ffSKozlov Sergey }
2896a6dc60ffSKozlov Sergey
cxd2841er_sleep_tc_to_active_t(struct cxd2841er_priv * priv,u32 bandwidth)2897a6dc60ffSKozlov Sergey static int cxd2841er_sleep_tc_to_active_t(struct cxd2841er_priv *priv,
2898a6dc60ffSKozlov Sergey u32 bandwidth)
2899a6dc60ffSKozlov Sergey {
2900a6dc60ffSKozlov Sergey u8 data[2] = { 0x09, 0x54 };
290183808c23SAbylay Ospan u8 data24m[3] = {0xDC, 0x6C, 0x00};
2902a6dc60ffSKozlov Sergey
2903a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2904a6dc60ffSKozlov Sergey cxd2841er_set_ts_clock_mode(priv, SYS_DVBT);
2905a6dc60ffSKozlov Sergey /* Set SLV-X Bank : 0x00 */
2906a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
2907a6dc60ffSKozlov Sergey /* Set demod mode */
2908a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x01);
2909a6dc60ffSKozlov Sergey /* Set SLV-T Bank : 0x00 */
2910a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2911a6dc60ffSKozlov Sergey /* Enable demod clock */
2912a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
2913a6dc60ffSKozlov Sergey /* Disable RF level monitor */
2914a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
2915a6dc60ffSKozlov Sergey /* Enable ADC clock */
2916a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
2917a6dc60ffSKozlov Sergey /* Enable ADC 1 */
2918a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x1a);
291983808c23SAbylay Ospan /* Enable ADC 2 & 3 */
292083808c23SAbylay Ospan if (priv->xtal == SONY_XTAL_41000) {
292183808c23SAbylay Ospan data[0] = 0x0A;
292283808c23SAbylay Ospan data[1] = 0xD4;
292383808c23SAbylay Ospan }
2924a6dc60ffSKozlov Sergey cxd2841er_write_regs(priv, I2C_SLVT, 0x43, data, 2);
2925a6dc60ffSKozlov Sergey /* Enable ADC 4 */
2926a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
2927a6dc60ffSKozlov Sergey /* Set SLV-T Bank : 0x10 */
2928a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2929a6dc60ffSKozlov Sergey /* IFAGC gain settings */
2930a6dc60ffSKozlov Sergey cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd2, 0x0c, 0x1f);
2931a6dc60ffSKozlov Sergey /* Set SLV-T Bank : 0x11 */
2932a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
2933a6dc60ffSKozlov Sergey /* BBAGC TARGET level setting */
2934a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x6a, 0x50);
2935a6dc60ffSKozlov Sergey /* Set SLV-T Bank : 0x10 */
2936a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
29377afe510aSDaniel Scheller /* ASCOT setting */
29387afe510aSDaniel Scheller cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa5,
29397afe510aSDaniel Scheller ((priv->flags & CXD2841ER_ASCOT) ? 0x01 : 0x00), 0x01);
2940a6dc60ffSKozlov Sergey /* Set SLV-T Bank : 0x18 */
2941a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x18);
2942868c9a17SMauro Carvalho Chehab /* Pre-RS BER monitor setting */
2943a6dc60ffSKozlov Sergey cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x36, 0x40, 0x07);
2944a6dc60ffSKozlov Sergey /* FEC Auto Recovery setting */
2945a6dc60ffSKozlov Sergey cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x30, 0x01, 0x01);
2946a6dc60ffSKozlov Sergey cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x31, 0x01, 0x01);
2947a6dc60ffSKozlov Sergey /* Set SLV-T Bank : 0x00 */
2948a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2949a6dc60ffSKozlov Sergey /* TSIF setting */
2950a6dc60ffSKozlov Sergey cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xce, 0x01, 0x01);
2951a6dc60ffSKozlov Sergey cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcf, 0x01, 0x01);
295283808c23SAbylay Ospan
295383808c23SAbylay Ospan if (priv->xtal == SONY_XTAL_24000) {
295483808c23SAbylay Ospan /* Set SLV-T Bank : 0x10 */
295583808c23SAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
295683808c23SAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0xBF, 0x60);
295783808c23SAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x18);
295883808c23SAbylay Ospan cxd2841er_write_regs(priv, I2C_SLVT, 0x24, data24m, 3);
295983808c23SAbylay Ospan }
296083808c23SAbylay Ospan
2961a6dc60ffSKozlov Sergey cxd2841er_sleep_tc_to_active_t_band(priv, bandwidth);
2962a6dc60ffSKozlov Sergey /* Set SLV-T Bank : 0x00 */
2963a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2964a6dc60ffSKozlov Sergey /* Disable HiZ Setting 1 */
2965a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x28);
2966a6dc60ffSKozlov Sergey /* Disable HiZ Setting 2 */
2967a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
2968a6dc60ffSKozlov Sergey priv->state = STATE_ACTIVE_TC;
2969a6dc60ffSKozlov Sergey return 0;
2970a6dc60ffSKozlov Sergey }
2971a6dc60ffSKozlov Sergey
cxd2841er_sleep_tc_to_active_t2(struct cxd2841er_priv * priv,u32 bandwidth)2972a6dc60ffSKozlov Sergey static int cxd2841er_sleep_tc_to_active_t2(struct cxd2841er_priv *priv,
2973a6dc60ffSKozlov Sergey u32 bandwidth)
2974a6dc60ffSKozlov Sergey {
29756c77161aSAbylay Ospan u8 data[MAX_WRITE_REGSIZE];
2976a6dc60ffSKozlov Sergey
2977a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2978a6dc60ffSKozlov Sergey cxd2841er_set_ts_clock_mode(priv, SYS_DVBT2);
2979a6dc60ffSKozlov Sergey /* Set SLV-X Bank : 0x00 */
2980a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
2981a6dc60ffSKozlov Sergey /* Set demod mode */
2982a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x02);
2983a6dc60ffSKozlov Sergey /* Set SLV-T Bank : 0x00 */
2984a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2985a6dc60ffSKozlov Sergey /* Enable demod clock */
2986a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
2987a6dc60ffSKozlov Sergey /* Disable RF level monitor */
29886c77161aSAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x59, 0x00);
2989a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
2990a6dc60ffSKozlov Sergey /* Enable ADC clock */
2991a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
2992a6dc60ffSKozlov Sergey /* Enable ADC 1 */
2993a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x1a);
29946c77161aSAbylay Ospan
29956c77161aSAbylay Ospan if (priv->xtal == SONY_XTAL_41000) {
29966c77161aSAbylay Ospan data[0] = 0x0A;
29976c77161aSAbylay Ospan data[1] = 0xD4;
29986c77161aSAbylay Ospan } else {
29996c77161aSAbylay Ospan data[0] = 0x09;
30006c77161aSAbylay Ospan data[1] = 0x54;
30016c77161aSAbylay Ospan }
30026c77161aSAbylay Ospan
3003a6dc60ffSKozlov Sergey cxd2841er_write_regs(priv, I2C_SLVT, 0x43, data, 2);
3004a6dc60ffSKozlov Sergey /* Enable ADC 4 */
3005a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
3006a6dc60ffSKozlov Sergey /* Set SLV-T Bank : 0x10 */
3007a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
3008a6dc60ffSKozlov Sergey /* IFAGC gain settings */
3009a6dc60ffSKozlov Sergey cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd2, 0x0c, 0x1f);
3010a6dc60ffSKozlov Sergey /* Set SLV-T Bank : 0x11 */
3011a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
3012a6dc60ffSKozlov Sergey /* BBAGC TARGET level setting */
3013a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x6a, 0x50);
3014a6dc60ffSKozlov Sergey /* Set SLV-T Bank : 0x10 */
3015a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
30167afe510aSDaniel Scheller /* ASCOT setting */
30177afe510aSDaniel Scheller cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa5,
30187afe510aSDaniel Scheller ((priv->flags & CXD2841ER_ASCOT) ? 0x01 : 0x00), 0x01);
3019a6dc60ffSKozlov Sergey /* Set SLV-T Bank : 0x20 */
3020a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
3021a6dc60ffSKozlov Sergey /* Acquisition optimization setting */
3022a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x8b, 0x3c);
3023a6dc60ffSKozlov Sergey /* Set SLV-T Bank : 0x2b */
3024a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2b);
3025a6dc60ffSKozlov Sergey cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x76, 0x20, 0x70);
30266c77161aSAbylay Ospan /* Set SLV-T Bank : 0x23 */
30276c77161aSAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x23);
30286c77161aSAbylay Ospan /* L1 Control setting */
30296c77161aSAbylay Ospan cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xE6, 0x00, 0x03);
3030a6dc60ffSKozlov Sergey /* Set SLV-T Bank : 0x00 */
3031a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
3032a6dc60ffSKozlov Sergey /* TSIF setting */
3033a6dc60ffSKozlov Sergey cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xce, 0x01, 0x01);
3034a6dc60ffSKozlov Sergey cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcf, 0x01, 0x01);
3035a6dc60ffSKozlov Sergey /* DVB-T2 initial setting */
3036a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x13);
3037a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x83, 0x10);
3038a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x86, 0x34);
3039a6dc60ffSKozlov Sergey cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x9e, 0x09, 0x0f);
3040a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x9f, 0xd8);
3041a6dc60ffSKozlov Sergey /* Set SLV-T Bank : 0x2a */
3042a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2a);
3043a6dc60ffSKozlov Sergey cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x38, 0x04, 0x0f);
3044a6dc60ffSKozlov Sergey /* Set SLV-T Bank : 0x2b */
3045a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2b);
3046a6dc60ffSKozlov Sergey cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x11, 0x20, 0x3f);
3047a6dc60ffSKozlov Sergey
30486c77161aSAbylay Ospan /* 24MHz Xtal setting */
30496c77161aSAbylay Ospan if (priv->xtal == SONY_XTAL_24000) {
30506c77161aSAbylay Ospan /* Set SLV-T Bank : 0x11 */
30516c77161aSAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
30526c77161aSAbylay Ospan data[0] = 0xEB;
30536c77161aSAbylay Ospan data[1] = 0x03;
30546c77161aSAbylay Ospan data[2] = 0x3B;
30556c77161aSAbylay Ospan cxd2841er_write_regs(priv, I2C_SLVT, 0x33, data, 3);
30566c77161aSAbylay Ospan
30576c77161aSAbylay Ospan /* Set SLV-T Bank : 0x20 */
30586c77161aSAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
30596c77161aSAbylay Ospan data[0] = 0x5E;
30606c77161aSAbylay Ospan data[1] = 0x5E;
30616c77161aSAbylay Ospan data[2] = 0x47;
30626c77161aSAbylay Ospan cxd2841er_write_regs(priv, I2C_SLVT, 0x95, data, 3);
30636c77161aSAbylay Ospan
30646c77161aSAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x99, 0x18);
30656c77161aSAbylay Ospan
30666c77161aSAbylay Ospan data[0] = 0x3F;
30676c77161aSAbylay Ospan data[1] = 0xFF;
30686c77161aSAbylay Ospan cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
30696c77161aSAbylay Ospan
30706c77161aSAbylay Ospan /* Set SLV-T Bank : 0x24 */
30716c77161aSAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x24);
30726c77161aSAbylay Ospan data[0] = 0x0B;
30736c77161aSAbylay Ospan data[1] = 0x72;
30746c77161aSAbylay Ospan cxd2841er_write_regs(priv, I2C_SLVT, 0x34, data, 2);
30756c77161aSAbylay Ospan
30766c77161aSAbylay Ospan data[0] = 0x93;
30776c77161aSAbylay Ospan data[1] = 0xF3;
30786c77161aSAbylay Ospan data[2] = 0x00;
30796c77161aSAbylay Ospan cxd2841er_write_regs(priv, I2C_SLVT, 0xD2, data, 3);
30806c77161aSAbylay Ospan
30816c77161aSAbylay Ospan data[0] = 0x05;
30826c77161aSAbylay Ospan data[1] = 0xB8;
30836c77161aSAbylay Ospan data[2] = 0xD8;
30846c77161aSAbylay Ospan cxd2841er_write_regs(priv, I2C_SLVT, 0xDD, data, 3);
30856c77161aSAbylay Ospan
30866c77161aSAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0xE0, 0x00);
30876c77161aSAbylay Ospan
30886c77161aSAbylay Ospan /* Set SLV-T Bank : 0x25 */
30896c77161aSAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x25);
30906c77161aSAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0xED, 0x60);
30916c77161aSAbylay Ospan
30926c77161aSAbylay Ospan /* Set SLV-T Bank : 0x27 */
30936c77161aSAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
30946c77161aSAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0xFA, 0x34);
30956c77161aSAbylay Ospan
30966c77161aSAbylay Ospan /* Set SLV-T Bank : 0x2B */
30976c77161aSAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2B);
30986c77161aSAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x4B, 0x2F);
30996c77161aSAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x9E, 0x0E);
31006c77161aSAbylay Ospan
31016c77161aSAbylay Ospan /* Set SLV-T Bank : 0x2D */
31026c77161aSAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2D);
31036c77161aSAbylay Ospan data[0] = 0x89;
31046c77161aSAbylay Ospan data[1] = 0x89;
31056c77161aSAbylay Ospan cxd2841er_write_regs(priv, I2C_SLVT, 0x24, data, 2);
31066c77161aSAbylay Ospan
31076c77161aSAbylay Ospan /* Set SLV-T Bank : 0x5E */
31086c77161aSAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x5E);
31096c77161aSAbylay Ospan data[0] = 0x24;
31106c77161aSAbylay Ospan data[1] = 0x95;
31116c77161aSAbylay Ospan cxd2841er_write_regs(priv, I2C_SLVT, 0x8C, data, 2);
31126c77161aSAbylay Ospan }
31136c77161aSAbylay Ospan
3114a6dc60ffSKozlov Sergey cxd2841er_sleep_tc_to_active_t2_band(priv, bandwidth);
3115a6dc60ffSKozlov Sergey
3116a6dc60ffSKozlov Sergey /* Set SLV-T Bank : 0x00 */
3117a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
3118a6dc60ffSKozlov Sergey /* Disable HiZ Setting 1 */
3119a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x28);
3120a6dc60ffSKozlov Sergey /* Disable HiZ Setting 2 */
3121a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
3122a6dc60ffSKozlov Sergey priv->state = STATE_ACTIVE_TC;
3123a6dc60ffSKozlov Sergey return 0;
3124a6dc60ffSKozlov Sergey }
3125a6dc60ffSKozlov Sergey
312683808c23SAbylay Ospan /* ISDB-Tb part */
cxd2841er_sleep_tc_to_active_i(struct cxd2841er_priv * priv,u32 bandwidth)312783808c23SAbylay Ospan static int cxd2841er_sleep_tc_to_active_i(struct cxd2841er_priv *priv,
312883808c23SAbylay Ospan u32 bandwidth)
312983808c23SAbylay Ospan {
313083808c23SAbylay Ospan u8 data[2] = { 0x09, 0x54 };
313183808c23SAbylay Ospan u8 data24m[2] = {0x60, 0x00};
313283808c23SAbylay Ospan u8 data24m2[3] = {0xB7, 0x1B, 0x00};
313383808c23SAbylay Ospan
313483808c23SAbylay Ospan dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
313583808c23SAbylay Ospan cxd2841er_set_ts_clock_mode(priv, SYS_DVBT);
313683808c23SAbylay Ospan /* Set SLV-X Bank : 0x00 */
313783808c23SAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
313883808c23SAbylay Ospan /* Set demod mode */
313983808c23SAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x06);
314083808c23SAbylay Ospan /* Set SLV-T Bank : 0x00 */
314183808c23SAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
314283808c23SAbylay Ospan /* Enable demod clock */
314383808c23SAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
314483808c23SAbylay Ospan /* Enable RF level monitor */
314583808c23SAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x01);
314683808c23SAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x59, 0x01);
314783808c23SAbylay Ospan /* Enable ADC clock */
314883808c23SAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
314983808c23SAbylay Ospan /* Enable ADC 1 */
315083808c23SAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x1a);
315183808c23SAbylay Ospan /* xtal freq 20.5MHz or 24M */
315283808c23SAbylay Ospan cxd2841er_write_regs(priv, I2C_SLVT, 0x43, data, 2);
315383808c23SAbylay Ospan /* Enable ADC 4 */
315483808c23SAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
31557afe510aSDaniel Scheller /* ASCOT setting */
31567afe510aSDaniel Scheller cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa5,
31577afe510aSDaniel Scheller ((priv->flags & CXD2841ER_ASCOT) ? 0x01 : 0x00), 0x01);
315883808c23SAbylay Ospan /* FEC Auto Recovery setting */
315983808c23SAbylay Ospan cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x30, 0x01, 0x01);
316083808c23SAbylay Ospan cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x31, 0x00, 0x01);
316183808c23SAbylay Ospan /* ISDB-T initial setting */
316283808c23SAbylay Ospan /* Set SLV-T Bank : 0x00 */
316383808c23SAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
316483808c23SAbylay Ospan cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xce, 0x00, 0x01);
316583808c23SAbylay Ospan cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcf, 0x00, 0x01);
316683808c23SAbylay Ospan /* Set SLV-T Bank : 0x10 */
316783808c23SAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
316883808c23SAbylay Ospan cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x69, 0x04, 0x07);
316983808c23SAbylay Ospan cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x6B, 0x03, 0x07);
317083808c23SAbylay Ospan cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x9D, 0x50, 0xFF);
317183808c23SAbylay Ospan cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xD3, 0x06, 0x1F);
317283808c23SAbylay Ospan cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xED, 0x00, 0x01);
317383808c23SAbylay Ospan cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xE2, 0xCE, 0x80);
317483808c23SAbylay Ospan cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xF2, 0x13, 0x10);
317583808c23SAbylay Ospan cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xDE, 0x2E, 0x3F);
317683808c23SAbylay Ospan /* Set SLV-T Bank : 0x15 */
317783808c23SAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x15);
317883808c23SAbylay Ospan cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xDE, 0x02, 0x03);
317983808c23SAbylay Ospan /* Set SLV-T Bank : 0x1E */
318083808c23SAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x1E);
318183808c23SAbylay Ospan cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x73, 0x68, 0xFF);
318283808c23SAbylay Ospan /* Set SLV-T Bank : 0x63 */
318383808c23SAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x63);
318483808c23SAbylay Ospan cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x81, 0x00, 0x01);
318583808c23SAbylay Ospan
318683808c23SAbylay Ospan /* for xtal 24MHz */
318783808c23SAbylay Ospan /* Set SLV-T Bank : 0x10 */
318883808c23SAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
318983808c23SAbylay Ospan cxd2841er_write_regs(priv, I2C_SLVT, 0xBF, data24m, 2);
319083808c23SAbylay Ospan /* Set SLV-T Bank : 0x60 */
319183808c23SAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
319283808c23SAbylay Ospan cxd2841er_write_regs(priv, I2C_SLVT, 0xA8, data24m2, 3);
319383808c23SAbylay Ospan
319483808c23SAbylay Ospan cxd2841er_sleep_tc_to_active_i_band(priv, bandwidth);
319583808c23SAbylay Ospan /* Set SLV-T Bank : 0x00 */
319683808c23SAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
319783808c23SAbylay Ospan /* Disable HiZ Setting 1 */
319883808c23SAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x28);
319983808c23SAbylay Ospan /* Disable HiZ Setting 2 */
320083808c23SAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
320183808c23SAbylay Ospan priv->state = STATE_ACTIVE_TC;
320283808c23SAbylay Ospan return 0;
320383808c23SAbylay Ospan }
320483808c23SAbylay Ospan
cxd2841er_sleep_tc_to_active_c(struct cxd2841er_priv * priv,u32 bandwidth)3205a6dc60ffSKozlov Sergey static int cxd2841er_sleep_tc_to_active_c(struct cxd2841er_priv *priv,
3206a6dc60ffSKozlov Sergey u32 bandwidth)
3207a6dc60ffSKozlov Sergey {
3208a6dc60ffSKozlov Sergey u8 data[2] = { 0x09, 0x54 };
3209a6dc60ffSKozlov Sergey
3210a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3211a6dc60ffSKozlov Sergey cxd2841er_set_ts_clock_mode(priv, SYS_DVBC_ANNEX_A);
3212a6dc60ffSKozlov Sergey /* Set SLV-X Bank : 0x00 */
3213a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
3214a6dc60ffSKozlov Sergey /* Set demod mode */
3215a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x04);
3216a6dc60ffSKozlov Sergey /* Set SLV-T Bank : 0x00 */
3217a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
3218a6dc60ffSKozlov Sergey /* Enable demod clock */
3219a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
3220a6dc60ffSKozlov Sergey /* Disable RF level monitor */
32214a86bc10SAbylay Ospan cxd2841er_write_reg(priv, I2C_SLVT, 0x59, 0x00);
3222a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
3223a6dc60ffSKozlov Sergey /* Enable ADC clock */
3224a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
3225a6dc60ffSKozlov Sergey /* Enable ADC 1 */
3226a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x1a);
3227a6dc60ffSKozlov Sergey /* xtal freq 20.5MHz */
3228a6dc60ffSKozlov Sergey cxd2841er_write_regs(priv, I2C_SLVT, 0x43, data, 2);
3229a6dc60ffSKozlov Sergey /* Enable ADC 4 */
3230a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
3231a6dc60ffSKozlov Sergey /* Set SLV-T Bank : 0x10 */
3232a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
3233a6dc60ffSKozlov Sergey /* IFAGC gain settings */
3234a6dc60ffSKozlov Sergey cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd2, 0x09, 0x1f);
3235a6dc60ffSKozlov Sergey /* Set SLV-T Bank : 0x11 */
3236a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
3237a6dc60ffSKozlov Sergey /* BBAGC TARGET level setting */
3238a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x6a, 0x48);
3239a6dc60ffSKozlov Sergey /* Set SLV-T Bank : 0x10 */
3240a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
32417afe510aSDaniel Scheller /* ASCOT setting */
32427afe510aSDaniel Scheller cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa5,
32437afe510aSDaniel Scheller ((priv->flags & CXD2841ER_ASCOT) ? 0x01 : 0x00), 0x01);
3244a6dc60ffSKozlov Sergey /* Set SLV-T Bank : 0x40 */
3245a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
3246a6dc60ffSKozlov Sergey /* Demod setting */
3247a6dc60ffSKozlov Sergey cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xc3, 0x00, 0x04);
3248a6dc60ffSKozlov Sergey /* Set SLV-T Bank : 0x00 */
3249a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
3250a6dc60ffSKozlov Sergey /* TSIF setting */
3251a6dc60ffSKozlov Sergey cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xce, 0x01, 0x01);
3252a6dc60ffSKozlov Sergey cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcf, 0x01, 0x01);
3253a6dc60ffSKozlov Sergey
32543f3b48a0SAbylay Ospan cxd2841er_sleep_tc_to_active_c_band(priv, bandwidth);
3255a6dc60ffSKozlov Sergey /* Set SLV-T Bank : 0x00 */
3256a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
3257a6dc60ffSKozlov Sergey /* Disable HiZ Setting 1 */
3258a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x28);
3259a6dc60ffSKozlov Sergey /* Disable HiZ Setting 2 */
3260a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
3261a6dc60ffSKozlov Sergey priv->state = STATE_ACTIVE_TC;
3262a6dc60ffSKozlov Sergey return 0;
3263a6dc60ffSKozlov Sergey }
3264a6dc60ffSKozlov Sergey
cxd2841er_get_frontend(struct dvb_frontend * fe,struct dtv_frontend_properties * p)32657e3e68bcSMauro Carvalho Chehab static int cxd2841er_get_frontend(struct dvb_frontend *fe,
32667e3e68bcSMauro Carvalho Chehab struct dtv_frontend_properties *p)
3267a6dc60ffSKozlov Sergey {
3268a6dc60ffSKozlov Sergey enum fe_status status = 0;
3269a6dc60ffSKozlov Sergey struct cxd2841er_priv *priv = fe->demodulator_priv;
3270a6dc60ffSKozlov Sergey
3271a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3272a6dc60ffSKozlov Sergey if (priv->state == STATE_ACTIVE_S)
3273a6dc60ffSKozlov Sergey cxd2841er_read_status_s(fe, &status);
3274a6dc60ffSKozlov Sergey else if (priv->state == STATE_ACTIVE_TC)
3275a6dc60ffSKozlov Sergey cxd2841er_read_status_tc(fe, &status);
3276a6dc60ffSKozlov Sergey
32778982735fSDaniel Scheller if (priv->state == STATE_ACTIVE_TC || priv->state == STATE_ACTIVE_S)
32785fda1b65SMauro Carvalho Chehab cxd2841er_read_signal_strength(fe);
32798982735fSDaniel Scheller else
32808982735fSDaniel Scheller p->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3281d0e20e13SMauro Carvalho Chehab
3282d0e20e13SMauro Carvalho Chehab if (status & FE_HAS_LOCK) {
3283d9aeaa6dSMauro Carvalho Chehab if (priv->stats_time &&
3284d9aeaa6dSMauro Carvalho Chehab (!time_after(jiffies, priv->stats_time)))
3285d9aeaa6dSMauro Carvalho Chehab return 0;
3286d9aeaa6dSMauro Carvalho Chehab
3287d9aeaa6dSMauro Carvalho Chehab /* Prevent retrieving stats faster than once per second */
3288d9aeaa6dSMauro Carvalho Chehab priv->stats_time = jiffies + msecs_to_jiffies(1000);
3289d9aeaa6dSMauro Carvalho Chehab
3290f1b26622SMauro Carvalho Chehab cxd2841er_read_snr(fe);
3291f1b26622SMauro Carvalho Chehab cxd2841er_read_ucblocks(fe);
3292f1b26622SMauro Carvalho Chehab cxd2841er_read_ber(fe);
3293a6dc60ffSKozlov Sergey } else {
3294a6dc60ffSKozlov Sergey p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3295a6dc60ffSKozlov Sergey p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3296a6dc60ffSKozlov Sergey p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
32974216be14SMauro Carvalho Chehab p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3298a6dc60ffSKozlov Sergey }
3299a6dc60ffSKozlov Sergey return 0;
3300a6dc60ffSKozlov Sergey }
3301a6dc60ffSKozlov Sergey
cxd2841er_set_frontend_s(struct dvb_frontend * fe)3302a6dc60ffSKozlov Sergey static int cxd2841er_set_frontend_s(struct dvb_frontend *fe)
3303a6dc60ffSKozlov Sergey {
3304a6dc60ffSKozlov Sergey int ret = 0, i, timeout, carr_offset;
3305a6dc60ffSKozlov Sergey enum fe_status status;
3306a6dc60ffSKozlov Sergey struct cxd2841er_priv *priv = fe->demodulator_priv;
3307a6dc60ffSKozlov Sergey struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3308a6dc60ffSKozlov Sergey u32 symbol_rate = p->symbol_rate/1000;
3309a6dc60ffSKozlov Sergey
331083808c23SAbylay Ospan dev_dbg(&priv->i2c->dev, "%s(): %s frequency=%d symbol_rate=%d xtal=%d\n",
3311a6dc60ffSKozlov Sergey __func__,
3312a6dc60ffSKozlov Sergey (p->delivery_system == SYS_DVBS ? "DVB-S" : "DVB-S2"),
331383808c23SAbylay Ospan p->frequency, symbol_rate, priv->xtal);
3314763f857eSDaniel Scheller
3315763f857eSDaniel Scheller if (priv->flags & CXD2841ER_EARLY_TUNE)
3316763f857eSDaniel Scheller cxd2841er_tuner_set(fe);
3317763f857eSDaniel Scheller
3318a6dc60ffSKozlov Sergey switch (priv->state) {
3319a6dc60ffSKozlov Sergey case STATE_SLEEP_S:
3320a6dc60ffSKozlov Sergey ret = cxd2841er_sleep_s_to_active_s(
3321a6dc60ffSKozlov Sergey priv, p->delivery_system, symbol_rate);
3322a6dc60ffSKozlov Sergey break;
3323a6dc60ffSKozlov Sergey case STATE_ACTIVE_S:
3324a6dc60ffSKozlov Sergey ret = cxd2841er_retune_active(priv, p);
3325a6dc60ffSKozlov Sergey break;
3326a6dc60ffSKozlov Sergey default:
3327a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
3328a6dc60ffSKozlov Sergey __func__, priv->state);
3329a6dc60ffSKozlov Sergey ret = -EINVAL;
3330a6dc60ffSKozlov Sergey goto done;
3331a6dc60ffSKozlov Sergey }
3332a6dc60ffSKozlov Sergey if (ret) {
3333a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s(): tune failed\n", __func__);
3334a6dc60ffSKozlov Sergey goto done;
3335a6dc60ffSKozlov Sergey }
3336c7518d13SDaniel Scheller
3337763f857eSDaniel Scheller if (!(priv->flags & CXD2841ER_EARLY_TUNE))
3338c7518d13SDaniel Scheller cxd2841er_tuner_set(fe);
3339c7518d13SDaniel Scheller
3340a6dc60ffSKozlov Sergey cxd2841er_tune_done(priv);
33419db0fcdeSZheng Yongjun timeout = DIV_ROUND_UP(3000000, symbol_rate) + 150;
334207ade2d0SMauro Carvalho Chehab
334307ade2d0SMauro Carvalho Chehab i = 0;
334407ade2d0SMauro Carvalho Chehab do {
3345a6dc60ffSKozlov Sergey usleep_range(CXD2841ER_DVBS_POLLING_INVL*1000,
3346a6dc60ffSKozlov Sergey (CXD2841ER_DVBS_POLLING_INVL + 2) * 1000);
3347a6dc60ffSKozlov Sergey cxd2841er_read_status_s(fe, &status);
3348a6dc60ffSKozlov Sergey if (status & FE_HAS_LOCK)
3349a6dc60ffSKozlov Sergey break;
335007ade2d0SMauro Carvalho Chehab i++;
335107ade2d0SMauro Carvalho Chehab } while (i < timeout / CXD2841ER_DVBS_POLLING_INVL);
335207ade2d0SMauro Carvalho Chehab
3353a6dc60ffSKozlov Sergey if (status & FE_HAS_LOCK) {
3354a6dc60ffSKozlov Sergey if (cxd2841er_get_carrier_offset_s_s2(
3355a6dc60ffSKozlov Sergey priv, &carr_offset)) {
3356a6dc60ffSKozlov Sergey ret = -EINVAL;
3357a6dc60ffSKozlov Sergey goto done;
3358a6dc60ffSKozlov Sergey }
3359a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s(): carrier_offset=%d\n",
3360a6dc60ffSKozlov Sergey __func__, carr_offset);
3361a6dc60ffSKozlov Sergey }
3362a6dc60ffSKozlov Sergey done:
3363d0e20e13SMauro Carvalho Chehab /* Reset stats */
3364d0e20e13SMauro Carvalho Chehab p->strength.stat[0].scale = FE_SCALE_RELATIVE;
3365d0e20e13SMauro Carvalho Chehab p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3366d0e20e13SMauro Carvalho Chehab p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3367d0e20e13SMauro Carvalho Chehab p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
33684216be14SMauro Carvalho Chehab p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3369d0e20e13SMauro Carvalho Chehab
3370d9aeaa6dSMauro Carvalho Chehab /* Reset the wait for jiffies logic */
3371d9aeaa6dSMauro Carvalho Chehab priv->stats_time = 0;
3372d9aeaa6dSMauro Carvalho Chehab
3373a6dc60ffSKozlov Sergey return ret;
3374a6dc60ffSKozlov Sergey }
3375a6dc60ffSKozlov Sergey
cxd2841er_set_frontend_tc(struct dvb_frontend * fe)3376a6dc60ffSKozlov Sergey static int cxd2841er_set_frontend_tc(struct dvb_frontend *fe)
3377a6dc60ffSKozlov Sergey {
3378a6dc60ffSKozlov Sergey int ret = 0, timeout;
3379a6dc60ffSKozlov Sergey enum fe_status status;
3380a6dc60ffSKozlov Sergey struct cxd2841er_priv *priv = fe->demodulator_priv;
3381a6dc60ffSKozlov Sergey struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3382a6dc60ffSKozlov Sergey
33833f3b48a0SAbylay Ospan dev_dbg(&priv->i2c->dev, "%s() delivery_system=%d bandwidth_hz=%d\n",
33843f3b48a0SAbylay Ospan __func__, p->delivery_system, p->bandwidth_hz);
3385763f857eSDaniel Scheller
3386763f857eSDaniel Scheller if (priv->flags & CXD2841ER_EARLY_TUNE)
3387763f857eSDaniel Scheller cxd2841er_tuner_set(fe);
3388763f857eSDaniel Scheller
3389bd2355b8SDaniel Scheller /* deconfigure/put demod to sleep on delsys switch if active */
3390bd2355b8SDaniel Scheller if (priv->state == STATE_ACTIVE_TC &&
3391bd2355b8SDaniel Scheller priv->system != p->delivery_system) {
3392bd2355b8SDaniel Scheller dev_dbg(&priv->i2c->dev, "%s(): old_delsys=%d, new_delsys=%d -> sleep\n",
3393bd2355b8SDaniel Scheller __func__, priv->system, p->delivery_system);
3394bd2355b8SDaniel Scheller cxd2841er_sleep_tc(fe);
3395bd2355b8SDaniel Scheller }
3396bd2355b8SDaniel Scheller
3397a6dc60ffSKozlov Sergey if (p->delivery_system == SYS_DVBT) {
3398a6dc60ffSKozlov Sergey priv->system = SYS_DVBT;
3399a6dc60ffSKozlov Sergey switch (priv->state) {
3400a6dc60ffSKozlov Sergey case STATE_SLEEP_TC:
3401a6dc60ffSKozlov Sergey ret = cxd2841er_sleep_tc_to_active_t(
3402a6dc60ffSKozlov Sergey priv, p->bandwidth_hz);
3403a6dc60ffSKozlov Sergey break;
3404a6dc60ffSKozlov Sergey case STATE_ACTIVE_TC:
3405a6dc60ffSKozlov Sergey ret = cxd2841er_retune_active(priv, p);
3406a6dc60ffSKozlov Sergey break;
3407a6dc60ffSKozlov Sergey default:
3408a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
3409a6dc60ffSKozlov Sergey __func__, priv->state);
3410a6dc60ffSKozlov Sergey ret = -EINVAL;
3411a6dc60ffSKozlov Sergey }
3412a6dc60ffSKozlov Sergey } else if (p->delivery_system == SYS_DVBT2) {
3413a6dc60ffSKozlov Sergey priv->system = SYS_DVBT2;
3414a6dc60ffSKozlov Sergey cxd2841er_dvbt2_set_plp_config(priv,
3415a6dc60ffSKozlov Sergey (int)(p->stream_id > 255), p->stream_id);
3416a6dc60ffSKozlov Sergey cxd2841er_dvbt2_set_profile(priv, DVBT2_PROFILE_BASE);
3417a6dc60ffSKozlov Sergey switch (priv->state) {
3418a6dc60ffSKozlov Sergey case STATE_SLEEP_TC:
3419a6dc60ffSKozlov Sergey ret = cxd2841er_sleep_tc_to_active_t2(priv,
3420a6dc60ffSKozlov Sergey p->bandwidth_hz);
3421a6dc60ffSKozlov Sergey break;
3422a6dc60ffSKozlov Sergey case STATE_ACTIVE_TC:
3423a6dc60ffSKozlov Sergey ret = cxd2841er_retune_active(priv, p);
3424a6dc60ffSKozlov Sergey break;
3425a6dc60ffSKozlov Sergey default:
3426a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
3427a6dc60ffSKozlov Sergey __func__, priv->state);
3428a6dc60ffSKozlov Sergey ret = -EINVAL;
3429a6dc60ffSKozlov Sergey }
343083808c23SAbylay Ospan } else if (p->delivery_system == SYS_ISDBT) {
343183808c23SAbylay Ospan priv->system = SYS_ISDBT;
343283808c23SAbylay Ospan switch (priv->state) {
343383808c23SAbylay Ospan case STATE_SLEEP_TC:
343483808c23SAbylay Ospan ret = cxd2841er_sleep_tc_to_active_i(
343583808c23SAbylay Ospan priv, p->bandwidth_hz);
343683808c23SAbylay Ospan break;
343783808c23SAbylay Ospan case STATE_ACTIVE_TC:
343883808c23SAbylay Ospan ret = cxd2841er_retune_active(priv, p);
343983808c23SAbylay Ospan break;
344083808c23SAbylay Ospan default:
344183808c23SAbylay Ospan dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
344283808c23SAbylay Ospan __func__, priv->state);
344383808c23SAbylay Ospan ret = -EINVAL;
344483808c23SAbylay Ospan }
3445a6dc60ffSKozlov Sergey } else if (p->delivery_system == SYS_DVBC_ANNEX_A ||
3446a6dc60ffSKozlov Sergey p->delivery_system == SYS_DVBC_ANNEX_C) {
3447a6dc60ffSKozlov Sergey priv->system = SYS_DVBC_ANNEX_A;
34483f3b48a0SAbylay Ospan /* correct bandwidth */
34493f3b48a0SAbylay Ospan if (p->bandwidth_hz != 6000000 &&
34503f3b48a0SAbylay Ospan p->bandwidth_hz != 7000000 &&
34513f3b48a0SAbylay Ospan p->bandwidth_hz != 8000000) {
34523f3b48a0SAbylay Ospan p->bandwidth_hz = 8000000;
34533f3b48a0SAbylay Ospan dev_dbg(&priv->i2c->dev, "%s(): forcing bandwidth to %d\n",
34543f3b48a0SAbylay Ospan __func__, p->bandwidth_hz);
34553f3b48a0SAbylay Ospan }
34563f3b48a0SAbylay Ospan
3457a6dc60ffSKozlov Sergey switch (priv->state) {
3458a6dc60ffSKozlov Sergey case STATE_SLEEP_TC:
3459a6dc60ffSKozlov Sergey ret = cxd2841er_sleep_tc_to_active_c(
3460a6dc60ffSKozlov Sergey priv, p->bandwidth_hz);
3461a6dc60ffSKozlov Sergey break;
3462a6dc60ffSKozlov Sergey case STATE_ACTIVE_TC:
3463a6dc60ffSKozlov Sergey ret = cxd2841er_retune_active(priv, p);
3464a6dc60ffSKozlov Sergey break;
3465a6dc60ffSKozlov Sergey default:
3466a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
3467a6dc60ffSKozlov Sergey __func__, priv->state);
3468a6dc60ffSKozlov Sergey ret = -EINVAL;
3469a6dc60ffSKozlov Sergey }
3470a6dc60ffSKozlov Sergey } else {
3471a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev,
3472a6dc60ffSKozlov Sergey "%s(): invalid delivery system %d\n",
3473a6dc60ffSKozlov Sergey __func__, p->delivery_system);
3474a6dc60ffSKozlov Sergey ret = -EINVAL;
3475a6dc60ffSKozlov Sergey }
3476a6dc60ffSKozlov Sergey if (ret)
3477a6dc60ffSKozlov Sergey goto done;
3478c7518d13SDaniel Scheller
3479763f857eSDaniel Scheller if (!(priv->flags & CXD2841ER_EARLY_TUNE))
3480c7518d13SDaniel Scheller cxd2841er_tuner_set(fe);
3481c7518d13SDaniel Scheller
3482a6dc60ffSKozlov Sergey cxd2841er_tune_done(priv);
3483e3943aa6SDaniel Scheller
3484e3943aa6SDaniel Scheller if (priv->flags & CXD2841ER_NO_WAIT_LOCK)
3485e3943aa6SDaniel Scheller goto done;
3486e3943aa6SDaniel Scheller
3487a6dc60ffSKozlov Sergey timeout = 2500;
3488a6dc60ffSKozlov Sergey while (timeout > 0) {
3489a6dc60ffSKozlov Sergey ret = cxd2841er_read_status_tc(fe, &status);
3490a6dc60ffSKozlov Sergey if (ret)
3491a6dc60ffSKozlov Sergey goto done;
3492a6dc60ffSKozlov Sergey if (status & FE_HAS_LOCK)
3493a6dc60ffSKozlov Sergey break;
3494a6dc60ffSKozlov Sergey msleep(20);
3495a6dc60ffSKozlov Sergey timeout -= 20;
3496a6dc60ffSKozlov Sergey }
3497a6dc60ffSKozlov Sergey if (timeout < 0)
3498a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev,
3499a6dc60ffSKozlov Sergey "%s(): LOCK wait timeout\n", __func__);
3500a6dc60ffSKozlov Sergey done:
3501a6dc60ffSKozlov Sergey return ret;
3502a6dc60ffSKozlov Sergey }
3503a6dc60ffSKozlov Sergey
cxd2841er_tune_s(struct dvb_frontend * fe,bool re_tune,unsigned int mode_flags,unsigned int * delay,enum fe_status * status)3504a6dc60ffSKozlov Sergey static int cxd2841er_tune_s(struct dvb_frontend *fe,
3505a6dc60ffSKozlov Sergey bool re_tune,
3506a6dc60ffSKozlov Sergey unsigned int mode_flags,
3507a6dc60ffSKozlov Sergey unsigned int *delay,
3508a6dc60ffSKozlov Sergey enum fe_status *status)
3509a6dc60ffSKozlov Sergey {
3510a6dc60ffSKozlov Sergey int ret, carrier_offset;
3511a6dc60ffSKozlov Sergey struct cxd2841er_priv *priv = fe->demodulator_priv;
3512a6dc60ffSKozlov Sergey struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3513a6dc60ffSKozlov Sergey
3514a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s() re_tune=%d\n", __func__, re_tune);
3515a6dc60ffSKozlov Sergey if (re_tune) {
3516a6dc60ffSKozlov Sergey ret = cxd2841er_set_frontend_s(fe);
3517a6dc60ffSKozlov Sergey if (ret)
3518a6dc60ffSKozlov Sergey return ret;
3519a6dc60ffSKozlov Sergey cxd2841er_read_status_s(fe, status);
3520a6dc60ffSKozlov Sergey if (*status & FE_HAS_LOCK) {
3521a6dc60ffSKozlov Sergey if (cxd2841er_get_carrier_offset_s_s2(
3522a6dc60ffSKozlov Sergey priv, &carrier_offset))
3523a6dc60ffSKozlov Sergey return -EINVAL;
3524a6dc60ffSKozlov Sergey p->frequency += carrier_offset;
3525a6dc60ffSKozlov Sergey ret = cxd2841er_set_frontend_s(fe);
3526a6dc60ffSKozlov Sergey if (ret)
3527a6dc60ffSKozlov Sergey return ret;
3528a6dc60ffSKozlov Sergey }
3529a6dc60ffSKozlov Sergey }
3530a6dc60ffSKozlov Sergey *delay = HZ / 5;
3531a6dc60ffSKozlov Sergey return cxd2841er_read_status_s(fe, status);
3532a6dc60ffSKozlov Sergey }
3533a6dc60ffSKozlov Sergey
cxd2841er_tune_tc(struct dvb_frontend * fe,bool re_tune,unsigned int mode_flags,unsigned int * delay,enum fe_status * status)3534a6dc60ffSKozlov Sergey static int cxd2841er_tune_tc(struct dvb_frontend *fe,
3535a6dc60ffSKozlov Sergey bool re_tune,
3536a6dc60ffSKozlov Sergey unsigned int mode_flags,
3537a6dc60ffSKozlov Sergey unsigned int *delay,
3538a6dc60ffSKozlov Sergey enum fe_status *status)
3539a6dc60ffSKozlov Sergey {
3540a6dc60ffSKozlov Sergey int ret, carrier_offset;
3541a6dc60ffSKozlov Sergey struct cxd2841er_priv *priv = fe->demodulator_priv;
3542a6dc60ffSKozlov Sergey struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3543a6dc60ffSKozlov Sergey
35443f3b48a0SAbylay Ospan dev_dbg(&priv->i2c->dev, "%s(): re_tune %d bandwidth=%d\n", __func__,
35453f3b48a0SAbylay Ospan re_tune, p->bandwidth_hz);
3546a6dc60ffSKozlov Sergey if (re_tune) {
3547a6dc60ffSKozlov Sergey ret = cxd2841er_set_frontend_tc(fe);
3548a6dc60ffSKozlov Sergey if (ret)
3549a6dc60ffSKozlov Sergey return ret;
3550a6dc60ffSKozlov Sergey cxd2841er_read_status_tc(fe, status);
3551a6dc60ffSKozlov Sergey if (*status & FE_HAS_LOCK) {
3552a6dc60ffSKozlov Sergey switch (priv->system) {
355376344a3fSMauro Carvalho Chehab case SYS_ISDBT:
355476344a3fSMauro Carvalho Chehab ret = cxd2841er_get_carrier_offset_i(
355576344a3fSMauro Carvalho Chehab priv, p->bandwidth_hz,
355676344a3fSMauro Carvalho Chehab &carrier_offset);
3557bb9bd878SArnd Bergmann if (ret)
3558bb9bd878SArnd Bergmann return ret;
355976344a3fSMauro Carvalho Chehab break;
3560a6dc60ffSKozlov Sergey case SYS_DVBT:
3561c5ea46daSAbylay Ospan ret = cxd2841er_get_carrier_offset_t(
3562c5ea46daSAbylay Ospan priv, p->bandwidth_hz,
3563c5ea46daSAbylay Ospan &carrier_offset);
3564bb9bd878SArnd Bergmann if (ret)
3565bb9bd878SArnd Bergmann return ret;
3566c5ea46daSAbylay Ospan break;
3567a6dc60ffSKozlov Sergey case SYS_DVBT2:
3568a6dc60ffSKozlov Sergey ret = cxd2841er_get_carrier_offset_t2(
3569a6dc60ffSKozlov Sergey priv, p->bandwidth_hz,
3570a6dc60ffSKozlov Sergey &carrier_offset);
3571bb9bd878SArnd Bergmann if (ret)
3572bb9bd878SArnd Bergmann return ret;
3573a6dc60ffSKozlov Sergey break;
3574a6dc60ffSKozlov Sergey case SYS_DVBC_ANNEX_A:
3575a6dc60ffSKozlov Sergey ret = cxd2841er_get_carrier_offset_c(
3576a6dc60ffSKozlov Sergey priv, &carrier_offset);
3577bb9bd878SArnd Bergmann if (ret)
3578bb9bd878SArnd Bergmann return ret;
3579a6dc60ffSKozlov Sergey break;
3580a6dc60ffSKozlov Sergey default:
3581a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev,
3582a6dc60ffSKozlov Sergey "%s(): invalid delivery system %d\n",
3583a6dc60ffSKozlov Sergey __func__, priv->system);
3584a6dc60ffSKozlov Sergey return -EINVAL;
3585a6dc60ffSKozlov Sergey }
3586a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s(): carrier offset %d\n",
3587a6dc60ffSKozlov Sergey __func__, carrier_offset);
3588a6dc60ffSKozlov Sergey p->frequency += carrier_offset;
3589a6dc60ffSKozlov Sergey ret = cxd2841er_set_frontend_tc(fe);
3590a6dc60ffSKozlov Sergey if (ret)
3591a6dc60ffSKozlov Sergey return ret;
3592a6dc60ffSKozlov Sergey }
3593a6dc60ffSKozlov Sergey }
3594a6dc60ffSKozlov Sergey *delay = HZ / 5;
3595a6dc60ffSKozlov Sergey return cxd2841er_read_status_tc(fe, status);
3596a6dc60ffSKozlov Sergey }
3597a6dc60ffSKozlov Sergey
cxd2841er_sleep_s(struct dvb_frontend * fe)3598a6dc60ffSKozlov Sergey static int cxd2841er_sleep_s(struct dvb_frontend *fe)
3599a6dc60ffSKozlov Sergey {
3600a6dc60ffSKozlov Sergey struct cxd2841er_priv *priv = fe->demodulator_priv;
3601a6dc60ffSKozlov Sergey
3602a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3603a6dc60ffSKozlov Sergey cxd2841er_active_s_to_sleep_s(fe->demodulator_priv);
3604a6dc60ffSKozlov Sergey cxd2841er_sleep_s_to_shutdown(fe->demodulator_priv);
3605a6dc60ffSKozlov Sergey return 0;
3606a6dc60ffSKozlov Sergey }
3607a6dc60ffSKozlov Sergey
cxd2841er_sleep_tc(struct dvb_frontend * fe)3608a6dc60ffSKozlov Sergey static int cxd2841er_sleep_tc(struct dvb_frontend *fe)
3609a6dc60ffSKozlov Sergey {
3610a6dc60ffSKozlov Sergey struct cxd2841er_priv *priv = fe->demodulator_priv;
3611a6dc60ffSKozlov Sergey
3612a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3613bd2355b8SDaniel Scheller
3614a6dc60ffSKozlov Sergey if (priv->state == STATE_ACTIVE_TC) {
3615a6dc60ffSKozlov Sergey switch (priv->system) {
3616a6dc60ffSKozlov Sergey case SYS_DVBT:
3617a6dc60ffSKozlov Sergey cxd2841er_active_t_to_sleep_tc(priv);
3618a6dc60ffSKozlov Sergey break;
3619a6dc60ffSKozlov Sergey case SYS_DVBT2:
3620a6dc60ffSKozlov Sergey cxd2841er_active_t2_to_sleep_tc(priv);
3621a6dc60ffSKozlov Sergey break;
362283808c23SAbylay Ospan case SYS_ISDBT:
362383808c23SAbylay Ospan cxd2841er_active_i_to_sleep_tc(priv);
362483808c23SAbylay Ospan break;
3625a6dc60ffSKozlov Sergey case SYS_DVBC_ANNEX_A:
3626a6dc60ffSKozlov Sergey cxd2841er_active_c_to_sleep_tc(priv);
3627a6dc60ffSKozlov Sergey break;
3628a6dc60ffSKozlov Sergey default:
3629a6dc60ffSKozlov Sergey dev_warn(&priv->i2c->dev,
3630a6dc60ffSKozlov Sergey "%s(): unknown delivery system %d\n",
3631a6dc60ffSKozlov Sergey __func__, priv->system);
3632a6dc60ffSKozlov Sergey }
3633a6dc60ffSKozlov Sergey }
3634a6dc60ffSKozlov Sergey if (priv->state != STATE_SLEEP_TC) {
3635a6dc60ffSKozlov Sergey dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
3636a6dc60ffSKozlov Sergey __func__, priv->state);
3637a6dc60ffSKozlov Sergey return -EINVAL;
3638a6dc60ffSKozlov Sergey }
3639bd2355b8SDaniel Scheller return 0;
3640bd2355b8SDaniel Scheller }
3641bd2355b8SDaniel Scheller
cxd2841er_shutdown_tc(struct dvb_frontend * fe)3642bd2355b8SDaniel Scheller static int cxd2841er_shutdown_tc(struct dvb_frontend *fe)
3643bd2355b8SDaniel Scheller {
3644bd2355b8SDaniel Scheller struct cxd2841er_priv *priv = fe->demodulator_priv;
3645bd2355b8SDaniel Scheller
3646bd2355b8SDaniel Scheller dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3647bd2355b8SDaniel Scheller
3648bd2355b8SDaniel Scheller if (!cxd2841er_sleep_tc(fe))
3649a6dc60ffSKozlov Sergey cxd2841er_sleep_tc_to_shutdown(priv);
3650a6dc60ffSKozlov Sergey return 0;
3651a6dc60ffSKozlov Sergey }
3652a6dc60ffSKozlov Sergey
cxd2841er_send_burst(struct dvb_frontend * fe,enum fe_sec_mini_cmd burst)3653a6dc60ffSKozlov Sergey static int cxd2841er_send_burst(struct dvb_frontend *fe,
3654a6dc60ffSKozlov Sergey enum fe_sec_mini_cmd burst)
3655a6dc60ffSKozlov Sergey {
3656a6dc60ffSKozlov Sergey u8 data;
3657a6dc60ffSKozlov Sergey struct cxd2841er_priv *priv = fe->demodulator_priv;
3658a6dc60ffSKozlov Sergey
3659a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s(): burst mode %s\n", __func__,
3660a6dc60ffSKozlov Sergey (burst == SEC_MINI_A ? "A" : "B"));
3661a6dc60ffSKozlov Sergey if (priv->state != STATE_SLEEP_S &&
3662a6dc60ffSKozlov Sergey priv->state != STATE_ACTIVE_S) {
3663a6dc60ffSKozlov Sergey dev_err(&priv->i2c->dev, "%s(): invalid demod state %d\n",
3664a6dc60ffSKozlov Sergey __func__, priv->state);
3665a6dc60ffSKozlov Sergey return -EINVAL;
3666a6dc60ffSKozlov Sergey }
3667a6dc60ffSKozlov Sergey data = (burst == SEC_MINI_A ? 0 : 1);
3668a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xbb);
3669a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x34, 0x01);
3670a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x35, data);
3671a6dc60ffSKozlov Sergey return 0;
3672a6dc60ffSKozlov Sergey }
3673a6dc60ffSKozlov Sergey
cxd2841er_set_tone(struct dvb_frontend * fe,enum fe_sec_tone_mode tone)3674a6dc60ffSKozlov Sergey static int cxd2841er_set_tone(struct dvb_frontend *fe,
3675a6dc60ffSKozlov Sergey enum fe_sec_tone_mode tone)
3676a6dc60ffSKozlov Sergey {
3677a6dc60ffSKozlov Sergey u8 data;
3678a6dc60ffSKozlov Sergey struct cxd2841er_priv *priv = fe->demodulator_priv;
3679a6dc60ffSKozlov Sergey
3680a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s(): tone %s\n", __func__,
3681a6dc60ffSKozlov Sergey (tone == SEC_TONE_ON ? "On" : "Off"));
3682a6dc60ffSKozlov Sergey if (priv->state != STATE_SLEEP_S &&
3683a6dc60ffSKozlov Sergey priv->state != STATE_ACTIVE_S) {
3684a6dc60ffSKozlov Sergey dev_err(&priv->i2c->dev, "%s(): invalid demod state %d\n",
3685a6dc60ffSKozlov Sergey __func__, priv->state);
3686a6dc60ffSKozlov Sergey return -EINVAL;
3687a6dc60ffSKozlov Sergey }
3688a6dc60ffSKozlov Sergey data = (tone == SEC_TONE_ON ? 1 : 0);
3689a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xbb);
3690a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x36, data);
3691a6dc60ffSKozlov Sergey return 0;
3692a6dc60ffSKozlov Sergey }
3693a6dc60ffSKozlov Sergey
cxd2841er_send_diseqc_msg(struct dvb_frontend * fe,struct dvb_diseqc_master_cmd * cmd)3694a6dc60ffSKozlov Sergey static int cxd2841er_send_diseqc_msg(struct dvb_frontend *fe,
3695a6dc60ffSKozlov Sergey struct dvb_diseqc_master_cmd *cmd)
3696a6dc60ffSKozlov Sergey {
3697a6dc60ffSKozlov Sergey int i;
3698a6dc60ffSKozlov Sergey u8 data[12];
3699a6dc60ffSKozlov Sergey struct cxd2841er_priv *priv = fe->demodulator_priv;
3700a6dc60ffSKozlov Sergey
3701a6dc60ffSKozlov Sergey if (priv->state != STATE_SLEEP_S &&
3702a6dc60ffSKozlov Sergey priv->state != STATE_ACTIVE_S) {
3703a6dc60ffSKozlov Sergey dev_err(&priv->i2c->dev, "%s(): invalid demod state %d\n",
3704a6dc60ffSKozlov Sergey __func__, priv->state);
3705a6dc60ffSKozlov Sergey return -EINVAL;
3706a6dc60ffSKozlov Sergey }
3707a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev,
3708a6dc60ffSKozlov Sergey "%s(): cmd->len %d\n", __func__, cmd->msg_len);
3709a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xbb);
3710a6dc60ffSKozlov Sergey /* DiDEqC enable */
3711a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x33, 0x01);
3712a6dc60ffSKozlov Sergey /* cmd1 length & data */
3713a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x3d, cmd->msg_len);
3714a6dc60ffSKozlov Sergey memset(data, 0, sizeof(data));
3715a6dc60ffSKozlov Sergey for (i = 0; i < cmd->msg_len && i < sizeof(data); i++)
3716a6dc60ffSKozlov Sergey data[i] = cmd->msg[i];
3717a6dc60ffSKozlov Sergey cxd2841er_write_regs(priv, I2C_SLVT, 0x3e, data, sizeof(data));
3718a6dc60ffSKozlov Sergey /* repeat count for cmd1 */
3719a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x37, 1);
3720a6dc60ffSKozlov Sergey /* repeat count for cmd2: always 0 */
3721a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x38, 0);
3722a6dc60ffSKozlov Sergey /* start transmit */
3723a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x32, 0x01);
3724a6dc60ffSKozlov Sergey /* wait for 1 sec timeout */
3725a6dc60ffSKozlov Sergey for (i = 0; i < 50; i++) {
3726a6dc60ffSKozlov Sergey cxd2841er_read_reg(priv, I2C_SLVT, 0x10, data);
3727a6dc60ffSKozlov Sergey if (!data[0]) {
3728a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev,
3729a6dc60ffSKozlov Sergey "%s(): DiSEqC cmd has been sent\n", __func__);
3730a6dc60ffSKozlov Sergey return 0;
3731a6dc60ffSKozlov Sergey }
3732a6dc60ffSKozlov Sergey msleep(20);
3733a6dc60ffSKozlov Sergey }
3734a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev,
3735a6dc60ffSKozlov Sergey "%s(): DiSEqC cmd transmit timeout\n", __func__);
3736a6dc60ffSKozlov Sergey return -ETIMEDOUT;
3737a6dc60ffSKozlov Sergey }
3738a6dc60ffSKozlov Sergey
cxd2841er_release(struct dvb_frontend * fe)3739a6dc60ffSKozlov Sergey static void cxd2841er_release(struct dvb_frontend *fe)
3740a6dc60ffSKozlov Sergey {
3741a6dc60ffSKozlov Sergey struct cxd2841er_priv *priv = fe->demodulator_priv;
3742a6dc60ffSKozlov Sergey
3743a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3744a6dc60ffSKozlov Sergey kfree(priv);
3745a6dc60ffSKozlov Sergey }
3746a6dc60ffSKozlov Sergey
cxd2841er_i2c_gate_ctrl(struct dvb_frontend * fe,int enable)3747a6dc60ffSKozlov Sergey static int cxd2841er_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
3748a6dc60ffSKozlov Sergey {
3749a6dc60ffSKozlov Sergey struct cxd2841er_priv *priv = fe->demodulator_priv;
3750a6dc60ffSKozlov Sergey
3751a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s(): enable=%d\n", __func__, enable);
3752a6dc60ffSKozlov Sergey cxd2841er_set_reg_bits(
3753a6dc60ffSKozlov Sergey priv, I2C_SLVX, 0x8, (enable ? 0x01 : 0x00), 0x01);
3754a6dc60ffSKozlov Sergey return 0;
3755a6dc60ffSKozlov Sergey }
3756a6dc60ffSKozlov Sergey
cxd2841er_get_algo(struct dvb_frontend * fe)3757a6dc60ffSKozlov Sergey static enum dvbfe_algo cxd2841er_get_algo(struct dvb_frontend *fe)
3758a6dc60ffSKozlov Sergey {
3759a6dc60ffSKozlov Sergey struct cxd2841er_priv *priv = fe->demodulator_priv;
3760a6dc60ffSKozlov Sergey
3761a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3762a6dc60ffSKozlov Sergey return DVBFE_ALGO_HW;
3763a6dc60ffSKozlov Sergey }
3764a6dc60ffSKozlov Sergey
cxd2841er_init_stats(struct dvb_frontend * fe)3765d0e20e13SMauro Carvalho Chehab static void cxd2841er_init_stats(struct dvb_frontend *fe)
3766d0e20e13SMauro Carvalho Chehab {
3767d0e20e13SMauro Carvalho Chehab struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3768d0e20e13SMauro Carvalho Chehab
3769d0e20e13SMauro Carvalho Chehab p->strength.len = 1;
3770d0e20e13SMauro Carvalho Chehab p->strength.stat[0].scale = FE_SCALE_RELATIVE;
3771d0e20e13SMauro Carvalho Chehab p->cnr.len = 1;
3772d0e20e13SMauro Carvalho Chehab p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3773d0e20e13SMauro Carvalho Chehab p->block_error.len = 1;
3774d0e20e13SMauro Carvalho Chehab p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3775d0e20e13SMauro Carvalho Chehab p->post_bit_error.len = 1;
3776d0e20e13SMauro Carvalho Chehab p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
37774216be14SMauro Carvalho Chehab p->post_bit_count.len = 1;
37784216be14SMauro Carvalho Chehab p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3779d0e20e13SMauro Carvalho Chehab }
3780d0e20e13SMauro Carvalho Chehab
3781d0e20e13SMauro Carvalho Chehab
cxd2841er_init_s(struct dvb_frontend * fe)3782a6dc60ffSKozlov Sergey static int cxd2841er_init_s(struct dvb_frontend *fe)
3783a6dc60ffSKozlov Sergey {
3784a6dc60ffSKozlov Sergey struct cxd2841er_priv *priv = fe->demodulator_priv;
3785a6dc60ffSKozlov Sergey
378630ae3307SAbylay Ospan /* sanity. force demod to SHUTDOWN state */
378730ae3307SAbylay Ospan if (priv->state == STATE_SLEEP_S) {
378830ae3307SAbylay Ospan dev_dbg(&priv->i2c->dev, "%s() forcing sleep->shutdown\n",
378930ae3307SAbylay Ospan __func__);
379030ae3307SAbylay Ospan cxd2841er_sleep_s_to_shutdown(priv);
379130ae3307SAbylay Ospan } else if (priv->state == STATE_ACTIVE_S) {
379230ae3307SAbylay Ospan dev_dbg(&priv->i2c->dev, "%s() forcing active->sleep->shutdown\n",
379330ae3307SAbylay Ospan __func__);
379430ae3307SAbylay Ospan cxd2841er_active_s_to_sleep_s(priv);
379530ae3307SAbylay Ospan cxd2841er_sleep_s_to_shutdown(priv);
379630ae3307SAbylay Ospan }
379730ae3307SAbylay Ospan
3798a6dc60ffSKozlov Sergey dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3799a6dc60ffSKozlov Sergey cxd2841er_shutdown_to_sleep_s(priv);
3800a6dc60ffSKozlov Sergey /* SONY_DEMOD_CONFIG_SAT_IFAGCNEG set to 1 */
3801a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
3802a6dc60ffSKozlov Sergey cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xb9, 0x01, 0x01);
3803d0e20e13SMauro Carvalho Chehab
3804d0e20e13SMauro Carvalho Chehab cxd2841er_init_stats(fe);
3805d0e20e13SMauro Carvalho Chehab
3806a6dc60ffSKozlov Sergey return 0;
3807a6dc60ffSKozlov Sergey }
3808a6dc60ffSKozlov Sergey
cxd2841er_init_tc(struct dvb_frontend * fe)3809a6dc60ffSKozlov Sergey static int cxd2841er_init_tc(struct dvb_frontend *fe)
3810a6dc60ffSKozlov Sergey {
3811a6dc60ffSKozlov Sergey struct cxd2841er_priv *priv = fe->demodulator_priv;
38123f3b48a0SAbylay Ospan struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3813a6dc60ffSKozlov Sergey
38143f3b48a0SAbylay Ospan dev_dbg(&priv->i2c->dev, "%s() bandwidth_hz=%d\n",
38153f3b48a0SAbylay Ospan __func__, p->bandwidth_hz);
3816a6dc60ffSKozlov Sergey cxd2841er_shutdown_to_sleep_tc(priv);
381714fd8629SDaniel Scheller /* SONY_DEMOD_CONFIG_IFAGCNEG = 1 (0 for NO_AGCNEG */
3818a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
381914fd8629SDaniel Scheller cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcb,
382014fd8629SDaniel Scheller ((priv->flags & CXD2841ER_NO_AGCNEG) ? 0x00 : 0x40), 0x40);
3821a6dc60ffSKozlov Sergey /* SONY_DEMOD_CONFIG_IFAGC_ADC_FS = 0 */
3822a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0xcd, 0x50);
3823a6dc60ffSKozlov Sergey /* SONY_DEMOD_CONFIG_PARALLEL_SEL = 1 */
3824a6dc60ffSKozlov Sergey cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
382503ab1bd5SDaniel Scheller cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xc4,
382603ab1bd5SDaniel Scheller ((priv->flags & CXD2841ER_TS_SERIAL) ? 0x80 : 0x00), 0x80);
3827d0e20e13SMauro Carvalho Chehab
3828bf51bbb0SDaniel Scheller /* clear TSCFG bits 3+4 */
3829bf51bbb0SDaniel Scheller if (priv->flags & CXD2841ER_TSBITS)
3830bf51bbb0SDaniel Scheller cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xc4, 0x00, 0x18);
3831bf51bbb0SDaniel Scheller
3832d0e20e13SMauro Carvalho Chehab cxd2841er_init_stats(fe);
3833d0e20e13SMauro Carvalho Chehab
3834a6dc60ffSKozlov Sergey return 0;
3835a6dc60ffSKozlov Sergey }
3836a6dc60ffSKozlov Sergey
3837bd336e63SMax Kellermann static const struct dvb_frontend_ops cxd2841er_dvbs_s2_ops;
38383f3b48a0SAbylay Ospan static struct dvb_frontend_ops cxd2841er_t_c_ops;
3839a6dc60ffSKozlov Sergey
cxd2841er_attach(struct cxd2841er_config * cfg,struct i2c_adapter * i2c,u8 system)3840a6dc60ffSKozlov Sergey static struct dvb_frontend *cxd2841er_attach(struct cxd2841er_config *cfg,
3841a6dc60ffSKozlov Sergey struct i2c_adapter *i2c,
3842a6dc60ffSKozlov Sergey u8 system)
3843a6dc60ffSKozlov Sergey {
3844a6dc60ffSKozlov Sergey u8 chip_id = 0;
3845a6dc60ffSKozlov Sergey const char *type;
38463f3b48a0SAbylay Ospan const char *name;
3847a6dc60ffSKozlov Sergey struct cxd2841er_priv *priv = NULL;
3848a6dc60ffSKozlov Sergey
3849a6dc60ffSKozlov Sergey /* allocate memory for the internal state */
3850a6dc60ffSKozlov Sergey priv = kzalloc(sizeof(struct cxd2841er_priv), GFP_KERNEL);
3851a6dc60ffSKozlov Sergey if (!priv)
3852a6dc60ffSKozlov Sergey return NULL;
3853a6dc60ffSKozlov Sergey priv->i2c = i2c;
3854a6dc60ffSKozlov Sergey priv->config = cfg;
3855a6dc60ffSKozlov Sergey priv->i2c_addr_slvx = (cfg->i2c_addr + 4) >> 1;
3856a6dc60ffSKozlov Sergey priv->i2c_addr_slvt = (cfg->i2c_addr) >> 1;
385783808c23SAbylay Ospan priv->xtal = cfg->xtal;
3858050863aaSDaniel Scheller priv->flags = cfg->flags;
3859a6dc60ffSKozlov Sergey priv->frontend.demodulator_priv = priv;
3860a6dc60ffSKozlov Sergey dev_info(&priv->i2c->dev,
3861a6dc60ffSKozlov Sergey "%s(): I2C adapter %p SLVX addr %x SLVT addr %x\n",
3862a6dc60ffSKozlov Sergey __func__, priv->i2c,
3863a6dc60ffSKozlov Sergey priv->i2c_addr_slvx, priv->i2c_addr_slvt);
3864a6dc60ffSKozlov Sergey chip_id = cxd2841er_chip_id(priv);
38653f3b48a0SAbylay Ospan switch (chip_id) {
38661ecda28cSDaniel Scheller case CXD2837ER_CHIP_ID:
38671ecda28cSDaniel Scheller snprintf(cxd2841er_t_c_ops.info.name, 128,
38681ecda28cSDaniel Scheller "Sony CXD2837ER DVB-T/T2/C demodulator");
38691ecda28cSDaniel Scheller name = "CXD2837ER";
38701ecda28cSDaniel Scheller type = "C/T/T2";
38711ecda28cSDaniel Scheller break;
38721ecda28cSDaniel Scheller case CXD2838ER_CHIP_ID:
38731ecda28cSDaniel Scheller snprintf(cxd2841er_t_c_ops.info.name, 128,
38741ecda28cSDaniel Scheller "Sony CXD2838ER ISDB-T demodulator");
38751ecda28cSDaniel Scheller cxd2841er_t_c_ops.delsys[0] = SYS_ISDBT;
38761ecda28cSDaniel Scheller cxd2841er_t_c_ops.delsys[1] = SYS_UNDEFINED;
38771ecda28cSDaniel Scheller cxd2841er_t_c_ops.delsys[2] = SYS_UNDEFINED;
38781ecda28cSDaniel Scheller name = "CXD2838ER";
38791ecda28cSDaniel Scheller type = "ISDB-T";
38801ecda28cSDaniel Scheller break;
38813f3b48a0SAbylay Ospan case CXD2841ER_CHIP_ID:
38823f3b48a0SAbylay Ospan snprintf(cxd2841er_t_c_ops.info.name, 128,
38833f3b48a0SAbylay Ospan "Sony CXD2841ER DVB-T/T2/C demodulator");
38843f3b48a0SAbylay Ospan name = "CXD2841ER";
38851ecda28cSDaniel Scheller type = "T/T2/C/ISDB-T";
38861ecda28cSDaniel Scheller break;
38871ecda28cSDaniel Scheller case CXD2843ER_CHIP_ID:
38881ecda28cSDaniel Scheller snprintf(cxd2841er_t_c_ops.info.name, 128,
38891ecda28cSDaniel Scheller "Sony CXD2843ER DVB-T/T2/C/C2 demodulator");
38901ecda28cSDaniel Scheller name = "CXD2843ER";
38911ecda28cSDaniel Scheller type = "C/C2/T/T2";
38923f3b48a0SAbylay Ospan break;
38933f3b48a0SAbylay Ospan case CXD2854ER_CHIP_ID:
38943f3b48a0SAbylay Ospan snprintf(cxd2841er_t_c_ops.info.name, 128,
38953f3b48a0SAbylay Ospan "Sony CXD2854ER DVB-T/T2/C and ISDB-T demodulator");
38963f3b48a0SAbylay Ospan cxd2841er_t_c_ops.delsys[3] = SYS_ISDBT;
38973f3b48a0SAbylay Ospan name = "CXD2854ER";
38981ecda28cSDaniel Scheller type = "C/C2/T/T2/ISDB-T";
38993f3b48a0SAbylay Ospan break;
39003f3b48a0SAbylay Ospan default:
3901a6dc60ffSKozlov Sergey dev_err(&priv->i2c->dev, "%s(): invalid chip ID 0x%02x\n",
3902a6dc60ffSKozlov Sergey __func__, chip_id);
3903a6dc60ffSKozlov Sergey priv->frontend.demodulator_priv = NULL;
3904a6dc60ffSKozlov Sergey kfree(priv);
3905a6dc60ffSKozlov Sergey return NULL;
3906a6dc60ffSKozlov Sergey }
39073f3b48a0SAbylay Ospan
39083f3b48a0SAbylay Ospan /* create dvb_frontend */
39093f3b48a0SAbylay Ospan if (system == SYS_DVBS) {
39103f3b48a0SAbylay Ospan memcpy(&priv->frontend.ops,
39113f3b48a0SAbylay Ospan &cxd2841er_dvbs_s2_ops,
39123f3b48a0SAbylay Ospan sizeof(struct dvb_frontend_ops));
39133f3b48a0SAbylay Ospan type = "S/S2";
39143f3b48a0SAbylay Ospan } else {
39153f3b48a0SAbylay Ospan memcpy(&priv->frontend.ops,
39163f3b48a0SAbylay Ospan &cxd2841er_t_c_ops,
39173f3b48a0SAbylay Ospan sizeof(struct dvb_frontend_ops));
39183f3b48a0SAbylay Ospan }
39193f3b48a0SAbylay Ospan
39203f3b48a0SAbylay Ospan dev_info(&priv->i2c->dev,
39213f3b48a0SAbylay Ospan "%s(): attaching %s DVB-%s frontend\n",
39223f3b48a0SAbylay Ospan __func__, name, type);
3923a6dc60ffSKozlov Sergey dev_info(&priv->i2c->dev, "%s(): chip ID 0x%02x OK.\n",
3924a6dc60ffSKozlov Sergey __func__, chip_id);
3925a6dc60ffSKozlov Sergey return &priv->frontend;
3926a6dc60ffSKozlov Sergey }
3927a6dc60ffSKozlov Sergey
cxd2841er_attach_s(struct cxd2841er_config * cfg,struct i2c_adapter * i2c)3928a6dc60ffSKozlov Sergey struct dvb_frontend *cxd2841er_attach_s(struct cxd2841er_config *cfg,
3929a6dc60ffSKozlov Sergey struct i2c_adapter *i2c)
3930a6dc60ffSKozlov Sergey {
3931a6dc60ffSKozlov Sergey return cxd2841er_attach(cfg, i2c, SYS_DVBS);
3932a6dc60ffSKozlov Sergey }
3933*86495af1SGreg Kroah-Hartman EXPORT_SYMBOL_GPL(cxd2841er_attach_s);
3934a6dc60ffSKozlov Sergey
cxd2841er_attach_t_c(struct cxd2841er_config * cfg,struct i2c_adapter * i2c)39353f3b48a0SAbylay Ospan struct dvb_frontend *cxd2841er_attach_t_c(struct cxd2841er_config *cfg,
3936a6dc60ffSKozlov Sergey struct i2c_adapter *i2c)
3937a6dc60ffSKozlov Sergey {
39383f3b48a0SAbylay Ospan return cxd2841er_attach(cfg, i2c, 0);
3939a6dc60ffSKozlov Sergey }
3940*86495af1SGreg Kroah-Hartman EXPORT_SYMBOL_GPL(cxd2841er_attach_t_c);
3941a6dc60ffSKozlov Sergey
3942bd336e63SMax Kellermann static const struct dvb_frontend_ops cxd2841er_dvbs_s2_ops = {
3943a6dc60ffSKozlov Sergey .delsys = { SYS_DVBS, SYS_DVBS2 },
3944a6dc60ffSKozlov Sergey .info = {
3945a6dc60ffSKozlov Sergey .name = "Sony CXD2841ER DVB-S/S2 demodulator",
3946f1b1eabfSMauro Carvalho Chehab .frequency_min_hz = 500 * MHz,
3947f1b1eabfSMauro Carvalho Chehab .frequency_max_hz = 2500 * MHz,
3948a6dc60ffSKozlov Sergey .symbol_rate_min = 1000000,
3949a6dc60ffSKozlov Sergey .symbol_rate_max = 45000000,
3950a6dc60ffSKozlov Sergey .symbol_rate_tolerance = 500,
3951a6dc60ffSKozlov Sergey .caps = FE_CAN_INVERSION_AUTO |
3952a6dc60ffSKozlov Sergey FE_CAN_FEC_AUTO |
3953a6dc60ffSKozlov Sergey FE_CAN_QPSK,
3954a6dc60ffSKozlov Sergey },
3955a6dc60ffSKozlov Sergey .init = cxd2841er_init_s,
3956a6dc60ffSKozlov Sergey .sleep = cxd2841er_sleep_s,
3957a6dc60ffSKozlov Sergey .release = cxd2841er_release,
3958a6dc60ffSKozlov Sergey .set_frontend = cxd2841er_set_frontend_s,
3959a6dc60ffSKozlov Sergey .get_frontend = cxd2841er_get_frontend,
3960a6dc60ffSKozlov Sergey .read_status = cxd2841er_read_status_s,
3961a6dc60ffSKozlov Sergey .i2c_gate_ctrl = cxd2841er_i2c_gate_ctrl,
3962a6dc60ffSKozlov Sergey .get_frontend_algo = cxd2841er_get_algo,
3963a6dc60ffSKozlov Sergey .set_tone = cxd2841er_set_tone,
3964a6dc60ffSKozlov Sergey .diseqc_send_burst = cxd2841er_send_burst,
3965a6dc60ffSKozlov Sergey .diseqc_send_master_cmd = cxd2841er_send_diseqc_msg,
3966a6dc60ffSKozlov Sergey .tune = cxd2841er_tune_s
3967a6dc60ffSKozlov Sergey };
3968a6dc60ffSKozlov Sergey
39693f3b48a0SAbylay Ospan static struct dvb_frontend_ops cxd2841er_t_c_ops = {
39703f3b48a0SAbylay Ospan .delsys = { SYS_DVBT, SYS_DVBT2, SYS_DVBC_ANNEX_A },
3971a6dc60ffSKozlov Sergey .info = {
39723f3b48a0SAbylay Ospan .name = "", /* will set in attach function */
3973a6dc60ffSKozlov Sergey .caps = FE_CAN_FEC_1_2 |
3974a6dc60ffSKozlov Sergey FE_CAN_FEC_2_3 |
3975a6dc60ffSKozlov Sergey FE_CAN_FEC_3_4 |
3976a6dc60ffSKozlov Sergey FE_CAN_FEC_5_6 |
3977a6dc60ffSKozlov Sergey FE_CAN_FEC_7_8 |
3978a6dc60ffSKozlov Sergey FE_CAN_FEC_AUTO |
3979a6dc60ffSKozlov Sergey FE_CAN_QPSK |
3980a6dc60ffSKozlov Sergey FE_CAN_QAM_16 |
3981a6dc60ffSKozlov Sergey FE_CAN_QAM_32 |
3982a6dc60ffSKozlov Sergey FE_CAN_QAM_64 |
3983a6dc60ffSKozlov Sergey FE_CAN_QAM_128 |
3984a6dc60ffSKozlov Sergey FE_CAN_QAM_256 |
3985a6dc60ffSKozlov Sergey FE_CAN_QAM_AUTO |
3986a6dc60ffSKozlov Sergey FE_CAN_TRANSMISSION_MODE_AUTO |
3987a6dc60ffSKozlov Sergey FE_CAN_GUARD_INTERVAL_AUTO |
3988a6dc60ffSKozlov Sergey FE_CAN_HIERARCHY_AUTO |
3989a6dc60ffSKozlov Sergey FE_CAN_MUTE_TS |
3990a6dc60ffSKozlov Sergey FE_CAN_2G_MODULATION,
3991f1b1eabfSMauro Carvalho Chehab .frequency_min_hz = 42 * MHz,
3992f1b1eabfSMauro Carvalho Chehab .frequency_max_hz = 1002 * MHz,
3993158f0328SDaniel Scheller .symbol_rate_min = 870000,
3994158f0328SDaniel Scheller .symbol_rate_max = 11700000
3995a6dc60ffSKozlov Sergey },
3996a6dc60ffSKozlov Sergey .init = cxd2841er_init_tc,
3997bd2355b8SDaniel Scheller .sleep = cxd2841er_shutdown_tc,
3998a6dc60ffSKozlov Sergey .release = cxd2841er_release,
3999a6dc60ffSKozlov Sergey .set_frontend = cxd2841er_set_frontend_tc,
4000a6dc60ffSKozlov Sergey .get_frontend = cxd2841er_get_frontend,
4001a6dc60ffSKozlov Sergey .read_status = cxd2841er_read_status_tc,
4002a6dc60ffSKozlov Sergey .tune = cxd2841er_tune_tc,
4003a6dc60ffSKozlov Sergey .i2c_gate_ctrl = cxd2841er_i2c_gate_ctrl,
4004a6dc60ffSKozlov Sergey .get_frontend_algo = cxd2841er_get_algo
4005a6dc60ffSKozlov Sergey };
4006a6dc60ffSKozlov Sergey
4007381a28beSDaniel Scheller MODULE_DESCRIPTION("Sony CXD2837/38/41/43/54ER DVB-C/C2/T/T2/S/S2 demodulator driver");
400883808c23SAbylay Ospan MODULE_AUTHOR("Sergey Kozlov <serjk@netup.ru>, Abylay Ospan <aospan@netup.ru>");
4009a6dc60ffSKozlov Sergey MODULE_LICENSE("GPL");
4010