1 /* 2 * Conexant cx24123/cx24109 - DVB QPSK Satellite demod/tuner driver 3 * 4 * Copyright (C) 2005 Steven Toth <stoth@linuxtv.org> 5 * 6 * Support for KWorld DVB-S 100 by Vadim Catana <skystar@moldova.cc> 7 * 8 * Support for CX24123/CX24113-NIM by Patrick Boettcher <pb@linuxtv.org> 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 18 * General Public License for more details. 19 */ 20 21 #include <linux/slab.h> 22 #include <linux/kernel.h> 23 #include <linux/module.h> 24 #include <linux/init.h> 25 #include <asm/div64.h> 26 27 #include "dvb_frontend.h" 28 #include "cx24123.h" 29 30 #define XTAL 10111000 31 32 static int force_band; 33 module_param(force_band, int, 0644); 34 MODULE_PARM_DESC(force_band, "Force a specific band select "\ 35 "(1-9, default:off)."); 36 37 static int debug; 38 module_param(debug, int, 0644); 39 MODULE_PARM_DESC(debug, "Activates frontend debugging (default:0)"); 40 41 #define info(args...) do { printk(KERN_INFO "CX24123: " args); } while (0) 42 #define err(args...) do { printk(KERN_ERR "CX24123: " args); } while (0) 43 44 #define dprintk(args...) \ 45 do { \ 46 if (debug) { \ 47 printk(KERN_DEBUG "CX24123: %s: ", __func__); \ 48 printk(args); \ 49 } \ 50 } while (0) 51 52 struct cx24123_state { 53 struct i2c_adapter *i2c; 54 const struct cx24123_config *config; 55 56 struct dvb_frontend frontend; 57 58 /* Some PLL specifics for tuning */ 59 u32 VCAarg; 60 u32 VGAarg; 61 u32 bandselectarg; 62 u32 pllarg; 63 u32 FILTune; 64 65 struct i2c_adapter tuner_i2c_adapter; 66 67 u8 demod_rev; 68 69 /* The Demod/Tuner can't easily provide these, we cache them */ 70 u32 currentfreq; 71 u32 currentsymbolrate; 72 }; 73 74 /* Various tuner defaults need to be established for a given symbol rate Sps */ 75 static struct cx24123_AGC_val { 76 u32 symbolrate_low; 77 u32 symbolrate_high; 78 u32 VCAprogdata; 79 u32 VGAprogdata; 80 u32 FILTune; 81 } cx24123_AGC_vals[] = 82 { 83 { 84 .symbolrate_low = 1000000, 85 .symbolrate_high = 4999999, 86 /* the specs recommend other values for VGA offsets, 87 but tests show they are wrong */ 88 .VGAprogdata = (1 << 19) | (0x180 << 9) | 0x1e0, 89 .VCAprogdata = (2 << 19) | (0x07 << 9) | 0x07, 90 .FILTune = 0x27f /* 0.41 V */ 91 }, 92 { 93 .symbolrate_low = 5000000, 94 .symbolrate_high = 14999999, 95 .VGAprogdata = (1 << 19) | (0x180 << 9) | 0x1e0, 96 .VCAprogdata = (2 << 19) | (0x07 << 9) | 0x1f, 97 .FILTune = 0x317 /* 0.90 V */ 98 }, 99 { 100 .symbolrate_low = 15000000, 101 .symbolrate_high = 45000000, 102 .VGAprogdata = (1 << 19) | (0x100 << 9) | 0x180, 103 .VCAprogdata = (2 << 19) | (0x07 << 9) | 0x3f, 104 .FILTune = 0x145 /* 2.70 V */ 105 }, 106 }; 107 108 /* 109 * Various tuner defaults need to be established for a given frequency kHz. 110 * fixme: The bounds on the bands do not match the doc in real life. 111 * fixme: Some of them have been moved, other might need adjustment. 112 */ 113 static struct cx24123_bandselect_val { 114 u32 freq_low; 115 u32 freq_high; 116 u32 VCOdivider; 117 u32 progdata; 118 } cx24123_bandselect_vals[] = 119 { 120 /* band 1 */ 121 { 122 .freq_low = 950000, 123 .freq_high = 1074999, 124 .VCOdivider = 4, 125 .progdata = (0 << 19) | (0 << 9) | 0x40, 126 }, 127 128 /* band 2 */ 129 { 130 .freq_low = 1075000, 131 .freq_high = 1177999, 132 .VCOdivider = 4, 133 .progdata = (0 << 19) | (0 << 9) | 0x80, 134 }, 135 136 /* band 3 */ 137 { 138 .freq_low = 1178000, 139 .freq_high = 1295999, 140 .VCOdivider = 2, 141 .progdata = (0 << 19) | (1 << 9) | 0x01, 142 }, 143 144 /* band 4 */ 145 { 146 .freq_low = 1296000, 147 .freq_high = 1431999, 148 .VCOdivider = 2, 149 .progdata = (0 << 19) | (1 << 9) | 0x02, 150 }, 151 152 /* band 5 */ 153 { 154 .freq_low = 1432000, 155 .freq_high = 1575999, 156 .VCOdivider = 2, 157 .progdata = (0 << 19) | (1 << 9) | 0x04, 158 }, 159 160 /* band 6 */ 161 { 162 .freq_low = 1576000, 163 .freq_high = 1717999, 164 .VCOdivider = 2, 165 .progdata = (0 << 19) | (1 << 9) | 0x08, 166 }, 167 168 /* band 7 */ 169 { 170 .freq_low = 1718000, 171 .freq_high = 1855999, 172 .VCOdivider = 2, 173 .progdata = (0 << 19) | (1 << 9) | 0x10, 174 }, 175 176 /* band 8 */ 177 { 178 .freq_low = 1856000, 179 .freq_high = 2035999, 180 .VCOdivider = 2, 181 .progdata = (0 << 19) | (1 << 9) | 0x20, 182 }, 183 184 /* band 9 */ 185 { 186 .freq_low = 2036000, 187 .freq_high = 2150000, 188 .VCOdivider = 2, 189 .progdata = (0 << 19) | (1 << 9) | 0x40, 190 }, 191 }; 192 193 static struct { 194 u8 reg; 195 u8 data; 196 } cx24123_regdata[] = 197 { 198 {0x00, 0x03}, /* Reset system */ 199 {0x00, 0x00}, /* Clear reset */ 200 {0x03, 0x07}, /* QPSK, DVB, Auto Acquisition (default) */ 201 {0x04, 0x10}, /* MPEG */ 202 {0x05, 0x04}, /* MPEG */ 203 {0x06, 0x31}, /* MPEG (default) */ 204 {0x0b, 0x00}, /* Freq search start point (default) */ 205 {0x0c, 0x00}, /* Demodulator sample gain (default) */ 206 {0x0d, 0x7f}, /* Force driver to shift until the maximum (+-10 MHz) */ 207 {0x0e, 0x03}, /* Default non-inverted, FEC 3/4 (default) */ 208 {0x0f, 0xfe}, /* FEC search mask (all supported codes) */ 209 {0x10, 0x01}, /* Default search inversion, no repeat (default) */ 210 {0x16, 0x00}, /* Enable reading of frequency */ 211 {0x17, 0x01}, /* Enable EsNO Ready Counter */ 212 {0x1c, 0x80}, /* Enable error counter */ 213 {0x20, 0x00}, /* Tuner burst clock rate = 500KHz */ 214 {0x21, 0x15}, /* Tuner burst mode, word length = 0x15 */ 215 {0x28, 0x00}, /* Enable FILTERV with positive pol., DiSEqC 2.x off */ 216 {0x29, 0x00}, /* DiSEqC LNB_DC off */ 217 {0x2a, 0xb0}, /* DiSEqC Parameters (default) */ 218 {0x2b, 0x73}, /* DiSEqC Tone Frequency (default) */ 219 {0x2c, 0x00}, /* DiSEqC Message (0x2c - 0x31) */ 220 {0x2d, 0x00}, 221 {0x2e, 0x00}, 222 {0x2f, 0x00}, 223 {0x30, 0x00}, 224 {0x31, 0x00}, 225 {0x32, 0x8c}, /* DiSEqC Parameters (default) */ 226 {0x33, 0x00}, /* Interrupts off (0x33 - 0x34) */ 227 {0x34, 0x00}, 228 {0x35, 0x03}, /* DiSEqC Tone Amplitude (default) */ 229 {0x36, 0x02}, /* DiSEqC Parameters (default) */ 230 {0x37, 0x3a}, /* DiSEqC Parameters (default) */ 231 {0x3a, 0x00}, /* Enable AGC accumulator (for signal strength) */ 232 {0x44, 0x00}, /* Constellation (default) */ 233 {0x45, 0x00}, /* Symbol count (default) */ 234 {0x46, 0x0d}, /* Symbol rate estimator on (default) */ 235 {0x56, 0xc1}, /* Error Counter = Viterbi BER */ 236 {0x57, 0xff}, /* Error Counter Window (default) */ 237 {0x5c, 0x20}, /* Acquisition AFC Expiration window (default is 0x10) */ 238 {0x67, 0x83}, /* Non-DCII symbol clock */ 239 }; 240 241 static int cx24123_i2c_writereg(struct cx24123_state *state, 242 u8 i2c_addr, int reg, int data) 243 { 244 u8 buf[] = { reg, data }; 245 struct i2c_msg msg = { 246 .addr = i2c_addr, .flags = 0, .buf = buf, .len = 2 247 }; 248 int err; 249 250 /* printk(KERN_DEBUG "wr(%02x): %02x %02x\n", i2c_addr, reg, data); */ 251 252 err = i2c_transfer(state->i2c, &msg, 1); 253 if (err != 1) { 254 printk("%s: writereg error(err == %i, reg == 0x%02x, data == 0x%02x)\n", 255 __func__, err, reg, data); 256 return err; 257 } 258 259 return 0; 260 } 261 262 static int cx24123_i2c_readreg(struct cx24123_state *state, u8 i2c_addr, u8 reg) 263 { 264 int ret; 265 u8 b = 0; 266 struct i2c_msg msg[] = { 267 { .addr = i2c_addr, .flags = 0, .buf = ®, .len = 1 }, 268 { .addr = i2c_addr, .flags = I2C_M_RD, .buf = &b, .len = 1 } 269 }; 270 271 ret = i2c_transfer(state->i2c, msg, 2); 272 273 if (ret != 2) { 274 err("%s: reg=0x%x (error=%d)\n", __func__, reg, ret); 275 return ret; 276 } 277 278 /* printk(KERN_DEBUG "rd(%02x): %02x %02x\n", i2c_addr, reg, b); */ 279 280 return b; 281 } 282 283 #define cx24123_readreg(state, reg) \ 284 cx24123_i2c_readreg(state, state->config->demod_address, reg) 285 #define cx24123_writereg(state, reg, val) \ 286 cx24123_i2c_writereg(state, state->config->demod_address, reg, val) 287 288 static int cx24123_set_inversion(struct cx24123_state *state, 289 enum fe_spectral_inversion inversion) 290 { 291 u8 nom_reg = cx24123_readreg(state, 0x0e); 292 u8 auto_reg = cx24123_readreg(state, 0x10); 293 294 switch (inversion) { 295 case INVERSION_OFF: 296 dprintk("inversion off\n"); 297 cx24123_writereg(state, 0x0e, nom_reg & ~0x80); 298 cx24123_writereg(state, 0x10, auto_reg | 0x80); 299 break; 300 case INVERSION_ON: 301 dprintk("inversion on\n"); 302 cx24123_writereg(state, 0x0e, nom_reg | 0x80); 303 cx24123_writereg(state, 0x10, auto_reg | 0x80); 304 break; 305 case INVERSION_AUTO: 306 dprintk("inversion auto\n"); 307 cx24123_writereg(state, 0x10, auto_reg & ~0x80); 308 break; 309 default: 310 return -EINVAL; 311 } 312 313 return 0; 314 } 315 316 static int cx24123_get_inversion(struct cx24123_state *state, 317 enum fe_spectral_inversion *inversion) 318 { 319 u8 val; 320 321 val = cx24123_readreg(state, 0x1b) >> 7; 322 323 if (val == 0) { 324 dprintk("read inversion off\n"); 325 *inversion = INVERSION_OFF; 326 } else { 327 dprintk("read inversion on\n"); 328 *inversion = INVERSION_ON; 329 } 330 331 return 0; 332 } 333 334 static int cx24123_set_fec(struct cx24123_state *state, enum fe_code_rate fec) 335 { 336 u8 nom_reg = cx24123_readreg(state, 0x0e) & ~0x07; 337 338 if (((int)fec < FEC_NONE) || (fec > FEC_AUTO)) 339 fec = FEC_AUTO; 340 341 /* Set the soft decision threshold */ 342 if (fec == FEC_1_2) 343 cx24123_writereg(state, 0x43, 344 cx24123_readreg(state, 0x43) | 0x01); 345 else 346 cx24123_writereg(state, 0x43, 347 cx24123_readreg(state, 0x43) & ~0x01); 348 349 switch (fec) { 350 case FEC_1_2: 351 dprintk("set FEC to 1/2\n"); 352 cx24123_writereg(state, 0x0e, nom_reg | 0x01); 353 cx24123_writereg(state, 0x0f, 0x02); 354 break; 355 case FEC_2_3: 356 dprintk("set FEC to 2/3\n"); 357 cx24123_writereg(state, 0x0e, nom_reg | 0x02); 358 cx24123_writereg(state, 0x0f, 0x04); 359 break; 360 case FEC_3_4: 361 dprintk("set FEC to 3/4\n"); 362 cx24123_writereg(state, 0x0e, nom_reg | 0x03); 363 cx24123_writereg(state, 0x0f, 0x08); 364 break; 365 case FEC_4_5: 366 dprintk("set FEC to 4/5\n"); 367 cx24123_writereg(state, 0x0e, nom_reg | 0x04); 368 cx24123_writereg(state, 0x0f, 0x10); 369 break; 370 case FEC_5_6: 371 dprintk("set FEC to 5/6\n"); 372 cx24123_writereg(state, 0x0e, nom_reg | 0x05); 373 cx24123_writereg(state, 0x0f, 0x20); 374 break; 375 case FEC_6_7: 376 dprintk("set FEC to 6/7\n"); 377 cx24123_writereg(state, 0x0e, nom_reg | 0x06); 378 cx24123_writereg(state, 0x0f, 0x40); 379 break; 380 case FEC_7_8: 381 dprintk("set FEC to 7/8\n"); 382 cx24123_writereg(state, 0x0e, nom_reg | 0x07); 383 cx24123_writereg(state, 0x0f, 0x80); 384 break; 385 case FEC_AUTO: 386 dprintk("set FEC to auto\n"); 387 cx24123_writereg(state, 0x0f, 0xfe); 388 break; 389 default: 390 return -EOPNOTSUPP; 391 } 392 393 return 0; 394 } 395 396 static int cx24123_get_fec(struct cx24123_state *state, enum fe_code_rate *fec) 397 { 398 int ret; 399 400 ret = cx24123_readreg(state, 0x1b); 401 if (ret < 0) 402 return ret; 403 ret = ret & 0x07; 404 405 switch (ret) { 406 case 1: 407 *fec = FEC_1_2; 408 break; 409 case 2: 410 *fec = FEC_2_3; 411 break; 412 case 3: 413 *fec = FEC_3_4; 414 break; 415 case 4: 416 *fec = FEC_4_5; 417 break; 418 case 5: 419 *fec = FEC_5_6; 420 break; 421 case 6: 422 *fec = FEC_6_7; 423 break; 424 case 7: 425 *fec = FEC_7_8; 426 break; 427 default: 428 /* this can happen when there's no lock */ 429 *fec = FEC_NONE; 430 } 431 432 return 0; 433 } 434 435 /* Approximation of closest integer of log2(a/b). It actually gives the 436 lowest integer i such that 2^i >= round(a/b) */ 437 static u32 cx24123_int_log2(u32 a, u32 b) 438 { 439 u32 exp, nearest = 0; 440 u32 div = a / b; 441 if (a % b >= b / 2) 442 ++div; 443 if (div < (1 << 31)) { 444 for (exp = 1; div > exp; nearest++) 445 exp += exp; 446 } 447 return nearest; 448 } 449 450 static int cx24123_set_symbolrate(struct cx24123_state *state, u32 srate) 451 { 452 u64 tmp; 453 u32 sample_rate, ratio, sample_gain; 454 u8 pll_mult; 455 456 /* check if symbol rate is within limits */ 457 if ((srate > state->frontend.ops.info.symbol_rate_max) || 458 (srate < state->frontend.ops.info.symbol_rate_min)) 459 return -EOPNOTSUPP; 460 461 /* choose the sampling rate high enough for the required operation, 462 while optimizing the power consumed by the demodulator */ 463 if (srate < (XTAL*2)/2) 464 pll_mult = 2; 465 else if (srate < (XTAL*3)/2) 466 pll_mult = 3; 467 else if (srate < (XTAL*4)/2) 468 pll_mult = 4; 469 else if (srate < (XTAL*5)/2) 470 pll_mult = 5; 471 else if (srate < (XTAL*6)/2) 472 pll_mult = 6; 473 else if (srate < (XTAL*7)/2) 474 pll_mult = 7; 475 else if (srate < (XTAL*8)/2) 476 pll_mult = 8; 477 else 478 pll_mult = 9; 479 480 481 sample_rate = pll_mult * XTAL; 482 483 /* SYSSymbolRate[21:0] = (srate << 23) / sample_rate */ 484 485 tmp = ((u64)srate) << 23; 486 do_div(tmp, sample_rate); 487 ratio = (u32) tmp; 488 489 cx24123_writereg(state, 0x01, pll_mult * 6); 490 491 cx24123_writereg(state, 0x08, (ratio >> 16) & 0x3f); 492 cx24123_writereg(state, 0x09, (ratio >> 8) & 0xff); 493 cx24123_writereg(state, 0x0a, ratio & 0xff); 494 495 /* also set the demodulator sample gain */ 496 sample_gain = cx24123_int_log2(sample_rate, srate); 497 tmp = cx24123_readreg(state, 0x0c) & ~0xe0; 498 cx24123_writereg(state, 0x0c, tmp | sample_gain << 5); 499 500 dprintk("srate=%d, ratio=0x%08x, sample_rate=%i sample_gain=%d\n", 501 srate, ratio, sample_rate, sample_gain); 502 503 return 0; 504 } 505 506 /* 507 * Based on the required frequency and symbolrate, the tuner AGC has 508 * to be configured and the correct band selected. 509 * Calculate those values. 510 */ 511 static int cx24123_pll_calculate(struct dvb_frontend *fe) 512 { 513 struct dtv_frontend_properties *p = &fe->dtv_property_cache; 514 struct cx24123_state *state = fe->demodulator_priv; 515 u32 ndiv = 0, adiv = 0, vco_div = 0; 516 int i = 0; 517 int pump = 2; 518 int band = 0; 519 int num_bands = ARRAY_SIZE(cx24123_bandselect_vals); 520 struct cx24123_bandselect_val *bsv = NULL; 521 struct cx24123_AGC_val *agcv = NULL; 522 523 /* Defaults for low freq, low rate */ 524 state->VCAarg = cx24123_AGC_vals[0].VCAprogdata; 525 state->VGAarg = cx24123_AGC_vals[0].VGAprogdata; 526 state->bandselectarg = cx24123_bandselect_vals[0].progdata; 527 vco_div = cx24123_bandselect_vals[0].VCOdivider; 528 529 /* For the given symbol rate, determine the VCA, VGA and 530 * FILTUNE programming bits */ 531 for (i = 0; i < ARRAY_SIZE(cx24123_AGC_vals); i++) { 532 agcv = &cx24123_AGC_vals[i]; 533 if ((agcv->symbolrate_low <= p->symbol_rate) && 534 (agcv->symbolrate_high >= p->symbol_rate)) { 535 state->VCAarg = agcv->VCAprogdata; 536 state->VGAarg = agcv->VGAprogdata; 537 state->FILTune = agcv->FILTune; 538 } 539 } 540 541 /* determine the band to use */ 542 if (force_band < 1 || force_band > num_bands) { 543 for (i = 0; i < num_bands; i++) { 544 bsv = &cx24123_bandselect_vals[i]; 545 if ((bsv->freq_low <= p->frequency) && 546 (bsv->freq_high >= p->frequency)) 547 band = i; 548 } 549 } else 550 band = force_band - 1; 551 552 state->bandselectarg = cx24123_bandselect_vals[band].progdata; 553 vco_div = cx24123_bandselect_vals[band].VCOdivider; 554 555 /* determine the charge pump current */ 556 if (p->frequency < (cx24123_bandselect_vals[band].freq_low + 557 cx24123_bandselect_vals[band].freq_high) / 2) 558 pump = 0x01; 559 else 560 pump = 0x02; 561 562 /* Determine the N/A dividers for the requested lband freq (in kHz). */ 563 /* Note: the reference divider R=10, frequency is in KHz, 564 * XTAL is in Hz */ 565 ndiv = (((p->frequency * vco_div * 10) / 566 (2 * XTAL / 1000)) / 32) & 0x1ff; 567 adiv = (((p->frequency * vco_div * 10) / 568 (2 * XTAL / 1000)) % 32) & 0x1f; 569 570 if (adiv == 0 && ndiv > 0) 571 ndiv--; 572 573 /* control bits 11, refdiv 11, charge pump polarity 1, 574 * charge pump current, ndiv, adiv */ 575 state->pllarg = (3 << 19) | (3 << 17) | (1 << 16) | 576 (pump << 14) | (ndiv << 5) | adiv; 577 578 return 0; 579 } 580 581 /* 582 * Tuner data is 21 bits long, must be left-aligned in data. 583 * Tuner cx24109 is written through a dedicated 3wire interface 584 * on the demod chip. 585 */ 586 static int cx24123_pll_writereg(struct dvb_frontend *fe, u32 data) 587 { 588 struct cx24123_state *state = fe->demodulator_priv; 589 unsigned long timeout; 590 591 dprintk("pll writereg called, data=0x%08x\n", data); 592 593 /* align the 21 bytes into to bit23 boundary */ 594 data = data << 3; 595 596 /* Reset the demod pll word length to 0x15 bits */ 597 cx24123_writereg(state, 0x21, 0x15); 598 599 /* write the msb 8 bits, wait for the send to be completed */ 600 timeout = jiffies + msecs_to_jiffies(40); 601 cx24123_writereg(state, 0x22, (data >> 16) & 0xff); 602 while ((cx24123_readreg(state, 0x20) & 0x40) == 0) { 603 if (time_after(jiffies, timeout)) { 604 err("%s: demodulator is not responding, "\ 605 "possibly hung, aborting.\n", __func__); 606 return -EREMOTEIO; 607 } 608 msleep(10); 609 } 610 611 /* send another 8 bytes, wait for the send to be completed */ 612 timeout = jiffies + msecs_to_jiffies(40); 613 cx24123_writereg(state, 0x22, (data >> 8) & 0xff); 614 while ((cx24123_readreg(state, 0x20) & 0x40) == 0) { 615 if (time_after(jiffies, timeout)) { 616 err("%s: demodulator is not responding, "\ 617 "possibly hung, aborting.\n", __func__); 618 return -EREMOTEIO; 619 } 620 msleep(10); 621 } 622 623 /* send the lower 5 bits of this byte, padded with 3 LBB, 624 * wait for the send to be completed */ 625 timeout = jiffies + msecs_to_jiffies(40); 626 cx24123_writereg(state, 0x22, (data) & 0xff); 627 while ((cx24123_readreg(state, 0x20) & 0x80)) { 628 if (time_after(jiffies, timeout)) { 629 err("%s: demodulator is not responding," \ 630 "possibly hung, aborting.\n", __func__); 631 return -EREMOTEIO; 632 } 633 msleep(10); 634 } 635 636 /* Trigger the demod to configure the tuner */ 637 cx24123_writereg(state, 0x20, cx24123_readreg(state, 0x20) | 2); 638 cx24123_writereg(state, 0x20, cx24123_readreg(state, 0x20) & 0xfd); 639 640 return 0; 641 } 642 643 static int cx24123_pll_tune(struct dvb_frontend *fe) 644 { 645 struct dtv_frontend_properties *p = &fe->dtv_property_cache; 646 struct cx24123_state *state = fe->demodulator_priv; 647 u8 val; 648 649 dprintk("frequency=%i\n", p->frequency); 650 651 if (cx24123_pll_calculate(fe) != 0) { 652 err("%s: cx24123_pll_calculate failed\n", __func__); 653 return -EINVAL; 654 } 655 656 /* Write the new VCO/VGA */ 657 cx24123_pll_writereg(fe, state->VCAarg); 658 cx24123_pll_writereg(fe, state->VGAarg); 659 660 /* Write the new bandselect and pll args */ 661 cx24123_pll_writereg(fe, state->bandselectarg); 662 cx24123_pll_writereg(fe, state->pllarg); 663 664 /* set the FILTUNE voltage */ 665 val = cx24123_readreg(state, 0x28) & ~0x3; 666 cx24123_writereg(state, 0x27, state->FILTune >> 2); 667 cx24123_writereg(state, 0x28, val | (state->FILTune & 0x3)); 668 669 dprintk("pll tune VCA=%d, band=%d, pll=%d\n", state->VCAarg, 670 state->bandselectarg, state->pllarg); 671 672 return 0; 673 } 674 675 676 /* 677 * 0x23: 678 * [7:7] = BTI enabled 679 * [6:6] = I2C repeater enabled 680 * [5:5] = I2C repeater start 681 * [0:0] = BTI start 682 */ 683 684 /* mode == 1 -> i2c-repeater, 0 -> bti */ 685 static int cx24123_repeater_mode(struct cx24123_state *state, u8 mode, u8 start) 686 { 687 u8 r = cx24123_readreg(state, 0x23) & 0x1e; 688 if (mode) 689 r |= (1 << 6) | (start << 5); 690 else 691 r |= (1 << 7) | (start); 692 return cx24123_writereg(state, 0x23, r); 693 } 694 695 static int cx24123_initfe(struct dvb_frontend *fe) 696 { 697 struct cx24123_state *state = fe->demodulator_priv; 698 int i; 699 700 dprintk("init frontend\n"); 701 702 /* Configure the demod to a good set of defaults */ 703 for (i = 0; i < ARRAY_SIZE(cx24123_regdata); i++) 704 cx24123_writereg(state, cx24123_regdata[i].reg, 705 cx24123_regdata[i].data); 706 707 /* Set the LNB polarity */ 708 if (state->config->lnb_polarity) 709 cx24123_writereg(state, 0x32, 710 cx24123_readreg(state, 0x32) | 0x02); 711 712 if (state->config->dont_use_pll) 713 cx24123_repeater_mode(state, 1, 0); 714 715 return 0; 716 } 717 718 static int cx24123_set_voltage(struct dvb_frontend *fe, 719 enum fe_sec_voltage voltage) 720 { 721 struct cx24123_state *state = fe->demodulator_priv; 722 u8 val; 723 724 val = cx24123_readreg(state, 0x29) & ~0x40; 725 726 switch (voltage) { 727 case SEC_VOLTAGE_13: 728 dprintk("setting voltage 13V\n"); 729 return cx24123_writereg(state, 0x29, val & 0x7f); 730 case SEC_VOLTAGE_18: 731 dprintk("setting voltage 18V\n"); 732 return cx24123_writereg(state, 0x29, val | 0x80); 733 case SEC_VOLTAGE_OFF: 734 /* already handled in cx88-dvb */ 735 return 0; 736 default: 737 return -EINVAL; 738 } 739 740 return 0; 741 } 742 743 /* wait for diseqc queue to become ready (or timeout) */ 744 static void cx24123_wait_for_diseqc(struct cx24123_state *state) 745 { 746 unsigned long timeout = jiffies + msecs_to_jiffies(200); 747 while (!(cx24123_readreg(state, 0x29) & 0x40)) { 748 if (time_after(jiffies, timeout)) { 749 err("%s: diseqc queue not ready, " \ 750 "command may be lost.\n", __func__); 751 break; 752 } 753 msleep(10); 754 } 755 } 756 757 static int cx24123_send_diseqc_msg(struct dvb_frontend *fe, 758 struct dvb_diseqc_master_cmd *cmd) 759 { 760 struct cx24123_state *state = fe->demodulator_priv; 761 int i, val, tone; 762 763 dprintk("\n"); 764 765 /* stop continuous tone if enabled */ 766 tone = cx24123_readreg(state, 0x29); 767 if (tone & 0x10) 768 cx24123_writereg(state, 0x29, tone & ~0x50); 769 770 /* wait for diseqc queue ready */ 771 cx24123_wait_for_diseqc(state); 772 773 /* select tone mode */ 774 cx24123_writereg(state, 0x2a, cx24123_readreg(state, 0x2a) & 0xfb); 775 776 for (i = 0; i < cmd->msg_len; i++) 777 cx24123_writereg(state, 0x2C + i, cmd->msg[i]); 778 779 val = cx24123_readreg(state, 0x29); 780 cx24123_writereg(state, 0x29, ((val & 0x90) | 0x40) | 781 ((cmd->msg_len-3) & 3)); 782 783 /* wait for diseqc message to finish sending */ 784 cx24123_wait_for_diseqc(state); 785 786 /* restart continuous tone if enabled */ 787 if (tone & 0x10) 788 cx24123_writereg(state, 0x29, tone & ~0x40); 789 790 return 0; 791 } 792 793 static int cx24123_diseqc_send_burst(struct dvb_frontend *fe, 794 enum fe_sec_mini_cmd burst) 795 { 796 struct cx24123_state *state = fe->demodulator_priv; 797 int val, tone; 798 799 dprintk("\n"); 800 801 /* stop continuous tone if enabled */ 802 tone = cx24123_readreg(state, 0x29); 803 if (tone & 0x10) 804 cx24123_writereg(state, 0x29, tone & ~0x50); 805 806 /* wait for diseqc queue ready */ 807 cx24123_wait_for_diseqc(state); 808 809 /* select tone mode */ 810 cx24123_writereg(state, 0x2a, cx24123_readreg(state, 0x2a) | 0x4); 811 msleep(30); 812 val = cx24123_readreg(state, 0x29); 813 if (burst == SEC_MINI_A) 814 cx24123_writereg(state, 0x29, ((val & 0x90) | 0x40 | 0x00)); 815 else if (burst == SEC_MINI_B) 816 cx24123_writereg(state, 0x29, ((val & 0x90) | 0x40 | 0x08)); 817 else 818 return -EINVAL; 819 820 cx24123_wait_for_diseqc(state); 821 cx24123_writereg(state, 0x2a, cx24123_readreg(state, 0x2a) & 0xfb); 822 823 /* restart continuous tone if enabled */ 824 if (tone & 0x10) 825 cx24123_writereg(state, 0x29, tone & ~0x40); 826 827 return 0; 828 } 829 830 static int cx24123_read_status(struct dvb_frontend *fe, enum fe_status *status) 831 { 832 struct cx24123_state *state = fe->demodulator_priv; 833 int sync = cx24123_readreg(state, 0x14); 834 835 *status = 0; 836 if (state->config->dont_use_pll) { 837 u32 tun_status = 0; 838 if (fe->ops.tuner_ops.get_status) 839 fe->ops.tuner_ops.get_status(fe, &tun_status); 840 if (tun_status & TUNER_STATUS_LOCKED) 841 *status |= FE_HAS_SIGNAL; 842 } else { 843 int lock = cx24123_readreg(state, 0x20); 844 if (lock & 0x01) 845 *status |= FE_HAS_SIGNAL; 846 } 847 848 if (sync & 0x02) 849 *status |= FE_HAS_CARRIER; /* Phase locked */ 850 if (sync & 0x04) 851 *status |= FE_HAS_VITERBI; 852 853 /* Reed-Solomon Status */ 854 if (sync & 0x08) 855 *status |= FE_HAS_SYNC; 856 if (sync & 0x80) 857 *status |= FE_HAS_LOCK; /*Full Sync */ 858 859 return 0; 860 } 861 862 /* 863 * Configured to return the measurement of errors in blocks, 864 * because no UCBLOCKS value is available, so this value doubles up 865 * to satisfy both measurements. 866 */ 867 static int cx24123_read_ber(struct dvb_frontend *fe, u32 *ber) 868 { 869 struct cx24123_state *state = fe->demodulator_priv; 870 871 /* The true bit error rate is this value divided by 872 the window size (set as 256 * 255) */ 873 *ber = ((cx24123_readreg(state, 0x1c) & 0x3f) << 16) | 874 (cx24123_readreg(state, 0x1d) << 8 | 875 cx24123_readreg(state, 0x1e)); 876 877 dprintk("BER = %d\n", *ber); 878 879 return 0; 880 } 881 882 static int cx24123_read_signal_strength(struct dvb_frontend *fe, 883 u16 *signal_strength) 884 { 885 struct cx24123_state *state = fe->demodulator_priv; 886 887 /* larger = better */ 888 *signal_strength = cx24123_readreg(state, 0x3b) << 8; 889 890 dprintk("Signal strength = %d\n", *signal_strength); 891 892 return 0; 893 } 894 895 static int cx24123_read_snr(struct dvb_frontend *fe, u16 *snr) 896 { 897 struct cx24123_state *state = fe->demodulator_priv; 898 899 /* Inverted raw Es/N0 count, totally bogus but better than the 900 BER threshold. */ 901 *snr = 65535 - (((u16)cx24123_readreg(state, 0x18) << 8) | 902 (u16)cx24123_readreg(state, 0x19)); 903 904 dprintk("read S/N index = %d\n", *snr); 905 906 return 0; 907 } 908 909 static int cx24123_set_frontend(struct dvb_frontend *fe) 910 { 911 struct cx24123_state *state = fe->demodulator_priv; 912 struct dtv_frontend_properties *p = &fe->dtv_property_cache; 913 914 dprintk("\n"); 915 916 if (state->config->set_ts_params) 917 state->config->set_ts_params(fe, 0); 918 919 state->currentfreq = p->frequency; 920 state->currentsymbolrate = p->symbol_rate; 921 922 cx24123_set_inversion(state, p->inversion); 923 cx24123_set_fec(state, p->fec_inner); 924 cx24123_set_symbolrate(state, p->symbol_rate); 925 926 if (!state->config->dont_use_pll) 927 cx24123_pll_tune(fe); 928 else if (fe->ops.tuner_ops.set_params) 929 fe->ops.tuner_ops.set_params(fe); 930 else 931 err("it seems I don't have a tuner..."); 932 933 /* Enable automatic acquisition and reset cycle */ 934 cx24123_writereg(state, 0x03, (cx24123_readreg(state, 0x03) | 0x07)); 935 cx24123_writereg(state, 0x00, 0x10); 936 cx24123_writereg(state, 0x00, 0); 937 938 if (state->config->agc_callback) 939 state->config->agc_callback(fe); 940 941 return 0; 942 } 943 944 static int cx24123_get_frontend(struct dvb_frontend *fe, 945 struct dtv_frontend_properties *p) 946 { 947 struct cx24123_state *state = fe->demodulator_priv; 948 949 dprintk("\n"); 950 951 if (cx24123_get_inversion(state, &p->inversion) != 0) { 952 err("%s: Failed to get inversion status\n", __func__); 953 return -EREMOTEIO; 954 } 955 if (cx24123_get_fec(state, &p->fec_inner) != 0) { 956 err("%s: Failed to get fec status\n", __func__); 957 return -EREMOTEIO; 958 } 959 p->frequency = state->currentfreq; 960 p->symbol_rate = state->currentsymbolrate; 961 962 return 0; 963 } 964 965 static int cx24123_set_tone(struct dvb_frontend *fe, enum fe_sec_tone_mode tone) 966 { 967 struct cx24123_state *state = fe->demodulator_priv; 968 u8 val; 969 970 /* wait for diseqc queue ready */ 971 cx24123_wait_for_diseqc(state); 972 973 val = cx24123_readreg(state, 0x29) & ~0x40; 974 975 switch (tone) { 976 case SEC_TONE_ON: 977 dprintk("setting tone on\n"); 978 return cx24123_writereg(state, 0x29, val | 0x10); 979 case SEC_TONE_OFF: 980 dprintk("setting tone off\n"); 981 return cx24123_writereg(state, 0x29, val & 0xef); 982 default: 983 err("CASE reached default with tone=%d\n", tone); 984 return -EINVAL; 985 } 986 987 return 0; 988 } 989 990 static int cx24123_tune(struct dvb_frontend *fe, 991 bool re_tune, 992 unsigned int mode_flags, 993 unsigned int *delay, 994 enum fe_status *status) 995 { 996 int retval = 0; 997 998 if (re_tune) 999 retval = cx24123_set_frontend(fe); 1000 1001 if (!(mode_flags & FE_TUNE_MODE_ONESHOT)) 1002 cx24123_read_status(fe, status); 1003 *delay = HZ/10; 1004 1005 return retval; 1006 } 1007 1008 static int cx24123_get_algo(struct dvb_frontend *fe) 1009 { 1010 return DVBFE_ALGO_HW; 1011 } 1012 1013 static void cx24123_release(struct dvb_frontend *fe) 1014 { 1015 struct cx24123_state *state = fe->demodulator_priv; 1016 dprintk("\n"); 1017 i2c_del_adapter(&state->tuner_i2c_adapter); 1018 kfree(state); 1019 } 1020 1021 static int cx24123_tuner_i2c_tuner_xfer(struct i2c_adapter *i2c_adap, 1022 struct i2c_msg msg[], int num) 1023 { 1024 struct cx24123_state *state = i2c_get_adapdata(i2c_adap); 1025 /* this repeater closes after the first stop */ 1026 cx24123_repeater_mode(state, 1, 1); 1027 return i2c_transfer(state->i2c, msg, num); 1028 } 1029 1030 static u32 cx24123_tuner_i2c_func(struct i2c_adapter *adapter) 1031 { 1032 return I2C_FUNC_I2C; 1033 } 1034 1035 static const struct i2c_algorithm cx24123_tuner_i2c_algo = { 1036 .master_xfer = cx24123_tuner_i2c_tuner_xfer, 1037 .functionality = cx24123_tuner_i2c_func, 1038 }; 1039 1040 struct i2c_adapter * 1041 cx24123_get_tuner_i2c_adapter(struct dvb_frontend *fe) 1042 { 1043 struct cx24123_state *state = fe->demodulator_priv; 1044 return &state->tuner_i2c_adapter; 1045 } 1046 EXPORT_SYMBOL(cx24123_get_tuner_i2c_adapter); 1047 1048 static const struct dvb_frontend_ops cx24123_ops; 1049 1050 struct dvb_frontend *cx24123_attach(const struct cx24123_config *config, 1051 struct i2c_adapter *i2c) 1052 { 1053 /* allocate memory for the internal state */ 1054 struct cx24123_state *state = 1055 kzalloc(sizeof(struct cx24123_state), GFP_KERNEL); 1056 1057 dprintk("\n"); 1058 if (state == NULL) { 1059 err("Unable to kzalloc\n"); 1060 goto error; 1061 } 1062 1063 /* setup the state */ 1064 state->config = config; 1065 state->i2c = i2c; 1066 1067 /* check if the demod is there */ 1068 state->demod_rev = cx24123_readreg(state, 0x00); 1069 switch (state->demod_rev) { 1070 case 0xe1: 1071 info("detected CX24123C\n"); 1072 break; 1073 case 0xd1: 1074 info("detected CX24123\n"); 1075 break; 1076 default: 1077 err("wrong demod revision: %x\n", state->demod_rev); 1078 goto error; 1079 } 1080 1081 /* create dvb_frontend */ 1082 memcpy(&state->frontend.ops, &cx24123_ops, 1083 sizeof(struct dvb_frontend_ops)); 1084 state->frontend.demodulator_priv = state; 1085 1086 /* create tuner i2c adapter */ 1087 if (config->dont_use_pll) 1088 cx24123_repeater_mode(state, 1, 0); 1089 1090 strlcpy(state->tuner_i2c_adapter.name, "CX24123 tuner I2C bus", 1091 sizeof(state->tuner_i2c_adapter.name)); 1092 state->tuner_i2c_adapter.algo = &cx24123_tuner_i2c_algo; 1093 state->tuner_i2c_adapter.algo_data = NULL; 1094 state->tuner_i2c_adapter.dev.parent = i2c->dev.parent; 1095 i2c_set_adapdata(&state->tuner_i2c_adapter, state); 1096 if (i2c_add_adapter(&state->tuner_i2c_adapter) < 0) { 1097 err("tuner i2c bus could not be initialized\n"); 1098 goto error; 1099 } 1100 1101 return &state->frontend; 1102 1103 error: 1104 kfree(state); 1105 1106 return NULL; 1107 } 1108 EXPORT_SYMBOL(cx24123_attach); 1109 1110 static const struct dvb_frontend_ops cx24123_ops = { 1111 .delsys = { SYS_DVBS }, 1112 .info = { 1113 .name = "Conexant CX24123/CX24109", 1114 .frequency_min = 950000, 1115 .frequency_max = 2150000, 1116 .frequency_stepsize = 1011, /* kHz for QPSK frontends */ 1117 .frequency_tolerance = 5000, 1118 .symbol_rate_min = 1000000, 1119 .symbol_rate_max = 45000000, 1120 .caps = FE_CAN_INVERSION_AUTO | 1121 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 | 1122 FE_CAN_FEC_4_5 | FE_CAN_FEC_5_6 | FE_CAN_FEC_6_7 | 1123 FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO | 1124 FE_CAN_QPSK | FE_CAN_RECOVER 1125 }, 1126 1127 .release = cx24123_release, 1128 1129 .init = cx24123_initfe, 1130 .set_frontend = cx24123_set_frontend, 1131 .get_frontend = cx24123_get_frontend, 1132 .read_status = cx24123_read_status, 1133 .read_ber = cx24123_read_ber, 1134 .read_signal_strength = cx24123_read_signal_strength, 1135 .read_snr = cx24123_read_snr, 1136 .diseqc_send_master_cmd = cx24123_send_diseqc_msg, 1137 .diseqc_send_burst = cx24123_diseqc_send_burst, 1138 .set_tone = cx24123_set_tone, 1139 .set_voltage = cx24123_set_voltage, 1140 .tune = cx24123_tune, 1141 .get_frontend_algo = cx24123_get_algo, 1142 }; 1143 1144 MODULE_DESCRIPTION("DVB Frontend module for Conexant " \ 1145 "CX24123/CX24109/CX24113 hardware"); 1146 MODULE_AUTHOR("Steven Toth"); 1147 MODULE_LICENSE("GPL"); 1148 1149