1 /*
2     cx24110 - Single Chip Satellite Channel Receiver driver module
3 
4     Copyright (C) 2002 Peter Hettkamp <peter.hettkamp@htp-tel.de> based on
5     work
6     Copyright (C) 1999 Convergence Integrated Media GmbH <ralph@convergence.de>
7 
8     This program is free software; you can redistribute it and/or modify
9     it under the terms of the GNU General Public License as published by
10     the Free Software Foundation; either version 2 of the License, or
11     (at your option) any later version.
12 
13     This program is distributed in the hope that it will be useful,
14     but WITHOUT ANY WARRANTY; without even the implied warranty of
15     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16 
17     GNU General Public License for more details.
18 
19     You should have received a copy of the GNU General Public License
20     along with this program; if not, write to the Free Software
21     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 
23 */
24 
25 #include <linux/slab.h>
26 #include <linux/kernel.h>
27 #include <linux/module.h>
28 #include <linux/init.h>
29 
30 #include "dvb_frontend.h"
31 #include "cx24110.h"
32 
33 
34 struct cx24110_state {
35 
36 	struct i2c_adapter* i2c;
37 
38 	const struct cx24110_config* config;
39 
40 	struct dvb_frontend frontend;
41 
42 	u32 lastber;
43 	u32 lastbler;
44 	u32 lastesn0;
45 };
46 
47 static int debug;
48 #define dprintk(args...) \
49 	do { \
50 		if (debug) printk(KERN_DEBUG "cx24110: " args); \
51 	} while (0)
52 
53 static struct {u8 reg; u8 data;} cx24110_regdata[]=
54 		      /* Comments beginning with @ denote this value should
55 			 be the default */
56 	{{0x09,0x01}, /* SoftResetAll */
57 	 {0x09,0x00}, /* release reset */
58 	 {0x01,0xe8}, /* MSB of code rate 27.5MS/s */
59 	 {0x02,0x17}, /* middle byte " */
60 	 {0x03,0x29}, /* LSB         " */
61 	 {0x05,0x03}, /* @ DVB mode, standard code rate 3/4 */
62 	 {0x06,0xa5}, /* @ PLL 60MHz */
63 	 {0x07,0x01}, /* @ Fclk, i.e. sampling clock, 60MHz */
64 	 {0x0a,0x00}, /* @ partial chip disables, do not set */
65 	 {0x0b,0x01}, /* set output clock in gapped mode, start signal low
66 			 active for first byte */
67 	 {0x0c,0x11}, /* no parity bytes, large hold time, serial data out */
68 	 {0x0d,0x6f}, /* @ RS Sync/Unsync thresholds */
69 	 {0x10,0x40}, /* chip doc is misleading here: write bit 6 as 1
70 			 to avoid starting the BER counter. Reset the
71 			 CRC test bit. Finite counting selected */
72 	 {0x15,0xff}, /* @ size of the limited time window for RS BER
73 			 estimation. It is <value>*256 RS blocks, this
74 			 gives approx. 2.6 sec at 27.5MS/s, rate 3/4 */
75 	 {0x16,0x00}, /* @ enable all RS output ports */
76 	 {0x17,0x04}, /* @ time window allowed for the RS to sync */
77 	 {0x18,0xae}, /* @ allow all standard DVB code rates to be scanned
78 			 for automatically */
79 		      /* leave the current code rate and normalization
80 			 registers as they are after reset... */
81 	 {0x21,0x10}, /* @ during AutoAcq, search each viterbi setting
82 			 only once */
83 	 {0x23,0x18}, /* @ size of the limited time window for Viterbi BER
84 			 estimation. It is <value>*65536 channel bits, i.e.
85 			 approx. 38ms at 27.5MS/s, rate 3/4 */
86 	 {0x24,0x24}, /* do not trigger Viterbi CRC test. Finite count window */
87 		      /* leave front-end AGC parameters at default values */
88 		      /* leave decimation AGC parameters at default values */
89 	 {0x35,0x40}, /* disable all interrupts. They are not connected anyway */
90 	 {0x36,0xff}, /* clear all interrupt pending flags */
91 	 {0x37,0x00}, /* @ fully enable AutoAcqq state machine */
92 	 {0x38,0x07}, /* @ enable fade recovery, but not autostart AutoAcq */
93 		      /* leave the equalizer parameters on their default values */
94 		      /* leave the final AGC parameters on their default values */
95 	 {0x41,0x00}, /* @ MSB of front-end derotator frequency */
96 	 {0x42,0x00}, /* @ middle bytes " */
97 	 {0x43,0x00}, /* @ LSB          " */
98 		      /* leave the carrier tracking loop parameters on default */
99 		      /* leave the bit timing loop parameters at default */
100 	 {0x56,0x4d}, /* set the filtune voltage to 2.7V, as recommended by */
101 		      /* the cx24108 data sheet for symbol rates above 15MS/s */
102 	 {0x57,0x00}, /* @ Filter sigma delta enabled, positive */
103 	 {0x61,0x95}, /* GPIO pins 1-4 have special function */
104 	 {0x62,0x05}, /* GPIO pin 5 has special function, pin 6 is GPIO */
105 	 {0x63,0x00}, /* All GPIO pins use CMOS output characteristics */
106 	 {0x64,0x20}, /* GPIO 6 is input, all others are outputs */
107 	 {0x6d,0x30}, /* tuner auto mode clock freq 62kHz */
108 	 {0x70,0x15}, /* use auto mode, tuner word is 21 bits long */
109 	 {0x73,0x00}, /* @ disable several demod bypasses */
110 	 {0x74,0x00}, /* @  " */
111 	 {0x75,0x00}  /* @  " */
112 		      /* the remaining registers are for SEC */
113 	};
114 
115 
116 static int cx24110_writereg (struct cx24110_state* state, int reg, int data)
117 {
118 	u8 buf [] = { reg, data };
119 	struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = buf, .len = 2 };
120 	int err;
121 
122 	if ((err = i2c_transfer(state->i2c, &msg, 1)) != 1) {
123 		dprintk ("%s: writereg error (err == %i, reg == 0x%02x,"
124 			 " data == 0x%02x)\n", __func__, err, reg, data);
125 		return -EREMOTEIO;
126 	}
127 
128 	return 0;
129 }
130 
131 static int cx24110_readreg (struct cx24110_state* state, u8 reg)
132 {
133 	int ret;
134 	u8 b0 [] = { reg };
135 	u8 b1 [] = { 0 };
136 	struct i2c_msg msg [] = { { .addr = state->config->demod_address, .flags = 0, .buf = b0, .len = 1 },
137 			   { .addr = state->config->demod_address, .flags = I2C_M_RD, .buf = b1, .len = 1 } };
138 
139 	ret = i2c_transfer(state->i2c, msg, 2);
140 
141 	if (ret != 2) return ret;
142 
143 	return b1[0];
144 }
145 
146 static int cx24110_set_inversion (struct cx24110_state* state, fe_spectral_inversion_t inversion)
147 {
148 /* fixme (low): error handling */
149 
150 	switch (inversion) {
151 	case INVERSION_OFF:
152 		cx24110_writereg(state,0x37,cx24110_readreg(state,0x37)|0x1);
153 		/* AcqSpectrInvDis on. No idea why someone should want this */
154 		cx24110_writereg(state,0x5,cx24110_readreg(state,0x5)&0xf7);
155 		/* Initial value 0 at start of acq */
156 		cx24110_writereg(state,0x22,cx24110_readreg(state,0x22)&0xef);
157 		/* current value 0 */
158 		/* The cx24110 manual tells us this reg is read-only.
159 		   But what the heck... set it ayways */
160 		break;
161 	case INVERSION_ON:
162 		cx24110_writereg(state,0x37,cx24110_readreg(state,0x37)|0x1);
163 		/* AcqSpectrInvDis on. No idea why someone should want this */
164 		cx24110_writereg(state,0x5,cx24110_readreg(state,0x5)|0x08);
165 		/* Initial value 1 at start of acq */
166 		cx24110_writereg(state,0x22,cx24110_readreg(state,0x22)|0x10);
167 		/* current value 1 */
168 		break;
169 	case INVERSION_AUTO:
170 		cx24110_writereg(state,0x37,cx24110_readreg(state,0x37)&0xfe);
171 		/* AcqSpectrInvDis off. Leave initial & current states as is */
172 		break;
173 	default:
174 		return -EINVAL;
175 	}
176 
177 	return 0;
178 }
179 
180 static int cx24110_set_fec(struct cx24110_state* state, fe_code_rate_t fec)
181 {
182 	static const int rate[FEC_AUTO] = {-1,    1,    2,    3,    5,    7, -1};
183 	static const int g1[FEC_AUTO]   = {-1, 0x01, 0x02, 0x05, 0x15, 0x45, -1};
184 	static const int g2[FEC_AUTO]   = {-1, 0x01, 0x03, 0x06, 0x1a, 0x7a, -1};
185 
186 	/* Well, the AutoAcq engine of the cx24106 and 24110 automatically
187 	   searches all enabled viterbi rates, and can handle non-standard
188 	   rates as well. */
189 
190 	if (fec > FEC_AUTO)
191 		fec = FEC_AUTO;
192 
193 	if (fec == FEC_AUTO) { /* (re-)establish AutoAcq behaviour */
194 		cx24110_writereg(state, 0x37, cx24110_readreg(state, 0x37) & 0xdf);
195 		/* clear AcqVitDis bit */
196 		cx24110_writereg(state, 0x18, 0xae);
197 		/* allow all DVB standard code rates */
198 		cx24110_writereg(state, 0x05, (cx24110_readreg(state, 0x05) & 0xf0) | 0x3);
199 		/* set nominal Viterbi rate 3/4 */
200 		cx24110_writereg(state, 0x22, (cx24110_readreg(state, 0x22) & 0xf0) | 0x3);
201 		/* set current Viterbi rate 3/4 */
202 		cx24110_writereg(state, 0x1a, 0x05);
203 		cx24110_writereg(state, 0x1b, 0x06);
204 		/* set the puncture registers for code rate 3/4 */
205 		return 0;
206 	} else {
207 		cx24110_writereg(state, 0x37, cx24110_readreg(state, 0x37) | 0x20);
208 		/* set AcqVitDis bit */
209 		if (rate[fec] < 0)
210 			return -EINVAL;
211 
212 		cx24110_writereg(state, 0x05, (cx24110_readreg(state, 0x05) & 0xf0) | rate[fec]);
213 		/* set nominal Viterbi rate */
214 		cx24110_writereg(state, 0x22, (cx24110_readreg(state, 0x22) & 0xf0) | rate[fec]);
215 		/* set current Viterbi rate */
216 		cx24110_writereg(state, 0x1a, g1[fec]);
217 		cx24110_writereg(state, 0x1b, g2[fec]);
218 		/* not sure if this is the right way: I always used AutoAcq mode */
219 	}
220 	return 0;
221 }
222 
223 static fe_code_rate_t cx24110_get_fec (struct cx24110_state* state)
224 {
225 	int i;
226 
227 	i=cx24110_readreg(state,0x22)&0x0f;
228 	if(!(i&0x08)) {
229 		return FEC_1_2 + i - 1;
230 	} else {
231 /* fixme (low): a special code rate has been selected. In theory, we need to
232    return a denominator value, a numerator value, and a pair of puncture
233    maps to correctly describe this mode. But this should never happen in
234    practice, because it cannot be set by cx24110_get_fec. */
235 	   return FEC_NONE;
236 	}
237 }
238 
239 static int cx24110_set_symbolrate (struct cx24110_state* state, u32 srate)
240 {
241 /* fixme (low): add error handling */
242 	u32 ratio;
243 	u32 tmp, fclk, BDRI;
244 
245 	static const u32 bands[]={5000000UL,15000000UL,90999000UL/2};
246 	int i;
247 
248 	dprintk("cx24110 debug: entering %s(%d)\n",__func__,srate);
249 	if (srate>90999000UL/2)
250 		srate=90999000UL/2;
251 	if (srate<500000)
252 		srate=500000;
253 
254 	for(i = 0; (i < ARRAY_SIZE(bands)) && (srate>bands[i]); i++)
255 		;
256 	/* first, check which sample rate is appropriate: 45, 60 80 or 90 MHz,
257 	   and set the PLL accordingly (R07[1:0] Fclk, R06[7:4] PLLmult,
258 	   R06[3:0] PLLphaseDetGain */
259 	tmp=cx24110_readreg(state,0x07)&0xfc;
260 	if(srate<90999000UL/4) { /* sample rate 45MHz*/
261 		cx24110_writereg(state,0x07,tmp);
262 		cx24110_writereg(state,0x06,0x78);
263 		fclk=90999000UL/2;
264 	} else if(srate<60666000UL/2) { /* sample rate 60MHz */
265 		cx24110_writereg(state,0x07,tmp|0x1);
266 		cx24110_writereg(state,0x06,0xa5);
267 		fclk=60666000UL;
268 	} else if(srate<80888000UL/2) { /* sample rate 80MHz */
269 		cx24110_writereg(state,0x07,tmp|0x2);
270 		cx24110_writereg(state,0x06,0x87);
271 		fclk=80888000UL;
272 	} else { /* sample rate 90MHz */
273 		cx24110_writereg(state,0x07,tmp|0x3);
274 		cx24110_writereg(state,0x06,0x78);
275 		fclk=90999000UL;
276 	}
277 	dprintk("cx24110 debug: fclk %d Hz\n",fclk);
278 	/* we need to divide two integers with approx. 27 bits in 32 bit
279 	   arithmetic giving a 25 bit result */
280 	/* the maximum dividend is 90999000/2, 0x02b6446c, this number is
281 	   also the most complex divisor. Hence, the dividend has,
282 	   assuming 32bit unsigned arithmetic, 6 clear bits on top, the
283 	   divisor 2 unused bits at the bottom. Also, the quotient is
284 	   always less than 1/2. Borrowed from VES1893.c, of course */
285 
286 	tmp=srate<<6;
287 	BDRI=fclk>>2;
288 	ratio=(tmp/BDRI);
289 
290 	tmp=(tmp%BDRI)<<8;
291 	ratio=(ratio<<8)+(tmp/BDRI);
292 
293 	tmp=(tmp%BDRI)<<8;
294 	ratio=(ratio<<8)+(tmp/BDRI);
295 
296 	tmp=(tmp%BDRI)<<1;
297 	ratio=(ratio<<1)+(tmp/BDRI);
298 
299 	dprintk("srate= %d (range %d, up to %d)\n", srate,i,bands[i]);
300 	dprintk("fclk = %d\n", fclk);
301 	dprintk("ratio= %08x\n", ratio);
302 
303 	cx24110_writereg(state, 0x1, (ratio>>16)&0xff);
304 	cx24110_writereg(state, 0x2, (ratio>>8)&0xff);
305 	cx24110_writereg(state, 0x3, (ratio)&0xff);
306 
307 	return 0;
308 
309 }
310 
311 static int _cx24110_pll_write (struct dvb_frontend* fe, const u8 buf[], int len)
312 {
313 	struct cx24110_state *state = fe->demodulator_priv;
314 
315 	if (len != 3)
316 		return -EINVAL;
317 
318 /* tuner data is 21 bits long, must be left-aligned in data */
319 /* tuner cx24108 is written through a dedicated 3wire interface on the demod chip */
320 /* FIXME (low): add error handling, avoid infinite loops if HW fails... */
321 
322 	cx24110_writereg(state,0x6d,0x30); /* auto mode at 62kHz */
323 	cx24110_writereg(state,0x70,0x15); /* auto mode 21 bits */
324 
325 	/* if the auto tuner writer is still busy, clear it out */
326 	while (cx24110_readreg(state,0x6d)&0x80)
327 		cx24110_writereg(state,0x72,0);
328 
329 	/* write the topmost 8 bits */
330 	cx24110_writereg(state,0x72,buf[0]);
331 
332 	/* wait for the send to be completed */
333 	while ((cx24110_readreg(state,0x6d)&0xc0)==0x80)
334 		;
335 
336 	/* send another 8 bytes */
337 	cx24110_writereg(state,0x72,buf[1]);
338 	while ((cx24110_readreg(state,0x6d)&0xc0)==0x80)
339 		;
340 
341 	/* and the topmost 5 bits of this byte */
342 	cx24110_writereg(state,0x72,buf[2]);
343 	while ((cx24110_readreg(state,0x6d)&0xc0)==0x80)
344 		;
345 
346 	/* now strobe the enable line once */
347 	cx24110_writereg(state,0x6d,0x32);
348 	cx24110_writereg(state,0x6d,0x30);
349 
350 	return 0;
351 }
352 
353 static int cx24110_initfe(struct dvb_frontend* fe)
354 {
355 	struct cx24110_state *state = fe->demodulator_priv;
356 /* fixme (low): error handling */
357 	int i;
358 
359 	dprintk("%s: init chip\n", __func__);
360 
361 	for(i = 0; i < ARRAY_SIZE(cx24110_regdata); i++) {
362 		cx24110_writereg(state, cx24110_regdata[i].reg, cx24110_regdata[i].data);
363 	}
364 
365 	return 0;
366 }
367 
368 static int cx24110_set_voltage (struct dvb_frontend* fe, fe_sec_voltage_t voltage)
369 {
370 	struct cx24110_state *state = fe->demodulator_priv;
371 
372 	switch (voltage) {
373 	case SEC_VOLTAGE_13:
374 		return cx24110_writereg(state,0x76,(cx24110_readreg(state,0x76)&0x3b)|0xc0);
375 	case SEC_VOLTAGE_18:
376 		return cx24110_writereg(state,0x76,(cx24110_readreg(state,0x76)&0x3b)|0x40);
377 	default:
378 		return -EINVAL;
379 	}
380 }
381 
382 static int cx24110_diseqc_send_burst(struct dvb_frontend* fe, fe_sec_mini_cmd_t burst)
383 {
384 	int rv, bit;
385 	struct cx24110_state *state = fe->demodulator_priv;
386 	unsigned long timeout;
387 
388 	if (burst == SEC_MINI_A)
389 		bit = 0x00;
390 	else if (burst == SEC_MINI_B)
391 		bit = 0x08;
392 	else
393 		return -EINVAL;
394 
395 	rv = cx24110_readreg(state, 0x77);
396 	if (!(rv & 0x04))
397 		cx24110_writereg(state, 0x77, rv | 0x04);
398 
399 	rv = cx24110_readreg(state, 0x76);
400 	cx24110_writereg(state, 0x76, ((rv & 0x90) | 0x40 | bit));
401 	timeout = jiffies + msecs_to_jiffies(100);
402 	while (!time_after(jiffies, timeout) && !(cx24110_readreg(state, 0x76) & 0x40))
403 		; /* wait for LNB ready */
404 
405 	return 0;
406 }
407 
408 static int cx24110_send_diseqc_msg(struct dvb_frontend* fe,
409 				   struct dvb_diseqc_master_cmd *cmd)
410 {
411 	int i, rv;
412 	struct cx24110_state *state = fe->demodulator_priv;
413 	unsigned long timeout;
414 
415 	if (cmd->msg_len < 3 || cmd->msg_len > 6)
416 		return -EINVAL;  /* not implemented */
417 
418 	for (i = 0; i < cmd->msg_len; i++)
419 		cx24110_writereg(state, 0x79 + i, cmd->msg[i]);
420 
421 	rv = cx24110_readreg(state, 0x77);
422 	if (rv & 0x04) {
423 		cx24110_writereg(state, 0x77, rv & ~0x04);
424 		msleep(30); /* reportedly fixes switching problems */
425 	}
426 
427 	rv = cx24110_readreg(state, 0x76);
428 
429 	cx24110_writereg(state, 0x76, ((rv & 0x90) | 0x40) | ((cmd->msg_len-3) & 3));
430 	timeout = jiffies + msecs_to_jiffies(100);
431 	while (!time_after(jiffies, timeout) && !(cx24110_readreg(state, 0x76) & 0x40))
432 		; /* wait for LNB ready */
433 
434 	return 0;
435 }
436 
437 static int cx24110_read_status(struct dvb_frontend* fe, fe_status_t* status)
438 {
439 	struct cx24110_state *state = fe->demodulator_priv;
440 
441 	int sync = cx24110_readreg (state, 0x55);
442 
443 	*status = 0;
444 
445 	if (sync & 0x10)
446 		*status |= FE_HAS_SIGNAL;
447 
448 	if (sync & 0x08)
449 		*status |= FE_HAS_CARRIER;
450 
451 	sync = cx24110_readreg (state, 0x08);
452 
453 	if (sync & 0x40)
454 		*status |= FE_HAS_VITERBI;
455 
456 	if (sync & 0x20)
457 		*status |= FE_HAS_SYNC;
458 
459 	if ((sync & 0x60) == 0x60)
460 		*status |= FE_HAS_LOCK;
461 
462 	return 0;
463 }
464 
465 static int cx24110_read_ber(struct dvb_frontend* fe, u32* ber)
466 {
467 	struct cx24110_state *state = fe->demodulator_priv;
468 
469 	/* fixme (maybe): value range is 16 bit. Scale? */
470 	if(cx24110_readreg(state,0x24)&0x10) {
471 		/* the Viterbi error counter has finished one counting window */
472 		cx24110_writereg(state,0x24,0x04); /* select the ber reg */
473 		state->lastber=cx24110_readreg(state,0x25)|
474 			(cx24110_readreg(state,0x26)<<8);
475 		cx24110_writereg(state,0x24,0x04); /* start new count window */
476 		cx24110_writereg(state,0x24,0x14);
477 	}
478 	*ber = state->lastber;
479 
480 	return 0;
481 }
482 
483 static int cx24110_read_signal_strength(struct dvb_frontend* fe, u16* signal_strength)
484 {
485 	struct cx24110_state *state = fe->demodulator_priv;
486 
487 /* no provision in hardware. Read the frontend AGC accumulator. No idea how to scale this, but I know it is 2s complement */
488 	u8 signal = cx24110_readreg (state, 0x27)+128;
489 	*signal_strength = (signal << 8) | signal;
490 
491 	return 0;
492 }
493 
494 static int cx24110_read_snr(struct dvb_frontend* fe, u16* snr)
495 {
496 	struct cx24110_state *state = fe->demodulator_priv;
497 
498 	/* no provision in hardware. Can be computed from the Es/N0 estimator, but I don't know how. */
499 	if(cx24110_readreg(state,0x6a)&0x80) {
500 		/* the Es/N0 error counter has finished one counting window */
501 		state->lastesn0=cx24110_readreg(state,0x69)|
502 			(cx24110_readreg(state,0x68)<<8);
503 		cx24110_writereg(state,0x6a,0x84); /* start new count window */
504 	}
505 	*snr = state->lastesn0;
506 
507 	return 0;
508 }
509 
510 static int cx24110_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
511 {
512 	struct cx24110_state *state = fe->demodulator_priv;
513 
514 	if(cx24110_readreg(state,0x10)&0x40) {
515 		/* the RS error counter has finished one counting window */
516 		cx24110_writereg(state,0x10,0x60); /* select the byer reg */
517 		(void)(cx24110_readreg(state, 0x12) |
518 			(cx24110_readreg(state, 0x13) << 8) |
519 			(cx24110_readreg(state, 0x14) << 16));
520 		cx24110_writereg(state,0x10,0x70); /* select the bler reg */
521 		state->lastbler=cx24110_readreg(state,0x12)|
522 			(cx24110_readreg(state,0x13)<<8)|
523 			(cx24110_readreg(state,0x14)<<16);
524 		cx24110_writereg(state,0x10,0x20); /* start new count window */
525 	}
526 	*ucblocks = state->lastbler;
527 
528 	return 0;
529 }
530 
531 static int cx24110_set_frontend(struct dvb_frontend *fe)
532 {
533 	struct cx24110_state *state = fe->demodulator_priv;
534 	struct dtv_frontend_properties *p = &fe->dtv_property_cache;
535 
536 	if (fe->ops.tuner_ops.set_params) {
537 		fe->ops.tuner_ops.set_params(fe);
538 		if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0);
539 	}
540 
541 	cx24110_set_inversion(state, p->inversion);
542 	cx24110_set_fec(state, p->fec_inner);
543 	cx24110_set_symbolrate(state, p->symbol_rate);
544 	cx24110_writereg(state,0x04,0x05); /* start acquisition */
545 
546 	return 0;
547 }
548 
549 static int cx24110_get_frontend(struct dvb_frontend *fe)
550 {
551 	struct dtv_frontend_properties *p = &fe->dtv_property_cache;
552 	struct cx24110_state *state = fe->demodulator_priv;
553 	s32 afc; unsigned sclk;
554 
555 /* cannot read back tuner settings (freq). Need to have some private storage */
556 
557 	sclk = cx24110_readreg (state, 0x07) & 0x03;
558 /* ok, real AFC (FEDR) freq. is afc/2^24*fsamp, fsamp=45/60/80/90MHz.
559  * Need 64 bit arithmetic. Is thiss possible in the kernel? */
560 	if (sclk==0) sclk=90999000L/2L;
561 	else if (sclk==1) sclk=60666000L;
562 	else if (sclk==2) sclk=80888000L;
563 	else sclk=90999000L;
564 	sclk>>=8;
565 	afc = sclk*(cx24110_readreg (state, 0x44)&0x1f)+
566 	      ((sclk*cx24110_readreg (state, 0x45))>>8)+
567 	      ((sclk*cx24110_readreg (state, 0x46))>>16);
568 
569 	p->frequency += afc;
570 	p->inversion = (cx24110_readreg (state, 0x22) & 0x10) ?
571 				INVERSION_ON : INVERSION_OFF;
572 	p->fec_inner = cx24110_get_fec(state);
573 
574 	return 0;
575 }
576 
577 static int cx24110_set_tone(struct dvb_frontend* fe, fe_sec_tone_mode_t tone)
578 {
579 	struct cx24110_state *state = fe->demodulator_priv;
580 
581 	return cx24110_writereg(state,0x76,(cx24110_readreg(state,0x76)&~0x10)|(((tone==SEC_TONE_ON))?0x10:0));
582 }
583 
584 static void cx24110_release(struct dvb_frontend* fe)
585 {
586 	struct cx24110_state* state = fe->demodulator_priv;
587 	kfree(state);
588 }
589 
590 static struct dvb_frontend_ops cx24110_ops;
591 
592 struct dvb_frontend* cx24110_attach(const struct cx24110_config* config,
593 				    struct i2c_adapter* i2c)
594 {
595 	struct cx24110_state* state = NULL;
596 	int ret;
597 
598 	/* allocate memory for the internal state */
599 	state = kzalloc(sizeof(struct cx24110_state), GFP_KERNEL);
600 	if (state == NULL) goto error;
601 
602 	/* setup the state */
603 	state->config = config;
604 	state->i2c = i2c;
605 	state->lastber = 0;
606 	state->lastbler = 0;
607 	state->lastesn0 = 0;
608 
609 	/* check if the demod is there */
610 	ret = cx24110_readreg(state, 0x00);
611 	if ((ret != 0x5a) && (ret != 0x69)) goto error;
612 
613 	/* create dvb_frontend */
614 	memcpy(&state->frontend.ops, &cx24110_ops, sizeof(struct dvb_frontend_ops));
615 	state->frontend.demodulator_priv = state;
616 	return &state->frontend;
617 
618 error:
619 	kfree(state);
620 	return NULL;
621 }
622 
623 static struct dvb_frontend_ops cx24110_ops = {
624 	.delsys = { SYS_DVBS },
625 	.info = {
626 		.name = "Conexant CX24110 DVB-S",
627 		.frequency_min = 950000,
628 		.frequency_max = 2150000,
629 		.frequency_stepsize = 1011,  /* kHz for QPSK frontends */
630 		.frequency_tolerance = 29500,
631 		.symbol_rate_min = 1000000,
632 		.symbol_rate_max = 45000000,
633 		.caps = FE_CAN_INVERSION_AUTO |
634 			FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
635 			FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
636 			FE_CAN_QPSK | FE_CAN_RECOVER
637 	},
638 
639 	.release = cx24110_release,
640 
641 	.init = cx24110_initfe,
642 	.write = _cx24110_pll_write,
643 	.set_frontend = cx24110_set_frontend,
644 	.get_frontend = cx24110_get_frontend,
645 	.read_status = cx24110_read_status,
646 	.read_ber = cx24110_read_ber,
647 	.read_signal_strength = cx24110_read_signal_strength,
648 	.read_snr = cx24110_read_snr,
649 	.read_ucblocks = cx24110_read_ucblocks,
650 
651 	.diseqc_send_master_cmd = cx24110_send_diseqc_msg,
652 	.set_tone = cx24110_set_tone,
653 	.set_voltage = cx24110_set_voltage,
654 	.diseqc_send_burst = cx24110_diseqc_send_burst,
655 };
656 
657 module_param(debug, int, 0644);
658 MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
659 
660 MODULE_DESCRIPTION("Conexant CX24110 DVB-S Demodulator driver");
661 MODULE_AUTHOR("Peter Hettkamp");
662 MODULE_LICENSE("GPL");
663 
664 EXPORT_SYMBOL(cx24110_attach);
665