1 /* 2 * bsbe1.h - ALPS BSBE1 tuner support 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * as published by the Free Software Foundation; either version 2 7 * of the License, or (at your option) any later version. 8 * 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 19 * Or, point your browser to http://www.gnu.org/copyleft/gpl.html 20 * 21 * 22 * the project's page is at https://linuxtv.org 23 */ 24 25 #ifndef BSBE1_H 26 #define BSBE1_H 27 28 static u8 alps_bsbe1_inittab[] = { 29 0x01, 0x15, /* XTAL = 4MHz, VCO = 352 MHz */ 30 0x02, 0x30, /* MCLK = 88 MHz */ 31 0x03, 0x00, /* ACR output 0 */ 32 0x04, 0x7d, /* F22FR = 0x7d, F22 = f_VCO / 128 / 0x7d = 22 kHz */ 33 0x05, 0x05, /* I2CT = 0, SCLT = 1, SDAT = 1 */ 34 0x06, 0x00, /* DAC output 0 */ 35 0x08, 0x40, /* DiSEqC off, LNB power on OP2/LOCK pin on */ 36 0x09, 0x00, /* FIFO */ 37 0x0c, 0x51, /* OP1/OP0 normal, val = 1 (LNB power on) */ 38 0x0d, 0x82, /* DC offset compensation = on, beta_agc1 = 2 */ 39 0x0f, 0x92, /* AGC1R */ 40 0x10, 0x34, /* AGC2O */ 41 0x11, 0x84, /* TLSR */ 42 0x12, 0xb9, /* CFD */ 43 0x15, 0xc9, /* lock detector threshold */ 44 0x28, 0x00, /* out imp: normal, type: parallel, FEC mode: QPSK */ 45 0x33, 0xfc, /* RS control */ 46 0x34, 0x93, /* count viterbi bit errors per 2E18 bytes */ 47 0xff, 0xff 48 }; 49 50 51 static int alps_bsbe1_set_symbol_rate(struct dvb_frontend* fe, u32 srate, u32 ratio) 52 { 53 u8 aclk = 0; 54 u8 bclk = 0; 55 56 if (srate < 1500000) { aclk = 0xb7; bclk = 0x47; } 57 else if (srate < 3000000) { aclk = 0xb7; bclk = 0x4b; } 58 else if (srate < 7000000) { aclk = 0xb7; bclk = 0x4f; } 59 else if (srate < 14000000) { aclk = 0xb7; bclk = 0x53; } 60 else if (srate < 30000000) { aclk = 0xb6; bclk = 0x53; } 61 else if (srate < 45000000) { aclk = 0xb4; bclk = 0x51; } 62 63 stv0299_writereg(fe, 0x13, aclk); 64 stv0299_writereg(fe, 0x14, bclk); 65 stv0299_writereg(fe, 0x1f, (ratio >> 16) & 0xff); 66 stv0299_writereg(fe, 0x20, (ratio >> 8) & 0xff); 67 stv0299_writereg(fe, 0x21, (ratio ) & 0xf0); 68 69 return 0; 70 } 71 72 static int alps_bsbe1_tuner_set_params(struct dvb_frontend *fe) 73 { 74 struct dtv_frontend_properties *p = &fe->dtv_property_cache; 75 int ret; 76 u8 data[4]; 77 u32 div; 78 struct i2c_msg msg = { .addr = 0x61, .flags = 0, .buf = data, .len = sizeof(data) }; 79 struct i2c_adapter *i2c = fe->tuner_priv; 80 81 if ((p->frequency < 950000) || (p->frequency > 2150000)) 82 return -EINVAL; 83 84 div = p->frequency / 1000; 85 data[0] = (div >> 8) & 0x7f; 86 data[1] = div & 0xff; 87 data[2] = 0x80 | ((div & 0x18000) >> 10) | 0x1; 88 data[3] = 0xe0; 89 90 if (fe->ops.i2c_gate_ctrl) 91 fe->ops.i2c_gate_ctrl(fe, 1); 92 ret = i2c_transfer(i2c, &msg, 1); 93 return (ret != 1) ? -EIO : 0; 94 } 95 96 static struct stv0299_config alps_bsbe1_config = { 97 .demod_address = 0x68, 98 .inittab = alps_bsbe1_inittab, 99 .mclk = 88000000UL, 100 .invert = 1, 101 .skip_reinit = 0, 102 .min_delay_ms = 100, 103 .set_symbol_rate = alps_bsbe1_set_symbol_rate, 104 }; 105 106 #endif 107