1 /* 2 * Support for the Broadcom BCM3510 ATSC demodulator (1st generation Air2PC) 3 * 4 * Copyright (C) 2001-5, B2C2 inc. 5 * 6 * GPL/Linux driver written by Patrick Boettcher <patrick.boettcher@posteo.de> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 */ 18 #ifndef __BCM3510_PRIV_H__ 19 #define __BCM3510_PRIV_H__ 20 21 #define PACKED __attribute__((packed)) 22 23 #undef err 24 #define err(format, arg...) printk(KERN_ERR "bcm3510: " format "\n" , ## arg) 25 #undef info 26 #define info(format, arg...) printk(KERN_INFO "bcm3510: " format "\n" , ## arg) 27 #undef warn 28 #define warn(format, arg...) printk(KERN_WARNING "bcm3510: " format "\n" , ## arg) 29 30 31 #define PANASONIC_FIRST_IF_BASE_IN_KHz 1407500 32 #define BCM3510_SYMBOL_RATE 5381000 33 34 typedef union { 35 u8 raw; 36 37 struct { 38 u8 CTL :8; 39 } TSTCTL_2e; 40 41 u8 LDCERC_4e; 42 u8 LDUERC_4f; 43 u8 LD_BER0_65; 44 u8 LD_BER1_66; 45 u8 LD_BER2_67; 46 u8 LD_BER3_68; 47 48 struct { 49 u8 RESET :1; 50 u8 IDLE :1; 51 u8 STOP :1; 52 u8 HIRQ0 :1; 53 u8 HIRQ1 :1; 54 u8 na0 :1; 55 u8 HABAV :1; 56 u8 na1 :1; 57 } HCTL1_a0; 58 59 struct { 60 u8 na0 :1; 61 u8 IDLMSK :1; 62 u8 STMSK :1; 63 u8 I0MSK :1; 64 u8 I1MSK :1; 65 u8 na1 :1; 66 u8 HABMSK :1; 67 u8 na2 :1; 68 } HCTLMSK_a1; 69 70 struct { 71 u8 RESET :1; 72 u8 IDLE :1; 73 u8 STOP :1; 74 u8 RUN :1; 75 u8 HABAV :1; 76 u8 MEMAV :1; 77 u8 ALDONE :1; 78 u8 REIRQ :1; 79 } APSTAT1_a2; 80 81 struct { 82 u8 RSTMSK :1; 83 u8 IMSK :1; 84 u8 SMSK :1; 85 u8 RMSK :1; 86 u8 HABMSK :1; 87 u8 MAVMSK :1; 88 u8 ALDMSK :1; 89 u8 REMSK :1; 90 } APMSK1_a3; 91 92 u8 APSTAT2_a4; 93 u8 APMSK2_a5; 94 95 struct { 96 u8 HABADR :7; 97 u8 na :1; 98 } HABADR_a6; 99 100 u8 HABDATA_a7; 101 102 struct { 103 u8 HABR :1; 104 u8 LDHABR :1; 105 u8 APMSK :1; 106 u8 HMSK :1; 107 u8 LDMSK :1; 108 u8 na :3; 109 } HABSTAT_a8; 110 111 u8 MADRH_a9; 112 u8 MADRL_aa; 113 u8 MDATA_ab; 114 115 struct { 116 #define JDEC_WAIT_AT_RAM 0x7 117 #define JDEC_EEPROM_LOAD_WAIT 0x4 118 u8 JDEC :3; 119 u8 na :5; 120 } JDEC_ca; 121 122 struct { 123 u8 REV :4; 124 u8 LAYER :4; 125 } REVID_e0; 126 127 struct { 128 u8 unk0 :1; 129 u8 CNTCTL :1; 130 u8 BITCNT :1; 131 u8 unk1 :1; 132 u8 RESYNC :1; 133 u8 unk2 :3; 134 } BERCTL_fa; 135 136 struct { 137 u8 CSEL0 :1; 138 u8 CLKED0 :1; 139 u8 CSEL1 :1; 140 u8 CLKED1 :1; 141 u8 CLKLEV :1; 142 u8 SPIVAR :1; 143 u8 na :2; 144 } TUNSET_fc; 145 146 struct { 147 u8 CLK :1; 148 u8 DATA :1; 149 u8 CS0 :1; 150 u8 CS1 :1; 151 u8 AGCSEL :1; 152 u8 na0 :1; 153 u8 TUNSEL :1; 154 u8 na1 :1; 155 } TUNCTL_fd; 156 157 u8 TUNSEL0_fe; 158 u8 TUNSEL1_ff; 159 160 } bcm3510_register_value; 161 162 /* HAB commands */ 163 164 /* version */ 165 #define CMD_GET_VERSION_INFO 0x3D 166 #define MSGID_GET_VERSION_INFO 0x15 167 struct bcm3510_hab_cmd_get_version_info { 168 u8 microcode_version; 169 u8 script_version; 170 u8 config_version; 171 u8 demod_version; 172 } PACKED; 173 174 #define BCM3510_DEF_MICROCODE_VERSION 0x0E 175 #define BCM3510_DEF_SCRIPT_VERSION 0x06 176 #define BCM3510_DEF_CONFIG_VERSION 0x01 177 #define BCM3510_DEF_DEMOD_VERSION 0xB1 178 179 /* acquire */ 180 #define CMD_ACQUIRE 0x38 181 182 #define MSGID_EXT_TUNER_ACQUIRE 0x0A 183 struct bcm3510_hab_cmd_ext_acquire { 184 struct { 185 u8 MODE :4; 186 u8 BW :1; 187 u8 FA :1; 188 u8 NTSCSWEEP :1; 189 u8 OFFSET :1; 190 } PACKED ACQUIRE0; /* control_byte */ 191 192 struct { 193 u8 IF_FREQ :3; 194 u8 zero0 :1; 195 u8 SYM_RATE :3; 196 u8 zero1 :1; 197 } PACKED ACQUIRE1; /* sym_if */ 198 199 u8 IF_OFFSET0; /* IF_Offset_10hz */ 200 u8 IF_OFFSET1; 201 u8 SYM_OFFSET0; /* SymbolRateOffset */ 202 u8 SYM_OFFSET1; 203 u8 NTSC_OFFSET0; /* NTSC_Offset_10hz */ 204 u8 NTSC_OFFSET1; 205 } PACKED; 206 207 #define MSGID_INT_TUNER_ACQUIRE 0x0B 208 struct bcm3510_hab_cmd_int_acquire { 209 struct { 210 u8 MODE :4; 211 u8 BW :1; 212 u8 FA :1; 213 u8 NTSCSWEEP :1; 214 u8 OFFSET :1; 215 } PACKED ACQUIRE0; /* control_byte */ 216 217 struct { 218 u8 IF_FREQ :3; 219 u8 zero0 :1; 220 u8 SYM_RATE :3; 221 u8 zero1 :1; 222 } PACKED ACQUIRE1; /* sym_if */ 223 224 u8 TUNER_FREQ0; 225 u8 TUNER_FREQ1; 226 u8 TUNER_FREQ2; 227 u8 TUNER_FREQ3; 228 u8 IF_OFFSET0; /* IF_Offset_10hz */ 229 u8 IF_OFFSET1; 230 u8 SYM_OFFSET0; /* SymbolRateOffset */ 231 u8 SYM_OFFSET1; 232 u8 NTSC_OFFSET0; /* NTSC_Offset_10hz */ 233 u8 NTSC_OFFSET1; 234 } PACKED; 235 236 /* modes */ 237 #define BCM3510_QAM16 = 0x01 238 #define BCM3510_QAM32 = 0x02 239 #define BCM3510_QAM64 = 0x03 240 #define BCM3510_QAM128 = 0x04 241 #define BCM3510_QAM256 = 0x05 242 #define BCM3510_8VSB = 0x0B 243 #define BCM3510_16VSB = 0x0D 244 245 /* IF_FREQS */ 246 #define BCM3510_IF_TERRESTRIAL 0x0 247 #define BCM3510_IF_CABLE 0x1 248 #define BCM3510_IF_USE_CMD 0x7 249 250 /* SYM_RATE */ 251 #define BCM3510_SR_8VSB 0x0 /* 5381119 s/sec */ 252 #define BCM3510_SR_256QAM 0x1 /* 5360537 s/sec */ 253 #define BCM3510_SR_16QAM 0x2 /* 5056971 s/sec */ 254 #define BCM3510_SR_MISC 0x3 /* 5000000 s/sec */ 255 #define BCM3510_SR_USE_CMD 0x7 256 257 /* special symbol rate */ 258 #define CMD_SET_VALUE_NOT_LISTED 0x2d 259 #define MSGID_SET_SYMBOL_RATE_NOT_LISTED 0x0c 260 struct bcm3510_hab_cmd_set_sr_not_listed { 261 u8 HOST_SYM_RATE0; 262 u8 HOST_SYM_RATE1; 263 u8 HOST_SYM_RATE2; 264 u8 HOST_SYM_RATE3; 265 } PACKED; 266 267 /* special IF */ 268 #define MSGID_SET_IF_FREQ_NOT_LISTED 0x0d 269 struct bcm3510_hab_cmd_set_if_freq_not_listed { 270 u8 HOST_IF_FREQ0; 271 u8 HOST_IF_FREQ1; 272 u8 HOST_IF_FREQ2; 273 u8 HOST_IF_FREQ3; 274 } PACKED; 275 276 /* auto reacquire */ 277 #define CMD_AUTO_PARAM 0x2a 278 #define MSGID_AUTO_REACQUIRE 0x0e 279 struct bcm3510_hab_cmd_auto_reacquire { 280 u8 ACQ :1; /* on/off*/ 281 u8 unused :7; 282 } PACKED; 283 284 #define MSGID_SET_RF_AGC_SEL 0x12 285 struct bcm3510_hab_cmd_set_agc { 286 u8 LVL :1; 287 u8 unused :6; 288 u8 SEL :1; 289 } PACKED; 290 291 #define MSGID_SET_AUTO_INVERSION 0x14 292 struct bcm3510_hab_cmd_auto_inversion { 293 u8 AI :1; 294 u8 unused :7; 295 } PACKED; 296 297 298 /* bert control */ 299 #define CMD_STATE_CONTROL 0x12 300 #define MSGID_BERT_CONTROL 0x0e 301 #define MSGID_BERT_SET 0xfa 302 struct bcm3510_hab_cmd_bert_control { 303 u8 BE :1; 304 u8 unused :7; 305 } PACKED; 306 307 #define MSGID_TRI_STATE 0x2e 308 struct bcm3510_hab_cmd_tri_state { 309 u8 RE :1; /* a/d ram port pins */ 310 u8 PE :1; /* baud clock pin */ 311 u8 AC :1; /* a/d clock pin */ 312 u8 BE :1; /* baud clock pin */ 313 u8 unused :4; 314 } PACKED; 315 316 317 /* tune */ 318 #define CMD_TUNE 0x38 319 #define MSGID_TUNE 0x16 320 struct bcm3510_hab_cmd_tune_ctrl_data_pair { 321 struct { 322 #define BITS_8 0x07 323 #define BITS_7 0x06 324 #define BITS_6 0x05 325 #define BITS_5 0x04 326 #define BITS_4 0x03 327 #define BITS_3 0x02 328 #define BITS_2 0x01 329 #define BITS_1 0x00 330 u8 size :3; 331 u8 unk :2; 332 u8 clk_off :1; 333 u8 cs0 :1; 334 u8 cs1 :1; 335 336 } PACKED ctrl; 337 338 u8 data; 339 } PACKED; 340 341 struct bcm3510_hab_cmd_tune { 342 u8 length; 343 u8 clock_width; 344 u8 misc; 345 u8 TUNCTL_state; 346 347 struct bcm3510_hab_cmd_tune_ctrl_data_pair ctl_dat[16]; 348 } PACKED; 349 350 #define CMD_STATUS 0x38 351 #define MSGID_STATUS1 0x08 352 struct bcm3510_hab_cmd_status1 { 353 struct { 354 u8 EQ_MODE :4; 355 u8 reserved :2; 356 u8 QRE :1; /* if QSE and the spectrum is inversed */ 357 u8 QSE :1; /* automatic spectral inversion */ 358 } PACKED STATUS0; 359 360 struct { 361 u8 RECEIVER_LOCK :1; 362 u8 FEC_LOCK :1; 363 u8 OUT_PLL_LOCK :1; 364 u8 reserved :5; 365 } PACKED STATUS1; 366 367 struct { 368 u8 reserved :2; 369 u8 BW :1; 370 u8 NTE :1; /* NTSC filter sweep enabled */ 371 u8 AQI :1; /* currently acquiring */ 372 u8 FA :1; /* fast acquisition */ 373 u8 ARI :1; /* auto reacquire */ 374 u8 TI :1; /* programming the tuner */ 375 } PACKED STATUS2; 376 u8 STATUS3; 377 u8 SNR_EST0; 378 u8 SNR_EST1; 379 u8 TUNER_FREQ0; 380 u8 TUNER_FREQ1; 381 u8 TUNER_FREQ2; 382 u8 TUNER_FREQ3; 383 u8 SYM_RATE0; 384 u8 SYM_RATE1; 385 u8 SYM_RATE2; 386 u8 SYM_RATE3; 387 u8 SYM_OFFSET0; 388 u8 SYM_OFFSET1; 389 u8 SYM_ERROR0; 390 u8 SYM_ERROR1; 391 u8 IF_FREQ0; 392 u8 IF_FREQ1; 393 u8 IF_FREQ2; 394 u8 IF_FREQ3; 395 u8 IF_OFFSET0; 396 u8 IF_OFFSET1; 397 u8 IF_ERROR0; 398 u8 IF_ERROR1; 399 u8 NTSC_FILTER0; 400 u8 NTSC_FILTER1; 401 u8 NTSC_FILTER2; 402 u8 NTSC_FILTER3; 403 u8 NTSC_OFFSET0; 404 u8 NTSC_OFFSET1; 405 u8 NTSC_ERROR0; 406 u8 NTSC_ERROR1; 407 u8 INT_AGC_LEVEL0; 408 u8 INT_AGC_LEVEL1; 409 u8 EXT_AGC_LEVEL0; 410 u8 EXT_AGC_LEVEL1; 411 } PACKED; 412 413 #define MSGID_STATUS2 0x14 414 struct bcm3510_hab_cmd_status2 { 415 struct { 416 u8 EQ_MODE :4; 417 u8 reserved :2; 418 u8 QRE :1; 419 u8 QSR :1; 420 } PACKED STATUS0; 421 struct { 422 u8 RL :1; 423 u8 FL :1; 424 u8 OL :1; 425 u8 reserved :5; 426 } PACKED STATUS1; 427 u8 SYMBOL_RATE0; 428 u8 SYMBOL_RATE1; 429 u8 SYMBOL_RATE2; 430 u8 SYMBOL_RATE3; 431 u8 LDCERC0; 432 u8 LDCERC1; 433 u8 LDCERC2; 434 u8 LDCERC3; 435 u8 LDUERC0; 436 u8 LDUERC1; 437 u8 LDUERC2; 438 u8 LDUERC3; 439 u8 LDBER0; 440 u8 LDBER1; 441 u8 LDBER2; 442 u8 LDBER3; 443 struct { 444 u8 MODE_TYPE :4; /* acquire mode 0 */ 445 u8 reservd :4; 446 } MODE_TYPE; 447 u8 SNR_EST0; 448 u8 SNR_EST1; 449 u8 SIGNAL; 450 } PACKED; 451 452 #define CMD_SET_RF_BW_NOT_LISTED 0x3f 453 #define MSGID_SET_RF_BW_NOT_LISTED 0x11 454 /* TODO */ 455 456 #endif 457