1 /* 2 * ascot2e.c 3 * 4 * Sony Ascot3E DVB-T/T2/C/C2 tuner driver 5 * 6 * Copyright 2012 Sony Corporation 7 * Copyright (C) 2014 NetUP Inc. 8 * Copyright (C) 2014 Sergey Kozlov <serjk@netup.ru> 9 * Copyright (C) 2014 Abylay Ospan <aospan@netup.ru> 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License, or 14 * (at your option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 */ 21 22 #include <linux/slab.h> 23 #include <linux/module.h> 24 #include <linux/dvb/frontend.h> 25 #include <linux/types.h> 26 #include "ascot2e.h" 27 #include <media/dvb_frontend.h> 28 29 #define MAX_WRITE_REGSIZE 10 30 31 enum ascot2e_state { 32 STATE_UNKNOWN, 33 STATE_SLEEP, 34 STATE_ACTIVE 35 }; 36 37 struct ascot2e_priv { 38 u32 frequency; 39 u8 i2c_address; 40 struct i2c_adapter *i2c; 41 enum ascot2e_state state; 42 void *set_tuner_data; 43 int (*set_tuner)(void *, int); 44 }; 45 46 enum ascot2e_tv_system_t { 47 ASCOT2E_DTV_DVBT_5, 48 ASCOT2E_DTV_DVBT_6, 49 ASCOT2E_DTV_DVBT_7, 50 ASCOT2E_DTV_DVBT_8, 51 ASCOT2E_DTV_DVBT2_1_7, 52 ASCOT2E_DTV_DVBT2_5, 53 ASCOT2E_DTV_DVBT2_6, 54 ASCOT2E_DTV_DVBT2_7, 55 ASCOT2E_DTV_DVBT2_8, 56 ASCOT2E_DTV_DVBC_6, 57 ASCOT2E_DTV_DVBC_8, 58 ASCOT2E_DTV_DVBC2_6, 59 ASCOT2E_DTV_DVBC2_8, 60 ASCOT2E_DTV_UNKNOWN 61 }; 62 63 struct ascot2e_band_sett { 64 u8 if_out_sel; 65 u8 agc_sel; 66 u8 mix_oll; 67 u8 rf_gain; 68 u8 if_bpf_gc; 69 u8 fif_offset; 70 u8 bw_offset; 71 u8 bw; 72 u8 rf_oldet; 73 u8 if_bpf_f0; 74 }; 75 76 #define ASCOT2E_AUTO 0xff 77 #define ASCOT2E_OFFSET(ofs) ((u8)(ofs) & 0x1F) 78 #define ASCOT2E_BW_6 0x00 79 #define ASCOT2E_BW_7 0x01 80 #define ASCOT2E_BW_8 0x02 81 #define ASCOT2E_BW_1_7 0x03 82 83 static struct ascot2e_band_sett ascot2e_sett[] = { 84 { ASCOT2E_AUTO, ASCOT2E_AUTO, 0x03, ASCOT2E_AUTO, 0x06, 85 ASCOT2E_OFFSET(-8), ASCOT2E_OFFSET(-6), ASCOT2E_BW_6, 0x0B, 0x00 }, 86 { ASCOT2E_AUTO, ASCOT2E_AUTO, 0x03, ASCOT2E_AUTO, 0x06, 87 ASCOT2E_OFFSET(-8), ASCOT2E_OFFSET(-6), ASCOT2E_BW_6, 0x0B, 0x00 }, 88 { ASCOT2E_AUTO, ASCOT2E_AUTO, 0x03, ASCOT2E_AUTO, 0x06, 89 ASCOT2E_OFFSET(-6), ASCOT2E_OFFSET(-4), ASCOT2E_BW_7, 0x0B, 0x00 }, 90 { ASCOT2E_AUTO, ASCOT2E_AUTO, 0x03, ASCOT2E_AUTO, 0x06, 91 ASCOT2E_OFFSET(-4), ASCOT2E_OFFSET(-2), ASCOT2E_BW_8, 0x0B, 0x00 }, 92 { ASCOT2E_AUTO, ASCOT2E_AUTO, 0x03, ASCOT2E_AUTO, 0x06, 93 ASCOT2E_OFFSET(-10), ASCOT2E_OFFSET(-16), ASCOT2E_BW_1_7, 0x0B, 0x00 }, 94 { ASCOT2E_AUTO, ASCOT2E_AUTO, 0x03, ASCOT2E_AUTO, 0x06, 95 ASCOT2E_OFFSET(-8), ASCOT2E_OFFSET(-6), ASCOT2E_BW_6, 0x0B, 0x00 }, 96 { ASCOT2E_AUTO, ASCOT2E_AUTO, 0x03, ASCOT2E_AUTO, 0x06, 97 ASCOT2E_OFFSET(-8), ASCOT2E_OFFSET(-6), ASCOT2E_BW_6, 0x0B, 0x00 }, 98 { ASCOT2E_AUTO, ASCOT2E_AUTO, 0x03, ASCOT2E_AUTO, 0x06, 99 ASCOT2E_OFFSET(-6), ASCOT2E_OFFSET(-4), ASCOT2E_BW_7, 0x0B, 0x00 }, 100 { ASCOT2E_AUTO, ASCOT2E_AUTO, 0x03, ASCOT2E_AUTO, 0x06, 101 ASCOT2E_OFFSET(-4), ASCOT2E_OFFSET(-2), ASCOT2E_BW_8, 0x0B, 0x00 }, 102 { ASCOT2E_AUTO, ASCOT2E_AUTO, 0x02, ASCOT2E_AUTO, 0x03, 103 ASCOT2E_OFFSET(-6), ASCOT2E_OFFSET(-8), ASCOT2E_BW_6, 0x09, 0x00 }, 104 { ASCOT2E_AUTO, ASCOT2E_AUTO, 0x02, ASCOT2E_AUTO, 0x03, 105 ASCOT2E_OFFSET(-2), ASCOT2E_OFFSET(-1), ASCOT2E_BW_8, 0x09, 0x00 }, 106 { ASCOT2E_AUTO, ASCOT2E_AUTO, 0x03, ASCOT2E_AUTO, 0x01, 107 ASCOT2E_OFFSET(-6), ASCOT2E_OFFSET(-4), ASCOT2E_BW_6, 0x09, 0x00 }, 108 { ASCOT2E_AUTO, ASCOT2E_AUTO, 0x03, ASCOT2E_AUTO, 0x01, 109 ASCOT2E_OFFSET(-2), ASCOT2E_OFFSET(2), ASCOT2E_BW_8, 0x09, 0x00 } 110 }; 111 112 static void ascot2e_i2c_debug(struct ascot2e_priv *priv, 113 u8 reg, u8 write, const u8 *data, u32 len) 114 { 115 dev_dbg(&priv->i2c->dev, "ascot2e: I2C %s reg 0x%02x size %d\n", 116 (write == 0 ? "read" : "write"), reg, len); 117 print_hex_dump_bytes("ascot2e: I2C data: ", 118 DUMP_PREFIX_OFFSET, data, len); 119 } 120 121 static int ascot2e_write_regs(struct ascot2e_priv *priv, 122 u8 reg, const u8 *data, u32 len) 123 { 124 int ret; 125 u8 buf[MAX_WRITE_REGSIZE + 1]; 126 struct i2c_msg msg[1] = { 127 { 128 .addr = priv->i2c_address, 129 .flags = 0, 130 .len = len + 1, 131 .buf = buf, 132 } 133 }; 134 135 if (len + 1 > sizeof(buf)) { 136 dev_warn(&priv->i2c->dev,"wr reg=%04x: len=%d is too big!\n", 137 reg, len + 1); 138 return -E2BIG; 139 } 140 141 ascot2e_i2c_debug(priv, reg, 1, data, len); 142 buf[0] = reg; 143 memcpy(&buf[1], data, len); 144 ret = i2c_transfer(priv->i2c, msg, 1); 145 if (ret >= 0 && ret != 1) 146 ret = -EREMOTEIO; 147 if (ret < 0) { 148 dev_warn(&priv->i2c->dev, 149 "%s: i2c wr failed=%d reg=%02x len=%d\n", 150 KBUILD_MODNAME, ret, reg, len); 151 return ret; 152 } 153 return 0; 154 } 155 156 static int ascot2e_write_reg(struct ascot2e_priv *priv, u8 reg, u8 val) 157 { 158 u8 tmp = val; /* see gcc.gnu.org/bugzilla/show_bug.cgi?id=81715 */ 159 160 return ascot2e_write_regs(priv, reg, &tmp, 1); 161 } 162 163 static int ascot2e_read_regs(struct ascot2e_priv *priv, 164 u8 reg, u8 *val, u32 len) 165 { 166 int ret; 167 struct i2c_msg msg[2] = { 168 { 169 .addr = priv->i2c_address, 170 .flags = 0, 171 .len = 1, 172 .buf = ®, 173 }, { 174 .addr = priv->i2c_address, 175 .flags = I2C_M_RD, 176 .len = len, 177 .buf = val, 178 } 179 }; 180 181 ret = i2c_transfer(priv->i2c, &msg[0], 1); 182 if (ret >= 0 && ret != 1) 183 ret = -EREMOTEIO; 184 if (ret < 0) { 185 dev_warn(&priv->i2c->dev, 186 "%s: I2C rw failed=%d addr=%02x reg=%02x\n", 187 KBUILD_MODNAME, ret, priv->i2c_address, reg); 188 return ret; 189 } 190 ret = i2c_transfer(priv->i2c, &msg[1], 1); 191 if (ret >= 0 && ret != 1) 192 ret = -EREMOTEIO; 193 if (ret < 0) { 194 dev_warn(&priv->i2c->dev, 195 "%s: i2c rd failed=%d addr=%02x reg=%02x\n", 196 KBUILD_MODNAME, ret, priv->i2c_address, reg); 197 return ret; 198 } 199 ascot2e_i2c_debug(priv, reg, 0, val, len); 200 return 0; 201 } 202 203 static int ascot2e_read_reg(struct ascot2e_priv *priv, u8 reg, u8 *val) 204 { 205 return ascot2e_read_regs(priv, reg, val, 1); 206 } 207 208 static int ascot2e_set_reg_bits(struct ascot2e_priv *priv, 209 u8 reg, u8 data, u8 mask) 210 { 211 int res; 212 u8 rdata; 213 214 if (mask != 0xff) { 215 res = ascot2e_read_reg(priv, reg, &rdata); 216 if (res != 0) 217 return res; 218 data = ((data & mask) | (rdata & (mask ^ 0xFF))); 219 } 220 return ascot2e_write_reg(priv, reg, data); 221 } 222 223 static int ascot2e_enter_power_save(struct ascot2e_priv *priv) 224 { 225 u8 data[2]; 226 227 dev_dbg(&priv->i2c->dev, "%s()\n", __func__); 228 if (priv->state == STATE_SLEEP) 229 return 0; 230 data[0] = 0x00; 231 data[1] = 0x04; 232 ascot2e_write_regs(priv, 0x14, data, 2); 233 ascot2e_write_reg(priv, 0x50, 0x01); 234 priv->state = STATE_SLEEP; 235 return 0; 236 } 237 238 static int ascot2e_leave_power_save(struct ascot2e_priv *priv) 239 { 240 u8 data[2] = { 0xFB, 0x0F }; 241 242 dev_dbg(&priv->i2c->dev, "%s()\n", __func__); 243 if (priv->state == STATE_ACTIVE) 244 return 0; 245 ascot2e_write_regs(priv, 0x14, data, 2); 246 ascot2e_write_reg(priv, 0x50, 0x00); 247 priv->state = STATE_ACTIVE; 248 return 0; 249 } 250 251 static int ascot2e_init(struct dvb_frontend *fe) 252 { 253 struct ascot2e_priv *priv = fe->tuner_priv; 254 255 dev_dbg(&priv->i2c->dev, "%s()\n", __func__); 256 return ascot2e_leave_power_save(priv); 257 } 258 259 static void ascot2e_release(struct dvb_frontend *fe) 260 { 261 struct ascot2e_priv *priv = fe->tuner_priv; 262 263 dev_dbg(&priv->i2c->dev, "%s()\n", __func__); 264 kfree(fe->tuner_priv); 265 fe->tuner_priv = NULL; 266 } 267 268 static int ascot2e_sleep(struct dvb_frontend *fe) 269 { 270 struct ascot2e_priv *priv = fe->tuner_priv; 271 272 dev_dbg(&priv->i2c->dev, "%s()\n", __func__); 273 ascot2e_enter_power_save(priv); 274 return 0; 275 } 276 277 static enum ascot2e_tv_system_t ascot2e_get_tv_system(struct dvb_frontend *fe) 278 { 279 enum ascot2e_tv_system_t system = ASCOT2E_DTV_UNKNOWN; 280 struct dtv_frontend_properties *p = &fe->dtv_property_cache; 281 struct ascot2e_priv *priv = fe->tuner_priv; 282 283 if (p->delivery_system == SYS_DVBT) { 284 if (p->bandwidth_hz <= 5000000) 285 system = ASCOT2E_DTV_DVBT_5; 286 else if (p->bandwidth_hz <= 6000000) 287 system = ASCOT2E_DTV_DVBT_6; 288 else if (p->bandwidth_hz <= 7000000) 289 system = ASCOT2E_DTV_DVBT_7; 290 else if (p->bandwidth_hz <= 8000000) 291 system = ASCOT2E_DTV_DVBT_8; 292 else { 293 system = ASCOT2E_DTV_DVBT_8; 294 p->bandwidth_hz = 8000000; 295 } 296 } else if (p->delivery_system == SYS_DVBT2) { 297 if (p->bandwidth_hz <= 5000000) 298 system = ASCOT2E_DTV_DVBT2_5; 299 else if (p->bandwidth_hz <= 6000000) 300 system = ASCOT2E_DTV_DVBT2_6; 301 else if (p->bandwidth_hz <= 7000000) 302 system = ASCOT2E_DTV_DVBT2_7; 303 else if (p->bandwidth_hz <= 8000000) 304 system = ASCOT2E_DTV_DVBT2_8; 305 else { 306 system = ASCOT2E_DTV_DVBT2_8; 307 p->bandwidth_hz = 8000000; 308 } 309 } else if (p->delivery_system == SYS_DVBC_ANNEX_A) { 310 if (p->bandwidth_hz <= 6000000) 311 system = ASCOT2E_DTV_DVBC_6; 312 else if (p->bandwidth_hz <= 8000000) 313 system = ASCOT2E_DTV_DVBC_8; 314 } 315 dev_dbg(&priv->i2c->dev, 316 "%s(): ASCOT2E DTV system %d (delsys %d, bandwidth %d)\n", 317 __func__, (int)system, p->delivery_system, p->bandwidth_hz); 318 return system; 319 } 320 321 static int ascot2e_set_params(struct dvb_frontend *fe) 322 { 323 u8 data[10]; 324 u32 frequency; 325 enum ascot2e_tv_system_t tv_system; 326 struct dtv_frontend_properties *p = &fe->dtv_property_cache; 327 struct ascot2e_priv *priv = fe->tuner_priv; 328 329 dev_dbg(&priv->i2c->dev, "%s(): tune frequency %dkHz\n", 330 __func__, p->frequency / 1000); 331 tv_system = ascot2e_get_tv_system(fe); 332 333 if (tv_system == ASCOT2E_DTV_UNKNOWN) { 334 dev_dbg(&priv->i2c->dev, "%s(): unknown DTV system\n", 335 __func__); 336 return -EINVAL; 337 } 338 if (priv->set_tuner) 339 priv->set_tuner(priv->set_tuner_data, 1); 340 frequency = roundup(p->frequency / 1000, 25); 341 if (priv->state == STATE_SLEEP) 342 ascot2e_leave_power_save(priv); 343 344 /* IF_OUT_SEL / AGC_SEL setting */ 345 data[0] = 0x00; 346 if (ascot2e_sett[tv_system].agc_sel != ASCOT2E_AUTO) { 347 /* AGC pin setting from parameter table */ 348 data[0] |= (u8)( 349 (ascot2e_sett[tv_system].agc_sel & 0x03) << 3); 350 } 351 if (ascot2e_sett[tv_system].if_out_sel != ASCOT2E_AUTO) { 352 /* IFOUT pin setting from parameter table */ 353 data[0] |= (u8)( 354 (ascot2e_sett[tv_system].if_out_sel & 0x01) << 2); 355 } 356 /* Set bit[4:2] only */ 357 ascot2e_set_reg_bits(priv, 0x05, data[0], 0x1c); 358 /* 0x06 - 0x0F */ 359 /* REF_R setting (0x06) */ 360 if (tv_system == ASCOT2E_DTV_DVBC_6 || 361 tv_system == ASCOT2E_DTV_DVBC_8) { 362 /* xtal, xtal*2 */ 363 data[0] = (frequency > 500000) ? 16 : 32; 364 } else { 365 /* xtal/8, xtal/4 */ 366 data[0] = (frequency > 500000) ? 2 : 4; 367 } 368 /* XOSC_SEL=100uA */ 369 data[1] = 0x04; 370 /* KBW setting (0x08), KC0 setting (0x09), KC1 setting (0x0A) */ 371 if (tv_system == ASCOT2E_DTV_DVBC_6 || 372 tv_system == ASCOT2E_DTV_DVBC_8) { 373 data[2] = 18; 374 data[3] = 120; 375 data[4] = 20; 376 } else { 377 data[2] = 48; 378 data[3] = 10; 379 data[4] = 30; 380 } 381 /* ORDER/R2_RANGE/R2_BANK/C2_BANK setting (0x0B) */ 382 if (tv_system == ASCOT2E_DTV_DVBC_6 || 383 tv_system == ASCOT2E_DTV_DVBC_8) 384 data[5] = (frequency > 500000) ? 0x08 : 0x0c; 385 else 386 data[5] = (frequency > 500000) ? 0x30 : 0x38; 387 /* Set MIX_OLL (0x0C) value from parameter table */ 388 data[6] = ascot2e_sett[tv_system].mix_oll; 389 /* Set RF_GAIN (0x0D) setting from parameter table */ 390 if (ascot2e_sett[tv_system].rf_gain == ASCOT2E_AUTO) { 391 /* RF_GAIN auto control enable */ 392 ascot2e_write_reg(priv, 0x4E, 0x01); 393 /* RF_GAIN Default value */ 394 data[7] = 0x00; 395 } else { 396 /* RF_GAIN auto control disable */ 397 ascot2e_write_reg(priv, 0x4E, 0x00); 398 data[7] = ascot2e_sett[tv_system].rf_gain; 399 } 400 /* Set IF_BPF_GC/FIF_OFFSET (0x0E) value from parameter table */ 401 data[8] = (u8)((ascot2e_sett[tv_system].fif_offset << 3) | 402 (ascot2e_sett[tv_system].if_bpf_gc & 0x07)); 403 /* Set BW_OFFSET (0x0F) value from parameter table */ 404 data[9] = ascot2e_sett[tv_system].bw_offset; 405 ascot2e_write_regs(priv, 0x06, data, 10); 406 /* 407 * 0x45 - 0x47 408 * LNA optimization setting 409 * RF_LNA_DIST1-5, RF_LNA_CM 410 */ 411 if (tv_system == ASCOT2E_DTV_DVBC_6 || 412 tv_system == ASCOT2E_DTV_DVBC_8) { 413 data[0] = 0x0F; 414 data[1] = 0x00; 415 data[2] = 0x01; 416 } else { 417 data[0] = 0x0F; 418 data[1] = 0x00; 419 data[2] = 0x03; 420 } 421 ascot2e_write_regs(priv, 0x45, data, 3); 422 /* 0x49 - 0x4A 423 Set RF_OLDET_ENX/RF_OLDET_OLL value from parameter table */ 424 data[0] = ascot2e_sett[tv_system].rf_oldet; 425 /* Set IF_BPF_F0 value from parameter table */ 426 data[1] = ascot2e_sett[tv_system].if_bpf_f0; 427 ascot2e_write_regs(priv, 0x49, data, 2); 428 /* 429 * Tune now 430 * RFAGC fast mode / RFAGC auto control enable 431 * (set bit[7], bit[5:4] only) 432 * vco_cal = 1, set MIX_OL_CPU_EN 433 */ 434 ascot2e_set_reg_bits(priv, 0x0c, 0x90, 0xb0); 435 /* Logic wake up, CPU wake up */ 436 data[0] = 0xc4; 437 data[1] = 0x40; 438 ascot2e_write_regs(priv, 0x03, data, 2); 439 /* 0x10 - 0x14 */ 440 data[0] = (u8)(frequency & 0xFF); /* 0x10: FRF_L */ 441 data[1] = (u8)((frequency >> 8) & 0xFF); /* 0x11: FRF_M */ 442 data[2] = (u8)((frequency >> 16) & 0x0F); /* 0x12: FRF_H (bit[3:0]) */ 443 /* 0x12: BW (bit[5:4]) */ 444 data[2] |= (u8)(ascot2e_sett[tv_system].bw << 4); 445 data[3] = 0xFF; /* 0x13: VCO calibration enable */ 446 data[4] = 0xFF; /* 0x14: Analog block enable */ 447 /* Tune (Burst write) */ 448 ascot2e_write_regs(priv, 0x10, data, 5); 449 msleep(50); 450 /* CPU deep sleep */ 451 ascot2e_write_reg(priv, 0x04, 0x00); 452 /* Logic sleep */ 453 ascot2e_write_reg(priv, 0x03, 0xC0); 454 /* RFAGC normal mode (set bit[5:4] only) */ 455 ascot2e_set_reg_bits(priv, 0x0C, 0x00, 0x30); 456 priv->frequency = frequency; 457 return 0; 458 } 459 460 static int ascot2e_get_frequency(struct dvb_frontend *fe, u32 *frequency) 461 { 462 struct ascot2e_priv *priv = fe->tuner_priv; 463 464 *frequency = priv->frequency * 1000; 465 return 0; 466 } 467 468 static const struct dvb_tuner_ops ascot2e_tuner_ops = { 469 .info = { 470 .name = "Sony ASCOT2E", 471 .frequency_min = 1000000, 472 .frequency_max = 1200000000, 473 .frequency_step = 25000, 474 }, 475 .init = ascot2e_init, 476 .release = ascot2e_release, 477 .sleep = ascot2e_sleep, 478 .set_params = ascot2e_set_params, 479 .get_frequency = ascot2e_get_frequency, 480 }; 481 482 struct dvb_frontend *ascot2e_attach(struct dvb_frontend *fe, 483 const struct ascot2e_config *config, 484 struct i2c_adapter *i2c) 485 { 486 u8 data[4]; 487 struct ascot2e_priv *priv = NULL; 488 489 priv = kzalloc(sizeof(struct ascot2e_priv), GFP_KERNEL); 490 if (priv == NULL) 491 return NULL; 492 priv->i2c_address = (config->i2c_address >> 1); 493 priv->i2c = i2c; 494 priv->set_tuner_data = config->set_tuner_priv; 495 priv->set_tuner = config->set_tuner_callback; 496 497 if (fe->ops.i2c_gate_ctrl) 498 fe->ops.i2c_gate_ctrl(fe, 1); 499 500 /* 16 MHz xTal frequency */ 501 data[0] = 16; 502 /* VCO current setting */ 503 data[1] = 0x06; 504 /* Logic wake up, CPU boot */ 505 data[2] = 0xC4; 506 data[3] = 0x40; 507 ascot2e_write_regs(priv, 0x01, data, 4); 508 /* RFVGA optimization setting (RF_DIST0 - RF_DIST2) */ 509 data[0] = 0x10; 510 data[1] = 0x3F; 511 data[2] = 0x25; 512 ascot2e_write_regs(priv, 0x22, data, 3); 513 /* PLL mode setting */ 514 ascot2e_write_reg(priv, 0x28, 0x1e); 515 /* RSSI setting */ 516 ascot2e_write_reg(priv, 0x59, 0x04); 517 /* TODO check CPU HW error state here */ 518 msleep(80); 519 /* Xtal oscillator current control setting */ 520 ascot2e_write_reg(priv, 0x4c, 0x01); 521 /* XOSC_SEL=100uA */ 522 ascot2e_write_reg(priv, 0x07, 0x04); 523 /* CPU deep sleep */ 524 ascot2e_write_reg(priv, 0x04, 0x00); 525 /* Logic sleep */ 526 ascot2e_write_reg(priv, 0x03, 0xc0); 527 /* Power save setting */ 528 data[0] = 0x00; 529 data[1] = 0x04; 530 ascot2e_write_regs(priv, 0x14, data, 2); 531 ascot2e_write_reg(priv, 0x50, 0x01); 532 priv->state = STATE_SLEEP; 533 534 if (fe->ops.i2c_gate_ctrl) 535 fe->ops.i2c_gate_ctrl(fe, 0); 536 537 memcpy(&fe->ops.tuner_ops, &ascot2e_tuner_ops, 538 sizeof(struct dvb_tuner_ops)); 539 fe->tuner_priv = priv; 540 dev_info(&priv->i2c->dev, 541 "Sony ASCOT2E attached on addr=%x at I2C adapter %p\n", 542 priv->i2c_address, priv->i2c); 543 return fe; 544 } 545 EXPORT_SYMBOL(ascot2e_attach); 546 547 MODULE_DESCRIPTION("Sony ASCOT2E terr/cab tuner driver"); 548 MODULE_AUTHOR("info@netup.ru"); 549 MODULE_LICENSE("GPL"); 550