1 /* 2 * Afatech AF9033 demodulator driver 3 * 4 * Copyright (C) 2009 Antti Palosaari <crope@iki.fi> 5 * Copyright (C) 2012 Antti Palosaari <crope@iki.fi> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License along 18 * with this program; if not, write to the Free Software Foundation, Inc., 19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. 20 */ 21 22 #include "af9033_priv.h" 23 24 struct af9033_state { 25 struct i2c_adapter *i2c; 26 struct dvb_frontend fe; 27 struct af9033_config cfg; 28 29 u32 bandwidth_hz; 30 bool ts_mode_parallel; 31 bool ts_mode_serial; 32 33 u32 ber; 34 u32 ucb; 35 unsigned long last_stat_check; 36 }; 37 38 /* write multiple registers */ 39 static int af9033_wr_regs(struct af9033_state *state, u32 reg, const u8 *val, 40 int len) 41 { 42 int ret; 43 u8 buf[3 + len]; 44 struct i2c_msg msg[1] = { 45 { 46 .addr = state->cfg.i2c_addr, 47 .flags = 0, 48 .len = sizeof(buf), 49 .buf = buf, 50 } 51 }; 52 53 buf[0] = (reg >> 16) & 0xff; 54 buf[1] = (reg >> 8) & 0xff; 55 buf[2] = (reg >> 0) & 0xff; 56 memcpy(&buf[3], val, len); 57 58 ret = i2c_transfer(state->i2c, msg, 1); 59 if (ret == 1) { 60 ret = 0; 61 } else { 62 dev_warn(&state->i2c->dev, "%s: i2c wr failed=%d reg=%06x " \ 63 "len=%d\n", KBUILD_MODNAME, ret, reg, len); 64 ret = -EREMOTEIO; 65 } 66 67 return ret; 68 } 69 70 /* read multiple registers */ 71 static int af9033_rd_regs(struct af9033_state *state, u32 reg, u8 *val, int len) 72 { 73 int ret; 74 u8 buf[3] = { (reg >> 16) & 0xff, (reg >> 8) & 0xff, 75 (reg >> 0) & 0xff }; 76 struct i2c_msg msg[2] = { 77 { 78 .addr = state->cfg.i2c_addr, 79 .flags = 0, 80 .len = sizeof(buf), 81 .buf = buf 82 }, { 83 .addr = state->cfg.i2c_addr, 84 .flags = I2C_M_RD, 85 .len = len, 86 .buf = val 87 } 88 }; 89 90 ret = i2c_transfer(state->i2c, msg, 2); 91 if (ret == 2) { 92 ret = 0; 93 } else { 94 dev_warn(&state->i2c->dev, "%s: i2c rd failed=%d reg=%06x " \ 95 "len=%d\n", KBUILD_MODNAME, ret, reg, len); 96 ret = -EREMOTEIO; 97 } 98 99 return ret; 100 } 101 102 103 /* write single register */ 104 static int af9033_wr_reg(struct af9033_state *state, u32 reg, u8 val) 105 { 106 return af9033_wr_regs(state, reg, &val, 1); 107 } 108 109 /* read single register */ 110 static int af9033_rd_reg(struct af9033_state *state, u32 reg, u8 *val) 111 { 112 return af9033_rd_regs(state, reg, val, 1); 113 } 114 115 /* write single register with mask */ 116 static int af9033_wr_reg_mask(struct af9033_state *state, u32 reg, u8 val, 117 u8 mask) 118 { 119 int ret; 120 u8 tmp; 121 122 /* no need for read if whole reg is written */ 123 if (mask != 0xff) { 124 ret = af9033_rd_regs(state, reg, &tmp, 1); 125 if (ret) 126 return ret; 127 128 val &= mask; 129 tmp &= ~mask; 130 val |= tmp; 131 } 132 133 return af9033_wr_regs(state, reg, &val, 1); 134 } 135 136 /* read single register with mask */ 137 static int af9033_rd_reg_mask(struct af9033_state *state, u32 reg, u8 *val, 138 u8 mask) 139 { 140 int ret, i; 141 u8 tmp; 142 143 ret = af9033_rd_regs(state, reg, &tmp, 1); 144 if (ret) 145 return ret; 146 147 tmp &= mask; 148 149 /* find position of the first bit */ 150 for (i = 0; i < 8; i++) { 151 if ((mask >> i) & 0x01) 152 break; 153 } 154 *val = tmp >> i; 155 156 return 0; 157 } 158 159 /* write reg val table using reg addr auto increment */ 160 static int af9033_wr_reg_val_tab(struct af9033_state *state, 161 const struct reg_val *tab, int tab_len) 162 { 163 int ret, i, j; 164 u8 buf[tab_len]; 165 166 dev_dbg(&state->i2c->dev, "%s: tab_len=%d\n", __func__, tab_len); 167 168 for (i = 0, j = 0; i < tab_len; i++) { 169 buf[j] = tab[i].val; 170 171 if (i == tab_len - 1 || tab[i].reg != tab[i + 1].reg - 1) { 172 ret = af9033_wr_regs(state, tab[i].reg - j, buf, j + 1); 173 if (ret < 0) 174 goto err; 175 176 j = 0; 177 } else { 178 j++; 179 } 180 } 181 182 return 0; 183 184 err: 185 dev_dbg(&state->i2c->dev, "%s: failed=%d\n", __func__, ret); 186 187 return ret; 188 } 189 190 static u32 af9033_div(struct af9033_state *state, u32 a, u32 b, u32 x) 191 { 192 u32 r = 0, c = 0, i; 193 194 dev_dbg(&state->i2c->dev, "%s: a=%d b=%d x=%d\n", __func__, a, b, x); 195 196 if (a > b) { 197 c = a / b; 198 a = a - c * b; 199 } 200 201 for (i = 0; i < x; i++) { 202 if (a >= b) { 203 r += 1; 204 a -= b; 205 } 206 a <<= 1; 207 r <<= 1; 208 } 209 r = (c << (u32)x) + r; 210 211 dev_dbg(&state->i2c->dev, "%s: a=%d b=%d x=%d r=%d r=%x\n", 212 __func__, a, b, x, r, r); 213 214 return r; 215 } 216 217 static void af9033_release(struct dvb_frontend *fe) 218 { 219 struct af9033_state *state = fe->demodulator_priv; 220 221 kfree(state); 222 } 223 224 static int af9033_init(struct dvb_frontend *fe) 225 { 226 struct af9033_state *state = fe->demodulator_priv; 227 int ret, i, len; 228 const struct reg_val *init; 229 u8 buf[4]; 230 u32 adc_cw, clock_cw; 231 struct reg_val_mask tab[] = { 232 { 0x80fb24, 0x00, 0x08 }, 233 { 0x80004c, 0x00, 0xff }, 234 { 0x00f641, state->cfg.tuner, 0xff }, 235 { 0x80f5ca, 0x01, 0x01 }, 236 { 0x80f715, 0x01, 0x01 }, 237 { 0x00f41f, 0x04, 0x04 }, 238 { 0x00f41a, 0x01, 0x01 }, 239 { 0x80f731, 0x00, 0x01 }, 240 { 0x00d91e, 0x00, 0x01 }, 241 { 0x00d919, 0x00, 0x01 }, 242 { 0x80f732, 0x00, 0x01 }, 243 { 0x00d91f, 0x00, 0x01 }, 244 { 0x00d91a, 0x00, 0x01 }, 245 { 0x80f730, 0x00, 0x01 }, 246 { 0x80f778, 0x00, 0xff }, 247 { 0x80f73c, 0x01, 0x01 }, 248 { 0x80f776, 0x00, 0x01 }, 249 { 0x00d8fd, 0x01, 0xff }, 250 { 0x00d830, 0x01, 0xff }, 251 { 0x00d831, 0x00, 0xff }, 252 { 0x00d832, 0x00, 0xff }, 253 { 0x80f985, state->ts_mode_serial, 0x01 }, 254 { 0x80f986, state->ts_mode_parallel, 0x01 }, 255 { 0x00d827, 0x00, 0xff }, 256 { 0x00d829, 0x00, 0xff }, 257 { 0x800045, state->cfg.adc_multiplier, 0xff }, 258 }; 259 260 /* program clock control */ 261 clock_cw = af9033_div(state, state->cfg.clock, 1000000ul, 19ul); 262 buf[0] = (clock_cw >> 0) & 0xff; 263 buf[1] = (clock_cw >> 8) & 0xff; 264 buf[2] = (clock_cw >> 16) & 0xff; 265 buf[3] = (clock_cw >> 24) & 0xff; 266 267 dev_dbg(&state->i2c->dev, "%s: clock=%d clock_cw=%08x\n", 268 __func__, state->cfg.clock, clock_cw); 269 270 ret = af9033_wr_regs(state, 0x800025, buf, 4); 271 if (ret < 0) 272 goto err; 273 274 /* program ADC control */ 275 for (i = 0; i < ARRAY_SIZE(clock_adc_lut); i++) { 276 if (clock_adc_lut[i].clock == state->cfg.clock) 277 break; 278 } 279 280 adc_cw = af9033_div(state, clock_adc_lut[i].adc, 1000000ul, 19ul); 281 buf[0] = (adc_cw >> 0) & 0xff; 282 buf[1] = (adc_cw >> 8) & 0xff; 283 buf[2] = (adc_cw >> 16) & 0xff; 284 285 dev_dbg(&state->i2c->dev, "%s: adc=%d adc_cw=%06x\n", 286 __func__, clock_adc_lut[i].adc, adc_cw); 287 288 ret = af9033_wr_regs(state, 0x80f1cd, buf, 3); 289 if (ret < 0) 290 goto err; 291 292 /* program register table */ 293 for (i = 0; i < ARRAY_SIZE(tab); i++) { 294 ret = af9033_wr_reg_mask(state, tab[i].reg, tab[i].val, 295 tab[i].mask); 296 if (ret < 0) 297 goto err; 298 } 299 300 /* settings for TS interface */ 301 if (state->cfg.ts_mode == AF9033_TS_MODE_USB) { 302 ret = af9033_wr_reg_mask(state, 0x80f9a5, 0x00, 0x01); 303 if (ret < 0) 304 goto err; 305 306 ret = af9033_wr_reg_mask(state, 0x80f9b5, 0x01, 0x01); 307 if (ret < 0) 308 goto err; 309 } else { 310 ret = af9033_wr_reg_mask(state, 0x80f990, 0x00, 0x01); 311 if (ret < 0) 312 goto err; 313 314 ret = af9033_wr_reg_mask(state, 0x80f9b5, 0x00, 0x01); 315 if (ret < 0) 316 goto err; 317 } 318 319 /* load OFSM settings */ 320 dev_dbg(&state->i2c->dev, "%s: load ofsm settings\n", __func__); 321 switch (state->cfg.tuner) { 322 case AF9033_TUNER_IT9135_38: 323 case AF9033_TUNER_IT9135_51: 324 case AF9033_TUNER_IT9135_52: 325 len = ARRAY_SIZE(ofsm_init_it9135_v1); 326 init = ofsm_init_it9135_v1; 327 break; 328 case AF9033_TUNER_IT9135_60: 329 case AF9033_TUNER_IT9135_61: 330 case AF9033_TUNER_IT9135_62: 331 len = ARRAY_SIZE(ofsm_init_it9135_v2); 332 init = ofsm_init_it9135_v2; 333 break; 334 default: 335 len = ARRAY_SIZE(ofsm_init); 336 init = ofsm_init; 337 break; 338 } 339 340 ret = af9033_wr_reg_val_tab(state, init, len); 341 if (ret < 0) 342 goto err; 343 344 /* load tuner specific settings */ 345 dev_dbg(&state->i2c->dev, "%s: load tuner specific settings\n", 346 __func__); 347 switch (state->cfg.tuner) { 348 case AF9033_TUNER_TUA9001: 349 len = ARRAY_SIZE(tuner_init_tua9001); 350 init = tuner_init_tua9001; 351 break; 352 case AF9033_TUNER_FC0011: 353 len = ARRAY_SIZE(tuner_init_fc0011); 354 init = tuner_init_fc0011; 355 break; 356 case AF9033_TUNER_MXL5007T: 357 len = ARRAY_SIZE(tuner_init_mxl5007t); 358 init = tuner_init_mxl5007t; 359 break; 360 case AF9033_TUNER_TDA18218: 361 len = ARRAY_SIZE(tuner_init_tda18218); 362 init = tuner_init_tda18218; 363 break; 364 case AF9033_TUNER_FC2580: 365 len = ARRAY_SIZE(tuner_init_fc2580); 366 init = tuner_init_fc2580; 367 break; 368 case AF9033_TUNER_FC0012: 369 len = ARRAY_SIZE(tuner_init_fc0012); 370 init = tuner_init_fc0012; 371 break; 372 case AF9033_TUNER_IT9135_38: 373 len = ARRAY_SIZE(tuner_init_it9135_38); 374 init = tuner_init_it9135_38; 375 break; 376 case AF9033_TUNER_IT9135_51: 377 len = ARRAY_SIZE(tuner_init_it9135_51); 378 init = tuner_init_it9135_51; 379 break; 380 case AF9033_TUNER_IT9135_52: 381 len = ARRAY_SIZE(tuner_init_it9135_52); 382 init = tuner_init_it9135_52; 383 break; 384 case AF9033_TUNER_IT9135_60: 385 len = ARRAY_SIZE(tuner_init_it9135_60); 386 init = tuner_init_it9135_60; 387 break; 388 case AF9033_TUNER_IT9135_61: 389 len = ARRAY_SIZE(tuner_init_it9135_61); 390 init = tuner_init_it9135_61; 391 break; 392 case AF9033_TUNER_IT9135_62: 393 len = ARRAY_SIZE(tuner_init_it9135_62); 394 init = tuner_init_it9135_62; 395 break; 396 default: 397 dev_dbg(&state->i2c->dev, "%s: unsupported tuner ID=%d\n", 398 __func__, state->cfg.tuner); 399 ret = -ENODEV; 400 goto err; 401 } 402 403 ret = af9033_wr_reg_val_tab(state, init, len); 404 if (ret < 0) 405 goto err; 406 407 if (state->cfg.ts_mode == AF9033_TS_MODE_SERIAL) { 408 ret = af9033_wr_reg_mask(state, 0x00d91c, 0x01, 0x01); 409 if (ret < 0) 410 goto err; 411 412 ret = af9033_wr_reg_mask(state, 0x00d917, 0x00, 0x01); 413 if (ret < 0) 414 goto err; 415 416 ret = af9033_wr_reg_mask(state, 0x00d916, 0x00, 0x01); 417 if (ret < 0) 418 goto err; 419 } 420 421 switch (state->cfg.tuner) { 422 case AF9033_TUNER_IT9135_60: 423 case AF9033_TUNER_IT9135_61: 424 case AF9033_TUNER_IT9135_62: 425 ret = af9033_wr_reg(state, 0x800000, 0x01); 426 if (ret < 0) 427 goto err; 428 } 429 430 state->bandwidth_hz = 0; /* force to program all parameters */ 431 432 return 0; 433 434 err: 435 dev_dbg(&state->i2c->dev, "%s: failed=%d\n", __func__, ret); 436 437 return ret; 438 } 439 440 static int af9033_sleep(struct dvb_frontend *fe) 441 { 442 struct af9033_state *state = fe->demodulator_priv; 443 int ret, i; 444 u8 tmp; 445 446 ret = af9033_wr_reg(state, 0x80004c, 1); 447 if (ret < 0) 448 goto err; 449 450 ret = af9033_wr_reg(state, 0x800000, 0); 451 if (ret < 0) 452 goto err; 453 454 for (i = 100, tmp = 1; i && tmp; i--) { 455 ret = af9033_rd_reg(state, 0x80004c, &tmp); 456 if (ret < 0) 457 goto err; 458 459 usleep_range(200, 10000); 460 } 461 462 dev_dbg(&state->i2c->dev, "%s: loop=%d\n", __func__, i); 463 464 if (i == 0) { 465 ret = -ETIMEDOUT; 466 goto err; 467 } 468 469 ret = af9033_wr_reg_mask(state, 0x80fb24, 0x08, 0x08); 470 if (ret < 0) 471 goto err; 472 473 /* prevent current leak (?) */ 474 if (state->cfg.ts_mode == AF9033_TS_MODE_SERIAL) { 475 /* enable parallel TS */ 476 ret = af9033_wr_reg_mask(state, 0x00d917, 0x00, 0x01); 477 if (ret < 0) 478 goto err; 479 480 ret = af9033_wr_reg_mask(state, 0x00d916, 0x01, 0x01); 481 if (ret < 0) 482 goto err; 483 } 484 485 return 0; 486 487 err: 488 dev_dbg(&state->i2c->dev, "%s: failed=%d\n", __func__, ret); 489 490 return ret; 491 } 492 493 static int af9033_get_tune_settings(struct dvb_frontend *fe, 494 struct dvb_frontend_tune_settings *fesettings) 495 { 496 /* 800 => 2000 because IT9135 v2 is slow to gain lock */ 497 fesettings->min_delay_ms = 2000; 498 fesettings->step_size = 0; 499 fesettings->max_drift = 0; 500 501 return 0; 502 } 503 504 static int af9033_set_frontend(struct dvb_frontend *fe) 505 { 506 struct af9033_state *state = fe->demodulator_priv; 507 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 508 int ret, i, spec_inv, sampling_freq; 509 u8 tmp, buf[3], bandwidth_reg_val; 510 u32 if_frequency, freq_cw, adc_freq; 511 512 dev_dbg(&state->i2c->dev, "%s: frequency=%d bandwidth_hz=%d\n", 513 __func__, c->frequency, c->bandwidth_hz); 514 515 /* check bandwidth */ 516 switch (c->bandwidth_hz) { 517 case 6000000: 518 bandwidth_reg_val = 0x00; 519 break; 520 case 7000000: 521 bandwidth_reg_val = 0x01; 522 break; 523 case 8000000: 524 bandwidth_reg_val = 0x02; 525 break; 526 default: 527 dev_dbg(&state->i2c->dev, "%s: invalid bandwidth_hz\n", 528 __func__); 529 ret = -EINVAL; 530 goto err; 531 } 532 533 /* program tuner */ 534 if (fe->ops.tuner_ops.set_params) 535 fe->ops.tuner_ops.set_params(fe); 536 537 /* program CFOE coefficients */ 538 if (c->bandwidth_hz != state->bandwidth_hz) { 539 for (i = 0; i < ARRAY_SIZE(coeff_lut); i++) { 540 if (coeff_lut[i].clock == state->cfg.clock && 541 coeff_lut[i].bandwidth_hz == c->bandwidth_hz) { 542 break; 543 } 544 } 545 ret = af9033_wr_regs(state, 0x800001, 546 coeff_lut[i].val, sizeof(coeff_lut[i].val)); 547 } 548 549 /* program frequency control */ 550 if (c->bandwidth_hz != state->bandwidth_hz) { 551 spec_inv = state->cfg.spec_inv ? -1 : 1; 552 553 for (i = 0; i < ARRAY_SIZE(clock_adc_lut); i++) { 554 if (clock_adc_lut[i].clock == state->cfg.clock) 555 break; 556 } 557 adc_freq = clock_adc_lut[i].adc; 558 559 /* get used IF frequency */ 560 if (fe->ops.tuner_ops.get_if_frequency) 561 fe->ops.tuner_ops.get_if_frequency(fe, &if_frequency); 562 else 563 if_frequency = 0; 564 565 sampling_freq = if_frequency; 566 567 while (sampling_freq > (adc_freq / 2)) 568 sampling_freq -= adc_freq; 569 570 if (sampling_freq >= 0) 571 spec_inv *= -1; 572 else 573 sampling_freq *= -1; 574 575 freq_cw = af9033_div(state, sampling_freq, adc_freq, 23ul); 576 577 if (spec_inv == -1) 578 freq_cw = 0x800000 - freq_cw; 579 580 if (state->cfg.adc_multiplier == AF9033_ADC_MULTIPLIER_2X) 581 freq_cw /= 2; 582 583 buf[0] = (freq_cw >> 0) & 0xff; 584 buf[1] = (freq_cw >> 8) & 0xff; 585 buf[2] = (freq_cw >> 16) & 0x7f; 586 587 /* FIXME: there seems to be calculation error here... */ 588 if (if_frequency == 0) 589 buf[2] = 0; 590 591 ret = af9033_wr_regs(state, 0x800029, buf, 3); 592 if (ret < 0) 593 goto err; 594 595 state->bandwidth_hz = c->bandwidth_hz; 596 } 597 598 ret = af9033_wr_reg_mask(state, 0x80f904, bandwidth_reg_val, 0x03); 599 if (ret < 0) 600 goto err; 601 602 ret = af9033_wr_reg(state, 0x800040, 0x00); 603 if (ret < 0) 604 goto err; 605 606 ret = af9033_wr_reg(state, 0x800047, 0x00); 607 if (ret < 0) 608 goto err; 609 610 ret = af9033_wr_reg_mask(state, 0x80f999, 0x00, 0x01); 611 if (ret < 0) 612 goto err; 613 614 if (c->frequency <= 230000000) 615 tmp = 0x00; /* VHF */ 616 else 617 tmp = 0x01; /* UHF */ 618 619 ret = af9033_wr_reg(state, 0x80004b, tmp); 620 if (ret < 0) 621 goto err; 622 623 ret = af9033_wr_reg(state, 0x800000, 0x00); 624 if (ret < 0) 625 goto err; 626 627 return 0; 628 629 err: 630 dev_dbg(&state->i2c->dev, "%s: failed=%d\n", __func__, ret); 631 632 return ret; 633 } 634 635 static int af9033_get_frontend(struct dvb_frontend *fe) 636 { 637 struct af9033_state *state = fe->demodulator_priv; 638 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 639 int ret; 640 u8 buf[8]; 641 642 dev_dbg(&state->i2c->dev, "%s:\n", __func__); 643 644 /* read all needed registers */ 645 ret = af9033_rd_regs(state, 0x80f900, buf, sizeof(buf)); 646 if (ret < 0) 647 goto err; 648 649 switch ((buf[0] >> 0) & 3) { 650 case 0: 651 c->transmission_mode = TRANSMISSION_MODE_2K; 652 break; 653 case 1: 654 c->transmission_mode = TRANSMISSION_MODE_8K; 655 break; 656 } 657 658 switch ((buf[1] >> 0) & 3) { 659 case 0: 660 c->guard_interval = GUARD_INTERVAL_1_32; 661 break; 662 case 1: 663 c->guard_interval = GUARD_INTERVAL_1_16; 664 break; 665 case 2: 666 c->guard_interval = GUARD_INTERVAL_1_8; 667 break; 668 case 3: 669 c->guard_interval = GUARD_INTERVAL_1_4; 670 break; 671 } 672 673 switch ((buf[2] >> 0) & 7) { 674 case 0: 675 c->hierarchy = HIERARCHY_NONE; 676 break; 677 case 1: 678 c->hierarchy = HIERARCHY_1; 679 break; 680 case 2: 681 c->hierarchy = HIERARCHY_2; 682 break; 683 case 3: 684 c->hierarchy = HIERARCHY_4; 685 break; 686 } 687 688 switch ((buf[3] >> 0) & 3) { 689 case 0: 690 c->modulation = QPSK; 691 break; 692 case 1: 693 c->modulation = QAM_16; 694 break; 695 case 2: 696 c->modulation = QAM_64; 697 break; 698 } 699 700 switch ((buf[4] >> 0) & 3) { 701 case 0: 702 c->bandwidth_hz = 6000000; 703 break; 704 case 1: 705 c->bandwidth_hz = 7000000; 706 break; 707 case 2: 708 c->bandwidth_hz = 8000000; 709 break; 710 } 711 712 switch ((buf[6] >> 0) & 7) { 713 case 0: 714 c->code_rate_HP = FEC_1_2; 715 break; 716 case 1: 717 c->code_rate_HP = FEC_2_3; 718 break; 719 case 2: 720 c->code_rate_HP = FEC_3_4; 721 break; 722 case 3: 723 c->code_rate_HP = FEC_5_6; 724 break; 725 case 4: 726 c->code_rate_HP = FEC_7_8; 727 break; 728 case 5: 729 c->code_rate_HP = FEC_NONE; 730 break; 731 } 732 733 switch ((buf[7] >> 0) & 7) { 734 case 0: 735 c->code_rate_LP = FEC_1_2; 736 break; 737 case 1: 738 c->code_rate_LP = FEC_2_3; 739 break; 740 case 2: 741 c->code_rate_LP = FEC_3_4; 742 break; 743 case 3: 744 c->code_rate_LP = FEC_5_6; 745 break; 746 case 4: 747 c->code_rate_LP = FEC_7_8; 748 break; 749 case 5: 750 c->code_rate_LP = FEC_NONE; 751 break; 752 } 753 754 return 0; 755 756 err: 757 dev_dbg(&state->i2c->dev, "%s: failed=%d\n", __func__, ret); 758 759 return ret; 760 } 761 762 static int af9033_read_status(struct dvb_frontend *fe, fe_status_t *status) 763 { 764 struct af9033_state *state = fe->demodulator_priv; 765 int ret; 766 u8 tmp; 767 768 *status = 0; 769 770 /* radio channel status, 0=no result, 1=has signal, 2=no signal */ 771 ret = af9033_rd_reg(state, 0x800047, &tmp); 772 if (ret < 0) 773 goto err; 774 775 /* has signal */ 776 if (tmp == 0x01) 777 *status |= FE_HAS_SIGNAL; 778 779 if (tmp != 0x02) { 780 /* TPS lock */ 781 ret = af9033_rd_reg_mask(state, 0x80f5a9, &tmp, 0x01); 782 if (ret < 0) 783 goto err; 784 785 if (tmp) 786 *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER | 787 FE_HAS_VITERBI; 788 789 /* full lock */ 790 ret = af9033_rd_reg_mask(state, 0x80f999, &tmp, 0x01); 791 if (ret < 0) 792 goto err; 793 794 if (tmp) 795 *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER | 796 FE_HAS_VITERBI | FE_HAS_SYNC | 797 FE_HAS_LOCK; 798 } 799 800 return 0; 801 802 err: 803 dev_dbg(&state->i2c->dev, "%s: failed=%d\n", __func__, ret); 804 805 return ret; 806 } 807 808 static int af9033_read_snr(struct dvb_frontend *fe, u16 *snr) 809 { 810 struct af9033_state *state = fe->demodulator_priv; 811 int ret, i, len; 812 u8 buf[3], tmp; 813 u32 snr_val; 814 const struct val_snr *uninitialized_var(snr_lut); 815 816 /* read value */ 817 ret = af9033_rd_regs(state, 0x80002c, buf, 3); 818 if (ret < 0) 819 goto err; 820 821 snr_val = (buf[2] << 16) | (buf[1] << 8) | buf[0]; 822 823 /* read current modulation */ 824 ret = af9033_rd_reg(state, 0x80f903, &tmp); 825 if (ret < 0) 826 goto err; 827 828 switch ((tmp >> 0) & 3) { 829 case 0: 830 len = ARRAY_SIZE(qpsk_snr_lut); 831 snr_lut = qpsk_snr_lut; 832 break; 833 case 1: 834 len = ARRAY_SIZE(qam16_snr_lut); 835 snr_lut = qam16_snr_lut; 836 break; 837 case 2: 838 len = ARRAY_SIZE(qam64_snr_lut); 839 snr_lut = qam64_snr_lut; 840 break; 841 default: 842 goto err; 843 } 844 845 for (i = 0; i < len; i++) { 846 tmp = snr_lut[i].snr; 847 848 if (snr_val < snr_lut[i].val) 849 break; 850 } 851 852 *snr = tmp * 10; /* dB/10 */ 853 854 return 0; 855 856 err: 857 dev_dbg(&state->i2c->dev, "%s: failed=%d\n", __func__, ret); 858 859 return ret; 860 } 861 862 static int af9033_read_signal_strength(struct dvb_frontend *fe, u16 *strength) 863 { 864 struct af9033_state *state = fe->demodulator_priv; 865 int ret; 866 u8 strength2; 867 868 /* read signal strength of 0-100 scale */ 869 ret = af9033_rd_reg(state, 0x800048, &strength2); 870 if (ret < 0) 871 goto err; 872 873 /* scale value to 0x0000-0xffff */ 874 *strength = strength2 * 0xffff / 100; 875 876 return 0; 877 878 err: 879 dev_dbg(&state->i2c->dev, "%s: failed=%d\n", __func__, ret); 880 881 return ret; 882 } 883 884 static int af9033_update_ch_stat(struct af9033_state *state) 885 { 886 int ret = 0; 887 u32 err_cnt, bit_cnt; 888 u16 abort_cnt; 889 u8 buf[7]; 890 891 /* only update data every half second */ 892 if (time_after(jiffies, state->last_stat_check + msecs_to_jiffies(500))) { 893 ret = af9033_rd_regs(state, 0x800032, buf, sizeof(buf)); 894 if (ret < 0) 895 goto err; 896 /* in 8 byte packets? */ 897 abort_cnt = (buf[1] << 8) + buf[0]; 898 /* in bits */ 899 err_cnt = (buf[4] << 16) + (buf[3] << 8) + buf[2]; 900 /* in 8 byte packets? always(?) 0x2710 = 10000 */ 901 bit_cnt = (buf[6] << 8) + buf[5]; 902 903 if (bit_cnt < abort_cnt) { 904 abort_cnt = 1000; 905 state->ber = 0xffffffff; 906 } else { 907 /* 8 byte packets, that have not been rejected already */ 908 bit_cnt -= (u32)abort_cnt; 909 if (bit_cnt == 0) { 910 state->ber = 0xffffffff; 911 } else { 912 err_cnt -= (u32)abort_cnt * 8 * 8; 913 bit_cnt *= 8 * 8; 914 state->ber = err_cnt * (0xffffffff / bit_cnt); 915 } 916 } 917 state->ucb += abort_cnt; 918 state->last_stat_check = jiffies; 919 } 920 921 return 0; 922 err: 923 dev_dbg(&state->i2c->dev, "%s: failed=%d\n", __func__, ret); 924 925 return ret; 926 } 927 928 static int af9033_read_ber(struct dvb_frontend *fe, u32 *ber) 929 { 930 struct af9033_state *state = fe->demodulator_priv; 931 int ret; 932 933 ret = af9033_update_ch_stat(state); 934 if (ret < 0) 935 return ret; 936 937 *ber = state->ber; 938 939 return 0; 940 } 941 942 static int af9033_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks) 943 { 944 struct af9033_state *state = fe->demodulator_priv; 945 int ret; 946 947 ret = af9033_update_ch_stat(state); 948 if (ret < 0) 949 return ret; 950 951 *ucblocks = state->ucb; 952 953 return 0; 954 } 955 956 static int af9033_i2c_gate_ctrl(struct dvb_frontend *fe, int enable) 957 { 958 struct af9033_state *state = fe->demodulator_priv; 959 int ret; 960 961 dev_dbg(&state->i2c->dev, "%s: enable=%d\n", __func__, enable); 962 963 ret = af9033_wr_reg_mask(state, 0x00fa04, enable, 0x01); 964 if (ret < 0) 965 goto err; 966 967 return 0; 968 969 err: 970 dev_dbg(&state->i2c->dev, "%s: failed=%d\n", __func__, ret); 971 972 return ret; 973 } 974 975 static struct dvb_frontend_ops af9033_ops; 976 977 struct dvb_frontend *af9033_attach(const struct af9033_config *config, 978 struct i2c_adapter *i2c) 979 { 980 int ret; 981 struct af9033_state *state; 982 u8 buf[8]; 983 984 dev_dbg(&i2c->dev, "%s:\n", __func__); 985 986 /* allocate memory for the internal state */ 987 state = kzalloc(sizeof(struct af9033_state), GFP_KERNEL); 988 if (state == NULL) 989 goto err; 990 991 /* setup the state */ 992 state->i2c = i2c; 993 memcpy(&state->cfg, config, sizeof(struct af9033_config)); 994 995 if (state->cfg.clock != 12000000) { 996 dev_err(&state->i2c->dev, "%s: af9033: unsupported clock=%d, " \ 997 "only 12000000 Hz is supported currently\n", 998 KBUILD_MODNAME, state->cfg.clock); 999 goto err; 1000 } 1001 1002 /* firmware version */ 1003 ret = af9033_rd_regs(state, 0x0083e9, &buf[0], 4); 1004 if (ret < 0) 1005 goto err; 1006 1007 ret = af9033_rd_regs(state, 0x804191, &buf[4], 4); 1008 if (ret < 0) 1009 goto err; 1010 1011 dev_info(&state->i2c->dev, "%s: firmware version: LINK=%d.%d.%d.%d " \ 1012 "OFDM=%d.%d.%d.%d\n", KBUILD_MODNAME, buf[0], buf[1], 1013 buf[2], buf[3], buf[4], buf[5], buf[6], buf[7]); 1014 1015 /* sleep */ 1016 switch (state->cfg.tuner) { 1017 case AF9033_TUNER_IT9135_38: 1018 case AF9033_TUNER_IT9135_51: 1019 case AF9033_TUNER_IT9135_52: 1020 case AF9033_TUNER_IT9135_60: 1021 case AF9033_TUNER_IT9135_61: 1022 case AF9033_TUNER_IT9135_62: 1023 /* IT9135 did not like to sleep at that early */ 1024 break; 1025 default: 1026 ret = af9033_wr_reg(state, 0x80004c, 1); 1027 if (ret < 0) 1028 goto err; 1029 1030 ret = af9033_wr_reg(state, 0x800000, 0); 1031 if (ret < 0) 1032 goto err; 1033 } 1034 1035 /* configure internal TS mode */ 1036 switch (state->cfg.ts_mode) { 1037 case AF9033_TS_MODE_PARALLEL: 1038 state->ts_mode_parallel = true; 1039 break; 1040 case AF9033_TS_MODE_SERIAL: 1041 state->ts_mode_serial = true; 1042 break; 1043 case AF9033_TS_MODE_USB: 1044 /* usb mode for AF9035 */ 1045 default: 1046 break; 1047 } 1048 1049 /* create dvb_frontend */ 1050 memcpy(&state->fe.ops, &af9033_ops, sizeof(struct dvb_frontend_ops)); 1051 state->fe.demodulator_priv = state; 1052 1053 return &state->fe; 1054 1055 err: 1056 kfree(state); 1057 return NULL; 1058 } 1059 EXPORT_SYMBOL(af9033_attach); 1060 1061 static struct dvb_frontend_ops af9033_ops = { 1062 .delsys = { SYS_DVBT }, 1063 .info = { 1064 .name = "Afatech AF9033 (DVB-T)", 1065 .frequency_min = 174000000, 1066 .frequency_max = 862000000, 1067 .frequency_stepsize = 250000, 1068 .frequency_tolerance = 0, 1069 .caps = FE_CAN_FEC_1_2 | 1070 FE_CAN_FEC_2_3 | 1071 FE_CAN_FEC_3_4 | 1072 FE_CAN_FEC_5_6 | 1073 FE_CAN_FEC_7_8 | 1074 FE_CAN_FEC_AUTO | 1075 FE_CAN_QPSK | 1076 FE_CAN_QAM_16 | 1077 FE_CAN_QAM_64 | 1078 FE_CAN_QAM_AUTO | 1079 FE_CAN_TRANSMISSION_MODE_AUTO | 1080 FE_CAN_GUARD_INTERVAL_AUTO | 1081 FE_CAN_HIERARCHY_AUTO | 1082 FE_CAN_RECOVER | 1083 FE_CAN_MUTE_TS 1084 }, 1085 1086 .release = af9033_release, 1087 1088 .init = af9033_init, 1089 .sleep = af9033_sleep, 1090 1091 .get_tune_settings = af9033_get_tune_settings, 1092 .set_frontend = af9033_set_frontend, 1093 .get_frontend = af9033_get_frontend, 1094 1095 .read_status = af9033_read_status, 1096 .read_snr = af9033_read_snr, 1097 .read_signal_strength = af9033_read_signal_strength, 1098 .read_ber = af9033_read_ber, 1099 .read_ucblocks = af9033_read_ucblocks, 1100 1101 .i2c_gate_ctrl = af9033_i2c_gate_ctrl, 1102 }; 1103 1104 MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>"); 1105 MODULE_DESCRIPTION("Afatech AF9033 DVB-T demodulator driver"); 1106 MODULE_LICENSE("GPL"); 1107