19a0bf528SMauro Carvalho Chehab /* 29a0bf528SMauro Carvalho Chehab * Afatech AF9033 demodulator driver 39a0bf528SMauro Carvalho Chehab * 49a0bf528SMauro Carvalho Chehab * Copyright (C) 2009 Antti Palosaari <crope@iki.fi> 59a0bf528SMauro Carvalho Chehab * Copyright (C) 2012 Antti Palosaari <crope@iki.fi> 69a0bf528SMauro Carvalho Chehab * 79a0bf528SMauro Carvalho Chehab * This program is free software; you can redistribute it and/or modify 89a0bf528SMauro Carvalho Chehab * it under the terms of the GNU General Public License as published by 99a0bf528SMauro Carvalho Chehab * the Free Software Foundation; either version 2 of the License, or 109a0bf528SMauro Carvalho Chehab * (at your option) any later version. 119a0bf528SMauro Carvalho Chehab * 129a0bf528SMauro Carvalho Chehab * This program is distributed in the hope that it will be useful, 139a0bf528SMauro Carvalho Chehab * but WITHOUT ANY WARRANTY; without even the implied warranty of 149a0bf528SMauro Carvalho Chehab * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 159a0bf528SMauro Carvalho Chehab * GNU General Public License for more details. 169a0bf528SMauro Carvalho Chehab * 179a0bf528SMauro Carvalho Chehab * You should have received a copy of the GNU General Public License along 189a0bf528SMauro Carvalho Chehab * with this program; if not, write to the Free Software Foundation, Inc., 199a0bf528SMauro Carvalho Chehab * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. 209a0bf528SMauro Carvalho Chehab */ 219a0bf528SMauro Carvalho Chehab 229a0bf528SMauro Carvalho Chehab #include "af9033_priv.h" 239a0bf528SMauro Carvalho Chehab 2437ebaf68SMauro Carvalho Chehab /* Max transfer size done by I2C transfer functions */ 2537ebaf68SMauro Carvalho Chehab #define MAX_XFER_SIZE 64 2637ebaf68SMauro Carvalho Chehab 2709611caaSAntti Palosaari struct af9033_dev { 28f5b00a76SAntti Palosaari struct i2c_client *client; 299a0bf528SMauro Carvalho Chehab struct dvb_frontend fe; 309a0bf528SMauro Carvalho Chehab struct af9033_config cfg; 3183f11619SAntti Palosaari bool is_af9035; 3283f11619SAntti Palosaari bool is_it9135; 339a0bf528SMauro Carvalho Chehab 349a0bf528SMauro Carvalho Chehab u32 bandwidth_hz; 359a0bf528SMauro Carvalho Chehab bool ts_mode_parallel; 369a0bf528SMauro Carvalho Chehab bool ts_mode_serial; 379a0bf528SMauro Carvalho Chehab 380df289a2SMauro Carvalho Chehab enum fe_status fe_status; 39e53c4744SAntti Palosaari u64 post_bit_error_prev; /* for old read_ber we return (curr - prev) */ 406bb096c9SAntti Palosaari u64 post_bit_error; 416bb096c9SAntti Palosaari u64 post_bit_count; 42204f4319SAntti Palosaari u64 error_block_count; 43204f4319SAntti Palosaari u64 total_block_count; 449a0bf528SMauro Carvalho Chehab }; 459a0bf528SMauro Carvalho Chehab 469a0bf528SMauro Carvalho Chehab /* write multiple registers */ 4709611caaSAntti Palosaari static int af9033_wr_regs(struct af9033_dev *dev, u32 reg, const u8 *val, 489a0bf528SMauro Carvalho Chehab int len) 499a0bf528SMauro Carvalho Chehab { 509a0bf528SMauro Carvalho Chehab int ret; 5137ebaf68SMauro Carvalho Chehab u8 buf[MAX_XFER_SIZE]; 529a0bf528SMauro Carvalho Chehab struct i2c_msg msg[1] = { 539a0bf528SMauro Carvalho Chehab { 54f5b00a76SAntti Palosaari .addr = dev->client->addr, 559a0bf528SMauro Carvalho Chehab .flags = 0, 5637ebaf68SMauro Carvalho Chehab .len = 3 + len, 579a0bf528SMauro Carvalho Chehab .buf = buf, 589a0bf528SMauro Carvalho Chehab } 599a0bf528SMauro Carvalho Chehab }; 609a0bf528SMauro Carvalho Chehab 6137ebaf68SMauro Carvalho Chehab if (3 + len > sizeof(buf)) { 62f5b00a76SAntti Palosaari dev_warn(&dev->client->dev, 636a087f1fSAntti Palosaari "i2c wr reg=%04x: len=%d is too big!\n", 646a087f1fSAntti Palosaari reg, len); 6537ebaf68SMauro Carvalho Chehab return -EINVAL; 6637ebaf68SMauro Carvalho Chehab } 6737ebaf68SMauro Carvalho Chehab 689a0bf528SMauro Carvalho Chehab buf[0] = (reg >> 16) & 0xff; 699a0bf528SMauro Carvalho Chehab buf[1] = (reg >> 8) & 0xff; 709a0bf528SMauro Carvalho Chehab buf[2] = (reg >> 0) & 0xff; 719a0bf528SMauro Carvalho Chehab memcpy(&buf[3], val, len); 729a0bf528SMauro Carvalho Chehab 73f5b00a76SAntti Palosaari ret = i2c_transfer(dev->client->adapter, msg, 1); 749a0bf528SMauro Carvalho Chehab if (ret == 1) { 759a0bf528SMauro Carvalho Chehab ret = 0; 769a0bf528SMauro Carvalho Chehab } else { 776a087f1fSAntti Palosaari dev_warn(&dev->client->dev, "i2c wr failed=%d reg=%06x len=%d\n", 786a087f1fSAntti Palosaari ret, reg, len); 799a0bf528SMauro Carvalho Chehab ret = -EREMOTEIO; 809a0bf528SMauro Carvalho Chehab } 819a0bf528SMauro Carvalho Chehab 829a0bf528SMauro Carvalho Chehab return ret; 839a0bf528SMauro Carvalho Chehab } 849a0bf528SMauro Carvalho Chehab 859a0bf528SMauro Carvalho Chehab /* read multiple registers */ 8609611caaSAntti Palosaari static int af9033_rd_regs(struct af9033_dev *dev, u32 reg, u8 *val, int len) 879a0bf528SMauro Carvalho Chehab { 889a0bf528SMauro Carvalho Chehab int ret; 899a0bf528SMauro Carvalho Chehab u8 buf[3] = { (reg >> 16) & 0xff, (reg >> 8) & 0xff, 909a0bf528SMauro Carvalho Chehab (reg >> 0) & 0xff }; 919a0bf528SMauro Carvalho Chehab struct i2c_msg msg[2] = { 929a0bf528SMauro Carvalho Chehab { 93f5b00a76SAntti Palosaari .addr = dev->client->addr, 949a0bf528SMauro Carvalho Chehab .flags = 0, 959a0bf528SMauro Carvalho Chehab .len = sizeof(buf), 969a0bf528SMauro Carvalho Chehab .buf = buf 979a0bf528SMauro Carvalho Chehab }, { 98f5b00a76SAntti Palosaari .addr = dev->client->addr, 999a0bf528SMauro Carvalho Chehab .flags = I2C_M_RD, 1009a0bf528SMauro Carvalho Chehab .len = len, 1019a0bf528SMauro Carvalho Chehab .buf = val 1029a0bf528SMauro Carvalho Chehab } 1039a0bf528SMauro Carvalho Chehab }; 1049a0bf528SMauro Carvalho Chehab 105f5b00a76SAntti Palosaari ret = i2c_transfer(dev->client->adapter, msg, 2); 1069a0bf528SMauro Carvalho Chehab if (ret == 2) { 1079a0bf528SMauro Carvalho Chehab ret = 0; 1089a0bf528SMauro Carvalho Chehab } else { 1096a087f1fSAntti Palosaari dev_warn(&dev->client->dev, "i2c rd failed=%d reg=%06x len=%d\n", 1106a087f1fSAntti Palosaari ret, reg, len); 1119a0bf528SMauro Carvalho Chehab ret = -EREMOTEIO; 1129a0bf528SMauro Carvalho Chehab } 1139a0bf528SMauro Carvalho Chehab 1149a0bf528SMauro Carvalho Chehab return ret; 1159a0bf528SMauro Carvalho Chehab } 1169a0bf528SMauro Carvalho Chehab 1179a0bf528SMauro Carvalho Chehab 1189a0bf528SMauro Carvalho Chehab /* write single register */ 11909611caaSAntti Palosaari static int af9033_wr_reg(struct af9033_dev *dev, u32 reg, u8 val) 1209a0bf528SMauro Carvalho Chehab { 12109611caaSAntti Palosaari return af9033_wr_regs(dev, reg, &val, 1); 1229a0bf528SMauro Carvalho Chehab } 1239a0bf528SMauro Carvalho Chehab 1249a0bf528SMauro Carvalho Chehab /* read single register */ 12509611caaSAntti Palosaari static int af9033_rd_reg(struct af9033_dev *dev, u32 reg, u8 *val) 1269a0bf528SMauro Carvalho Chehab { 12709611caaSAntti Palosaari return af9033_rd_regs(dev, reg, val, 1); 1289a0bf528SMauro Carvalho Chehab } 1299a0bf528SMauro Carvalho Chehab 1309a0bf528SMauro Carvalho Chehab /* write single register with mask */ 13109611caaSAntti Palosaari static int af9033_wr_reg_mask(struct af9033_dev *dev, u32 reg, u8 val, 1329a0bf528SMauro Carvalho Chehab u8 mask) 1339a0bf528SMauro Carvalho Chehab { 1349a0bf528SMauro Carvalho Chehab int ret; 1359a0bf528SMauro Carvalho Chehab u8 tmp; 1369a0bf528SMauro Carvalho Chehab 1379a0bf528SMauro Carvalho Chehab /* no need for read if whole reg is written */ 1389a0bf528SMauro Carvalho Chehab if (mask != 0xff) { 13909611caaSAntti Palosaari ret = af9033_rd_regs(dev, reg, &tmp, 1); 1409a0bf528SMauro Carvalho Chehab if (ret) 1419a0bf528SMauro Carvalho Chehab return ret; 1429a0bf528SMauro Carvalho Chehab 1439a0bf528SMauro Carvalho Chehab val &= mask; 1449a0bf528SMauro Carvalho Chehab tmp &= ~mask; 1459a0bf528SMauro Carvalho Chehab val |= tmp; 1469a0bf528SMauro Carvalho Chehab } 1479a0bf528SMauro Carvalho Chehab 14809611caaSAntti Palosaari return af9033_wr_regs(dev, reg, &val, 1); 1499a0bf528SMauro Carvalho Chehab } 1509a0bf528SMauro Carvalho Chehab 1519a0bf528SMauro Carvalho Chehab /* read single register with mask */ 15209611caaSAntti Palosaari static int af9033_rd_reg_mask(struct af9033_dev *dev, u32 reg, u8 *val, 1539a0bf528SMauro Carvalho Chehab u8 mask) 1549a0bf528SMauro Carvalho Chehab { 1559a0bf528SMauro Carvalho Chehab int ret, i; 1569a0bf528SMauro Carvalho Chehab u8 tmp; 1579a0bf528SMauro Carvalho Chehab 15809611caaSAntti Palosaari ret = af9033_rd_regs(dev, reg, &tmp, 1); 1599a0bf528SMauro Carvalho Chehab if (ret) 1609a0bf528SMauro Carvalho Chehab return ret; 1619a0bf528SMauro Carvalho Chehab 1629a0bf528SMauro Carvalho Chehab tmp &= mask; 1639a0bf528SMauro Carvalho Chehab 1649a0bf528SMauro Carvalho Chehab /* find position of the first bit */ 1659a0bf528SMauro Carvalho Chehab for (i = 0; i < 8; i++) { 1669a0bf528SMauro Carvalho Chehab if ((mask >> i) & 0x01) 1679a0bf528SMauro Carvalho Chehab break; 1689a0bf528SMauro Carvalho Chehab } 1699a0bf528SMauro Carvalho Chehab *val = tmp >> i; 1709a0bf528SMauro Carvalho Chehab 1719a0bf528SMauro Carvalho Chehab return 0; 1729a0bf528SMauro Carvalho Chehab } 1739a0bf528SMauro Carvalho Chehab 1743bf5e552SAntti Palosaari /* write reg val table using reg addr auto increment */ 17509611caaSAntti Palosaari static int af9033_wr_reg_val_tab(struct af9033_dev *dev, 1763bf5e552SAntti Palosaari const struct reg_val *tab, int tab_len) 1773bf5e552SAntti Palosaari { 178d18a88b1SAntti Palosaari #define MAX_TAB_LEN 212 1793bf5e552SAntti Palosaari int ret, i, j; 180d18a88b1SAntti Palosaari u8 buf[1 + MAX_TAB_LEN]; 181d18a88b1SAntti Palosaari 1826a087f1fSAntti Palosaari dev_dbg(&dev->client->dev, "tab_len=%d\n", tab_len); 18337ebaf68SMauro Carvalho Chehab 18437ebaf68SMauro Carvalho Chehab if (tab_len > sizeof(buf)) { 1856a087f1fSAntti Palosaari dev_warn(&dev->client->dev, "tab len %d is too big\n", tab_len); 18637ebaf68SMauro Carvalho Chehab return -EINVAL; 18737ebaf68SMauro Carvalho Chehab } 1883bf5e552SAntti Palosaari 1893bf5e552SAntti Palosaari for (i = 0, j = 0; i < tab_len; i++) { 1903bf5e552SAntti Palosaari buf[j] = tab[i].val; 1913bf5e552SAntti Palosaari 1923bf5e552SAntti Palosaari if (i == tab_len - 1 || tab[i].reg != tab[i + 1].reg - 1) { 19309611caaSAntti Palosaari ret = af9033_wr_regs(dev, tab[i].reg - j, buf, j + 1); 1943bf5e552SAntti Palosaari if (ret < 0) 1953bf5e552SAntti Palosaari goto err; 1963bf5e552SAntti Palosaari 1973bf5e552SAntti Palosaari j = 0; 1983bf5e552SAntti Palosaari } else { 1993bf5e552SAntti Palosaari j++; 2003bf5e552SAntti Palosaari } 2013bf5e552SAntti Palosaari } 2023bf5e552SAntti Palosaari 2033bf5e552SAntti Palosaari return 0; 2043bf5e552SAntti Palosaari 2053bf5e552SAntti Palosaari err: 2066a087f1fSAntti Palosaari dev_dbg(&dev->client->dev, "failed=%d\n", ret); 2073bf5e552SAntti Palosaari 2083bf5e552SAntti Palosaari return ret; 2093bf5e552SAntti Palosaari } 2103bf5e552SAntti Palosaari 21109611caaSAntti Palosaari static u32 af9033_div(struct af9033_dev *dev, u32 a, u32 b, u32 x) 2129a0bf528SMauro Carvalho Chehab { 2139a0bf528SMauro Carvalho Chehab u32 r = 0, c = 0, i; 2149a0bf528SMauro Carvalho Chehab 2156a087f1fSAntti Palosaari dev_dbg(&dev->client->dev, "a=%d b=%d x=%d\n", a, b, x); 2169a0bf528SMauro Carvalho Chehab 2179a0bf528SMauro Carvalho Chehab if (a > b) { 2189a0bf528SMauro Carvalho Chehab c = a / b; 2199a0bf528SMauro Carvalho Chehab a = a - c * b; 2209a0bf528SMauro Carvalho Chehab } 2219a0bf528SMauro Carvalho Chehab 2229a0bf528SMauro Carvalho Chehab for (i = 0; i < x; i++) { 2239a0bf528SMauro Carvalho Chehab if (a >= b) { 2249a0bf528SMauro Carvalho Chehab r += 1; 2259a0bf528SMauro Carvalho Chehab a -= b; 2269a0bf528SMauro Carvalho Chehab } 2279a0bf528SMauro Carvalho Chehab a <<= 1; 2289a0bf528SMauro Carvalho Chehab r <<= 1; 2299a0bf528SMauro Carvalho Chehab } 2309a0bf528SMauro Carvalho Chehab r = (c << (u32)x) + r; 2319a0bf528SMauro Carvalho Chehab 2326a087f1fSAntti Palosaari dev_dbg(&dev->client->dev, "a=%d b=%d x=%d r=%d r=%x\n", a, b, x, r, r); 2339a0bf528SMauro Carvalho Chehab 2349a0bf528SMauro Carvalho Chehab return r; 2359a0bf528SMauro Carvalho Chehab } 2369a0bf528SMauro Carvalho Chehab 2379a0bf528SMauro Carvalho Chehab static int af9033_init(struct dvb_frontend *fe) 2389a0bf528SMauro Carvalho Chehab { 23909611caaSAntti Palosaari struct af9033_dev *dev = fe->demodulator_priv; 2402db4d179SAntti Palosaari struct dtv_frontend_properties *c = &fe->dtv_property_cache; 2419a0bf528SMauro Carvalho Chehab int ret, i, len; 2429a0bf528SMauro Carvalho Chehab const struct reg_val *init; 2439a0bf528SMauro Carvalho Chehab u8 buf[4]; 2449a0bf528SMauro Carvalho Chehab u32 adc_cw, clock_cw; 2459a0bf528SMauro Carvalho Chehab struct reg_val_mask tab[] = { 2469a0bf528SMauro Carvalho Chehab { 0x80fb24, 0x00, 0x08 }, 2479a0bf528SMauro Carvalho Chehab { 0x80004c, 0x00, 0xff }, 24809611caaSAntti Palosaari { 0x00f641, dev->cfg.tuner, 0xff }, 2499a0bf528SMauro Carvalho Chehab { 0x80f5ca, 0x01, 0x01 }, 2509a0bf528SMauro Carvalho Chehab { 0x80f715, 0x01, 0x01 }, 2519a0bf528SMauro Carvalho Chehab { 0x00f41f, 0x04, 0x04 }, 2529a0bf528SMauro Carvalho Chehab { 0x00f41a, 0x01, 0x01 }, 2539a0bf528SMauro Carvalho Chehab { 0x80f731, 0x00, 0x01 }, 2549a0bf528SMauro Carvalho Chehab { 0x00d91e, 0x00, 0x01 }, 2559a0bf528SMauro Carvalho Chehab { 0x00d919, 0x00, 0x01 }, 2569a0bf528SMauro Carvalho Chehab { 0x80f732, 0x00, 0x01 }, 2579a0bf528SMauro Carvalho Chehab { 0x00d91f, 0x00, 0x01 }, 2589a0bf528SMauro Carvalho Chehab { 0x00d91a, 0x00, 0x01 }, 2599a0bf528SMauro Carvalho Chehab { 0x80f730, 0x00, 0x01 }, 2609a0bf528SMauro Carvalho Chehab { 0x80f778, 0x00, 0xff }, 2619a0bf528SMauro Carvalho Chehab { 0x80f73c, 0x01, 0x01 }, 2629a0bf528SMauro Carvalho Chehab { 0x80f776, 0x00, 0x01 }, 2639a0bf528SMauro Carvalho Chehab { 0x00d8fd, 0x01, 0xff }, 2649a0bf528SMauro Carvalho Chehab { 0x00d830, 0x01, 0xff }, 2659a0bf528SMauro Carvalho Chehab { 0x00d831, 0x00, 0xff }, 2669a0bf528SMauro Carvalho Chehab { 0x00d832, 0x00, 0xff }, 26709611caaSAntti Palosaari { 0x80f985, dev->ts_mode_serial, 0x01 }, 26809611caaSAntti Palosaari { 0x80f986, dev->ts_mode_parallel, 0x01 }, 2699a0bf528SMauro Carvalho Chehab { 0x00d827, 0x00, 0xff }, 2709a0bf528SMauro Carvalho Chehab { 0x00d829, 0x00, 0xff }, 27109611caaSAntti Palosaari { 0x800045, dev->cfg.adc_multiplier, 0xff }, 2729a0bf528SMauro Carvalho Chehab }; 2739a0bf528SMauro Carvalho Chehab 2749a0bf528SMauro Carvalho Chehab /* program clock control */ 27509611caaSAntti Palosaari clock_cw = af9033_div(dev, dev->cfg.clock, 1000000ul, 19ul); 2769a0bf528SMauro Carvalho Chehab buf[0] = (clock_cw >> 0) & 0xff; 2779a0bf528SMauro Carvalho Chehab buf[1] = (clock_cw >> 8) & 0xff; 2789a0bf528SMauro Carvalho Chehab buf[2] = (clock_cw >> 16) & 0xff; 2799a0bf528SMauro Carvalho Chehab buf[3] = (clock_cw >> 24) & 0xff; 2809a0bf528SMauro Carvalho Chehab 2816a087f1fSAntti Palosaari dev_dbg(&dev->client->dev, "clock=%d clock_cw=%08x\n", 2826a087f1fSAntti Palosaari dev->cfg.clock, clock_cw); 2839a0bf528SMauro Carvalho Chehab 28409611caaSAntti Palosaari ret = af9033_wr_regs(dev, 0x800025, buf, 4); 2859a0bf528SMauro Carvalho Chehab if (ret < 0) 2869a0bf528SMauro Carvalho Chehab goto err; 2879a0bf528SMauro Carvalho Chehab 2889a0bf528SMauro Carvalho Chehab /* program ADC control */ 2899a0bf528SMauro Carvalho Chehab for (i = 0; i < ARRAY_SIZE(clock_adc_lut); i++) { 29009611caaSAntti Palosaari if (clock_adc_lut[i].clock == dev->cfg.clock) 2919a0bf528SMauro Carvalho Chehab break; 2929a0bf528SMauro Carvalho Chehab } 293060f79d5SMauro Carvalho Chehab if (i == ARRAY_SIZE(clock_adc_lut)) { 294060f79d5SMauro Carvalho Chehab dev_err(&dev->client->dev, 295060f79d5SMauro Carvalho Chehab "Couldn't find ADC config for clock=%d\n", 296060f79d5SMauro Carvalho Chehab dev->cfg.clock); 297060f79d5SMauro Carvalho Chehab goto err; 298060f79d5SMauro Carvalho Chehab } 2999a0bf528SMauro Carvalho Chehab 30009611caaSAntti Palosaari adc_cw = af9033_div(dev, clock_adc_lut[i].adc, 1000000ul, 19ul); 3019a0bf528SMauro Carvalho Chehab buf[0] = (adc_cw >> 0) & 0xff; 3029a0bf528SMauro Carvalho Chehab buf[1] = (adc_cw >> 8) & 0xff; 3039a0bf528SMauro Carvalho Chehab buf[2] = (adc_cw >> 16) & 0xff; 3049a0bf528SMauro Carvalho Chehab 3056a087f1fSAntti Palosaari dev_dbg(&dev->client->dev, "adc=%d adc_cw=%06x\n", 3066a087f1fSAntti Palosaari clock_adc_lut[i].adc, adc_cw); 3079a0bf528SMauro Carvalho Chehab 30809611caaSAntti Palosaari ret = af9033_wr_regs(dev, 0x80f1cd, buf, 3); 3099a0bf528SMauro Carvalho Chehab if (ret < 0) 3109a0bf528SMauro Carvalho Chehab goto err; 3119a0bf528SMauro Carvalho Chehab 3129a0bf528SMauro Carvalho Chehab /* program register table */ 3139a0bf528SMauro Carvalho Chehab for (i = 0; i < ARRAY_SIZE(tab); i++) { 31409611caaSAntti Palosaari ret = af9033_wr_reg_mask(dev, tab[i].reg, tab[i].val, 3159a0bf528SMauro Carvalho Chehab tab[i].mask); 3169a0bf528SMauro Carvalho Chehab if (ret < 0) 3179a0bf528SMauro Carvalho Chehab goto err; 3189a0bf528SMauro Carvalho Chehab } 3199a0bf528SMauro Carvalho Chehab 320ca681fe0SAntti Palosaari /* clock output */ 32109611caaSAntti Palosaari if (dev->cfg.dyn0_clk) { 32209611caaSAntti Palosaari ret = af9033_wr_reg(dev, 0x80fba8, 0x00); 3239dc0f3feSAntti Palosaari if (ret < 0) 3249dc0f3feSAntti Palosaari goto err; 3259dc0f3feSAntti Palosaari } 3269dc0f3feSAntti Palosaari 3279a0bf528SMauro Carvalho Chehab /* settings for TS interface */ 32809611caaSAntti Palosaari if (dev->cfg.ts_mode == AF9033_TS_MODE_USB) { 32909611caaSAntti Palosaari ret = af9033_wr_reg_mask(dev, 0x80f9a5, 0x00, 0x01); 3309a0bf528SMauro Carvalho Chehab if (ret < 0) 3319a0bf528SMauro Carvalho Chehab goto err; 3329a0bf528SMauro Carvalho Chehab 33309611caaSAntti Palosaari ret = af9033_wr_reg_mask(dev, 0x80f9b5, 0x01, 0x01); 3349a0bf528SMauro Carvalho Chehab if (ret < 0) 3359a0bf528SMauro Carvalho Chehab goto err; 3369a0bf528SMauro Carvalho Chehab } else { 33709611caaSAntti Palosaari ret = af9033_wr_reg_mask(dev, 0x80f990, 0x00, 0x01); 3389a0bf528SMauro Carvalho Chehab if (ret < 0) 3399a0bf528SMauro Carvalho Chehab goto err; 3409a0bf528SMauro Carvalho Chehab 34109611caaSAntti Palosaari ret = af9033_wr_reg_mask(dev, 0x80f9b5, 0x00, 0x01); 3429a0bf528SMauro Carvalho Chehab if (ret < 0) 3439a0bf528SMauro Carvalho Chehab goto err; 3449a0bf528SMauro Carvalho Chehab } 3459a0bf528SMauro Carvalho Chehab 3469a0bf528SMauro Carvalho Chehab /* load OFSM settings */ 3476a087f1fSAntti Palosaari dev_dbg(&dev->client->dev, "load ofsm settings\n"); 34809611caaSAntti Palosaari switch (dev->cfg.tuner) { 349fe8eece1SAntti Palosaari case AF9033_TUNER_IT9135_38: 350fe8eece1SAntti Palosaari case AF9033_TUNER_IT9135_51: 351fe8eece1SAntti Palosaari case AF9033_TUNER_IT9135_52: 352463c399cSAntti Palosaari len = ARRAY_SIZE(ofsm_init_it9135_v1); 353463c399cSAntti Palosaari init = ofsm_init_it9135_v1; 354463c399cSAntti Palosaari break; 355fe8eece1SAntti Palosaari case AF9033_TUNER_IT9135_60: 356fe8eece1SAntti Palosaari case AF9033_TUNER_IT9135_61: 357fe8eece1SAntti Palosaari case AF9033_TUNER_IT9135_62: 358463c399cSAntti Palosaari len = ARRAY_SIZE(ofsm_init_it9135_v2); 359463c399cSAntti Palosaari init = ofsm_init_it9135_v2; 360fe8eece1SAntti Palosaari break; 361fe8eece1SAntti Palosaari default: 3629a0bf528SMauro Carvalho Chehab len = ARRAY_SIZE(ofsm_init); 3639a0bf528SMauro Carvalho Chehab init = ofsm_init; 364fe8eece1SAntti Palosaari break; 365fe8eece1SAntti Palosaari } 366fe8eece1SAntti Palosaari 36709611caaSAntti Palosaari ret = af9033_wr_reg_val_tab(dev, init, len); 3689a0bf528SMauro Carvalho Chehab if (ret < 0) 3699a0bf528SMauro Carvalho Chehab goto err; 3709a0bf528SMauro Carvalho Chehab 3719a0bf528SMauro Carvalho Chehab /* load tuner specific settings */ 3726a087f1fSAntti Palosaari dev_dbg(&dev->client->dev, "load tuner specific settings\n"); 37309611caaSAntti Palosaari switch (dev->cfg.tuner) { 3749a0bf528SMauro Carvalho Chehab case AF9033_TUNER_TUA9001: 3759a0bf528SMauro Carvalho Chehab len = ARRAY_SIZE(tuner_init_tua9001); 3769a0bf528SMauro Carvalho Chehab init = tuner_init_tua9001; 3779a0bf528SMauro Carvalho Chehab break; 3789a0bf528SMauro Carvalho Chehab case AF9033_TUNER_FC0011: 3799a0bf528SMauro Carvalho Chehab len = ARRAY_SIZE(tuner_init_fc0011); 3809a0bf528SMauro Carvalho Chehab init = tuner_init_fc0011; 3819a0bf528SMauro Carvalho Chehab break; 3829a0bf528SMauro Carvalho Chehab case AF9033_TUNER_MXL5007T: 3839a0bf528SMauro Carvalho Chehab len = ARRAY_SIZE(tuner_init_mxl5007t); 3849a0bf528SMauro Carvalho Chehab init = tuner_init_mxl5007t; 3859a0bf528SMauro Carvalho Chehab break; 3869a0bf528SMauro Carvalho Chehab case AF9033_TUNER_TDA18218: 3879a0bf528SMauro Carvalho Chehab len = ARRAY_SIZE(tuner_init_tda18218); 3889a0bf528SMauro Carvalho Chehab init = tuner_init_tda18218; 3899a0bf528SMauro Carvalho Chehab break; 390d67ceb33SOliver Schinagl case AF9033_TUNER_FC2580: 391d67ceb33SOliver Schinagl len = ARRAY_SIZE(tuner_init_fc2580); 392d67ceb33SOliver Schinagl init = tuner_init_fc2580; 393d67ceb33SOliver Schinagl break; 394e713ad15SAntti Palosaari case AF9033_TUNER_FC0012: 395e713ad15SAntti Palosaari len = ARRAY_SIZE(tuner_init_fc0012); 396e713ad15SAntti Palosaari init = tuner_init_fc0012; 397e713ad15SAntti Palosaari break; 3984902bb39SAntti Palosaari case AF9033_TUNER_IT9135_38: 399a72cbb77SAntti Palosaari len = ARRAY_SIZE(tuner_init_it9135_38); 400a72cbb77SAntti Palosaari init = tuner_init_it9135_38; 401a72cbb77SAntti Palosaari break; 4024902bb39SAntti Palosaari case AF9033_TUNER_IT9135_51: 403bb2e12a6SAntti Palosaari len = ARRAY_SIZE(tuner_init_it9135_51); 404bb2e12a6SAntti Palosaari init = tuner_init_it9135_51; 405bb2e12a6SAntti Palosaari break; 4064902bb39SAntti Palosaari case AF9033_TUNER_IT9135_52: 40722d729f3SAntti Palosaari len = ARRAY_SIZE(tuner_init_it9135_52); 40822d729f3SAntti Palosaari init = tuner_init_it9135_52; 40922d729f3SAntti Palosaari break; 4104902bb39SAntti Palosaari case AF9033_TUNER_IT9135_60: 411a49f53a0SAntti Palosaari len = ARRAY_SIZE(tuner_init_it9135_60); 412a49f53a0SAntti Palosaari init = tuner_init_it9135_60; 413a49f53a0SAntti Palosaari break; 4144902bb39SAntti Palosaari case AF9033_TUNER_IT9135_61: 41585211323SAntti Palosaari len = ARRAY_SIZE(tuner_init_it9135_61); 41685211323SAntti Palosaari init = tuner_init_it9135_61; 41785211323SAntti Palosaari break; 4184902bb39SAntti Palosaari case AF9033_TUNER_IT9135_62: 419dc4a2c40SAntti Palosaari len = ARRAY_SIZE(tuner_init_it9135_62); 420dc4a2c40SAntti Palosaari init = tuner_init_it9135_62; 4214902bb39SAntti Palosaari break; 4229a0bf528SMauro Carvalho Chehab default: 4236a087f1fSAntti Palosaari dev_dbg(&dev->client->dev, "unsupported tuner ID=%d\n", 4246a087f1fSAntti Palosaari dev->cfg.tuner); 4259a0bf528SMauro Carvalho Chehab ret = -ENODEV; 4269a0bf528SMauro Carvalho Chehab goto err; 4279a0bf528SMauro Carvalho Chehab } 4289a0bf528SMauro Carvalho Chehab 42909611caaSAntti Palosaari ret = af9033_wr_reg_val_tab(dev, init, len); 4309a0bf528SMauro Carvalho Chehab if (ret < 0) 4319a0bf528SMauro Carvalho Chehab goto err; 4329a0bf528SMauro Carvalho Chehab 43309611caaSAntti Palosaari if (dev->cfg.ts_mode == AF9033_TS_MODE_SERIAL) { 43409611caaSAntti Palosaari ret = af9033_wr_reg_mask(dev, 0x00d91c, 0x01, 0x01); 4359805992fSJose Alberto Reguero if (ret < 0) 4369805992fSJose Alberto Reguero goto err; 437bf97b637SAntti Palosaari 43809611caaSAntti Palosaari ret = af9033_wr_reg_mask(dev, 0x00d917, 0x00, 0x01); 4399805992fSJose Alberto Reguero if (ret < 0) 4409805992fSJose Alberto Reguero goto err; 441bf97b637SAntti Palosaari 44209611caaSAntti Palosaari ret = af9033_wr_reg_mask(dev, 0x00d916, 0x00, 0x01); 4439805992fSJose Alberto Reguero if (ret < 0) 4449805992fSJose Alberto Reguero goto err; 4459805992fSJose Alberto Reguero } 4469805992fSJose Alberto Reguero 44709611caaSAntti Palosaari switch (dev->cfg.tuner) { 448086991ddSAntti Palosaari case AF9033_TUNER_IT9135_60: 449086991ddSAntti Palosaari case AF9033_TUNER_IT9135_61: 450086991ddSAntti Palosaari case AF9033_TUNER_IT9135_62: 45109611caaSAntti Palosaari ret = af9033_wr_reg(dev, 0x800000, 0x01); 452086991ddSAntti Palosaari if (ret < 0) 453086991ddSAntti Palosaari goto err; 454086991ddSAntti Palosaari } 455086991ddSAntti Palosaari 45609611caaSAntti Palosaari dev->bandwidth_hz = 0; /* force to program all parameters */ 4572db4d179SAntti Palosaari /* init stats here in order signal app which stats are supported */ 4582db4d179SAntti Palosaari c->strength.len = 1; 4592db4d179SAntti Palosaari c->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 4602db4d179SAntti Palosaari c->cnr.len = 1; 4612db4d179SAntti Palosaari c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 4622db4d179SAntti Palosaari c->block_count.len = 1; 4632db4d179SAntti Palosaari c->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 4642db4d179SAntti Palosaari c->block_error.len = 1; 4652db4d179SAntti Palosaari c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 4662db4d179SAntti Palosaari c->post_bit_count.len = 1; 4672db4d179SAntti Palosaari c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 4682db4d179SAntti Palosaari c->post_bit_error.len = 1; 4692db4d179SAntti Palosaari c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 4709a0bf528SMauro Carvalho Chehab 4719a0bf528SMauro Carvalho Chehab return 0; 4729a0bf528SMauro Carvalho Chehab 4739a0bf528SMauro Carvalho Chehab err: 4746a087f1fSAntti Palosaari dev_dbg(&dev->client->dev, "failed=%d\n", ret); 4759a0bf528SMauro Carvalho Chehab 4769a0bf528SMauro Carvalho Chehab return ret; 4779a0bf528SMauro Carvalho Chehab } 4789a0bf528SMauro Carvalho Chehab 4799a0bf528SMauro Carvalho Chehab static int af9033_sleep(struct dvb_frontend *fe) 4809a0bf528SMauro Carvalho Chehab { 48109611caaSAntti Palosaari struct af9033_dev *dev = fe->demodulator_priv; 4829a0bf528SMauro Carvalho Chehab int ret, i; 4839a0bf528SMauro Carvalho Chehab u8 tmp; 4849a0bf528SMauro Carvalho Chehab 48509611caaSAntti Palosaari ret = af9033_wr_reg(dev, 0x80004c, 1); 4869a0bf528SMauro Carvalho Chehab if (ret < 0) 4879a0bf528SMauro Carvalho Chehab goto err; 4889a0bf528SMauro Carvalho Chehab 48909611caaSAntti Palosaari ret = af9033_wr_reg(dev, 0x800000, 0); 4909a0bf528SMauro Carvalho Chehab if (ret < 0) 4919a0bf528SMauro Carvalho Chehab goto err; 4929a0bf528SMauro Carvalho Chehab 4939a0bf528SMauro Carvalho Chehab for (i = 100, tmp = 1; i && tmp; i--) { 49409611caaSAntti Palosaari ret = af9033_rd_reg(dev, 0x80004c, &tmp); 4959a0bf528SMauro Carvalho Chehab if (ret < 0) 4969a0bf528SMauro Carvalho Chehab goto err; 4979a0bf528SMauro Carvalho Chehab 4989a0bf528SMauro Carvalho Chehab usleep_range(200, 10000); 4999a0bf528SMauro Carvalho Chehab } 5009a0bf528SMauro Carvalho Chehab 5016a087f1fSAntti Palosaari dev_dbg(&dev->client->dev, "loop=%d\n", i); 5029a0bf528SMauro Carvalho Chehab 5039a0bf528SMauro Carvalho Chehab if (i == 0) { 5049a0bf528SMauro Carvalho Chehab ret = -ETIMEDOUT; 5059a0bf528SMauro Carvalho Chehab goto err; 5069a0bf528SMauro Carvalho Chehab } 5079a0bf528SMauro Carvalho Chehab 50809611caaSAntti Palosaari ret = af9033_wr_reg_mask(dev, 0x80fb24, 0x08, 0x08); 5099a0bf528SMauro Carvalho Chehab if (ret < 0) 5109a0bf528SMauro Carvalho Chehab goto err; 5119a0bf528SMauro Carvalho Chehab 5129a0bf528SMauro Carvalho Chehab /* prevent current leak (?) */ 51309611caaSAntti Palosaari if (dev->cfg.ts_mode == AF9033_TS_MODE_SERIAL) { 5149a0bf528SMauro Carvalho Chehab /* enable parallel TS */ 51509611caaSAntti Palosaari ret = af9033_wr_reg_mask(dev, 0x00d917, 0x00, 0x01); 5169a0bf528SMauro Carvalho Chehab if (ret < 0) 5179a0bf528SMauro Carvalho Chehab goto err; 5189a0bf528SMauro Carvalho Chehab 51909611caaSAntti Palosaari ret = af9033_wr_reg_mask(dev, 0x00d916, 0x01, 0x01); 5209a0bf528SMauro Carvalho Chehab if (ret < 0) 5219a0bf528SMauro Carvalho Chehab goto err; 5229a0bf528SMauro Carvalho Chehab } 5239a0bf528SMauro Carvalho Chehab 5249a0bf528SMauro Carvalho Chehab return 0; 5259a0bf528SMauro Carvalho Chehab 5269a0bf528SMauro Carvalho Chehab err: 5276a087f1fSAntti Palosaari dev_dbg(&dev->client->dev, "failed=%d\n", ret); 5289a0bf528SMauro Carvalho Chehab 5299a0bf528SMauro Carvalho Chehab return ret; 5309a0bf528SMauro Carvalho Chehab } 5319a0bf528SMauro Carvalho Chehab 5329a0bf528SMauro Carvalho Chehab static int af9033_get_tune_settings(struct dvb_frontend *fe, 5339a0bf528SMauro Carvalho Chehab struct dvb_frontend_tune_settings *fesettings) 5349a0bf528SMauro Carvalho Chehab { 535fe8eece1SAntti Palosaari /* 800 => 2000 because IT9135 v2 is slow to gain lock */ 536fe8eece1SAntti Palosaari fesettings->min_delay_ms = 2000; 5379a0bf528SMauro Carvalho Chehab fesettings->step_size = 0; 5389a0bf528SMauro Carvalho Chehab fesettings->max_drift = 0; 5399a0bf528SMauro Carvalho Chehab 5409a0bf528SMauro Carvalho Chehab return 0; 5419a0bf528SMauro Carvalho Chehab } 5429a0bf528SMauro Carvalho Chehab 5439a0bf528SMauro Carvalho Chehab static int af9033_set_frontend(struct dvb_frontend *fe) 5449a0bf528SMauro Carvalho Chehab { 54509611caaSAntti Palosaari struct af9033_dev *dev = fe->demodulator_priv; 5469a0bf528SMauro Carvalho Chehab struct dtv_frontend_properties *c = &fe->dtv_property_cache; 547182b967eSHans-Frieder Vogt int ret, i, spec_inv, sampling_freq; 5489a0bf528SMauro Carvalho Chehab u8 tmp, buf[3], bandwidth_reg_val; 5499a0bf528SMauro Carvalho Chehab u32 if_frequency, freq_cw, adc_freq; 5509a0bf528SMauro Carvalho Chehab 5516a087f1fSAntti Palosaari dev_dbg(&dev->client->dev, "frequency=%d bandwidth_hz=%d\n", 5526a087f1fSAntti Palosaari c->frequency, c->bandwidth_hz); 5539a0bf528SMauro Carvalho Chehab 5549a0bf528SMauro Carvalho Chehab /* check bandwidth */ 5559a0bf528SMauro Carvalho Chehab switch (c->bandwidth_hz) { 5569a0bf528SMauro Carvalho Chehab case 6000000: 5579a0bf528SMauro Carvalho Chehab bandwidth_reg_val = 0x00; 5589a0bf528SMauro Carvalho Chehab break; 5599a0bf528SMauro Carvalho Chehab case 7000000: 5609a0bf528SMauro Carvalho Chehab bandwidth_reg_val = 0x01; 5619a0bf528SMauro Carvalho Chehab break; 5629a0bf528SMauro Carvalho Chehab case 8000000: 5639a0bf528SMauro Carvalho Chehab bandwidth_reg_val = 0x02; 5649a0bf528SMauro Carvalho Chehab break; 5659a0bf528SMauro Carvalho Chehab default: 5666a087f1fSAntti Palosaari dev_dbg(&dev->client->dev, "invalid bandwidth_hz\n"); 5679a0bf528SMauro Carvalho Chehab ret = -EINVAL; 5689a0bf528SMauro Carvalho Chehab goto err; 5699a0bf528SMauro Carvalho Chehab } 5709a0bf528SMauro Carvalho Chehab 5719a0bf528SMauro Carvalho Chehab /* program tuner */ 5729a0bf528SMauro Carvalho Chehab if (fe->ops.tuner_ops.set_params) 5739a0bf528SMauro Carvalho Chehab fe->ops.tuner_ops.set_params(fe); 5749a0bf528SMauro Carvalho Chehab 5759a0bf528SMauro Carvalho Chehab /* program CFOE coefficients */ 57609611caaSAntti Palosaari if (c->bandwidth_hz != dev->bandwidth_hz) { 5779a0bf528SMauro Carvalho Chehab for (i = 0; i < ARRAY_SIZE(coeff_lut); i++) { 57809611caaSAntti Palosaari if (coeff_lut[i].clock == dev->cfg.clock && 5799a0bf528SMauro Carvalho Chehab coeff_lut[i].bandwidth_hz == c->bandwidth_hz) { 5809a0bf528SMauro Carvalho Chehab break; 5819a0bf528SMauro Carvalho Chehab } 5829a0bf528SMauro Carvalho Chehab } 583060f79d5SMauro Carvalho Chehab if (i == ARRAY_SIZE(coeff_lut)) { 584060f79d5SMauro Carvalho Chehab dev_err(&dev->client->dev, 585060f79d5SMauro Carvalho Chehab "Couldn't find LUT config for clock=%d\n", 586060f79d5SMauro Carvalho Chehab dev->cfg.clock); 587060f79d5SMauro Carvalho Chehab ret = -EINVAL; 588060f79d5SMauro Carvalho Chehab goto err; 589060f79d5SMauro Carvalho Chehab } 590060f79d5SMauro Carvalho Chehab 59109611caaSAntti Palosaari ret = af9033_wr_regs(dev, 0x800001, 5929a0bf528SMauro Carvalho Chehab coeff_lut[i].val, sizeof(coeff_lut[i].val)); 5939a0bf528SMauro Carvalho Chehab } 5949a0bf528SMauro Carvalho Chehab 5959a0bf528SMauro Carvalho Chehab /* program frequency control */ 59609611caaSAntti Palosaari if (c->bandwidth_hz != dev->bandwidth_hz) { 59709611caaSAntti Palosaari spec_inv = dev->cfg.spec_inv ? -1 : 1; 5989a0bf528SMauro Carvalho Chehab 5999a0bf528SMauro Carvalho Chehab for (i = 0; i < ARRAY_SIZE(clock_adc_lut); i++) { 60009611caaSAntti Palosaari if (clock_adc_lut[i].clock == dev->cfg.clock) 6019a0bf528SMauro Carvalho Chehab break; 6029a0bf528SMauro Carvalho Chehab } 603060f79d5SMauro Carvalho Chehab if (i == ARRAY_SIZE(clock_adc_lut)) { 604060f79d5SMauro Carvalho Chehab dev_err(&dev->client->dev, 605060f79d5SMauro Carvalho Chehab "Couldn't find ADC clock for clock=%d\n", 606060f79d5SMauro Carvalho Chehab dev->cfg.clock); 607060f79d5SMauro Carvalho Chehab ret = -EINVAL; 608060f79d5SMauro Carvalho Chehab goto err; 609060f79d5SMauro Carvalho Chehab } 6109a0bf528SMauro Carvalho Chehab adc_freq = clock_adc_lut[i].adc; 6119a0bf528SMauro Carvalho Chehab 6129a0bf528SMauro Carvalho Chehab /* get used IF frequency */ 6139a0bf528SMauro Carvalho Chehab if (fe->ops.tuner_ops.get_if_frequency) 6149a0bf528SMauro Carvalho Chehab fe->ops.tuner_ops.get_if_frequency(fe, &if_frequency); 6159a0bf528SMauro Carvalho Chehab else 6169a0bf528SMauro Carvalho Chehab if_frequency = 0; 6179a0bf528SMauro Carvalho Chehab 618182b967eSHans-Frieder Vogt sampling_freq = if_frequency; 6199a0bf528SMauro Carvalho Chehab 620182b967eSHans-Frieder Vogt while (sampling_freq > (adc_freq / 2)) 621182b967eSHans-Frieder Vogt sampling_freq -= adc_freq; 622182b967eSHans-Frieder Vogt 623182b967eSHans-Frieder Vogt if (sampling_freq >= 0) 6249a0bf528SMauro Carvalho Chehab spec_inv *= -1; 6259a0bf528SMauro Carvalho Chehab else 626182b967eSHans-Frieder Vogt sampling_freq *= -1; 6279a0bf528SMauro Carvalho Chehab 62809611caaSAntti Palosaari freq_cw = af9033_div(dev, sampling_freq, adc_freq, 23ul); 6299a0bf528SMauro Carvalho Chehab 6309a0bf528SMauro Carvalho Chehab if (spec_inv == -1) 631182b967eSHans-Frieder Vogt freq_cw = 0x800000 - freq_cw; 6329a0bf528SMauro Carvalho Chehab 63309611caaSAntti Palosaari if (dev->cfg.adc_multiplier == AF9033_ADC_MULTIPLIER_2X) 6349a0bf528SMauro Carvalho Chehab freq_cw /= 2; 6359a0bf528SMauro Carvalho Chehab 6369a0bf528SMauro Carvalho Chehab buf[0] = (freq_cw >> 0) & 0xff; 6379a0bf528SMauro Carvalho Chehab buf[1] = (freq_cw >> 8) & 0xff; 6389a0bf528SMauro Carvalho Chehab buf[2] = (freq_cw >> 16) & 0x7f; 639fe8eece1SAntti Palosaari 640fe8eece1SAntti Palosaari /* FIXME: there seems to be calculation error here... */ 641fe8eece1SAntti Palosaari if (if_frequency == 0) 642fe8eece1SAntti Palosaari buf[2] = 0; 643fe8eece1SAntti Palosaari 64409611caaSAntti Palosaari ret = af9033_wr_regs(dev, 0x800029, buf, 3); 6459a0bf528SMauro Carvalho Chehab if (ret < 0) 6469a0bf528SMauro Carvalho Chehab goto err; 6479a0bf528SMauro Carvalho Chehab 64809611caaSAntti Palosaari dev->bandwidth_hz = c->bandwidth_hz; 6499a0bf528SMauro Carvalho Chehab } 6509a0bf528SMauro Carvalho Chehab 65109611caaSAntti Palosaari ret = af9033_wr_reg_mask(dev, 0x80f904, bandwidth_reg_val, 0x03); 6529a0bf528SMauro Carvalho Chehab if (ret < 0) 6539a0bf528SMauro Carvalho Chehab goto err; 6549a0bf528SMauro Carvalho Chehab 65509611caaSAntti Palosaari ret = af9033_wr_reg(dev, 0x800040, 0x00); 6569a0bf528SMauro Carvalho Chehab if (ret < 0) 6579a0bf528SMauro Carvalho Chehab goto err; 6589a0bf528SMauro Carvalho Chehab 65909611caaSAntti Palosaari ret = af9033_wr_reg(dev, 0x800047, 0x00); 6609a0bf528SMauro Carvalho Chehab if (ret < 0) 6619a0bf528SMauro Carvalho Chehab goto err; 6629a0bf528SMauro Carvalho Chehab 66309611caaSAntti Palosaari ret = af9033_wr_reg_mask(dev, 0x80f999, 0x00, 0x01); 6649a0bf528SMauro Carvalho Chehab if (ret < 0) 6659a0bf528SMauro Carvalho Chehab goto err; 6669a0bf528SMauro Carvalho Chehab 6679a0bf528SMauro Carvalho Chehab if (c->frequency <= 230000000) 6689a0bf528SMauro Carvalho Chehab tmp = 0x00; /* VHF */ 6699a0bf528SMauro Carvalho Chehab else 6709a0bf528SMauro Carvalho Chehab tmp = 0x01; /* UHF */ 6719a0bf528SMauro Carvalho Chehab 67209611caaSAntti Palosaari ret = af9033_wr_reg(dev, 0x80004b, tmp); 6739a0bf528SMauro Carvalho Chehab if (ret < 0) 6749a0bf528SMauro Carvalho Chehab goto err; 6759a0bf528SMauro Carvalho Chehab 67609611caaSAntti Palosaari ret = af9033_wr_reg(dev, 0x800000, 0x00); 6779a0bf528SMauro Carvalho Chehab if (ret < 0) 6789a0bf528SMauro Carvalho Chehab goto err; 6799a0bf528SMauro Carvalho Chehab 6809a0bf528SMauro Carvalho Chehab return 0; 6819a0bf528SMauro Carvalho Chehab 6829a0bf528SMauro Carvalho Chehab err: 6836a087f1fSAntti Palosaari dev_dbg(&dev->client->dev, "failed=%d\n", ret); 6849a0bf528SMauro Carvalho Chehab 6859a0bf528SMauro Carvalho Chehab return ret; 6869a0bf528SMauro Carvalho Chehab } 6879a0bf528SMauro Carvalho Chehab 6887e3e68bcSMauro Carvalho Chehab static int af9033_get_frontend(struct dvb_frontend *fe, 6897e3e68bcSMauro Carvalho Chehab struct dtv_frontend_properties *c) 6909a0bf528SMauro Carvalho Chehab { 69109611caaSAntti Palosaari struct af9033_dev *dev = fe->demodulator_priv; 6929a0bf528SMauro Carvalho Chehab int ret; 6939a0bf528SMauro Carvalho Chehab u8 buf[8]; 6949a0bf528SMauro Carvalho Chehab 6956a087f1fSAntti Palosaari dev_dbg(&dev->client->dev, "\n"); 6969a0bf528SMauro Carvalho Chehab 6979a0bf528SMauro Carvalho Chehab /* read all needed registers */ 69809611caaSAntti Palosaari ret = af9033_rd_regs(dev, 0x80f900, buf, sizeof(buf)); 6999a0bf528SMauro Carvalho Chehab if (ret < 0) 7009a0bf528SMauro Carvalho Chehab goto err; 7019a0bf528SMauro Carvalho Chehab 7029a0bf528SMauro Carvalho Chehab switch ((buf[0] >> 0) & 3) { 7039a0bf528SMauro Carvalho Chehab case 0: 7049a0bf528SMauro Carvalho Chehab c->transmission_mode = TRANSMISSION_MODE_2K; 7059a0bf528SMauro Carvalho Chehab break; 7069a0bf528SMauro Carvalho Chehab case 1: 7079a0bf528SMauro Carvalho Chehab c->transmission_mode = TRANSMISSION_MODE_8K; 7089a0bf528SMauro Carvalho Chehab break; 7099a0bf528SMauro Carvalho Chehab } 7109a0bf528SMauro Carvalho Chehab 7119a0bf528SMauro Carvalho Chehab switch ((buf[1] >> 0) & 3) { 7129a0bf528SMauro Carvalho Chehab case 0: 7139a0bf528SMauro Carvalho Chehab c->guard_interval = GUARD_INTERVAL_1_32; 7149a0bf528SMauro Carvalho Chehab break; 7159a0bf528SMauro Carvalho Chehab case 1: 7169a0bf528SMauro Carvalho Chehab c->guard_interval = GUARD_INTERVAL_1_16; 7179a0bf528SMauro Carvalho Chehab break; 7189a0bf528SMauro Carvalho Chehab case 2: 7199a0bf528SMauro Carvalho Chehab c->guard_interval = GUARD_INTERVAL_1_8; 7209a0bf528SMauro Carvalho Chehab break; 7219a0bf528SMauro Carvalho Chehab case 3: 7229a0bf528SMauro Carvalho Chehab c->guard_interval = GUARD_INTERVAL_1_4; 7239a0bf528SMauro Carvalho Chehab break; 7249a0bf528SMauro Carvalho Chehab } 7259a0bf528SMauro Carvalho Chehab 7269a0bf528SMauro Carvalho Chehab switch ((buf[2] >> 0) & 7) { 7279a0bf528SMauro Carvalho Chehab case 0: 7289a0bf528SMauro Carvalho Chehab c->hierarchy = HIERARCHY_NONE; 7299a0bf528SMauro Carvalho Chehab break; 7309a0bf528SMauro Carvalho Chehab case 1: 7319a0bf528SMauro Carvalho Chehab c->hierarchy = HIERARCHY_1; 7329a0bf528SMauro Carvalho Chehab break; 7339a0bf528SMauro Carvalho Chehab case 2: 7349a0bf528SMauro Carvalho Chehab c->hierarchy = HIERARCHY_2; 7359a0bf528SMauro Carvalho Chehab break; 7369a0bf528SMauro Carvalho Chehab case 3: 7379a0bf528SMauro Carvalho Chehab c->hierarchy = HIERARCHY_4; 7389a0bf528SMauro Carvalho Chehab break; 7399a0bf528SMauro Carvalho Chehab } 7409a0bf528SMauro Carvalho Chehab 7419a0bf528SMauro Carvalho Chehab switch ((buf[3] >> 0) & 3) { 7429a0bf528SMauro Carvalho Chehab case 0: 7439a0bf528SMauro Carvalho Chehab c->modulation = QPSK; 7449a0bf528SMauro Carvalho Chehab break; 7459a0bf528SMauro Carvalho Chehab case 1: 7469a0bf528SMauro Carvalho Chehab c->modulation = QAM_16; 7479a0bf528SMauro Carvalho Chehab break; 7489a0bf528SMauro Carvalho Chehab case 2: 7499a0bf528SMauro Carvalho Chehab c->modulation = QAM_64; 7509a0bf528SMauro Carvalho Chehab break; 7519a0bf528SMauro Carvalho Chehab } 7529a0bf528SMauro Carvalho Chehab 7539a0bf528SMauro Carvalho Chehab switch ((buf[4] >> 0) & 3) { 7549a0bf528SMauro Carvalho Chehab case 0: 7559a0bf528SMauro Carvalho Chehab c->bandwidth_hz = 6000000; 7569a0bf528SMauro Carvalho Chehab break; 7579a0bf528SMauro Carvalho Chehab case 1: 7589a0bf528SMauro Carvalho Chehab c->bandwidth_hz = 7000000; 7599a0bf528SMauro Carvalho Chehab break; 7609a0bf528SMauro Carvalho Chehab case 2: 7619a0bf528SMauro Carvalho Chehab c->bandwidth_hz = 8000000; 7629a0bf528SMauro Carvalho Chehab break; 7639a0bf528SMauro Carvalho Chehab } 7649a0bf528SMauro Carvalho Chehab 7659a0bf528SMauro Carvalho Chehab switch ((buf[6] >> 0) & 7) { 7669a0bf528SMauro Carvalho Chehab case 0: 7679a0bf528SMauro Carvalho Chehab c->code_rate_HP = FEC_1_2; 7689a0bf528SMauro Carvalho Chehab break; 7699a0bf528SMauro Carvalho Chehab case 1: 7709a0bf528SMauro Carvalho Chehab c->code_rate_HP = FEC_2_3; 7719a0bf528SMauro Carvalho Chehab break; 7729a0bf528SMauro Carvalho Chehab case 2: 7739a0bf528SMauro Carvalho Chehab c->code_rate_HP = FEC_3_4; 7749a0bf528SMauro Carvalho Chehab break; 7759a0bf528SMauro Carvalho Chehab case 3: 7769a0bf528SMauro Carvalho Chehab c->code_rate_HP = FEC_5_6; 7779a0bf528SMauro Carvalho Chehab break; 7789a0bf528SMauro Carvalho Chehab case 4: 7799a0bf528SMauro Carvalho Chehab c->code_rate_HP = FEC_7_8; 7809a0bf528SMauro Carvalho Chehab break; 7819a0bf528SMauro Carvalho Chehab case 5: 7829a0bf528SMauro Carvalho Chehab c->code_rate_HP = FEC_NONE; 7839a0bf528SMauro Carvalho Chehab break; 7849a0bf528SMauro Carvalho Chehab } 7859a0bf528SMauro Carvalho Chehab 7869a0bf528SMauro Carvalho Chehab switch ((buf[7] >> 0) & 7) { 7879a0bf528SMauro Carvalho Chehab case 0: 7889a0bf528SMauro Carvalho Chehab c->code_rate_LP = FEC_1_2; 7899a0bf528SMauro Carvalho Chehab break; 7909a0bf528SMauro Carvalho Chehab case 1: 7919a0bf528SMauro Carvalho Chehab c->code_rate_LP = FEC_2_3; 7929a0bf528SMauro Carvalho Chehab break; 7939a0bf528SMauro Carvalho Chehab case 2: 7949a0bf528SMauro Carvalho Chehab c->code_rate_LP = FEC_3_4; 7959a0bf528SMauro Carvalho Chehab break; 7969a0bf528SMauro Carvalho Chehab case 3: 7979a0bf528SMauro Carvalho Chehab c->code_rate_LP = FEC_5_6; 7989a0bf528SMauro Carvalho Chehab break; 7999a0bf528SMauro Carvalho Chehab case 4: 8009a0bf528SMauro Carvalho Chehab c->code_rate_LP = FEC_7_8; 8019a0bf528SMauro Carvalho Chehab break; 8029a0bf528SMauro Carvalho Chehab case 5: 8039a0bf528SMauro Carvalho Chehab c->code_rate_LP = FEC_NONE; 8049a0bf528SMauro Carvalho Chehab break; 8059a0bf528SMauro Carvalho Chehab } 8069a0bf528SMauro Carvalho Chehab 8079a0bf528SMauro Carvalho Chehab return 0; 8089a0bf528SMauro Carvalho Chehab 8099a0bf528SMauro Carvalho Chehab err: 8106a087f1fSAntti Palosaari dev_dbg(&dev->client->dev, "failed=%d\n", ret); 8119a0bf528SMauro Carvalho Chehab 8129a0bf528SMauro Carvalho Chehab return ret; 8139a0bf528SMauro Carvalho Chehab } 8149a0bf528SMauro Carvalho Chehab 8150df289a2SMauro Carvalho Chehab static int af9033_read_status(struct dvb_frontend *fe, enum fe_status *status) 8169a0bf528SMauro Carvalho Chehab { 81709611caaSAntti Palosaari struct af9033_dev *dev = fe->demodulator_priv; 818659a0999SAntti Palosaari struct dtv_frontend_properties *c = &fe->dtv_property_cache; 819659a0999SAntti Palosaari int ret, i, tmp; 820659a0999SAntti Palosaari u8 u8tmp, buf[7]; 821659a0999SAntti Palosaari 822659a0999SAntti Palosaari dev_dbg(&dev->client->dev, "\n"); 8239a0bf528SMauro Carvalho Chehab 8249a0bf528SMauro Carvalho Chehab *status = 0; 8259a0bf528SMauro Carvalho Chehab 8269a0bf528SMauro Carvalho Chehab /* radio channel status, 0=no result, 1=has signal, 2=no signal */ 827659a0999SAntti Palosaari ret = af9033_rd_reg(dev, 0x800047, &u8tmp); 8289a0bf528SMauro Carvalho Chehab if (ret < 0) 8299a0bf528SMauro Carvalho Chehab goto err; 8309a0bf528SMauro Carvalho Chehab 8319a0bf528SMauro Carvalho Chehab /* has signal */ 832659a0999SAntti Palosaari if (u8tmp == 0x01) 8339a0bf528SMauro Carvalho Chehab *status |= FE_HAS_SIGNAL; 8349a0bf528SMauro Carvalho Chehab 835659a0999SAntti Palosaari if (u8tmp != 0x02) { 8369a0bf528SMauro Carvalho Chehab /* TPS lock */ 837659a0999SAntti Palosaari ret = af9033_rd_reg_mask(dev, 0x80f5a9, &u8tmp, 0x01); 8389a0bf528SMauro Carvalho Chehab if (ret < 0) 8399a0bf528SMauro Carvalho Chehab goto err; 8409a0bf528SMauro Carvalho Chehab 841659a0999SAntti Palosaari if (u8tmp) 8429a0bf528SMauro Carvalho Chehab *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER | 8439a0bf528SMauro Carvalho Chehab FE_HAS_VITERBI; 8449a0bf528SMauro Carvalho Chehab 8459a0bf528SMauro Carvalho Chehab /* full lock */ 846659a0999SAntti Palosaari ret = af9033_rd_reg_mask(dev, 0x80f999, &u8tmp, 0x01); 8479a0bf528SMauro Carvalho Chehab if (ret < 0) 8489a0bf528SMauro Carvalho Chehab goto err; 8499a0bf528SMauro Carvalho Chehab 850659a0999SAntti Palosaari if (u8tmp) 8519a0bf528SMauro Carvalho Chehab *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER | 8529a0bf528SMauro Carvalho Chehab FE_HAS_VITERBI | FE_HAS_SYNC | 8539a0bf528SMauro Carvalho Chehab FE_HAS_LOCK; 8549a0bf528SMauro Carvalho Chehab } 8559a0bf528SMauro Carvalho Chehab 85683f11619SAntti Palosaari dev->fe_status = *status; 85783f11619SAntti Palosaari 858659a0999SAntti Palosaari /* signal strength */ 859659a0999SAntti Palosaari if (dev->fe_status & FE_HAS_SIGNAL) { 860659a0999SAntti Palosaari if (dev->is_af9035) { 861659a0999SAntti Palosaari ret = af9033_rd_reg(dev, 0x80004a, &u8tmp); 862659a0999SAntti Palosaari if (ret) 863659a0999SAntti Palosaari goto err; 864659a0999SAntti Palosaari tmp = -u8tmp * 1000; 865659a0999SAntti Palosaari } else { 866659a0999SAntti Palosaari ret = af9033_rd_reg(dev, 0x8000f7, &u8tmp); 867659a0999SAntti Palosaari if (ret) 868659a0999SAntti Palosaari goto err; 869659a0999SAntti Palosaari tmp = (u8tmp - 100) * 1000; 870659a0999SAntti Palosaari } 871659a0999SAntti Palosaari 872659a0999SAntti Palosaari c->strength.len = 1; 873659a0999SAntti Palosaari c->strength.stat[0].scale = FE_SCALE_DECIBEL; 874659a0999SAntti Palosaari c->strength.stat[0].svalue = tmp; 875659a0999SAntti Palosaari } else { 876659a0999SAntti Palosaari c->strength.len = 1; 877659a0999SAntti Palosaari c->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 878659a0999SAntti Palosaari } 879659a0999SAntti Palosaari 880659a0999SAntti Palosaari /* CNR */ 881659a0999SAntti Palosaari if (dev->fe_status & FE_HAS_VITERBI) { 882659a0999SAntti Palosaari u32 snr_val, snr_lut_size; 883659a0999SAntti Palosaari const struct val_snr *snr_lut; 884659a0999SAntti Palosaari 885659a0999SAntti Palosaari /* read value */ 886659a0999SAntti Palosaari ret = af9033_rd_regs(dev, 0x80002c, buf, 3); 887659a0999SAntti Palosaari if (ret) 888659a0999SAntti Palosaari goto err; 889659a0999SAntti Palosaari 890659a0999SAntti Palosaari snr_val = (buf[2] << 16) | (buf[1] << 8) | (buf[0] << 0); 891659a0999SAntti Palosaari 892659a0999SAntti Palosaari /* read superframe number */ 893659a0999SAntti Palosaari ret = af9033_rd_reg(dev, 0x80f78b, &u8tmp); 894659a0999SAntti Palosaari if (ret) 895659a0999SAntti Palosaari goto err; 896659a0999SAntti Palosaari 897659a0999SAntti Palosaari if (u8tmp) 898659a0999SAntti Palosaari snr_val /= u8tmp; 899659a0999SAntti Palosaari 900659a0999SAntti Palosaari /* read current transmission mode */ 901659a0999SAntti Palosaari ret = af9033_rd_reg(dev, 0x80f900, &u8tmp); 902659a0999SAntti Palosaari if (ret) 903659a0999SAntti Palosaari goto err; 904659a0999SAntti Palosaari 905659a0999SAntti Palosaari switch ((u8tmp >> 0) & 3) { 906659a0999SAntti Palosaari case 0: 907659a0999SAntti Palosaari snr_val *= 4; 908659a0999SAntti Palosaari break; 909659a0999SAntti Palosaari case 1: 910659a0999SAntti Palosaari snr_val *= 1; 911659a0999SAntti Palosaari break; 912659a0999SAntti Palosaari case 2: 913659a0999SAntti Palosaari snr_val *= 2; 914659a0999SAntti Palosaari break; 915659a0999SAntti Palosaari default: 916659a0999SAntti Palosaari snr_val *= 0; 917659a0999SAntti Palosaari break; 918659a0999SAntti Palosaari } 919659a0999SAntti Palosaari 920659a0999SAntti Palosaari /* read current modulation */ 921659a0999SAntti Palosaari ret = af9033_rd_reg(dev, 0x80f903, &u8tmp); 922659a0999SAntti Palosaari if (ret) 923659a0999SAntti Palosaari goto err; 924659a0999SAntti Palosaari 925659a0999SAntti Palosaari switch ((u8tmp >> 0) & 3) { 926659a0999SAntti Palosaari case 0: 927659a0999SAntti Palosaari snr_lut_size = ARRAY_SIZE(qpsk_snr_lut); 928659a0999SAntti Palosaari snr_lut = qpsk_snr_lut; 929659a0999SAntti Palosaari break; 930659a0999SAntti Palosaari case 1: 931659a0999SAntti Palosaari snr_lut_size = ARRAY_SIZE(qam16_snr_lut); 932659a0999SAntti Palosaari snr_lut = qam16_snr_lut; 933659a0999SAntti Palosaari break; 934659a0999SAntti Palosaari case 2: 935659a0999SAntti Palosaari snr_lut_size = ARRAY_SIZE(qam64_snr_lut); 936659a0999SAntti Palosaari snr_lut = qam64_snr_lut; 937659a0999SAntti Palosaari break; 938659a0999SAntti Palosaari default: 939659a0999SAntti Palosaari snr_lut_size = 0; 940659a0999SAntti Palosaari tmp = 0; 941659a0999SAntti Palosaari break; 942659a0999SAntti Palosaari } 943659a0999SAntti Palosaari 944659a0999SAntti Palosaari for (i = 0; i < snr_lut_size; i++) { 945659a0999SAntti Palosaari tmp = snr_lut[i].snr * 1000; 946659a0999SAntti Palosaari if (snr_val < snr_lut[i].val) 947659a0999SAntti Palosaari break; 948659a0999SAntti Palosaari } 949659a0999SAntti Palosaari 950659a0999SAntti Palosaari c->cnr.len = 1; 951659a0999SAntti Palosaari c->cnr.stat[0].scale = FE_SCALE_DECIBEL; 952659a0999SAntti Palosaari c->cnr.stat[0].svalue = tmp; 953659a0999SAntti Palosaari } else { 954659a0999SAntti Palosaari c->cnr.len = 1; 955659a0999SAntti Palosaari c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 956659a0999SAntti Palosaari } 957659a0999SAntti Palosaari 958659a0999SAntti Palosaari /* UCB/PER/BER */ 959659a0999SAntti Palosaari if (dev->fe_status & FE_HAS_LOCK) { 960659a0999SAntti Palosaari /* outer FEC, 204 byte packets */ 961659a0999SAntti Palosaari u16 abort_packet_count, rsd_packet_count; 962659a0999SAntti Palosaari /* inner FEC, bits */ 963659a0999SAntti Palosaari u32 rsd_bit_err_count; 964659a0999SAntti Palosaari 965659a0999SAntti Palosaari /* 966659a0999SAntti Palosaari * Packet count used for measurement is 10000 967659a0999SAntti Palosaari * (rsd_packet_count). Maybe it should be increased? 968659a0999SAntti Palosaari */ 969659a0999SAntti Palosaari 970659a0999SAntti Palosaari ret = af9033_rd_regs(dev, 0x800032, buf, 7); 971659a0999SAntti Palosaari if (ret) 972659a0999SAntti Palosaari goto err; 973659a0999SAntti Palosaari 974659a0999SAntti Palosaari abort_packet_count = (buf[1] << 8) | (buf[0] << 0); 975659a0999SAntti Palosaari rsd_bit_err_count = (buf[4] << 16) | (buf[3] << 8) | buf[2]; 976659a0999SAntti Palosaari rsd_packet_count = (buf[6] << 8) | (buf[5] << 0); 977659a0999SAntti Palosaari 978659a0999SAntti Palosaari dev->error_block_count += abort_packet_count; 979659a0999SAntti Palosaari dev->total_block_count += rsd_packet_count; 980659a0999SAntti Palosaari dev->post_bit_error += rsd_bit_err_count; 981659a0999SAntti Palosaari dev->post_bit_count += rsd_packet_count * 204 * 8; 982659a0999SAntti Palosaari 983659a0999SAntti Palosaari c->block_count.len = 1; 984659a0999SAntti Palosaari c->block_count.stat[0].scale = FE_SCALE_COUNTER; 985659a0999SAntti Palosaari c->block_count.stat[0].uvalue = dev->total_block_count; 986659a0999SAntti Palosaari 987659a0999SAntti Palosaari c->block_error.len = 1; 988659a0999SAntti Palosaari c->block_error.stat[0].scale = FE_SCALE_COUNTER; 989659a0999SAntti Palosaari c->block_error.stat[0].uvalue = dev->error_block_count; 990659a0999SAntti Palosaari 991659a0999SAntti Palosaari c->post_bit_count.len = 1; 992659a0999SAntti Palosaari c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER; 993659a0999SAntti Palosaari c->post_bit_count.stat[0].uvalue = dev->post_bit_count; 994659a0999SAntti Palosaari 995659a0999SAntti Palosaari c->post_bit_error.len = 1; 996659a0999SAntti Palosaari c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER; 997659a0999SAntti Palosaari c->post_bit_error.stat[0].uvalue = dev->post_bit_error; 998659a0999SAntti Palosaari } 999659a0999SAntti Palosaari 10009a0bf528SMauro Carvalho Chehab return 0; 10019a0bf528SMauro Carvalho Chehab 10029a0bf528SMauro Carvalho Chehab err: 10036a087f1fSAntti Palosaari dev_dbg(&dev->client->dev, "failed=%d\n", ret); 10049a0bf528SMauro Carvalho Chehab 10059a0bf528SMauro Carvalho Chehab return ret; 10069a0bf528SMauro Carvalho Chehab } 10079a0bf528SMauro Carvalho Chehab 10089a0bf528SMauro Carvalho Chehab static int af9033_read_snr(struct dvb_frontend *fe, u16 *snr) 10099a0bf528SMauro Carvalho Chehab { 101009611caaSAntti Palosaari struct af9033_dev *dev = fe->demodulator_priv; 10116b457786SAntti Palosaari struct dtv_frontend_properties *c = &dev->fe.dtv_property_cache; 10126d03f6a8SBimow Chen int ret; 10136d03f6a8SBimow Chen u8 u8tmp; 10149a0bf528SMauro Carvalho Chehab 10156b457786SAntti Palosaari /* use DVBv5 CNR */ 10166d03f6a8SBimow Chen if (c->cnr.stat[0].scale == FE_SCALE_DECIBEL) { 1017c3a80cd0SAntti Palosaari /* Return 0.1 dB for AF9030 and 0-0xffff for IT9130. */ 1018c3a80cd0SAntti Palosaari if (dev->is_af9035) { 1019c3a80cd0SAntti Palosaari /* 1000x => 10x (0.1 dB) */ 1020c3a80cd0SAntti Palosaari *snr = div_s64(c->cnr.stat[0].svalue, 100); 1021c3a80cd0SAntti Palosaari } else { 1022c3a80cd0SAntti Palosaari /* 1000x => 1x (1 dB) */ 10236d03f6a8SBimow Chen *snr = div_s64(c->cnr.stat[0].svalue, 1000); 10246d03f6a8SBimow Chen 10256d03f6a8SBimow Chen /* read current modulation */ 10266d03f6a8SBimow Chen ret = af9033_rd_reg(dev, 0x80f903, &u8tmp); 10276d03f6a8SBimow Chen if (ret) 10286d03f6a8SBimow Chen goto err; 10296d03f6a8SBimow Chen 10306d03f6a8SBimow Chen /* scale value to 0x0000-0xffff */ 10316d03f6a8SBimow Chen switch ((u8tmp >> 0) & 3) { 10326d03f6a8SBimow Chen case 0: 1033c3a80cd0SAntti Palosaari *snr = *snr * 0xffff / 23; 10346d03f6a8SBimow Chen break; 10356d03f6a8SBimow Chen case 1: 1036c3a80cd0SAntti Palosaari *snr = *snr * 0xffff / 26; 10376d03f6a8SBimow Chen break; 10386d03f6a8SBimow Chen case 2: 1039c3a80cd0SAntti Palosaari *snr = *snr * 0xffff / 32; 10406d03f6a8SBimow Chen break; 10416d03f6a8SBimow Chen default: 10426d03f6a8SBimow Chen goto err; 10436d03f6a8SBimow Chen } 1044c3a80cd0SAntti Palosaari } 10456d03f6a8SBimow Chen } else { 10466b457786SAntti Palosaari *snr = 0; 10476d03f6a8SBimow Chen } 10489a0bf528SMauro Carvalho Chehab 10499a0bf528SMauro Carvalho Chehab return 0; 10506d03f6a8SBimow Chen 10516d03f6a8SBimow Chen err: 10526d03f6a8SBimow Chen dev_dbg(&dev->client->dev, "failed=%d\n", ret); 10536d03f6a8SBimow Chen 10546d03f6a8SBimow Chen return ret; 10559a0bf528SMauro Carvalho Chehab } 10569a0bf528SMauro Carvalho Chehab 10579a0bf528SMauro Carvalho Chehab static int af9033_read_signal_strength(struct dvb_frontend *fe, u16 *strength) 10589a0bf528SMauro Carvalho Chehab { 105909611caaSAntti Palosaari struct af9033_dev *dev = fe->demodulator_priv; 10603adec272SBimow Chen struct dtv_frontend_properties *c = &dev->fe.dtv_property_cache; 10613adec272SBimow Chen int ret, tmp, power_real; 10623adec272SBimow Chen u8 u8tmp, gain_offset, buf[7]; 10639a0bf528SMauro Carvalho Chehab 10643adec272SBimow Chen if (dev->is_af9035) { 10650b0d9628SAntti Palosaari /* read signal strength of 0-100 scale */ 10660b0d9628SAntti Palosaari ret = af9033_rd_reg(dev, 0x800048, &u8tmp); 10670b0d9628SAntti Palosaari if (ret < 0) 10680b0d9628SAntti Palosaari goto err; 10690b0d9628SAntti Palosaari 10703adec272SBimow Chen /* scale value to 0x0000-0xffff */ 10713adec272SBimow Chen *strength = u8tmp * 0xffff / 100; 10723adec272SBimow Chen } else { 10733adec272SBimow Chen ret = af9033_rd_reg(dev, 0x8000f7, &u8tmp); 10741620d221SAntti Palosaari if (ret < 0) 10751620d221SAntti Palosaari goto err; 10761620d221SAntti Palosaari 10771620d221SAntti Palosaari ret = af9033_rd_regs(dev, 0x80f900, buf, 7); 10781620d221SAntti Palosaari if (ret < 0) 10791620d221SAntti Palosaari goto err; 10803adec272SBimow Chen 10813adec272SBimow Chen if (c->frequency <= 300000000) 10823adec272SBimow Chen gain_offset = 7; /* VHF */ 10833adec272SBimow Chen else 10843adec272SBimow Chen gain_offset = 4; /* UHF */ 10853adec272SBimow Chen 10863adec272SBimow Chen power_real = (u8tmp - 100 - gain_offset) - 10873adec272SBimow Chen power_reference[((buf[3] >> 0) & 3)][((buf[6] >> 0) & 7)]; 10883adec272SBimow Chen 10893adec272SBimow Chen if (power_real < -15) 10903adec272SBimow Chen tmp = 0; 10913adec272SBimow Chen else if ((power_real >= -15) && (power_real < 0)) 10923adec272SBimow Chen tmp = (2 * (power_real + 15)) / 3; 10933adec272SBimow Chen else if ((power_real >= 0) && (power_real < 20)) 10943adec272SBimow Chen tmp = 4 * power_real + 10; 10953adec272SBimow Chen else if ((power_real >= 20) && (power_real < 35)) 10963adec272SBimow Chen tmp = (2 * (power_real - 20)) / 3 + 90; 10973adec272SBimow Chen else 10983adec272SBimow Chen tmp = 100; 10999a0bf528SMauro Carvalho Chehab 11009a0bf528SMauro Carvalho Chehab /* scale value to 0x0000-0xffff */ 11013adec272SBimow Chen *strength = tmp * 0xffff / 100; 11023adec272SBimow Chen } 11033adec272SBimow Chen 11049a0bf528SMauro Carvalho Chehab return 0; 11059a0bf528SMauro Carvalho Chehab 11069a0bf528SMauro Carvalho Chehab err: 11076a087f1fSAntti Palosaari dev_dbg(&dev->client->dev, "failed=%d\n", ret); 11089a0bf528SMauro Carvalho Chehab 11099a0bf528SMauro Carvalho Chehab return ret; 11109a0bf528SMauro Carvalho Chehab } 11119a0bf528SMauro Carvalho Chehab 11129a0bf528SMauro Carvalho Chehab static int af9033_read_ber(struct dvb_frontend *fe, u32 *ber) 11139a0bf528SMauro Carvalho Chehab { 111409611caaSAntti Palosaari struct af9033_dev *dev = fe->demodulator_priv; 11159a0bf528SMauro Carvalho Chehab 1116e53c4744SAntti Palosaari *ber = (dev->post_bit_error - dev->post_bit_error_prev); 1117e53c4744SAntti Palosaari dev->post_bit_error_prev = dev->post_bit_error; 11189a0bf528SMauro Carvalho Chehab 11199a0bf528SMauro Carvalho Chehab return 0; 11209a0bf528SMauro Carvalho Chehab } 11219a0bf528SMauro Carvalho Chehab 11229a0bf528SMauro Carvalho Chehab static int af9033_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks) 11239a0bf528SMauro Carvalho Chehab { 112409611caaSAntti Palosaari struct af9033_dev *dev = fe->demodulator_priv; 11259a0bf528SMauro Carvalho Chehab 11261d0ceae4SAntti Palosaari *ucblocks = dev->error_block_count; 11279a0bf528SMauro Carvalho Chehab return 0; 11289a0bf528SMauro Carvalho Chehab } 11299a0bf528SMauro Carvalho Chehab 11309a0bf528SMauro Carvalho Chehab static int af9033_i2c_gate_ctrl(struct dvb_frontend *fe, int enable) 11319a0bf528SMauro Carvalho Chehab { 113209611caaSAntti Palosaari struct af9033_dev *dev = fe->demodulator_priv; 11339a0bf528SMauro Carvalho Chehab int ret; 11349a0bf528SMauro Carvalho Chehab 11356a087f1fSAntti Palosaari dev_dbg(&dev->client->dev, "enable=%d\n", enable); 11369a0bf528SMauro Carvalho Chehab 113709611caaSAntti Palosaari ret = af9033_wr_reg_mask(dev, 0x00fa04, enable, 0x01); 11389a0bf528SMauro Carvalho Chehab if (ret < 0) 11399a0bf528SMauro Carvalho Chehab goto err; 11409a0bf528SMauro Carvalho Chehab 11419a0bf528SMauro Carvalho Chehab return 0; 11429a0bf528SMauro Carvalho Chehab 11439a0bf528SMauro Carvalho Chehab err: 11446a087f1fSAntti Palosaari dev_dbg(&dev->client->dev, "failed=%d\n", ret); 11459a0bf528SMauro Carvalho Chehab 11469a0bf528SMauro Carvalho Chehab return ret; 11479a0bf528SMauro Carvalho Chehab } 11489a0bf528SMauro Carvalho Chehab 1149ed97a6feSMauro Carvalho Chehab static int af9033_pid_filter_ctrl(struct dvb_frontend *fe, int onoff) 1150040cf86cSAntti Palosaari { 115109611caaSAntti Palosaari struct af9033_dev *dev = fe->demodulator_priv; 1152040cf86cSAntti Palosaari int ret; 1153040cf86cSAntti Palosaari 11546a087f1fSAntti Palosaari dev_dbg(&dev->client->dev, "onoff=%d\n", onoff); 1155040cf86cSAntti Palosaari 115609611caaSAntti Palosaari ret = af9033_wr_reg_mask(dev, 0x80f993, onoff, 0x01); 1157040cf86cSAntti Palosaari if (ret < 0) 1158040cf86cSAntti Palosaari goto err; 1159040cf86cSAntti Palosaari 1160040cf86cSAntti Palosaari return 0; 1161040cf86cSAntti Palosaari 1162040cf86cSAntti Palosaari err: 11636a087f1fSAntti Palosaari dev_dbg(&dev->client->dev, "failed=%d\n", ret); 1164040cf86cSAntti Palosaari 1165040cf86cSAntti Palosaari return ret; 1166040cf86cSAntti Palosaari } 1167040cf86cSAntti Palosaari 116824e419a0SAntti Palosaari static int af9033_pid_filter(struct dvb_frontend *fe, int index, u16 pid, 116924e419a0SAntti Palosaari int onoff) 1170040cf86cSAntti Palosaari { 117109611caaSAntti Palosaari struct af9033_dev *dev = fe->demodulator_priv; 1172040cf86cSAntti Palosaari int ret; 1173040cf86cSAntti Palosaari u8 wbuf[2] = {(pid >> 0) & 0xff, (pid >> 8) & 0xff}; 1174040cf86cSAntti Palosaari 11756a087f1fSAntti Palosaari dev_dbg(&dev->client->dev, "index=%d pid=%04x onoff=%d\n", 11766a087f1fSAntti Palosaari index, pid, onoff); 1177040cf86cSAntti Palosaari 1178040cf86cSAntti Palosaari if (pid > 0x1fff) 1179040cf86cSAntti Palosaari return 0; 1180040cf86cSAntti Palosaari 118109611caaSAntti Palosaari ret = af9033_wr_regs(dev, 0x80f996, wbuf, 2); 1182040cf86cSAntti Palosaari if (ret < 0) 1183040cf86cSAntti Palosaari goto err; 1184040cf86cSAntti Palosaari 118509611caaSAntti Palosaari ret = af9033_wr_reg(dev, 0x80f994, onoff); 1186040cf86cSAntti Palosaari if (ret < 0) 1187040cf86cSAntti Palosaari goto err; 1188040cf86cSAntti Palosaari 118909611caaSAntti Palosaari ret = af9033_wr_reg(dev, 0x80f995, index); 1190040cf86cSAntti Palosaari if (ret < 0) 1191040cf86cSAntti Palosaari goto err; 1192040cf86cSAntti Palosaari 1193040cf86cSAntti Palosaari return 0; 1194040cf86cSAntti Palosaari 1195040cf86cSAntti Palosaari err: 11966a087f1fSAntti Palosaari dev_dbg(&dev->client->dev, "failed=%d\n", ret); 1197040cf86cSAntti Palosaari 1198040cf86cSAntti Palosaari return ret; 1199040cf86cSAntti Palosaari } 1200040cf86cSAntti Palosaari 12019a0bf528SMauro Carvalho Chehab static struct dvb_frontend_ops af9033_ops = { 12029a0bf528SMauro Carvalho Chehab .delsys = { SYS_DVBT }, 12039a0bf528SMauro Carvalho Chehab .info = { 12049a0bf528SMauro Carvalho Chehab .name = "Afatech AF9033 (DVB-T)", 12059a0bf528SMauro Carvalho Chehab .frequency_min = 174000000, 12069a0bf528SMauro Carvalho Chehab .frequency_max = 862000000, 12079a0bf528SMauro Carvalho Chehab .frequency_stepsize = 250000, 12089a0bf528SMauro Carvalho Chehab .frequency_tolerance = 0, 12099a0bf528SMauro Carvalho Chehab .caps = FE_CAN_FEC_1_2 | 12109a0bf528SMauro Carvalho Chehab FE_CAN_FEC_2_3 | 12119a0bf528SMauro Carvalho Chehab FE_CAN_FEC_3_4 | 12129a0bf528SMauro Carvalho Chehab FE_CAN_FEC_5_6 | 12139a0bf528SMauro Carvalho Chehab FE_CAN_FEC_7_8 | 12149a0bf528SMauro Carvalho Chehab FE_CAN_FEC_AUTO | 12159a0bf528SMauro Carvalho Chehab FE_CAN_QPSK | 12169a0bf528SMauro Carvalho Chehab FE_CAN_QAM_16 | 12179a0bf528SMauro Carvalho Chehab FE_CAN_QAM_64 | 12189a0bf528SMauro Carvalho Chehab FE_CAN_QAM_AUTO | 12199a0bf528SMauro Carvalho Chehab FE_CAN_TRANSMISSION_MODE_AUTO | 12209a0bf528SMauro Carvalho Chehab FE_CAN_GUARD_INTERVAL_AUTO | 12219a0bf528SMauro Carvalho Chehab FE_CAN_HIERARCHY_AUTO | 12229a0bf528SMauro Carvalho Chehab FE_CAN_RECOVER | 12239a0bf528SMauro Carvalho Chehab FE_CAN_MUTE_TS 12249a0bf528SMauro Carvalho Chehab }, 12259a0bf528SMauro Carvalho Chehab 12269a0bf528SMauro Carvalho Chehab .init = af9033_init, 12279a0bf528SMauro Carvalho Chehab .sleep = af9033_sleep, 12289a0bf528SMauro Carvalho Chehab 12299a0bf528SMauro Carvalho Chehab .get_tune_settings = af9033_get_tune_settings, 12309a0bf528SMauro Carvalho Chehab .set_frontend = af9033_set_frontend, 12319a0bf528SMauro Carvalho Chehab .get_frontend = af9033_get_frontend, 12329a0bf528SMauro Carvalho Chehab 12339a0bf528SMauro Carvalho Chehab .read_status = af9033_read_status, 12349a0bf528SMauro Carvalho Chehab .read_snr = af9033_read_snr, 12359a0bf528SMauro Carvalho Chehab .read_signal_strength = af9033_read_signal_strength, 12369a0bf528SMauro Carvalho Chehab .read_ber = af9033_read_ber, 12379a0bf528SMauro Carvalho Chehab .read_ucblocks = af9033_read_ucblocks, 12389a0bf528SMauro Carvalho Chehab 12399a0bf528SMauro Carvalho Chehab .i2c_gate_ctrl = af9033_i2c_gate_ctrl, 12409a0bf528SMauro Carvalho Chehab }; 12419a0bf528SMauro Carvalho Chehab 1242f5b00a76SAntti Palosaari static int af9033_probe(struct i2c_client *client, 1243f5b00a76SAntti Palosaari const struct i2c_device_id *id) 1244f5b00a76SAntti Palosaari { 1245f5b00a76SAntti Palosaari struct af9033_config *cfg = client->dev.platform_data; 1246f5b00a76SAntti Palosaari struct af9033_dev *dev; 1247f5b00a76SAntti Palosaari int ret; 1248f5b00a76SAntti Palosaari u8 buf[8]; 1249f5b00a76SAntti Palosaari u32 reg; 1250f5b00a76SAntti Palosaari 1251f5b00a76SAntti Palosaari /* allocate memory for the internal state */ 1252f5b00a76SAntti Palosaari dev = kzalloc(sizeof(struct af9033_dev), GFP_KERNEL); 1253f5b00a76SAntti Palosaari if (dev == NULL) { 1254f5b00a76SAntti Palosaari ret = -ENOMEM; 1255f5b00a76SAntti Palosaari dev_err(&client->dev, "Could not allocate memory for state\n"); 1256f5b00a76SAntti Palosaari goto err; 1257f5b00a76SAntti Palosaari } 1258f5b00a76SAntti Palosaari 1259f5b00a76SAntti Palosaari /* setup the state */ 1260f5b00a76SAntti Palosaari dev->client = client; 1261f5b00a76SAntti Palosaari memcpy(&dev->cfg, cfg, sizeof(struct af9033_config)); 1262f5b00a76SAntti Palosaari 1263f5b00a76SAntti Palosaari if (dev->cfg.clock != 12000000) { 1264f5b00a76SAntti Palosaari ret = -ENODEV; 1265f5b00a76SAntti Palosaari dev_err(&dev->client->dev, 12666a087f1fSAntti Palosaari "unsupported clock %d Hz, only 12000000 Hz is supported currently\n", 12676a087f1fSAntti Palosaari dev->cfg.clock); 1268f5b00a76SAntti Palosaari goto err_kfree; 1269f5b00a76SAntti Palosaari } 1270f5b00a76SAntti Palosaari 1271f5b00a76SAntti Palosaari /* firmware version */ 1272f5b00a76SAntti Palosaari switch (dev->cfg.tuner) { 1273f5b00a76SAntti Palosaari case AF9033_TUNER_IT9135_38: 1274f5b00a76SAntti Palosaari case AF9033_TUNER_IT9135_51: 1275f5b00a76SAntti Palosaari case AF9033_TUNER_IT9135_52: 1276f5b00a76SAntti Palosaari case AF9033_TUNER_IT9135_60: 1277f5b00a76SAntti Palosaari case AF9033_TUNER_IT9135_61: 1278f5b00a76SAntti Palosaari case AF9033_TUNER_IT9135_62: 127983f11619SAntti Palosaari dev->is_it9135 = true; 1280f5b00a76SAntti Palosaari reg = 0x004bfc; 1281f5b00a76SAntti Palosaari break; 1282f5b00a76SAntti Palosaari default: 128383f11619SAntti Palosaari dev->is_af9035 = true; 1284f5b00a76SAntti Palosaari reg = 0x0083e9; 1285f5b00a76SAntti Palosaari break; 1286f5b00a76SAntti Palosaari } 1287f5b00a76SAntti Palosaari 1288f5b00a76SAntti Palosaari ret = af9033_rd_regs(dev, reg, &buf[0], 4); 1289f5b00a76SAntti Palosaari if (ret < 0) 1290f5b00a76SAntti Palosaari goto err_kfree; 1291f5b00a76SAntti Palosaari 1292f5b00a76SAntti Palosaari ret = af9033_rd_regs(dev, 0x804191, &buf[4], 4); 1293f5b00a76SAntti Palosaari if (ret < 0) 1294f5b00a76SAntti Palosaari goto err_kfree; 1295f5b00a76SAntti Palosaari 1296f5b00a76SAntti Palosaari dev_info(&dev->client->dev, 12976a087f1fSAntti Palosaari "firmware version: LINK %d.%d.%d.%d - OFDM %d.%d.%d.%d\n", 12986a087f1fSAntti Palosaari buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6], 12996a087f1fSAntti Palosaari buf[7]); 1300f5b00a76SAntti Palosaari 1301f5b00a76SAntti Palosaari /* sleep */ 1302f5b00a76SAntti Palosaari switch (dev->cfg.tuner) { 1303f5b00a76SAntti Palosaari case AF9033_TUNER_IT9135_38: 1304f5b00a76SAntti Palosaari case AF9033_TUNER_IT9135_51: 1305f5b00a76SAntti Palosaari case AF9033_TUNER_IT9135_52: 1306f5b00a76SAntti Palosaari case AF9033_TUNER_IT9135_60: 1307f5b00a76SAntti Palosaari case AF9033_TUNER_IT9135_61: 1308f5b00a76SAntti Palosaari case AF9033_TUNER_IT9135_62: 1309f5b00a76SAntti Palosaari /* IT9135 did not like to sleep at that early */ 1310f5b00a76SAntti Palosaari break; 1311f5b00a76SAntti Palosaari default: 1312f5b00a76SAntti Palosaari ret = af9033_wr_reg(dev, 0x80004c, 1); 1313f5b00a76SAntti Palosaari if (ret < 0) 1314f5b00a76SAntti Palosaari goto err_kfree; 1315f5b00a76SAntti Palosaari 1316f5b00a76SAntti Palosaari ret = af9033_wr_reg(dev, 0x800000, 0); 1317f5b00a76SAntti Palosaari if (ret < 0) 1318f5b00a76SAntti Palosaari goto err_kfree; 1319f5b00a76SAntti Palosaari } 1320f5b00a76SAntti Palosaari 1321f5b00a76SAntti Palosaari /* configure internal TS mode */ 1322f5b00a76SAntti Palosaari switch (dev->cfg.ts_mode) { 1323f5b00a76SAntti Palosaari case AF9033_TS_MODE_PARALLEL: 1324f5b00a76SAntti Palosaari dev->ts_mode_parallel = true; 1325f5b00a76SAntti Palosaari break; 1326f5b00a76SAntti Palosaari case AF9033_TS_MODE_SERIAL: 1327f5b00a76SAntti Palosaari dev->ts_mode_serial = true; 1328f5b00a76SAntti Palosaari break; 1329f5b00a76SAntti Palosaari case AF9033_TS_MODE_USB: 1330f5b00a76SAntti Palosaari /* usb mode for AF9035 */ 1331f5b00a76SAntti Palosaari default: 1332f5b00a76SAntti Palosaari break; 1333f5b00a76SAntti Palosaari } 1334f5b00a76SAntti Palosaari 1335f5b00a76SAntti Palosaari /* create dvb_frontend */ 1336f5b00a76SAntti Palosaari memcpy(&dev->fe.ops, &af9033_ops, sizeof(struct dvb_frontend_ops)); 1337f5b00a76SAntti Palosaari dev->fe.demodulator_priv = dev; 1338f5b00a76SAntti Palosaari *cfg->fe = &dev->fe; 1339f5b00a76SAntti Palosaari if (cfg->ops) { 1340f5b00a76SAntti Palosaari cfg->ops->pid_filter = af9033_pid_filter; 1341f5b00a76SAntti Palosaari cfg->ops->pid_filter_ctrl = af9033_pid_filter_ctrl; 1342f5b00a76SAntti Palosaari } 1343f5b00a76SAntti Palosaari i2c_set_clientdata(client, dev); 1344f5b00a76SAntti Palosaari 1345f5b00a76SAntti Palosaari dev_info(&dev->client->dev, "Afatech AF9033 successfully attached\n"); 1346f5b00a76SAntti Palosaari return 0; 1347f5b00a76SAntti Palosaari err_kfree: 1348f5b00a76SAntti Palosaari kfree(dev); 1349f5b00a76SAntti Palosaari err: 13506a087f1fSAntti Palosaari dev_dbg(&client->dev, "failed=%d\n", ret); 1351f5b00a76SAntti Palosaari return ret; 1352f5b00a76SAntti Palosaari } 1353f5b00a76SAntti Palosaari 1354f5b00a76SAntti Palosaari static int af9033_remove(struct i2c_client *client) 1355f5b00a76SAntti Palosaari { 1356f5b00a76SAntti Palosaari struct af9033_dev *dev = i2c_get_clientdata(client); 1357f5b00a76SAntti Palosaari 13586a087f1fSAntti Palosaari dev_dbg(&dev->client->dev, "\n"); 1359f5b00a76SAntti Palosaari 1360f5b00a76SAntti Palosaari dev->fe.ops.release = NULL; 1361f5b00a76SAntti Palosaari dev->fe.demodulator_priv = NULL; 1362f5b00a76SAntti Palosaari kfree(dev); 1363f5b00a76SAntti Palosaari 1364f5b00a76SAntti Palosaari return 0; 1365f5b00a76SAntti Palosaari } 1366f5b00a76SAntti Palosaari 1367f5b00a76SAntti Palosaari static const struct i2c_device_id af9033_id_table[] = { 1368f5b00a76SAntti Palosaari {"af9033", 0}, 1369f5b00a76SAntti Palosaari {} 1370f5b00a76SAntti Palosaari }; 1371f5b00a76SAntti Palosaari MODULE_DEVICE_TABLE(i2c, af9033_id_table); 1372f5b00a76SAntti Palosaari 1373f5b00a76SAntti Palosaari static struct i2c_driver af9033_driver = { 1374f5b00a76SAntti Palosaari .driver = { 1375f5b00a76SAntti Palosaari .name = "af9033", 137672812175SAntti Palosaari .suppress_bind_attrs = true, 1377f5b00a76SAntti Palosaari }, 1378f5b00a76SAntti Palosaari .probe = af9033_probe, 1379f5b00a76SAntti Palosaari .remove = af9033_remove, 1380f5b00a76SAntti Palosaari .id_table = af9033_id_table, 1381f5b00a76SAntti Palosaari }; 1382f5b00a76SAntti Palosaari 1383f5b00a76SAntti Palosaari module_i2c_driver(af9033_driver); 1384f5b00a76SAntti Palosaari 13859a0bf528SMauro Carvalho Chehab MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>"); 13869a0bf528SMauro Carvalho Chehab MODULE_DESCRIPTION("Afatech AF9033 DVB-T demodulator driver"); 13879a0bf528SMauro Carvalho Chehab MODULE_LICENSE("GPL"); 1388