1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. 4 */ 5 6 #include <linux/delay.h> 7 #include <linux/interrupt.h> 8 #include <linux/io.h> 9 #include <linux/mailbox_controller.h> 10 #include <linux/of.h> 11 #include <linux/of_device.h> 12 #include <linux/platform_device.h> 13 #include <linux/pm.h> 14 #include <linux/slab.h> 15 16 #include <soc/tegra/fuse.h> 17 18 #include <dt-bindings/mailbox/tegra186-hsp.h> 19 20 #include "mailbox.h" 21 22 #define HSP_INT_IE(x) (0x100 + ((x) * 4)) 23 #define HSP_INT_IV 0x300 24 #define HSP_INT_IR 0x304 25 26 #define HSP_INT_EMPTY_SHIFT 0 27 #define HSP_INT_EMPTY_MASK 0xff 28 #define HSP_INT_FULL_SHIFT 8 29 #define HSP_INT_FULL_MASK 0xff 30 31 #define HSP_INT_DIMENSIONING 0x380 32 #define HSP_nSM_SHIFT 0 33 #define HSP_nSS_SHIFT 4 34 #define HSP_nAS_SHIFT 8 35 #define HSP_nDB_SHIFT 12 36 #define HSP_nSI_SHIFT 16 37 #define HSP_nINT_MASK 0xf 38 39 #define HSP_DB_TRIGGER 0x0 40 #define HSP_DB_ENABLE 0x4 41 #define HSP_DB_RAW 0x8 42 #define HSP_DB_PENDING 0xc 43 44 #define HSP_SM_SHRD_MBOX 0x0 45 #define HSP_SM_SHRD_MBOX_FULL BIT(31) 46 #define HSP_SM_SHRD_MBOX_FULL_INT_IE 0x04 47 #define HSP_SM_SHRD_MBOX_EMPTY_INT_IE 0x08 48 49 #define HSP_DB_CCPLEX 1 50 #define HSP_DB_BPMP 3 51 #define HSP_DB_MAX 7 52 53 struct tegra_hsp_channel; 54 struct tegra_hsp; 55 56 struct tegra_hsp_channel { 57 struct tegra_hsp *hsp; 58 struct mbox_chan *chan; 59 void __iomem *regs; 60 }; 61 62 struct tegra_hsp_doorbell { 63 struct tegra_hsp_channel channel; 64 struct list_head list; 65 const char *name; 66 unsigned int master; 67 unsigned int index; 68 }; 69 70 struct tegra_hsp_sm_ops { 71 void (*send)(struct tegra_hsp_channel *channel, void *data); 72 void (*recv)(struct tegra_hsp_channel *channel); 73 }; 74 75 struct tegra_hsp_mailbox { 76 struct tegra_hsp_channel channel; 77 const struct tegra_hsp_sm_ops *ops; 78 unsigned int index; 79 bool producer; 80 }; 81 82 struct tegra_hsp_db_map { 83 const char *name; 84 unsigned int master; 85 unsigned int index; 86 }; 87 88 struct tegra_hsp_soc { 89 const struct tegra_hsp_db_map *map; 90 bool has_per_mb_ie; 91 }; 92 93 struct tegra_hsp { 94 struct device *dev; 95 const struct tegra_hsp_soc *soc; 96 struct mbox_controller mbox_db; 97 struct mbox_controller mbox_sm; 98 void __iomem *regs; 99 unsigned int doorbell_irq; 100 unsigned int *shared_irqs; 101 unsigned int shared_irq; 102 unsigned int num_sm; 103 unsigned int num_as; 104 unsigned int num_ss; 105 unsigned int num_db; 106 unsigned int num_si; 107 108 spinlock_t lock; 109 struct lock_class_key lock_key; 110 111 struct list_head doorbells; 112 struct tegra_hsp_mailbox *mailboxes; 113 114 unsigned long mask; 115 }; 116 117 static inline u32 tegra_hsp_readl(struct tegra_hsp *hsp, unsigned int offset) 118 { 119 return readl(hsp->regs + offset); 120 } 121 122 static inline void tegra_hsp_writel(struct tegra_hsp *hsp, u32 value, 123 unsigned int offset) 124 { 125 writel(value, hsp->regs + offset); 126 } 127 128 static inline u32 tegra_hsp_channel_readl(struct tegra_hsp_channel *channel, 129 unsigned int offset) 130 { 131 return readl(channel->regs + offset); 132 } 133 134 static inline void tegra_hsp_channel_writel(struct tegra_hsp_channel *channel, 135 u32 value, unsigned int offset) 136 { 137 writel(value, channel->regs + offset); 138 } 139 140 static bool tegra_hsp_doorbell_can_ring(struct tegra_hsp_doorbell *db) 141 { 142 u32 value; 143 144 value = tegra_hsp_channel_readl(&db->channel, HSP_DB_ENABLE); 145 146 return (value & BIT(TEGRA_HSP_DB_MASTER_CCPLEX)) != 0; 147 } 148 149 static struct tegra_hsp_doorbell * 150 __tegra_hsp_doorbell_get(struct tegra_hsp *hsp, unsigned int master) 151 { 152 struct tegra_hsp_doorbell *entry; 153 154 list_for_each_entry(entry, &hsp->doorbells, list) 155 if (entry->master == master) 156 return entry; 157 158 return NULL; 159 } 160 161 static struct tegra_hsp_doorbell * 162 tegra_hsp_doorbell_get(struct tegra_hsp *hsp, unsigned int master) 163 { 164 struct tegra_hsp_doorbell *db; 165 unsigned long flags; 166 167 spin_lock_irqsave(&hsp->lock, flags); 168 db = __tegra_hsp_doorbell_get(hsp, master); 169 spin_unlock_irqrestore(&hsp->lock, flags); 170 171 return db; 172 } 173 174 static irqreturn_t tegra_hsp_doorbell_irq(int irq, void *data) 175 { 176 struct tegra_hsp *hsp = data; 177 struct tegra_hsp_doorbell *db; 178 unsigned long master, value; 179 180 db = tegra_hsp_doorbell_get(hsp, TEGRA_HSP_DB_MASTER_CCPLEX); 181 if (!db) 182 return IRQ_NONE; 183 184 value = tegra_hsp_channel_readl(&db->channel, HSP_DB_PENDING); 185 tegra_hsp_channel_writel(&db->channel, value, HSP_DB_PENDING); 186 187 spin_lock(&hsp->lock); 188 189 for_each_set_bit(master, &value, hsp->mbox_db.num_chans) { 190 struct tegra_hsp_doorbell *db; 191 192 db = __tegra_hsp_doorbell_get(hsp, master); 193 /* 194 * Depending on the bootloader chain, the CCPLEX doorbell will 195 * have some doorbells enabled, which means that requesting an 196 * interrupt will immediately fire. 197 * 198 * In that case, db->channel.chan will still be NULL here and 199 * cause a crash if not properly guarded. 200 * 201 * It remains to be seen if ignoring the doorbell in that case 202 * is the correct solution. 203 */ 204 if (db && db->channel.chan) 205 mbox_chan_received_data(db->channel.chan, NULL); 206 } 207 208 spin_unlock(&hsp->lock); 209 210 return IRQ_HANDLED; 211 } 212 213 static irqreturn_t tegra_hsp_shared_irq(int irq, void *data) 214 { 215 struct tegra_hsp *hsp = data; 216 unsigned long bit, mask; 217 u32 status; 218 219 status = tegra_hsp_readl(hsp, HSP_INT_IR) & hsp->mask; 220 221 /* process EMPTY interrupts first */ 222 mask = (status >> HSP_INT_EMPTY_SHIFT) & HSP_INT_EMPTY_MASK; 223 224 for_each_set_bit(bit, &mask, hsp->num_sm) { 225 struct tegra_hsp_mailbox *mb = &hsp->mailboxes[bit]; 226 227 if (mb->producer) { 228 /* 229 * Disable EMPTY interrupts until data is sent with 230 * the next message. These interrupts are level- 231 * triggered, so if we kept them enabled they would 232 * constantly trigger until we next write data into 233 * the message. 234 */ 235 spin_lock(&hsp->lock); 236 237 hsp->mask &= ~BIT(HSP_INT_EMPTY_SHIFT + mb->index); 238 tegra_hsp_writel(hsp, hsp->mask, 239 HSP_INT_IE(hsp->shared_irq)); 240 241 spin_unlock(&hsp->lock); 242 243 mbox_chan_txdone(mb->channel.chan, 0); 244 } 245 } 246 247 /* process FULL interrupts */ 248 mask = (status >> HSP_INT_FULL_SHIFT) & HSP_INT_FULL_MASK; 249 250 for_each_set_bit(bit, &mask, hsp->num_sm) { 251 struct tegra_hsp_mailbox *mb = &hsp->mailboxes[bit]; 252 253 if (!mb->producer) 254 mb->ops->recv(&mb->channel); 255 } 256 257 return IRQ_HANDLED; 258 } 259 260 static struct tegra_hsp_channel * 261 tegra_hsp_doorbell_create(struct tegra_hsp *hsp, const char *name, 262 unsigned int master, unsigned int index) 263 { 264 struct tegra_hsp_doorbell *db; 265 unsigned int offset; 266 unsigned long flags; 267 268 db = devm_kzalloc(hsp->dev, sizeof(*db), GFP_KERNEL); 269 if (!db) 270 return ERR_PTR(-ENOMEM); 271 272 offset = (1 + (hsp->num_sm / 2) + hsp->num_ss + hsp->num_as) * SZ_64K; 273 offset += index * 0x100; 274 275 db->channel.regs = hsp->regs + offset; 276 db->channel.hsp = hsp; 277 278 db->name = devm_kstrdup_const(hsp->dev, name, GFP_KERNEL); 279 db->master = master; 280 db->index = index; 281 282 spin_lock_irqsave(&hsp->lock, flags); 283 list_add_tail(&db->list, &hsp->doorbells); 284 spin_unlock_irqrestore(&hsp->lock, flags); 285 286 return &db->channel; 287 } 288 289 static int tegra_hsp_doorbell_send_data(struct mbox_chan *chan, void *data) 290 { 291 struct tegra_hsp_doorbell *db = chan->con_priv; 292 293 tegra_hsp_channel_writel(&db->channel, 1, HSP_DB_TRIGGER); 294 295 return 0; 296 } 297 298 static int tegra_hsp_doorbell_startup(struct mbox_chan *chan) 299 { 300 struct tegra_hsp_doorbell *db = chan->con_priv; 301 struct tegra_hsp *hsp = db->channel.hsp; 302 struct tegra_hsp_doorbell *ccplex; 303 unsigned long flags; 304 u32 value; 305 306 if (db->master >= chan->mbox->num_chans) { 307 dev_err(chan->mbox->dev, 308 "invalid master ID %u for HSP channel\n", 309 db->master); 310 return -EINVAL; 311 } 312 313 ccplex = tegra_hsp_doorbell_get(hsp, TEGRA_HSP_DB_MASTER_CCPLEX); 314 if (!ccplex) 315 return -ENODEV; 316 317 /* 318 * On simulation platforms the BPMP hasn't had a chance yet to mark 319 * the doorbell as ringable by the CCPLEX, so we want to skip extra 320 * checks here. 321 */ 322 if (tegra_is_silicon() && !tegra_hsp_doorbell_can_ring(db)) 323 return -ENODEV; 324 325 spin_lock_irqsave(&hsp->lock, flags); 326 327 value = tegra_hsp_channel_readl(&ccplex->channel, HSP_DB_ENABLE); 328 value |= BIT(db->master); 329 tegra_hsp_channel_writel(&ccplex->channel, value, HSP_DB_ENABLE); 330 331 spin_unlock_irqrestore(&hsp->lock, flags); 332 333 return 0; 334 } 335 336 static void tegra_hsp_doorbell_shutdown(struct mbox_chan *chan) 337 { 338 struct tegra_hsp_doorbell *db = chan->con_priv; 339 struct tegra_hsp *hsp = db->channel.hsp; 340 struct tegra_hsp_doorbell *ccplex; 341 unsigned long flags; 342 u32 value; 343 344 ccplex = tegra_hsp_doorbell_get(hsp, TEGRA_HSP_DB_MASTER_CCPLEX); 345 if (!ccplex) 346 return; 347 348 spin_lock_irqsave(&hsp->lock, flags); 349 350 value = tegra_hsp_channel_readl(&ccplex->channel, HSP_DB_ENABLE); 351 value &= ~BIT(db->master); 352 tegra_hsp_channel_writel(&ccplex->channel, value, HSP_DB_ENABLE); 353 354 spin_unlock_irqrestore(&hsp->lock, flags); 355 } 356 357 static const struct mbox_chan_ops tegra_hsp_db_ops = { 358 .send_data = tegra_hsp_doorbell_send_data, 359 .startup = tegra_hsp_doorbell_startup, 360 .shutdown = tegra_hsp_doorbell_shutdown, 361 }; 362 363 static void tegra_hsp_sm_send32(struct tegra_hsp_channel *channel, void *data) 364 { 365 u32 value; 366 367 /* copy data and mark mailbox full */ 368 value = (u32)(unsigned long)data; 369 value |= HSP_SM_SHRD_MBOX_FULL; 370 371 tegra_hsp_channel_writel(channel, value, HSP_SM_SHRD_MBOX); 372 } 373 374 static void tegra_hsp_sm_recv32(struct tegra_hsp_channel *channel) 375 { 376 u32 value; 377 void *msg; 378 379 value = tegra_hsp_channel_readl(channel, HSP_SM_SHRD_MBOX); 380 value &= ~HSP_SM_SHRD_MBOX_FULL; 381 msg = (void *)(unsigned long)value; 382 mbox_chan_received_data(channel->chan, msg); 383 384 /* 385 * Need to clear all bits here since some producers, such as TCU, depend 386 * on fields in the register getting cleared by the consumer. 387 * 388 * The mailbox API doesn't give the consumers a way of doing that 389 * explicitly, so we have to make sure we cover all possible cases. 390 */ 391 tegra_hsp_channel_writel(channel, 0x0, HSP_SM_SHRD_MBOX); 392 } 393 394 static const struct tegra_hsp_sm_ops tegra_hsp_sm_32bit_ops = { 395 .send = tegra_hsp_sm_send32, 396 .recv = tegra_hsp_sm_recv32, 397 }; 398 399 static int tegra_hsp_mailbox_send_data(struct mbox_chan *chan, void *data) 400 { 401 struct tegra_hsp_mailbox *mb = chan->con_priv; 402 struct tegra_hsp *hsp = mb->channel.hsp; 403 unsigned long flags; 404 405 if (WARN_ON(!mb->producer)) 406 return -EPERM; 407 408 mb->ops->send(&mb->channel, data); 409 410 /* enable EMPTY interrupt for the shared mailbox */ 411 spin_lock_irqsave(&hsp->lock, flags); 412 413 hsp->mask |= BIT(HSP_INT_EMPTY_SHIFT + mb->index); 414 tegra_hsp_writel(hsp, hsp->mask, HSP_INT_IE(hsp->shared_irq)); 415 416 spin_unlock_irqrestore(&hsp->lock, flags); 417 418 return 0; 419 } 420 421 static int tegra_hsp_mailbox_flush(struct mbox_chan *chan, 422 unsigned long timeout) 423 { 424 struct tegra_hsp_mailbox *mb = chan->con_priv; 425 struct tegra_hsp_channel *ch = &mb->channel; 426 u32 value; 427 428 timeout = jiffies + msecs_to_jiffies(timeout); 429 430 while (time_before(jiffies, timeout)) { 431 value = tegra_hsp_channel_readl(ch, HSP_SM_SHRD_MBOX); 432 if ((value & HSP_SM_SHRD_MBOX_FULL) == 0) { 433 mbox_chan_txdone(chan, 0); 434 435 /* Wait until channel is empty */ 436 if (chan->active_req != NULL) 437 continue; 438 439 return 0; 440 } 441 442 udelay(1); 443 } 444 445 return -ETIME; 446 } 447 448 static int tegra_hsp_mailbox_startup(struct mbox_chan *chan) 449 { 450 struct tegra_hsp_mailbox *mb = chan->con_priv; 451 struct tegra_hsp_channel *ch = &mb->channel; 452 struct tegra_hsp *hsp = mb->channel.hsp; 453 unsigned long flags; 454 455 chan->txdone_method = TXDONE_BY_IRQ; 456 457 /* 458 * Shared mailboxes start out as consumers by default. FULL and EMPTY 459 * interrupts are coalesced at the same shared interrupt. 460 * 461 * Keep EMPTY interrupts disabled at startup and only enable them when 462 * the mailbox is actually full. This is required because the FULL and 463 * EMPTY interrupts are level-triggered, so keeping EMPTY interrupts 464 * enabled all the time would cause an interrupt storm while mailboxes 465 * are idle. 466 */ 467 468 spin_lock_irqsave(&hsp->lock, flags); 469 470 if (mb->producer) 471 hsp->mask &= ~BIT(HSP_INT_EMPTY_SHIFT + mb->index); 472 else 473 hsp->mask |= BIT(HSP_INT_FULL_SHIFT + mb->index); 474 475 tegra_hsp_writel(hsp, hsp->mask, HSP_INT_IE(hsp->shared_irq)); 476 477 spin_unlock_irqrestore(&hsp->lock, flags); 478 479 if (hsp->soc->has_per_mb_ie) { 480 if (mb->producer) 481 tegra_hsp_channel_writel(ch, 0x0, 482 HSP_SM_SHRD_MBOX_EMPTY_INT_IE); 483 else 484 tegra_hsp_channel_writel(ch, 0x1, 485 HSP_SM_SHRD_MBOX_FULL_INT_IE); 486 } 487 488 return 0; 489 } 490 491 static void tegra_hsp_mailbox_shutdown(struct mbox_chan *chan) 492 { 493 struct tegra_hsp_mailbox *mb = chan->con_priv; 494 struct tegra_hsp_channel *ch = &mb->channel; 495 struct tegra_hsp *hsp = mb->channel.hsp; 496 unsigned long flags; 497 498 if (hsp->soc->has_per_mb_ie) { 499 if (mb->producer) 500 tegra_hsp_channel_writel(ch, 0x0, 501 HSP_SM_SHRD_MBOX_EMPTY_INT_IE); 502 else 503 tegra_hsp_channel_writel(ch, 0x0, 504 HSP_SM_SHRD_MBOX_FULL_INT_IE); 505 } 506 507 spin_lock_irqsave(&hsp->lock, flags); 508 509 if (mb->producer) 510 hsp->mask &= ~BIT(HSP_INT_EMPTY_SHIFT + mb->index); 511 else 512 hsp->mask &= ~BIT(HSP_INT_FULL_SHIFT + mb->index); 513 514 tegra_hsp_writel(hsp, hsp->mask, HSP_INT_IE(hsp->shared_irq)); 515 516 spin_unlock_irqrestore(&hsp->lock, flags); 517 } 518 519 static const struct mbox_chan_ops tegra_hsp_sm_ops = { 520 .send_data = tegra_hsp_mailbox_send_data, 521 .flush = tegra_hsp_mailbox_flush, 522 .startup = tegra_hsp_mailbox_startup, 523 .shutdown = tegra_hsp_mailbox_shutdown, 524 }; 525 526 static struct mbox_chan *tegra_hsp_db_xlate(struct mbox_controller *mbox, 527 const struct of_phandle_args *args) 528 { 529 struct tegra_hsp *hsp = container_of(mbox, struct tegra_hsp, mbox_db); 530 unsigned int type = args->args[0], master = args->args[1]; 531 struct tegra_hsp_channel *channel = ERR_PTR(-ENODEV); 532 struct tegra_hsp_doorbell *db; 533 struct mbox_chan *chan; 534 unsigned long flags; 535 unsigned int i; 536 537 if (type != TEGRA_HSP_MBOX_TYPE_DB || !hsp->doorbell_irq) 538 return ERR_PTR(-ENODEV); 539 540 db = tegra_hsp_doorbell_get(hsp, master); 541 if (db) 542 channel = &db->channel; 543 544 if (IS_ERR(channel)) 545 return ERR_CAST(channel); 546 547 spin_lock_irqsave(&hsp->lock, flags); 548 549 for (i = 0; i < mbox->num_chans; i++) { 550 chan = &mbox->chans[i]; 551 if (!chan->con_priv) { 552 channel->chan = chan; 553 chan->con_priv = db; 554 break; 555 } 556 557 chan = NULL; 558 } 559 560 spin_unlock_irqrestore(&hsp->lock, flags); 561 562 return chan ?: ERR_PTR(-EBUSY); 563 } 564 565 static struct mbox_chan *tegra_hsp_sm_xlate(struct mbox_controller *mbox, 566 const struct of_phandle_args *args) 567 { 568 struct tegra_hsp *hsp = container_of(mbox, struct tegra_hsp, mbox_sm); 569 unsigned int type = args->args[0], index; 570 struct tegra_hsp_mailbox *mb; 571 572 index = args->args[1] & TEGRA_HSP_SM_MASK; 573 574 if (type != TEGRA_HSP_MBOX_TYPE_SM || !hsp->shared_irqs || 575 index >= hsp->num_sm) 576 return ERR_PTR(-ENODEV); 577 578 mb = &hsp->mailboxes[index]; 579 mb->ops = &tegra_hsp_sm_32bit_ops; 580 581 if ((args->args[1] & TEGRA_HSP_SM_FLAG_TX) == 0) 582 mb->producer = false; 583 else 584 mb->producer = true; 585 586 return mb->channel.chan; 587 } 588 589 static int tegra_hsp_add_doorbells(struct tegra_hsp *hsp) 590 { 591 const struct tegra_hsp_db_map *map = hsp->soc->map; 592 struct tegra_hsp_channel *channel; 593 594 while (map->name) { 595 channel = tegra_hsp_doorbell_create(hsp, map->name, 596 map->master, map->index); 597 if (IS_ERR(channel)) 598 return PTR_ERR(channel); 599 600 map++; 601 } 602 603 return 0; 604 } 605 606 static int tegra_hsp_add_mailboxes(struct tegra_hsp *hsp, struct device *dev) 607 { 608 int i; 609 610 hsp->mailboxes = devm_kcalloc(dev, hsp->num_sm, sizeof(*hsp->mailboxes), 611 GFP_KERNEL); 612 if (!hsp->mailboxes) 613 return -ENOMEM; 614 615 for (i = 0; i < hsp->num_sm; i++) { 616 struct tegra_hsp_mailbox *mb = &hsp->mailboxes[i]; 617 618 mb->index = i; 619 620 mb->channel.hsp = hsp; 621 mb->channel.regs = hsp->regs + SZ_64K + i * SZ_32K; 622 mb->channel.chan = &hsp->mbox_sm.chans[i]; 623 mb->channel.chan->con_priv = mb; 624 } 625 626 return 0; 627 } 628 629 static int tegra_hsp_request_shared_irq(struct tegra_hsp *hsp) 630 { 631 unsigned int i, irq = 0; 632 int err; 633 634 for (i = 0; i < hsp->num_si; i++) { 635 irq = hsp->shared_irqs[i]; 636 if (irq <= 0) 637 continue; 638 639 err = devm_request_irq(hsp->dev, irq, tegra_hsp_shared_irq, 0, 640 dev_name(hsp->dev), hsp); 641 if (err < 0) { 642 dev_err(hsp->dev, "failed to request interrupt: %d\n", 643 err); 644 continue; 645 } 646 647 hsp->shared_irq = i; 648 649 /* disable all interrupts */ 650 tegra_hsp_writel(hsp, 0, HSP_INT_IE(hsp->shared_irq)); 651 652 dev_dbg(hsp->dev, "interrupt requested: %u\n", irq); 653 654 break; 655 } 656 657 if (i == hsp->num_si) { 658 dev_err(hsp->dev, "failed to find available interrupt\n"); 659 return -ENOENT; 660 } 661 662 return 0; 663 } 664 665 static int tegra_hsp_probe(struct platform_device *pdev) 666 { 667 struct tegra_hsp *hsp; 668 struct resource *res; 669 unsigned int i; 670 u32 value; 671 int err; 672 673 hsp = devm_kzalloc(&pdev->dev, sizeof(*hsp), GFP_KERNEL); 674 if (!hsp) 675 return -ENOMEM; 676 677 hsp->dev = &pdev->dev; 678 hsp->soc = of_device_get_match_data(&pdev->dev); 679 INIT_LIST_HEAD(&hsp->doorbells); 680 spin_lock_init(&hsp->lock); 681 682 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 683 hsp->regs = devm_ioremap_resource(&pdev->dev, res); 684 if (IS_ERR(hsp->regs)) 685 return PTR_ERR(hsp->regs); 686 687 value = tegra_hsp_readl(hsp, HSP_INT_DIMENSIONING); 688 hsp->num_sm = (value >> HSP_nSM_SHIFT) & HSP_nINT_MASK; 689 hsp->num_ss = (value >> HSP_nSS_SHIFT) & HSP_nINT_MASK; 690 hsp->num_as = (value >> HSP_nAS_SHIFT) & HSP_nINT_MASK; 691 hsp->num_db = (value >> HSP_nDB_SHIFT) & HSP_nINT_MASK; 692 hsp->num_si = (value >> HSP_nSI_SHIFT) & HSP_nINT_MASK; 693 694 err = platform_get_irq_byname_optional(pdev, "doorbell"); 695 if (err >= 0) 696 hsp->doorbell_irq = err; 697 698 if (hsp->num_si > 0) { 699 unsigned int count = 0; 700 701 hsp->shared_irqs = devm_kcalloc(&pdev->dev, hsp->num_si, 702 sizeof(*hsp->shared_irqs), 703 GFP_KERNEL); 704 if (!hsp->shared_irqs) 705 return -ENOMEM; 706 707 for (i = 0; i < hsp->num_si; i++) { 708 char *name; 709 710 name = kasprintf(GFP_KERNEL, "shared%u", i); 711 if (!name) 712 return -ENOMEM; 713 714 err = platform_get_irq_byname_optional(pdev, name); 715 if (err >= 0) { 716 hsp->shared_irqs[i] = err; 717 count++; 718 } 719 720 kfree(name); 721 } 722 723 if (count == 0) { 724 devm_kfree(&pdev->dev, hsp->shared_irqs); 725 hsp->shared_irqs = NULL; 726 } 727 } 728 729 /* setup the doorbell controller */ 730 hsp->mbox_db.of_xlate = tegra_hsp_db_xlate; 731 hsp->mbox_db.num_chans = 32; 732 hsp->mbox_db.dev = &pdev->dev; 733 hsp->mbox_db.ops = &tegra_hsp_db_ops; 734 735 hsp->mbox_db.chans = devm_kcalloc(&pdev->dev, hsp->mbox_db.num_chans, 736 sizeof(*hsp->mbox_db.chans), 737 GFP_KERNEL); 738 if (!hsp->mbox_db.chans) 739 return -ENOMEM; 740 741 if (hsp->doorbell_irq) { 742 err = tegra_hsp_add_doorbells(hsp); 743 if (err < 0) { 744 dev_err(&pdev->dev, "failed to add doorbells: %d\n", 745 err); 746 return err; 747 } 748 } 749 750 err = devm_mbox_controller_register(&pdev->dev, &hsp->mbox_db); 751 if (err < 0) { 752 dev_err(&pdev->dev, "failed to register doorbell mailbox: %d\n", 753 err); 754 return err; 755 } 756 757 /* setup the shared mailbox controller */ 758 hsp->mbox_sm.of_xlate = tegra_hsp_sm_xlate; 759 hsp->mbox_sm.num_chans = hsp->num_sm; 760 hsp->mbox_sm.dev = &pdev->dev; 761 hsp->mbox_sm.ops = &tegra_hsp_sm_ops; 762 763 hsp->mbox_sm.chans = devm_kcalloc(&pdev->dev, hsp->mbox_sm.num_chans, 764 sizeof(*hsp->mbox_sm.chans), 765 GFP_KERNEL); 766 if (!hsp->mbox_sm.chans) 767 return -ENOMEM; 768 769 if (hsp->shared_irqs) { 770 err = tegra_hsp_add_mailboxes(hsp, &pdev->dev); 771 if (err < 0) { 772 dev_err(&pdev->dev, "failed to add mailboxes: %d\n", 773 err); 774 return err; 775 } 776 } 777 778 err = devm_mbox_controller_register(&pdev->dev, &hsp->mbox_sm); 779 if (err < 0) { 780 dev_err(&pdev->dev, "failed to register shared mailbox: %d\n", 781 err); 782 return err; 783 } 784 785 platform_set_drvdata(pdev, hsp); 786 787 if (hsp->doorbell_irq) { 788 err = devm_request_irq(&pdev->dev, hsp->doorbell_irq, 789 tegra_hsp_doorbell_irq, IRQF_NO_SUSPEND, 790 dev_name(&pdev->dev), hsp); 791 if (err < 0) { 792 dev_err(&pdev->dev, 793 "failed to request doorbell IRQ#%u: %d\n", 794 hsp->doorbell_irq, err); 795 return err; 796 } 797 } 798 799 if (hsp->shared_irqs) { 800 err = tegra_hsp_request_shared_irq(hsp); 801 if (err < 0) 802 return err; 803 } 804 805 lockdep_register_key(&hsp->lock_key); 806 lockdep_set_class(&hsp->lock, &hsp->lock_key); 807 808 return 0; 809 } 810 811 static int tegra_hsp_remove(struct platform_device *pdev) 812 { 813 struct tegra_hsp *hsp = platform_get_drvdata(pdev); 814 815 lockdep_unregister_key(&hsp->lock_key); 816 817 return 0; 818 } 819 820 static int __maybe_unused tegra_hsp_resume(struct device *dev) 821 { 822 struct tegra_hsp *hsp = dev_get_drvdata(dev); 823 unsigned int i; 824 struct tegra_hsp_doorbell *db; 825 826 list_for_each_entry(db, &hsp->doorbells, list) { 827 if (db->channel.chan) 828 tegra_hsp_doorbell_startup(db->channel.chan); 829 } 830 831 if (hsp->mailboxes) { 832 for (i = 0; i < hsp->num_sm; i++) { 833 struct tegra_hsp_mailbox *mb = &hsp->mailboxes[i]; 834 835 if (mb->channel.chan->cl) 836 tegra_hsp_mailbox_startup(mb->channel.chan); 837 } 838 } 839 840 return 0; 841 } 842 843 static const struct dev_pm_ops tegra_hsp_pm_ops = { 844 .resume_noirq = tegra_hsp_resume, 845 }; 846 847 static const struct tegra_hsp_db_map tegra186_hsp_db_map[] = { 848 { "ccplex", TEGRA_HSP_DB_MASTER_CCPLEX, HSP_DB_CCPLEX, }, 849 { "bpmp", TEGRA_HSP_DB_MASTER_BPMP, HSP_DB_BPMP, }, 850 { /* sentinel */ } 851 }; 852 853 static const struct tegra_hsp_soc tegra186_hsp_soc = { 854 .map = tegra186_hsp_db_map, 855 .has_per_mb_ie = false, 856 }; 857 858 static const struct tegra_hsp_soc tegra194_hsp_soc = { 859 .map = tegra186_hsp_db_map, 860 .has_per_mb_ie = true, 861 }; 862 863 static const struct of_device_id tegra_hsp_match[] = { 864 { .compatible = "nvidia,tegra186-hsp", .data = &tegra186_hsp_soc }, 865 { .compatible = "nvidia,tegra194-hsp", .data = &tegra194_hsp_soc }, 866 { } 867 }; 868 869 static struct platform_driver tegra_hsp_driver = { 870 .driver = { 871 .name = "tegra-hsp", 872 .of_match_table = tegra_hsp_match, 873 .pm = &tegra_hsp_pm_ops, 874 }, 875 .probe = tegra_hsp_probe, 876 .remove = tegra_hsp_remove, 877 }; 878 879 static int __init tegra_hsp_init(void) 880 { 881 return platform_driver_register(&tegra_hsp_driver); 882 } 883 core_initcall(tegra_hsp_init); 884