xref: /openbmc/linux/drivers/mailbox/tegra-hsp.c (revision 8a1e6bb3) 
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (c) 2016-2018, NVIDIA CORPORATION.  All rights reserved.
4  */
5 
6 #include <linux/delay.h>
7 #include <linux/interrupt.h>
8 #include <linux/io.h>
9 #include <linux/mailbox_controller.h>
10 #include <linux/of.h>
11 #include <linux/of_device.h>
12 #include <linux/platform_device.h>
13 #include <linux/pm.h>
14 #include <linux/slab.h>
15 
16 #include <soc/tegra/fuse.h>
17 
18 #include <dt-bindings/mailbox/tegra186-hsp.h>
19 
20 #include "mailbox.h"
21 
22 #define HSP_INT_IE(x)		(0x100 + ((x) * 4))
23 #define HSP_INT_IV		0x300
24 #define HSP_INT_IR		0x304
25 
26 #define HSP_INT_EMPTY_SHIFT	0
27 #define HSP_INT_EMPTY_MASK	0xff
28 #define HSP_INT_FULL_SHIFT	8
29 #define HSP_INT_FULL_MASK	0xff
30 
31 #define HSP_INT_DIMENSIONING	0x380
32 #define HSP_nSM_SHIFT		0
33 #define HSP_nSS_SHIFT		4
34 #define HSP_nAS_SHIFT		8
35 #define HSP_nDB_SHIFT		12
36 #define HSP_nSI_SHIFT		16
37 #define HSP_nINT_MASK		0xf
38 
39 #define HSP_DB_TRIGGER	0x0
40 #define HSP_DB_ENABLE	0x4
41 #define HSP_DB_RAW	0x8
42 #define HSP_DB_PENDING	0xc
43 
44 #define HSP_SM_SHRD_MBOX	0x0
45 #define HSP_SM_SHRD_MBOX_FULL	BIT(31)
46 #define HSP_SM_SHRD_MBOX_FULL_INT_IE	0x04
47 #define HSP_SM_SHRD_MBOX_EMPTY_INT_IE	0x08
48 
49 #define HSP_DB_CCPLEX		1
50 #define HSP_DB_BPMP		3
51 #define HSP_DB_MAX		7
52 
53 struct tegra_hsp_channel;
54 struct tegra_hsp;
55 
56 struct tegra_hsp_channel {
57 	struct tegra_hsp *hsp;
58 	struct mbox_chan *chan;
59 	void __iomem *regs;
60 };
61 
62 struct tegra_hsp_doorbell {
63 	struct tegra_hsp_channel channel;
64 	struct list_head list;
65 	const char *name;
66 	unsigned int master;
67 	unsigned int index;
68 };
69 
70 struct tegra_hsp_mailbox {
71 	struct tegra_hsp_channel channel;
72 	unsigned int index;
73 	bool producer;
74 };
75 
76 struct tegra_hsp_db_map {
77 	const char *name;
78 	unsigned int master;
79 	unsigned int index;
80 };
81 
82 struct tegra_hsp_soc {
83 	const struct tegra_hsp_db_map *map;
84 	bool has_per_mb_ie;
85 };
86 
87 struct tegra_hsp {
88 	struct device *dev;
89 	const struct tegra_hsp_soc *soc;
90 	struct mbox_controller mbox_db;
91 	struct mbox_controller mbox_sm;
92 	void __iomem *regs;
93 	unsigned int doorbell_irq;
94 	unsigned int *shared_irqs;
95 	unsigned int shared_irq;
96 	unsigned int num_sm;
97 	unsigned int num_as;
98 	unsigned int num_ss;
99 	unsigned int num_db;
100 	unsigned int num_si;
101 
102 	spinlock_t lock;
103 	struct lock_class_key lock_key;
104 
105 	struct list_head doorbells;
106 	struct tegra_hsp_mailbox *mailboxes;
107 
108 	unsigned long mask;
109 };
110 
111 static inline u32 tegra_hsp_readl(struct tegra_hsp *hsp, unsigned int offset)
112 {
113 	return readl(hsp->regs + offset);
114 }
115 
116 static inline void tegra_hsp_writel(struct tegra_hsp *hsp, u32 value,
117 				    unsigned int offset)
118 {
119 	writel(value, hsp->regs + offset);
120 }
121 
122 static inline u32 tegra_hsp_channel_readl(struct tegra_hsp_channel *channel,
123 					  unsigned int offset)
124 {
125 	return readl(channel->regs + offset);
126 }
127 
128 static inline void tegra_hsp_channel_writel(struct tegra_hsp_channel *channel,
129 					    u32 value, unsigned int offset)
130 {
131 	writel(value, channel->regs + offset);
132 }
133 
134 static bool tegra_hsp_doorbell_can_ring(struct tegra_hsp_doorbell *db)
135 {
136 	u32 value;
137 
138 	value = tegra_hsp_channel_readl(&db->channel, HSP_DB_ENABLE);
139 
140 	return (value & BIT(TEGRA_HSP_DB_MASTER_CCPLEX)) != 0;
141 }
142 
143 static struct tegra_hsp_doorbell *
144 __tegra_hsp_doorbell_get(struct tegra_hsp *hsp, unsigned int master)
145 {
146 	struct tegra_hsp_doorbell *entry;
147 
148 	list_for_each_entry(entry, &hsp->doorbells, list)
149 		if (entry->master == master)
150 			return entry;
151 
152 	return NULL;
153 }
154 
155 static struct tegra_hsp_doorbell *
156 tegra_hsp_doorbell_get(struct tegra_hsp *hsp, unsigned int master)
157 {
158 	struct tegra_hsp_doorbell *db;
159 	unsigned long flags;
160 
161 	spin_lock_irqsave(&hsp->lock, flags);
162 	db = __tegra_hsp_doorbell_get(hsp, master);
163 	spin_unlock_irqrestore(&hsp->lock, flags);
164 
165 	return db;
166 }
167 
168 static irqreturn_t tegra_hsp_doorbell_irq(int irq, void *data)
169 {
170 	struct tegra_hsp *hsp = data;
171 	struct tegra_hsp_doorbell *db;
172 	unsigned long master, value;
173 
174 	db = tegra_hsp_doorbell_get(hsp, TEGRA_HSP_DB_MASTER_CCPLEX);
175 	if (!db)
176 		return IRQ_NONE;
177 
178 	value = tegra_hsp_channel_readl(&db->channel, HSP_DB_PENDING);
179 	tegra_hsp_channel_writel(&db->channel, value, HSP_DB_PENDING);
180 
181 	spin_lock(&hsp->lock);
182 
183 	for_each_set_bit(master, &value, hsp->mbox_db.num_chans) {
184 		struct tegra_hsp_doorbell *db;
185 
186 		db = __tegra_hsp_doorbell_get(hsp, master);
187 		/*
188 		 * Depending on the bootloader chain, the CCPLEX doorbell will
189 		 * have some doorbells enabled, which means that requesting an
190 		 * interrupt will immediately fire.
191 		 *
192 		 * In that case, db->channel.chan will still be NULL here and
193 		 * cause a crash if not properly guarded.
194 		 *
195 		 * It remains to be seen if ignoring the doorbell in that case
196 		 * is the correct solution.
197 		 */
198 		if (db && db->channel.chan)
199 			mbox_chan_received_data(db->channel.chan, NULL);
200 	}
201 
202 	spin_unlock(&hsp->lock);
203 
204 	return IRQ_HANDLED;
205 }
206 
207 static irqreturn_t tegra_hsp_shared_irq(int irq, void *data)
208 {
209 	struct tegra_hsp *hsp = data;
210 	unsigned long bit, mask;
211 	u32 status, value;
212 	void *msg;
213 
214 	status = tegra_hsp_readl(hsp, HSP_INT_IR) & hsp->mask;
215 
216 	/* process EMPTY interrupts first */
217 	mask = (status >> HSP_INT_EMPTY_SHIFT) & HSP_INT_EMPTY_MASK;
218 
219 	for_each_set_bit(bit, &mask, hsp->num_sm) {
220 		struct tegra_hsp_mailbox *mb = &hsp->mailboxes[bit];
221 
222 		if (mb->producer) {
223 			/*
224 			 * Disable EMPTY interrupts until data is sent with
225 			 * the next message. These interrupts are level-
226 			 * triggered, so if we kept them enabled they would
227 			 * constantly trigger until we next write data into
228 			 * the message.
229 			 */
230 			spin_lock(&hsp->lock);
231 
232 			hsp->mask &= ~BIT(HSP_INT_EMPTY_SHIFT + mb->index);
233 			tegra_hsp_writel(hsp, hsp->mask,
234 					 HSP_INT_IE(hsp->shared_irq));
235 
236 			spin_unlock(&hsp->lock);
237 
238 			mbox_chan_txdone(mb->channel.chan, 0);
239 		}
240 	}
241 
242 	/* process FULL interrupts */
243 	mask = (status >> HSP_INT_FULL_SHIFT) & HSP_INT_FULL_MASK;
244 
245 	for_each_set_bit(bit, &mask, hsp->num_sm) {
246 		struct tegra_hsp_mailbox *mb = &hsp->mailboxes[bit];
247 
248 		if (!mb->producer) {
249 			value = tegra_hsp_channel_readl(&mb->channel,
250 							HSP_SM_SHRD_MBOX);
251 			value &= ~HSP_SM_SHRD_MBOX_FULL;
252 			msg = (void *)(unsigned long)value;
253 			mbox_chan_received_data(mb->channel.chan, msg);
254 
255 			/*
256 			 * Need to clear all bits here since some producers,
257 			 * such as TCU, depend on fields in the register
258 			 * getting cleared by the consumer.
259 			 *
260 			 * The mailbox API doesn't give the consumers a way
261 			 * of doing that explicitly, so we have to make sure
262 			 * we cover all possible cases.
263 			 */
264 			tegra_hsp_channel_writel(&mb->channel, 0x0,
265 						 HSP_SM_SHRD_MBOX);
266 		}
267 	}
268 
269 	return IRQ_HANDLED;
270 }
271 
272 static struct tegra_hsp_channel *
273 tegra_hsp_doorbell_create(struct tegra_hsp *hsp, const char *name,
274 			  unsigned int master, unsigned int index)
275 {
276 	struct tegra_hsp_doorbell *db;
277 	unsigned int offset;
278 	unsigned long flags;
279 
280 	db = devm_kzalloc(hsp->dev, sizeof(*db), GFP_KERNEL);
281 	if (!db)
282 		return ERR_PTR(-ENOMEM);
283 
284 	offset = (1 + (hsp->num_sm / 2) + hsp->num_ss + hsp->num_as) * SZ_64K;
285 	offset += index * 0x100;
286 
287 	db->channel.regs = hsp->regs + offset;
288 	db->channel.hsp = hsp;
289 
290 	db->name = devm_kstrdup_const(hsp->dev, name, GFP_KERNEL);
291 	db->master = master;
292 	db->index = index;
293 
294 	spin_lock_irqsave(&hsp->lock, flags);
295 	list_add_tail(&db->list, &hsp->doorbells);
296 	spin_unlock_irqrestore(&hsp->lock, flags);
297 
298 	return &db->channel;
299 }
300 
301 static int tegra_hsp_doorbell_send_data(struct mbox_chan *chan, void *data)
302 {
303 	struct tegra_hsp_doorbell *db = chan->con_priv;
304 
305 	tegra_hsp_channel_writel(&db->channel, 1, HSP_DB_TRIGGER);
306 
307 	return 0;
308 }
309 
310 static int tegra_hsp_doorbell_startup(struct mbox_chan *chan)
311 {
312 	struct tegra_hsp_doorbell *db = chan->con_priv;
313 	struct tegra_hsp *hsp = db->channel.hsp;
314 	struct tegra_hsp_doorbell *ccplex;
315 	unsigned long flags;
316 	u32 value;
317 
318 	if (db->master >= chan->mbox->num_chans) {
319 		dev_err(chan->mbox->dev,
320 			"invalid master ID %u for HSP channel\n",
321 			db->master);
322 		return -EINVAL;
323 	}
324 
325 	ccplex = tegra_hsp_doorbell_get(hsp, TEGRA_HSP_DB_MASTER_CCPLEX);
326 	if (!ccplex)
327 		return -ENODEV;
328 
329 	/*
330 	 * On simulation platforms the BPMP hasn't had a chance yet to mark
331 	 * the doorbell as ringable by the CCPLEX, so we want to skip extra
332 	 * checks here.
333 	 */
334 	if (tegra_is_silicon() && !tegra_hsp_doorbell_can_ring(db))
335 		return -ENODEV;
336 
337 	spin_lock_irqsave(&hsp->lock, flags);
338 
339 	value = tegra_hsp_channel_readl(&ccplex->channel, HSP_DB_ENABLE);
340 	value |= BIT(db->master);
341 	tegra_hsp_channel_writel(&ccplex->channel, value, HSP_DB_ENABLE);
342 
343 	spin_unlock_irqrestore(&hsp->lock, flags);
344 
345 	return 0;
346 }
347 
348 static void tegra_hsp_doorbell_shutdown(struct mbox_chan *chan)
349 {
350 	struct tegra_hsp_doorbell *db = chan->con_priv;
351 	struct tegra_hsp *hsp = db->channel.hsp;
352 	struct tegra_hsp_doorbell *ccplex;
353 	unsigned long flags;
354 	u32 value;
355 
356 	ccplex = tegra_hsp_doorbell_get(hsp, TEGRA_HSP_DB_MASTER_CCPLEX);
357 	if (!ccplex)
358 		return;
359 
360 	spin_lock_irqsave(&hsp->lock, flags);
361 
362 	value = tegra_hsp_channel_readl(&ccplex->channel, HSP_DB_ENABLE);
363 	value &= ~BIT(db->master);
364 	tegra_hsp_channel_writel(&ccplex->channel, value, HSP_DB_ENABLE);
365 
366 	spin_unlock_irqrestore(&hsp->lock, flags);
367 }
368 
369 static const struct mbox_chan_ops tegra_hsp_db_ops = {
370 	.send_data = tegra_hsp_doorbell_send_data,
371 	.startup = tegra_hsp_doorbell_startup,
372 	.shutdown = tegra_hsp_doorbell_shutdown,
373 };
374 
375 static int tegra_hsp_mailbox_send_data(struct mbox_chan *chan, void *data)
376 {
377 	struct tegra_hsp_mailbox *mb = chan->con_priv;
378 	struct tegra_hsp *hsp = mb->channel.hsp;
379 	unsigned long flags;
380 	u32 value;
381 
382 	if (WARN_ON(!mb->producer))
383 		return -EPERM;
384 
385 	/* copy data and mark mailbox full */
386 	value = (u32)(unsigned long)data;
387 	value |= HSP_SM_SHRD_MBOX_FULL;
388 
389 	tegra_hsp_channel_writel(&mb->channel, value, HSP_SM_SHRD_MBOX);
390 
391 	/* enable EMPTY interrupt for the shared mailbox */
392 	spin_lock_irqsave(&hsp->lock, flags);
393 
394 	hsp->mask |= BIT(HSP_INT_EMPTY_SHIFT + mb->index);
395 	tegra_hsp_writel(hsp, hsp->mask, HSP_INT_IE(hsp->shared_irq));
396 
397 	spin_unlock_irqrestore(&hsp->lock, flags);
398 
399 	return 0;
400 }
401 
402 static int tegra_hsp_mailbox_flush(struct mbox_chan *chan,
403 				   unsigned long timeout)
404 {
405 	struct tegra_hsp_mailbox *mb = chan->con_priv;
406 	struct tegra_hsp_channel *ch = &mb->channel;
407 	u32 value;
408 
409 	timeout = jiffies + msecs_to_jiffies(timeout);
410 
411 	while (time_before(jiffies, timeout)) {
412 		value = tegra_hsp_channel_readl(ch, HSP_SM_SHRD_MBOX);
413 		if ((value & HSP_SM_SHRD_MBOX_FULL) == 0) {
414 			mbox_chan_txdone(chan, 0);
415 
416 			/* Wait until channel is empty */
417 			if (chan->active_req != NULL)
418 				continue;
419 
420 			return 0;
421 		}
422 
423 		udelay(1);
424 	}
425 
426 	return -ETIME;
427 }
428 
429 static int tegra_hsp_mailbox_startup(struct mbox_chan *chan)
430 {
431 	struct tegra_hsp_mailbox *mb = chan->con_priv;
432 	struct tegra_hsp_channel *ch = &mb->channel;
433 	struct tegra_hsp *hsp = mb->channel.hsp;
434 	unsigned long flags;
435 
436 	chan->txdone_method = TXDONE_BY_IRQ;
437 
438 	/*
439 	 * Shared mailboxes start out as consumers by default. FULL and EMPTY
440 	 * interrupts are coalesced at the same shared interrupt.
441 	 *
442 	 * Keep EMPTY interrupts disabled at startup and only enable them when
443 	 * the mailbox is actually full. This is required because the FULL and
444 	 * EMPTY interrupts are level-triggered, so keeping EMPTY interrupts
445 	 * enabled all the time would cause an interrupt storm while mailboxes
446 	 * are idle.
447 	 */
448 
449 	spin_lock_irqsave(&hsp->lock, flags);
450 
451 	if (mb->producer)
452 		hsp->mask &= ~BIT(HSP_INT_EMPTY_SHIFT + mb->index);
453 	else
454 		hsp->mask |= BIT(HSP_INT_FULL_SHIFT + mb->index);
455 
456 	tegra_hsp_writel(hsp, hsp->mask, HSP_INT_IE(hsp->shared_irq));
457 
458 	spin_unlock_irqrestore(&hsp->lock, flags);
459 
460 	if (hsp->soc->has_per_mb_ie) {
461 		if (mb->producer)
462 			tegra_hsp_channel_writel(ch, 0x0,
463 						 HSP_SM_SHRD_MBOX_EMPTY_INT_IE);
464 		else
465 			tegra_hsp_channel_writel(ch, 0x1,
466 						 HSP_SM_SHRD_MBOX_FULL_INT_IE);
467 	}
468 
469 	return 0;
470 }
471 
472 static void tegra_hsp_mailbox_shutdown(struct mbox_chan *chan)
473 {
474 	struct tegra_hsp_mailbox *mb = chan->con_priv;
475 	struct tegra_hsp_channel *ch = &mb->channel;
476 	struct tegra_hsp *hsp = mb->channel.hsp;
477 	unsigned long flags;
478 
479 	if (hsp->soc->has_per_mb_ie) {
480 		if (mb->producer)
481 			tegra_hsp_channel_writel(ch, 0x0,
482 						 HSP_SM_SHRD_MBOX_EMPTY_INT_IE);
483 		else
484 			tegra_hsp_channel_writel(ch, 0x0,
485 						 HSP_SM_SHRD_MBOX_FULL_INT_IE);
486 	}
487 
488 	spin_lock_irqsave(&hsp->lock, flags);
489 
490 	if (mb->producer)
491 		hsp->mask &= ~BIT(HSP_INT_EMPTY_SHIFT + mb->index);
492 	else
493 		hsp->mask &= ~BIT(HSP_INT_FULL_SHIFT + mb->index);
494 
495 	tegra_hsp_writel(hsp, hsp->mask, HSP_INT_IE(hsp->shared_irq));
496 
497 	spin_unlock_irqrestore(&hsp->lock, flags);
498 }
499 
500 static const struct mbox_chan_ops tegra_hsp_sm_ops = {
501 	.send_data = tegra_hsp_mailbox_send_data,
502 	.flush = tegra_hsp_mailbox_flush,
503 	.startup = tegra_hsp_mailbox_startup,
504 	.shutdown = tegra_hsp_mailbox_shutdown,
505 };
506 
507 static struct mbox_chan *tegra_hsp_db_xlate(struct mbox_controller *mbox,
508 					    const struct of_phandle_args *args)
509 {
510 	struct tegra_hsp *hsp = container_of(mbox, struct tegra_hsp, mbox_db);
511 	unsigned int type = args->args[0], master = args->args[1];
512 	struct tegra_hsp_channel *channel = ERR_PTR(-ENODEV);
513 	struct tegra_hsp_doorbell *db;
514 	struct mbox_chan *chan;
515 	unsigned long flags;
516 	unsigned int i;
517 
518 	if (type != TEGRA_HSP_MBOX_TYPE_DB || !hsp->doorbell_irq)
519 		return ERR_PTR(-ENODEV);
520 
521 	db = tegra_hsp_doorbell_get(hsp, master);
522 	if (db)
523 		channel = &db->channel;
524 
525 	if (IS_ERR(channel))
526 		return ERR_CAST(channel);
527 
528 	spin_lock_irqsave(&hsp->lock, flags);
529 
530 	for (i = 0; i < mbox->num_chans; i++) {
531 		chan = &mbox->chans[i];
532 		if (!chan->con_priv) {
533 			channel->chan = chan;
534 			chan->con_priv = db;
535 			break;
536 		}
537 
538 		chan = NULL;
539 	}
540 
541 	spin_unlock_irqrestore(&hsp->lock, flags);
542 
543 	return chan ?: ERR_PTR(-EBUSY);
544 }
545 
546 static struct mbox_chan *tegra_hsp_sm_xlate(struct mbox_controller *mbox,
547 					    const struct of_phandle_args *args)
548 {
549 	struct tegra_hsp *hsp = container_of(mbox, struct tegra_hsp, mbox_sm);
550 	unsigned int type = args->args[0], index;
551 	struct tegra_hsp_mailbox *mb;
552 
553 	index = args->args[1] & TEGRA_HSP_SM_MASK;
554 
555 	if (type != TEGRA_HSP_MBOX_TYPE_SM || !hsp->shared_irqs ||
556 	    index >= hsp->num_sm)
557 		return ERR_PTR(-ENODEV);
558 
559 	mb = &hsp->mailboxes[index];
560 
561 	if ((args->args[1] & TEGRA_HSP_SM_FLAG_TX) == 0)
562 		mb->producer = false;
563 	else
564 		mb->producer = true;
565 
566 	return mb->channel.chan;
567 }
568 
569 static int tegra_hsp_add_doorbells(struct tegra_hsp *hsp)
570 {
571 	const struct tegra_hsp_db_map *map = hsp->soc->map;
572 	struct tegra_hsp_channel *channel;
573 
574 	while (map->name) {
575 		channel = tegra_hsp_doorbell_create(hsp, map->name,
576 						    map->master, map->index);
577 		if (IS_ERR(channel))
578 			return PTR_ERR(channel);
579 
580 		map++;
581 	}
582 
583 	return 0;
584 }
585 
586 static int tegra_hsp_add_mailboxes(struct tegra_hsp *hsp, struct device *dev)
587 {
588 	int i;
589 
590 	hsp->mailboxes = devm_kcalloc(dev, hsp->num_sm, sizeof(*hsp->mailboxes),
591 				      GFP_KERNEL);
592 	if (!hsp->mailboxes)
593 		return -ENOMEM;
594 
595 	for (i = 0; i < hsp->num_sm; i++) {
596 		struct tegra_hsp_mailbox *mb = &hsp->mailboxes[i];
597 
598 		mb->index = i;
599 
600 		mb->channel.hsp = hsp;
601 		mb->channel.regs = hsp->regs + SZ_64K + i * SZ_32K;
602 		mb->channel.chan = &hsp->mbox_sm.chans[i];
603 		mb->channel.chan->con_priv = mb;
604 	}
605 
606 	return 0;
607 }
608 
609 static int tegra_hsp_request_shared_irq(struct tegra_hsp *hsp)
610 {
611 	unsigned int i, irq = 0;
612 	int err;
613 
614 	for (i = 0; i < hsp->num_si; i++) {
615 		irq = hsp->shared_irqs[i];
616 		if (irq <= 0)
617 			continue;
618 
619 		err = devm_request_irq(hsp->dev, irq, tegra_hsp_shared_irq, 0,
620 				       dev_name(hsp->dev), hsp);
621 		if (err < 0) {
622 			dev_err(hsp->dev, "failed to request interrupt: %d\n",
623 				err);
624 			continue;
625 		}
626 
627 		hsp->shared_irq = i;
628 
629 		/* disable all interrupts */
630 		tegra_hsp_writel(hsp, 0, HSP_INT_IE(hsp->shared_irq));
631 
632 		dev_dbg(hsp->dev, "interrupt requested: %u\n", irq);
633 
634 		break;
635 	}
636 
637 	if (i == hsp->num_si) {
638 		dev_err(hsp->dev, "failed to find available interrupt\n");
639 		return -ENOENT;
640 	}
641 
642 	return 0;
643 }
644 
645 static int tegra_hsp_probe(struct platform_device *pdev)
646 {
647 	struct tegra_hsp *hsp;
648 	struct resource *res;
649 	unsigned int i;
650 	u32 value;
651 	int err;
652 
653 	hsp = devm_kzalloc(&pdev->dev, sizeof(*hsp), GFP_KERNEL);
654 	if (!hsp)
655 		return -ENOMEM;
656 
657 	hsp->dev = &pdev->dev;
658 	hsp->soc = of_device_get_match_data(&pdev->dev);
659 	INIT_LIST_HEAD(&hsp->doorbells);
660 	spin_lock_init(&hsp->lock);
661 
662 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
663 	hsp->regs = devm_ioremap_resource(&pdev->dev, res);
664 	if (IS_ERR(hsp->regs))
665 		return PTR_ERR(hsp->regs);
666 
667 	value = tegra_hsp_readl(hsp, HSP_INT_DIMENSIONING);
668 	hsp->num_sm = (value >> HSP_nSM_SHIFT) & HSP_nINT_MASK;
669 	hsp->num_ss = (value >> HSP_nSS_SHIFT) & HSP_nINT_MASK;
670 	hsp->num_as = (value >> HSP_nAS_SHIFT) & HSP_nINT_MASK;
671 	hsp->num_db = (value >> HSP_nDB_SHIFT) & HSP_nINT_MASK;
672 	hsp->num_si = (value >> HSP_nSI_SHIFT) & HSP_nINT_MASK;
673 
674 	err = platform_get_irq_byname_optional(pdev, "doorbell");
675 	if (err >= 0)
676 		hsp->doorbell_irq = err;
677 
678 	if (hsp->num_si > 0) {
679 		unsigned int count = 0;
680 
681 		hsp->shared_irqs = devm_kcalloc(&pdev->dev, hsp->num_si,
682 						sizeof(*hsp->shared_irqs),
683 						GFP_KERNEL);
684 		if (!hsp->shared_irqs)
685 			return -ENOMEM;
686 
687 		for (i = 0; i < hsp->num_si; i++) {
688 			char *name;
689 
690 			name = kasprintf(GFP_KERNEL, "shared%u", i);
691 			if (!name)
692 				return -ENOMEM;
693 
694 			err = platform_get_irq_byname_optional(pdev, name);
695 			if (err >= 0) {
696 				hsp->shared_irqs[i] = err;
697 				count++;
698 			}
699 
700 			kfree(name);
701 		}
702 
703 		if (count == 0) {
704 			devm_kfree(&pdev->dev, hsp->shared_irqs);
705 			hsp->shared_irqs = NULL;
706 		}
707 	}
708 
709 	/* setup the doorbell controller */
710 	hsp->mbox_db.of_xlate = tegra_hsp_db_xlate;
711 	hsp->mbox_db.num_chans = 32;
712 	hsp->mbox_db.dev = &pdev->dev;
713 	hsp->mbox_db.ops = &tegra_hsp_db_ops;
714 
715 	hsp->mbox_db.chans = devm_kcalloc(&pdev->dev, hsp->mbox_db.num_chans,
716 					  sizeof(*hsp->mbox_db.chans),
717 					  GFP_KERNEL);
718 	if (!hsp->mbox_db.chans)
719 		return -ENOMEM;
720 
721 	if (hsp->doorbell_irq) {
722 		err = tegra_hsp_add_doorbells(hsp);
723 		if (err < 0) {
724 			dev_err(&pdev->dev, "failed to add doorbells: %d\n",
725 			        err);
726 			return err;
727 		}
728 	}
729 
730 	err = devm_mbox_controller_register(&pdev->dev, &hsp->mbox_db);
731 	if (err < 0) {
732 		dev_err(&pdev->dev, "failed to register doorbell mailbox: %d\n",
733 			err);
734 		return err;
735 	}
736 
737 	/* setup the shared mailbox controller */
738 	hsp->mbox_sm.of_xlate = tegra_hsp_sm_xlate;
739 	hsp->mbox_sm.num_chans = hsp->num_sm;
740 	hsp->mbox_sm.dev = &pdev->dev;
741 	hsp->mbox_sm.ops = &tegra_hsp_sm_ops;
742 
743 	hsp->mbox_sm.chans = devm_kcalloc(&pdev->dev, hsp->mbox_sm.num_chans,
744 					  sizeof(*hsp->mbox_sm.chans),
745 					  GFP_KERNEL);
746 	if (!hsp->mbox_sm.chans)
747 		return -ENOMEM;
748 
749 	if (hsp->shared_irqs) {
750 		err = tegra_hsp_add_mailboxes(hsp, &pdev->dev);
751 		if (err < 0) {
752 			dev_err(&pdev->dev, "failed to add mailboxes: %d\n",
753 			        err);
754 			return err;
755 		}
756 	}
757 
758 	err = devm_mbox_controller_register(&pdev->dev, &hsp->mbox_sm);
759 	if (err < 0) {
760 		dev_err(&pdev->dev, "failed to register shared mailbox: %d\n",
761 			err);
762 		return err;
763 	}
764 
765 	platform_set_drvdata(pdev, hsp);
766 
767 	if (hsp->doorbell_irq) {
768 		err = devm_request_irq(&pdev->dev, hsp->doorbell_irq,
769 				       tegra_hsp_doorbell_irq, IRQF_NO_SUSPEND,
770 				       dev_name(&pdev->dev), hsp);
771 		if (err < 0) {
772 			dev_err(&pdev->dev,
773 			        "failed to request doorbell IRQ#%u: %d\n",
774 				hsp->doorbell_irq, err);
775 			return err;
776 		}
777 	}
778 
779 	if (hsp->shared_irqs) {
780 		err = tegra_hsp_request_shared_irq(hsp);
781 		if (err < 0)
782 			return err;
783 	}
784 
785 	lockdep_register_key(&hsp->lock_key);
786 	lockdep_set_class(&hsp->lock, &hsp->lock_key);
787 
788 	return 0;
789 }
790 
791 static int tegra_hsp_remove(struct platform_device *pdev)
792 {
793 	struct tegra_hsp *hsp = platform_get_drvdata(pdev);
794 
795 	lockdep_unregister_key(&hsp->lock_key);
796 
797 	return 0;
798 }
799 
800 static int __maybe_unused tegra_hsp_resume(struct device *dev)
801 {
802 	struct tegra_hsp *hsp = dev_get_drvdata(dev);
803 	unsigned int i;
804 	struct tegra_hsp_doorbell *db;
805 
806 	list_for_each_entry(db, &hsp->doorbells, list) {
807 		if (db && db->channel.chan)
808 			tegra_hsp_doorbell_startup(db->channel.chan);
809 	}
810 
811 	if (hsp->mailboxes) {
812 		for (i = 0; i < hsp->num_sm; i++) {
813 			struct tegra_hsp_mailbox *mb = &hsp->mailboxes[i];
814 
815 			if (mb->channel.chan->cl)
816 				tegra_hsp_mailbox_startup(mb->channel.chan);
817 		}
818 	}
819 
820 	return 0;
821 }
822 
823 static const struct dev_pm_ops tegra_hsp_pm_ops = {
824 	.resume_noirq = tegra_hsp_resume,
825 };
826 
827 static const struct tegra_hsp_db_map tegra186_hsp_db_map[] = {
828 	{ "ccplex", TEGRA_HSP_DB_MASTER_CCPLEX, HSP_DB_CCPLEX, },
829 	{ "bpmp",   TEGRA_HSP_DB_MASTER_BPMP,   HSP_DB_BPMP,   },
830 	{ /* sentinel */ }
831 };
832 
833 static const struct tegra_hsp_soc tegra186_hsp_soc = {
834 	.map = tegra186_hsp_db_map,
835 	.has_per_mb_ie = false,
836 };
837 
838 static const struct tegra_hsp_soc tegra194_hsp_soc = {
839 	.map = tegra186_hsp_db_map,
840 	.has_per_mb_ie = true,
841 };
842 
843 static const struct of_device_id tegra_hsp_match[] = {
844 	{ .compatible = "nvidia,tegra186-hsp", .data = &tegra186_hsp_soc },
845 	{ .compatible = "nvidia,tegra194-hsp", .data = &tegra194_hsp_soc },
846 	{ }
847 };
848 
849 static struct platform_driver tegra_hsp_driver = {
850 	.driver = {
851 		.name = "tegra-hsp",
852 		.of_match_table = tegra_hsp_match,
853 		.pm = &tegra_hsp_pm_ops,
854 	},
855 	.probe = tegra_hsp_probe,
856 	.remove = tegra_hsp_remove,
857 };
858 
859 static int __init tegra_hsp_init(void)
860 {
861 	return platform_driver_register(&tegra_hsp_driver);
862 }
863 core_initcall(tegra_hsp_init);
864