1ca27fc26SBaolin Wang // SPDX-License-Identifier: GPL-2.0-only
2ca27fc26SBaolin Wang /*
3ca27fc26SBaolin Wang * Spreadtrum mailbox driver
4ca27fc26SBaolin Wang *
5ca27fc26SBaolin Wang * Copyright (c) 2020 Spreadtrum Communications Inc.
6ca27fc26SBaolin Wang */
7ca27fc26SBaolin Wang
8ca27fc26SBaolin Wang #include <linux/delay.h>
9ca27fc26SBaolin Wang #include <linux/err.h>
10ca27fc26SBaolin Wang #include <linux/interrupt.h>
11ca27fc26SBaolin Wang #include <linux/io.h>
12ca27fc26SBaolin Wang #include <linux/mailbox_controller.h>
13ca27fc26SBaolin Wang #include <linux/module.h>
14*e9803aacSRob Herring #include <linux/of.h>
15ca27fc26SBaolin Wang #include <linux/platform_device.h>
16ca27fc26SBaolin Wang #include <linux/clk.h>
17ca27fc26SBaolin Wang
18ca27fc26SBaolin Wang #define SPRD_MBOX_ID 0x0
19ca27fc26SBaolin Wang #define SPRD_MBOX_MSG_LOW 0x4
20ca27fc26SBaolin Wang #define SPRD_MBOX_MSG_HIGH 0x8
21ca27fc26SBaolin Wang #define SPRD_MBOX_TRIGGER 0xc
22ca27fc26SBaolin Wang #define SPRD_MBOX_FIFO_RST 0x10
23ca27fc26SBaolin Wang #define SPRD_MBOX_FIFO_STS 0x14
24ca27fc26SBaolin Wang #define SPRD_MBOX_IRQ_STS 0x18
25ca27fc26SBaolin Wang #define SPRD_MBOX_IRQ_MSK 0x1c
26ca27fc26SBaolin Wang #define SPRD_MBOX_LOCK 0x20
27ca27fc26SBaolin Wang #define SPRD_MBOX_FIFO_DEPTH 0x24
28ca27fc26SBaolin Wang
299d2e8b93STom Saeger /* Bit and mask definition for inbox's SPRD_MBOX_FIFO_STS register */
30ca27fc26SBaolin Wang #define SPRD_INBOX_FIFO_DELIVER_MASK GENMASK(23, 16)
31ca27fc26SBaolin Wang #define SPRD_INBOX_FIFO_OVERLOW_MASK GENMASK(15, 8)
32ca27fc26SBaolin Wang #define SPRD_INBOX_FIFO_DELIVER_SHIFT 16
33ca27fc26SBaolin Wang #define SPRD_INBOX_FIFO_BUSY_MASK GENMASK(7, 0)
34ca27fc26SBaolin Wang
359d2e8b93STom Saeger /* Bit and mask definition for SPRD_MBOX_IRQ_STS register */
36ca27fc26SBaolin Wang #define SPRD_MBOX_IRQ_CLR BIT(0)
37ca27fc26SBaolin Wang
389d2e8b93STom Saeger /* Bit and mask definition for outbox's SPRD_MBOX_FIFO_STS register */
394450f128SMagnum Shan #define SPRD_OUTBOX_FIFO_FULL BIT(2)
40ca27fc26SBaolin Wang #define SPRD_OUTBOX_FIFO_WR_SHIFT 16
41ca27fc26SBaolin Wang #define SPRD_OUTBOX_FIFO_RD_SHIFT 24
42ca27fc26SBaolin Wang #define SPRD_OUTBOX_FIFO_POS_MASK GENMASK(7, 0)
43ca27fc26SBaolin Wang
449d2e8b93STom Saeger /* Bit and mask definition for inbox's SPRD_MBOX_IRQ_MSK register */
45ca27fc26SBaolin Wang #define SPRD_INBOX_FIFO_BLOCK_IRQ BIT(0)
46ca27fc26SBaolin Wang #define SPRD_INBOX_FIFO_OVERFLOW_IRQ BIT(1)
47ca27fc26SBaolin Wang #define SPRD_INBOX_FIFO_DELIVER_IRQ BIT(2)
48ca27fc26SBaolin Wang #define SPRD_INBOX_FIFO_IRQ_MASK GENMASK(2, 0)
49ca27fc26SBaolin Wang
509d2e8b93STom Saeger /* Bit and mask definition for outbox's SPRD_MBOX_IRQ_MSK register */
51ca27fc26SBaolin Wang #define SPRD_OUTBOX_FIFO_NOT_EMPTY_IRQ BIT(0)
52ca27fc26SBaolin Wang #define SPRD_OUTBOX_FIFO_IRQ_MASK GENMASK(4, 0)
53ca27fc26SBaolin Wang
546457f4cdSOrson Zhai #define SPRD_OUTBOX_BASE_SPAN 0x1000
55ca27fc26SBaolin Wang #define SPRD_MBOX_CHAN_MAX 8
566457f4cdSOrson Zhai #define SPRD_SUPP_INBOX_ID_SC9863A 7
57ca27fc26SBaolin Wang
58ca27fc26SBaolin Wang struct sprd_mbox_priv {
59ca27fc26SBaolin Wang struct mbox_controller mbox;
60ca27fc26SBaolin Wang struct device *dev;
61ca27fc26SBaolin Wang void __iomem *inbox_base;
62ca27fc26SBaolin Wang void __iomem *outbox_base;
636457f4cdSOrson Zhai /* Base register address for supplementary outbox */
646457f4cdSOrson Zhai void __iomem *supp_base;
65ca27fc26SBaolin Wang struct clk *clk;
66ca27fc26SBaolin Wang u32 outbox_fifo_depth;
67ca27fc26SBaolin Wang
689468ab84SOrson Zhai struct mutex lock;
699468ab84SOrson Zhai u32 refcnt;
70ca27fc26SBaolin Wang struct mbox_chan chan[SPRD_MBOX_CHAN_MAX];
71ca27fc26SBaolin Wang };
72ca27fc26SBaolin Wang
to_sprd_mbox_priv(struct mbox_controller * mbox)73ca27fc26SBaolin Wang static struct sprd_mbox_priv *to_sprd_mbox_priv(struct mbox_controller *mbox)
74ca27fc26SBaolin Wang {
75ca27fc26SBaolin Wang return container_of(mbox, struct sprd_mbox_priv, mbox);
76ca27fc26SBaolin Wang }
77ca27fc26SBaolin Wang
sprd_mbox_get_fifo_len(struct sprd_mbox_priv * priv,u32 fifo_sts)78ca27fc26SBaolin Wang static u32 sprd_mbox_get_fifo_len(struct sprd_mbox_priv *priv, u32 fifo_sts)
79ca27fc26SBaolin Wang {
80ca27fc26SBaolin Wang u32 wr_pos = (fifo_sts >> SPRD_OUTBOX_FIFO_WR_SHIFT) &
81ca27fc26SBaolin Wang SPRD_OUTBOX_FIFO_POS_MASK;
82ca27fc26SBaolin Wang u32 rd_pos = (fifo_sts >> SPRD_OUTBOX_FIFO_RD_SHIFT) &
83ca27fc26SBaolin Wang SPRD_OUTBOX_FIFO_POS_MASK;
84ca27fc26SBaolin Wang u32 fifo_len;
85ca27fc26SBaolin Wang
86ca27fc26SBaolin Wang /*
87ca27fc26SBaolin Wang * If the read pointer is equal with write pointer, which means the fifo
88ca27fc26SBaolin Wang * is full or empty.
89ca27fc26SBaolin Wang */
90ca27fc26SBaolin Wang if (wr_pos == rd_pos) {
91ca27fc26SBaolin Wang if (fifo_sts & SPRD_OUTBOX_FIFO_FULL)
92ca27fc26SBaolin Wang fifo_len = priv->outbox_fifo_depth;
93ca27fc26SBaolin Wang else
94ca27fc26SBaolin Wang fifo_len = 0;
95ca27fc26SBaolin Wang } else if (wr_pos > rd_pos) {
96ca27fc26SBaolin Wang fifo_len = wr_pos - rd_pos;
97ca27fc26SBaolin Wang } else {
98ca27fc26SBaolin Wang fifo_len = priv->outbox_fifo_depth - rd_pos + wr_pos;
99ca27fc26SBaolin Wang }
100ca27fc26SBaolin Wang
101ca27fc26SBaolin Wang return fifo_len;
102ca27fc26SBaolin Wang }
103ca27fc26SBaolin Wang
do_outbox_isr(void __iomem * base,struct sprd_mbox_priv * priv)1046457f4cdSOrson Zhai static irqreturn_t do_outbox_isr(void __iomem *base, struct sprd_mbox_priv *priv)
105ca27fc26SBaolin Wang {
106ca27fc26SBaolin Wang struct mbox_chan *chan;
107ca27fc26SBaolin Wang u32 fifo_sts, fifo_len, msg[2];
108ca27fc26SBaolin Wang int i, id;
109ca27fc26SBaolin Wang
1106457f4cdSOrson Zhai fifo_sts = readl(base + SPRD_MBOX_FIFO_STS);
111ca27fc26SBaolin Wang
112ca27fc26SBaolin Wang fifo_len = sprd_mbox_get_fifo_len(priv, fifo_sts);
113ca27fc26SBaolin Wang if (!fifo_len) {
114ca27fc26SBaolin Wang dev_warn_ratelimited(priv->dev, "spurious outbox interrupt\n");
115ca27fc26SBaolin Wang return IRQ_NONE;
116ca27fc26SBaolin Wang }
117ca27fc26SBaolin Wang
118ca27fc26SBaolin Wang for (i = 0; i < fifo_len; i++) {
1196457f4cdSOrson Zhai msg[0] = readl(base + SPRD_MBOX_MSG_LOW);
1206457f4cdSOrson Zhai msg[1] = readl(base + SPRD_MBOX_MSG_HIGH);
1216457f4cdSOrson Zhai id = readl(base + SPRD_MBOX_ID);
122ca27fc26SBaolin Wang
123ca27fc26SBaolin Wang chan = &priv->chan[id];
1249468ab84SOrson Zhai if (chan->cl)
125ca27fc26SBaolin Wang mbox_chan_received_data(chan, (void *)msg);
1269468ab84SOrson Zhai else
1279468ab84SOrson Zhai dev_warn_ratelimited(priv->dev,
1289468ab84SOrson Zhai "message's been dropped at ch[%d]\n", id);
129ca27fc26SBaolin Wang
130ca27fc26SBaolin Wang /* Trigger to update outbox FIFO pointer */
1316457f4cdSOrson Zhai writel(0x1, base + SPRD_MBOX_TRIGGER);
132ca27fc26SBaolin Wang }
133ca27fc26SBaolin Wang
134ca27fc26SBaolin Wang /* Clear irq status after reading all message. */
1356457f4cdSOrson Zhai writel(SPRD_MBOX_IRQ_CLR, base + SPRD_MBOX_IRQ_STS);
136ca27fc26SBaolin Wang
137ca27fc26SBaolin Wang return IRQ_HANDLED;
138ca27fc26SBaolin Wang }
139ca27fc26SBaolin Wang
sprd_mbox_outbox_isr(int irq,void * data)1406457f4cdSOrson Zhai static irqreturn_t sprd_mbox_outbox_isr(int irq, void *data)
1416457f4cdSOrson Zhai {
1426457f4cdSOrson Zhai struct sprd_mbox_priv *priv = data;
1436457f4cdSOrson Zhai
1446457f4cdSOrson Zhai return do_outbox_isr(priv->outbox_base, priv);
1456457f4cdSOrson Zhai }
1466457f4cdSOrson Zhai
sprd_mbox_supp_isr(int irq,void * data)1476457f4cdSOrson Zhai static irqreturn_t sprd_mbox_supp_isr(int irq, void *data)
1486457f4cdSOrson Zhai {
1496457f4cdSOrson Zhai struct sprd_mbox_priv *priv = data;
1506457f4cdSOrson Zhai
1516457f4cdSOrson Zhai return do_outbox_isr(priv->supp_base, priv);
1526457f4cdSOrson Zhai }
1536457f4cdSOrson Zhai
sprd_mbox_inbox_isr(int irq,void * data)154ca27fc26SBaolin Wang static irqreturn_t sprd_mbox_inbox_isr(int irq, void *data)
155ca27fc26SBaolin Wang {
156ca27fc26SBaolin Wang struct sprd_mbox_priv *priv = data;
157ca27fc26SBaolin Wang struct mbox_chan *chan;
158ca27fc26SBaolin Wang u32 fifo_sts, send_sts, busy, id;
159ca27fc26SBaolin Wang
160ca27fc26SBaolin Wang fifo_sts = readl(priv->inbox_base + SPRD_MBOX_FIFO_STS);
161ca27fc26SBaolin Wang
162ca27fc26SBaolin Wang /* Get the inbox data delivery status */
163ca27fc26SBaolin Wang send_sts = (fifo_sts & SPRD_INBOX_FIFO_DELIVER_MASK) >>
164ca27fc26SBaolin Wang SPRD_INBOX_FIFO_DELIVER_SHIFT;
165ca27fc26SBaolin Wang if (!send_sts) {
166ca27fc26SBaolin Wang dev_warn_ratelimited(priv->dev, "spurious inbox interrupt\n");
167ca27fc26SBaolin Wang return IRQ_NONE;
168ca27fc26SBaolin Wang }
169ca27fc26SBaolin Wang
170ca27fc26SBaolin Wang while (send_sts) {
171ca27fc26SBaolin Wang id = __ffs(send_sts);
172ca27fc26SBaolin Wang send_sts &= (send_sts - 1);
173ca27fc26SBaolin Wang
174ca27fc26SBaolin Wang chan = &priv->chan[id];
175ca27fc26SBaolin Wang
176ca27fc26SBaolin Wang /*
1779d2e8b93STom Saeger * Check if the message was fetched by remote target, if yes,
178ca27fc26SBaolin Wang * that means the transmission has been completed.
179ca27fc26SBaolin Wang */
180ca27fc26SBaolin Wang busy = fifo_sts & SPRD_INBOX_FIFO_BUSY_MASK;
181ca27fc26SBaolin Wang if (!(busy & BIT(id)))
182ca27fc26SBaolin Wang mbox_chan_txdone(chan, 0);
183ca27fc26SBaolin Wang }
184ca27fc26SBaolin Wang
185ca27fc26SBaolin Wang /* Clear FIFO delivery and overflow status */
186ca27fc26SBaolin Wang writel(fifo_sts &
187ca27fc26SBaolin Wang (SPRD_INBOX_FIFO_DELIVER_MASK | SPRD_INBOX_FIFO_OVERLOW_MASK),
188ca27fc26SBaolin Wang priv->inbox_base + SPRD_MBOX_FIFO_RST);
189ca27fc26SBaolin Wang
190ca27fc26SBaolin Wang /* Clear irq status */
191ca27fc26SBaolin Wang writel(SPRD_MBOX_IRQ_CLR, priv->inbox_base + SPRD_MBOX_IRQ_STS);
192ca27fc26SBaolin Wang
193ca27fc26SBaolin Wang return IRQ_HANDLED;
194ca27fc26SBaolin Wang }
195ca27fc26SBaolin Wang
sprd_mbox_send_data(struct mbox_chan * chan,void * msg)196ca27fc26SBaolin Wang static int sprd_mbox_send_data(struct mbox_chan *chan, void *msg)
197ca27fc26SBaolin Wang {
198ca27fc26SBaolin Wang struct sprd_mbox_priv *priv = to_sprd_mbox_priv(chan->mbox);
199ca27fc26SBaolin Wang unsigned long id = (unsigned long)chan->con_priv;
200ca27fc26SBaolin Wang u32 *data = msg;
201ca27fc26SBaolin Wang
202ca27fc26SBaolin Wang /* Write data into inbox FIFO, and only support 8 bytes every time */
203ca27fc26SBaolin Wang writel(data[0], priv->inbox_base + SPRD_MBOX_MSG_LOW);
204ca27fc26SBaolin Wang writel(data[1], priv->inbox_base + SPRD_MBOX_MSG_HIGH);
205ca27fc26SBaolin Wang
206ca27fc26SBaolin Wang /* Set target core id */
207ca27fc26SBaolin Wang writel(id, priv->inbox_base + SPRD_MBOX_ID);
208ca27fc26SBaolin Wang
209ca27fc26SBaolin Wang /* Trigger remote request */
210ca27fc26SBaolin Wang writel(0x1, priv->inbox_base + SPRD_MBOX_TRIGGER);
211ca27fc26SBaolin Wang
212ca27fc26SBaolin Wang return 0;
213ca27fc26SBaolin Wang }
214ca27fc26SBaolin Wang
sprd_mbox_flush(struct mbox_chan * chan,unsigned long timeout)215ca27fc26SBaolin Wang static int sprd_mbox_flush(struct mbox_chan *chan, unsigned long timeout)
216ca27fc26SBaolin Wang {
217ca27fc26SBaolin Wang struct sprd_mbox_priv *priv = to_sprd_mbox_priv(chan->mbox);
218ca27fc26SBaolin Wang unsigned long id = (unsigned long)chan->con_priv;
219ca27fc26SBaolin Wang u32 busy;
220ca27fc26SBaolin Wang
221ca27fc26SBaolin Wang timeout = jiffies + msecs_to_jiffies(timeout);
222ca27fc26SBaolin Wang
223ca27fc26SBaolin Wang while (time_before(jiffies, timeout)) {
224ca27fc26SBaolin Wang busy = readl(priv->inbox_base + SPRD_MBOX_FIFO_STS) &
225ca27fc26SBaolin Wang SPRD_INBOX_FIFO_BUSY_MASK;
226ca27fc26SBaolin Wang if (!(busy & BIT(id))) {
227ca27fc26SBaolin Wang mbox_chan_txdone(chan, 0);
228ca27fc26SBaolin Wang return 0;
229ca27fc26SBaolin Wang }
230ca27fc26SBaolin Wang
231ca27fc26SBaolin Wang udelay(1);
232ca27fc26SBaolin Wang }
233ca27fc26SBaolin Wang
234ca27fc26SBaolin Wang return -ETIME;
235ca27fc26SBaolin Wang }
236ca27fc26SBaolin Wang
sprd_mbox_startup(struct mbox_chan * chan)237ca27fc26SBaolin Wang static int sprd_mbox_startup(struct mbox_chan *chan)
238ca27fc26SBaolin Wang {
239ca27fc26SBaolin Wang struct sprd_mbox_priv *priv = to_sprd_mbox_priv(chan->mbox);
240ca27fc26SBaolin Wang u32 val;
241ca27fc26SBaolin Wang
2429468ab84SOrson Zhai mutex_lock(&priv->lock);
2439468ab84SOrson Zhai if (priv->refcnt++ == 0) {
244ca27fc26SBaolin Wang /* Select outbox FIFO mode and reset the outbox FIFO status */
245ca27fc26SBaolin Wang writel(0x0, priv->outbox_base + SPRD_MBOX_FIFO_RST);
246ca27fc26SBaolin Wang
247ca27fc26SBaolin Wang /* Enable inbox FIFO overflow and delivery interrupt */
248ca27fc26SBaolin Wang val = readl(priv->inbox_base + SPRD_MBOX_IRQ_MSK);
249ca27fc26SBaolin Wang val &= ~(SPRD_INBOX_FIFO_OVERFLOW_IRQ | SPRD_INBOX_FIFO_DELIVER_IRQ);
250ca27fc26SBaolin Wang writel(val, priv->inbox_base + SPRD_MBOX_IRQ_MSK);
251ca27fc26SBaolin Wang
252ca27fc26SBaolin Wang /* Enable outbox FIFO not empty interrupt */
253ca27fc26SBaolin Wang val = readl(priv->outbox_base + SPRD_MBOX_IRQ_MSK);
254ca27fc26SBaolin Wang val &= ~SPRD_OUTBOX_FIFO_NOT_EMPTY_IRQ;
255ca27fc26SBaolin Wang writel(val, priv->outbox_base + SPRD_MBOX_IRQ_MSK);
2566457f4cdSOrson Zhai
2576457f4cdSOrson Zhai /* Enable supplementary outbox as the fundamental one */
2586457f4cdSOrson Zhai if (priv->supp_base) {
2596457f4cdSOrson Zhai writel(0x0, priv->supp_base + SPRD_MBOX_FIFO_RST);
2606457f4cdSOrson Zhai val = readl(priv->supp_base + SPRD_MBOX_IRQ_MSK);
2616457f4cdSOrson Zhai val &= ~SPRD_OUTBOX_FIFO_NOT_EMPTY_IRQ;
2626457f4cdSOrson Zhai writel(val, priv->supp_base + SPRD_MBOX_IRQ_MSK);
2636457f4cdSOrson Zhai }
2649468ab84SOrson Zhai }
2659468ab84SOrson Zhai mutex_unlock(&priv->lock);
266ca27fc26SBaolin Wang
267ca27fc26SBaolin Wang return 0;
268ca27fc26SBaolin Wang }
269ca27fc26SBaolin Wang
sprd_mbox_shutdown(struct mbox_chan * chan)270ca27fc26SBaolin Wang static void sprd_mbox_shutdown(struct mbox_chan *chan)
271ca27fc26SBaolin Wang {
272ca27fc26SBaolin Wang struct sprd_mbox_priv *priv = to_sprd_mbox_priv(chan->mbox);
273ca27fc26SBaolin Wang
2749468ab84SOrson Zhai mutex_lock(&priv->lock);
2759468ab84SOrson Zhai if (--priv->refcnt == 0) {
276ca27fc26SBaolin Wang /* Disable inbox & outbox interrupt */
277ca27fc26SBaolin Wang writel(SPRD_INBOX_FIFO_IRQ_MASK, priv->inbox_base + SPRD_MBOX_IRQ_MSK);
278ca27fc26SBaolin Wang writel(SPRD_OUTBOX_FIFO_IRQ_MASK, priv->outbox_base + SPRD_MBOX_IRQ_MSK);
2796457f4cdSOrson Zhai
2806457f4cdSOrson Zhai if (priv->supp_base)
2816457f4cdSOrson Zhai writel(SPRD_OUTBOX_FIFO_IRQ_MASK,
2826457f4cdSOrson Zhai priv->supp_base + SPRD_MBOX_IRQ_MSK);
283ca27fc26SBaolin Wang }
2849468ab84SOrson Zhai mutex_unlock(&priv->lock);
2859468ab84SOrson Zhai }
286ca27fc26SBaolin Wang
287ca27fc26SBaolin Wang static const struct mbox_chan_ops sprd_mbox_ops = {
288ca27fc26SBaolin Wang .send_data = sprd_mbox_send_data,
289ca27fc26SBaolin Wang .flush = sprd_mbox_flush,
290ca27fc26SBaolin Wang .startup = sprd_mbox_startup,
291ca27fc26SBaolin Wang .shutdown = sprd_mbox_shutdown,
292ca27fc26SBaolin Wang };
293ca27fc26SBaolin Wang
sprd_mbox_disable(void * data)294ca27fc26SBaolin Wang static void sprd_mbox_disable(void *data)
295ca27fc26SBaolin Wang {
296ca27fc26SBaolin Wang struct sprd_mbox_priv *priv = data;
297ca27fc26SBaolin Wang
298ca27fc26SBaolin Wang clk_disable_unprepare(priv->clk);
299ca27fc26SBaolin Wang }
300ca27fc26SBaolin Wang
sprd_mbox_probe(struct platform_device * pdev)301ca27fc26SBaolin Wang static int sprd_mbox_probe(struct platform_device *pdev)
302ca27fc26SBaolin Wang {
303ca27fc26SBaolin Wang struct device *dev = &pdev->dev;
304ca27fc26SBaolin Wang struct sprd_mbox_priv *priv;
3056457f4cdSOrson Zhai int ret, inbox_irq, outbox_irq, supp_irq;
3066457f4cdSOrson Zhai unsigned long id, supp;
307ca27fc26SBaolin Wang
308ca27fc26SBaolin Wang priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
309ca27fc26SBaolin Wang if (!priv)
310ca27fc26SBaolin Wang return -ENOMEM;
311ca27fc26SBaolin Wang
312ca27fc26SBaolin Wang priv->dev = dev;
3139468ab84SOrson Zhai mutex_init(&priv->lock);
314ca27fc26SBaolin Wang
315ca27fc26SBaolin Wang /*
3166457f4cdSOrson Zhai * Unisoc mailbox uses an inbox to send messages to the target
3176457f4cdSOrson Zhai * core, and uses (an) outbox(es) to receive messages from other
3186457f4cdSOrson Zhai * cores.
319ca27fc26SBaolin Wang *
3206457f4cdSOrson Zhai * Thus in general the mailbox controller supplies 2 different
3216457f4cdSOrson Zhai * register addresses and IRQ numbers for inbox and outbox.
3226457f4cdSOrson Zhai *
3236457f4cdSOrson Zhai * If necessary, a supplementary inbox could be enabled optionally
3246457f4cdSOrson Zhai * with an independent FIFO and an extra interrupt.
325ca27fc26SBaolin Wang */
326ca27fc26SBaolin Wang priv->inbox_base = devm_platform_ioremap_resource(pdev, 0);
327ca27fc26SBaolin Wang if (IS_ERR(priv->inbox_base))
328ca27fc26SBaolin Wang return PTR_ERR(priv->inbox_base);
329ca27fc26SBaolin Wang
330ca27fc26SBaolin Wang priv->outbox_base = devm_platform_ioremap_resource(pdev, 1);
331ca27fc26SBaolin Wang if (IS_ERR(priv->outbox_base))
332ca27fc26SBaolin Wang return PTR_ERR(priv->outbox_base);
333ca27fc26SBaolin Wang
334ca27fc26SBaolin Wang priv->clk = devm_clk_get(dev, "enable");
335ca27fc26SBaolin Wang if (IS_ERR(priv->clk)) {
336ca27fc26SBaolin Wang dev_err(dev, "failed to get mailbox clock\n");
337ca27fc26SBaolin Wang return PTR_ERR(priv->clk);
338ca27fc26SBaolin Wang }
339ca27fc26SBaolin Wang
340ca27fc26SBaolin Wang ret = clk_prepare_enable(priv->clk);
341ca27fc26SBaolin Wang if (ret)
342ca27fc26SBaolin Wang return ret;
343ca27fc26SBaolin Wang
344ca27fc26SBaolin Wang ret = devm_add_action_or_reset(dev, sprd_mbox_disable, priv);
345ca27fc26SBaolin Wang if (ret) {
346ca27fc26SBaolin Wang dev_err(dev, "failed to add mailbox disable action\n");
347ca27fc26SBaolin Wang return ret;
348ca27fc26SBaolin Wang }
349ca27fc26SBaolin Wang
3506457f4cdSOrson Zhai inbox_irq = platform_get_irq_byname(pdev, "inbox");
351ca27fc26SBaolin Wang if (inbox_irq < 0)
352ca27fc26SBaolin Wang return inbox_irq;
353ca27fc26SBaolin Wang
354ca27fc26SBaolin Wang ret = devm_request_irq(dev, inbox_irq, sprd_mbox_inbox_isr,
355ca27fc26SBaolin Wang IRQF_NO_SUSPEND, dev_name(dev), priv);
356ca27fc26SBaolin Wang if (ret) {
357ca27fc26SBaolin Wang dev_err(dev, "failed to request inbox IRQ: %d\n", ret);
358ca27fc26SBaolin Wang return ret;
359ca27fc26SBaolin Wang }
360ca27fc26SBaolin Wang
3616457f4cdSOrson Zhai outbox_irq = platform_get_irq_byname(pdev, "outbox");
362ca27fc26SBaolin Wang if (outbox_irq < 0)
363ca27fc26SBaolin Wang return outbox_irq;
364ca27fc26SBaolin Wang
365ca27fc26SBaolin Wang ret = devm_request_irq(dev, outbox_irq, sprd_mbox_outbox_isr,
366ca27fc26SBaolin Wang IRQF_NO_SUSPEND, dev_name(dev), priv);
367ca27fc26SBaolin Wang if (ret) {
368ca27fc26SBaolin Wang dev_err(dev, "failed to request outbox IRQ: %d\n", ret);
369ca27fc26SBaolin Wang return ret;
370ca27fc26SBaolin Wang }
371ca27fc26SBaolin Wang
3726457f4cdSOrson Zhai /* Supplementary outbox IRQ is optional */
3736457f4cdSOrson Zhai supp_irq = platform_get_irq_byname(pdev, "supp-outbox");
3746457f4cdSOrson Zhai if (supp_irq > 0) {
3756457f4cdSOrson Zhai ret = devm_request_irq(dev, supp_irq, sprd_mbox_supp_isr,
3766457f4cdSOrson Zhai IRQF_NO_SUSPEND, dev_name(dev), priv);
3776457f4cdSOrson Zhai if (ret) {
3786457f4cdSOrson Zhai dev_err(dev, "failed to request outbox IRQ: %d\n", ret);
3796457f4cdSOrson Zhai return ret;
3806457f4cdSOrson Zhai }
3816457f4cdSOrson Zhai
3826457f4cdSOrson Zhai supp = (unsigned long) of_device_get_match_data(dev);
3836457f4cdSOrson Zhai if (!supp) {
3846457f4cdSOrson Zhai dev_err(dev, "no supplementary outbox specified\n");
3856457f4cdSOrson Zhai return -ENODEV;
3866457f4cdSOrson Zhai }
3876457f4cdSOrson Zhai priv->supp_base = priv->outbox_base + (SPRD_OUTBOX_BASE_SPAN * supp);
3886457f4cdSOrson Zhai }
3896457f4cdSOrson Zhai
390ca27fc26SBaolin Wang /* Get the default outbox FIFO depth */
391ca27fc26SBaolin Wang priv->outbox_fifo_depth =
392ca27fc26SBaolin Wang readl(priv->outbox_base + SPRD_MBOX_FIFO_DEPTH) + 1;
393ca27fc26SBaolin Wang priv->mbox.dev = dev;
394ca27fc26SBaolin Wang priv->mbox.chans = &priv->chan[0];
395ca27fc26SBaolin Wang priv->mbox.num_chans = SPRD_MBOX_CHAN_MAX;
396ca27fc26SBaolin Wang priv->mbox.ops = &sprd_mbox_ops;
397ca27fc26SBaolin Wang priv->mbox.txdone_irq = true;
398ca27fc26SBaolin Wang
399ca27fc26SBaolin Wang for (id = 0; id < SPRD_MBOX_CHAN_MAX; id++)
400ca27fc26SBaolin Wang priv->chan[id].con_priv = (void *)id;
401ca27fc26SBaolin Wang
402ca27fc26SBaolin Wang ret = devm_mbox_controller_register(dev, &priv->mbox);
403ca27fc26SBaolin Wang if (ret) {
404ca27fc26SBaolin Wang dev_err(dev, "failed to register mailbox: %d\n", ret);
405ca27fc26SBaolin Wang return ret;
406ca27fc26SBaolin Wang }
407ca27fc26SBaolin Wang
408ca27fc26SBaolin Wang return 0;
409ca27fc26SBaolin Wang }
410ca27fc26SBaolin Wang
411ca27fc26SBaolin Wang static const struct of_device_id sprd_mbox_of_match[] = {
4126457f4cdSOrson Zhai { .compatible = "sprd,sc9860-mailbox" },
4136457f4cdSOrson Zhai { .compatible = "sprd,sc9863a-mailbox",
4146457f4cdSOrson Zhai .data = (void *)SPRD_SUPP_INBOX_ID_SC9863A },
415ca27fc26SBaolin Wang { },
416ca27fc26SBaolin Wang };
417ca27fc26SBaolin Wang MODULE_DEVICE_TABLE(of, sprd_mbox_of_match);
418ca27fc26SBaolin Wang
419ca27fc26SBaolin Wang static struct platform_driver sprd_mbox_driver = {
420ca27fc26SBaolin Wang .driver = {
421ca27fc26SBaolin Wang .name = "sprd-mailbox",
422ca27fc26SBaolin Wang .of_match_table = sprd_mbox_of_match,
423ca27fc26SBaolin Wang },
424ca27fc26SBaolin Wang .probe = sprd_mbox_probe,
425ca27fc26SBaolin Wang };
426ca27fc26SBaolin Wang module_platform_driver(sprd_mbox_driver);
427ca27fc26SBaolin Wang
428ca27fc26SBaolin Wang MODULE_AUTHOR("Baolin Wang <baolin.wang@unisoc.com>");
429ca27fc26SBaolin Wang MODULE_DESCRIPTION("Spreadtrum mailbox driver");
430ca27fc26SBaolin Wang MODULE_LICENSE("GPL v2");
431