xref: /openbmc/linux/drivers/mailbox/qcom-ipcc.c (revision ee7da21a)
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
4  */
5 
6 #include <linux/bitfield.h>
7 #include <linux/interrupt.h>
8 #include <linux/irq.h>
9 #include <linux/irqdomain.h>
10 #include <linux/mailbox_controller.h>
11 #include <linux/module.h>
12 #include <linux/platform_device.h>
13 
14 #include <dt-bindings/mailbox/qcom-ipcc.h>
15 
16 #define IPCC_MBOX_MAX_CHAN		48
17 
18 /* IPCC Register offsets */
19 #define IPCC_REG_SEND_ID		0x0c
20 #define IPCC_REG_RECV_ID		0x10
21 #define IPCC_REG_RECV_SIGNAL_ENABLE	0x14
22 #define IPCC_REG_RECV_SIGNAL_DISABLE	0x18
23 #define IPCC_REG_RECV_SIGNAL_CLEAR	0x1c
24 #define IPCC_REG_CLIENT_CLEAR		0x38
25 
26 #define IPCC_SIGNAL_ID_MASK		GENMASK(15, 0)
27 #define IPCC_CLIENT_ID_MASK		GENMASK(31, 16)
28 
29 #define IPCC_NO_PENDING_IRQ		GENMASK(31, 0)
30 
31 /**
32  * struct qcom_ipcc_chan_info - Per-mailbox-channel info
33  * @client_id:	The client-id to which the interrupt has to be triggered
34  * @signal_id:	The signal-id to which the interrupt has to be triggered
35  */
36 struct qcom_ipcc_chan_info {
37 	u16 client_id;
38 	u16 signal_id;
39 };
40 
41 /**
42  * struct qcom_ipcc - Holder for the mailbox driver
43  * @dev:		Device associated with this instance
44  * @base:		Base address of the IPCC frame associated to APSS
45  * @irq_domain:		The irq_domain associated with this instance
46  * @chan:		The mailbox channels array
47  * @mchan:		The per-mailbox channel info array
48  * @mbox:		The mailbox controller
49  * @irq:		Summary irq
50  */
51 struct qcom_ipcc {
52 	struct device *dev;
53 	void __iomem *base;
54 	struct irq_domain *irq_domain;
55 	struct mbox_chan chan[IPCC_MBOX_MAX_CHAN];
56 	struct qcom_ipcc_chan_info mchan[IPCC_MBOX_MAX_CHAN];
57 	struct mbox_controller mbox;
58 	int irq;
59 };
60 
61 static inline struct qcom_ipcc *to_qcom_ipcc(struct mbox_controller *mbox)
62 {
63 	return container_of(mbox, struct qcom_ipcc, mbox);
64 }
65 
66 static inline u32 qcom_ipcc_get_hwirq(u16 client_id, u16 signal_id)
67 {
68 	return FIELD_PREP(IPCC_CLIENT_ID_MASK, client_id) |
69 	       FIELD_PREP(IPCC_SIGNAL_ID_MASK, signal_id);
70 }
71 
72 static irqreturn_t qcom_ipcc_irq_fn(int irq, void *data)
73 {
74 	struct qcom_ipcc *ipcc = data;
75 	u32 hwirq;
76 	int virq;
77 
78 	for (;;) {
79 		hwirq = readl(ipcc->base + IPCC_REG_RECV_ID);
80 		if (hwirq == IPCC_NO_PENDING_IRQ)
81 			break;
82 
83 		virq = irq_find_mapping(ipcc->irq_domain, hwirq);
84 		writel(hwirq, ipcc->base + IPCC_REG_RECV_SIGNAL_CLEAR);
85 		generic_handle_irq(virq);
86 	}
87 
88 	return IRQ_HANDLED;
89 }
90 
91 static void qcom_ipcc_mask_irq(struct irq_data *irqd)
92 {
93 	struct qcom_ipcc *ipcc = irq_data_get_irq_chip_data(irqd);
94 	irq_hw_number_t hwirq = irqd_to_hwirq(irqd);
95 
96 	writel(hwirq, ipcc->base + IPCC_REG_RECV_SIGNAL_DISABLE);
97 }
98 
99 static void qcom_ipcc_unmask_irq(struct irq_data *irqd)
100 {
101 	struct qcom_ipcc *ipcc = irq_data_get_irq_chip_data(irqd);
102 	irq_hw_number_t hwirq = irqd_to_hwirq(irqd);
103 
104 	writel(hwirq, ipcc->base + IPCC_REG_RECV_SIGNAL_ENABLE);
105 }
106 
107 static struct irq_chip qcom_ipcc_irq_chip = {
108 	.name = "ipcc",
109 	.irq_mask = qcom_ipcc_mask_irq,
110 	.irq_unmask = qcom_ipcc_unmask_irq,
111 	.flags = IRQCHIP_SKIP_SET_WAKE,
112 };
113 
114 static int qcom_ipcc_domain_map(struct irq_domain *d, unsigned int irq,
115 				irq_hw_number_t hw)
116 {
117 	struct qcom_ipcc *ipcc = d->host_data;
118 
119 	irq_set_chip_and_handler(irq, &qcom_ipcc_irq_chip, handle_level_irq);
120 	irq_set_chip_data(irq, ipcc);
121 	irq_set_noprobe(irq);
122 
123 	return 0;
124 }
125 
126 static int qcom_ipcc_domain_xlate(struct irq_domain *d,
127 				  struct device_node *node, const u32 *intspec,
128 				  unsigned int intsize,
129 				  unsigned long *out_hwirq,
130 				  unsigned int *out_type)
131 {
132 	if (intsize != 3)
133 		return -EINVAL;
134 
135 	*out_hwirq = qcom_ipcc_get_hwirq(intspec[0], intspec[1]);
136 	*out_type = intspec[2] & IRQ_TYPE_SENSE_MASK;
137 
138 	return 0;
139 }
140 
141 static const struct irq_domain_ops qcom_ipcc_irq_ops = {
142 	.map = qcom_ipcc_domain_map,
143 	.xlate = qcom_ipcc_domain_xlate,
144 };
145 
146 static int qcom_ipcc_mbox_send_data(struct mbox_chan *chan, void *data)
147 {
148 	struct qcom_ipcc *ipcc = to_qcom_ipcc(chan->mbox);
149 	struct qcom_ipcc_chan_info *mchan = chan->con_priv;
150 	u32 hwirq;
151 
152 	hwirq = qcom_ipcc_get_hwirq(mchan->client_id, mchan->signal_id);
153 	writel(hwirq, ipcc->base + IPCC_REG_SEND_ID);
154 
155 	return 0;
156 }
157 
158 static void qcom_ipcc_mbox_shutdown(struct mbox_chan *chan)
159 {
160 	chan->con_priv = NULL;
161 }
162 
163 static struct mbox_chan *qcom_ipcc_mbox_xlate(struct mbox_controller *mbox,
164 					const struct of_phandle_args *ph)
165 {
166 	struct qcom_ipcc *ipcc = to_qcom_ipcc(mbox);
167 	struct qcom_ipcc_chan_info *mchan;
168 	struct mbox_chan *chan;
169 	unsigned int i;
170 
171 	if (ph->args_count != 2)
172 		return ERR_PTR(-EINVAL);
173 
174 	for (i = 0; i < IPCC_MBOX_MAX_CHAN; i++) {
175 		chan = &ipcc->chan[i];
176 		if (!chan->con_priv) {
177 			mchan = &ipcc->mchan[i];
178 			mchan->client_id = ph->args[0];
179 			mchan->signal_id = ph->args[1];
180 			chan->con_priv = mchan;
181 			break;
182 		}
183 
184 		chan = NULL;
185 	}
186 
187 	return chan ?: ERR_PTR(-EBUSY);
188 }
189 
190 static const struct mbox_chan_ops ipcc_mbox_chan_ops = {
191 	.send_data = qcom_ipcc_mbox_send_data,
192 	.shutdown = qcom_ipcc_mbox_shutdown,
193 };
194 
195 static int qcom_ipcc_setup_mbox(struct qcom_ipcc *ipcc)
196 {
197 	struct mbox_controller *mbox;
198 	struct device *dev = ipcc->dev;
199 
200 	mbox = &ipcc->mbox;
201 	mbox->dev = dev;
202 	mbox->num_chans = IPCC_MBOX_MAX_CHAN;
203 	mbox->chans = ipcc->chan;
204 	mbox->ops = &ipcc_mbox_chan_ops;
205 	mbox->of_xlate = qcom_ipcc_mbox_xlate;
206 	mbox->txdone_irq = false;
207 	mbox->txdone_poll = false;
208 
209 	return devm_mbox_controller_register(dev, mbox);
210 }
211 
212 static int qcom_ipcc_probe(struct platform_device *pdev)
213 {
214 	struct qcom_ipcc *ipcc;
215 	int ret;
216 
217 	ipcc = devm_kzalloc(&pdev->dev, sizeof(*ipcc), GFP_KERNEL);
218 	if (!ipcc)
219 		return -ENOMEM;
220 
221 	ipcc->dev = &pdev->dev;
222 
223 	ipcc->base = devm_platform_ioremap_resource(pdev, 0);
224 	if (IS_ERR(ipcc->base))
225 		return PTR_ERR(ipcc->base);
226 
227 	ipcc->irq = platform_get_irq(pdev, 0);
228 	if (ipcc->irq < 0)
229 		return ipcc->irq;
230 
231 	ipcc->irq_domain = irq_domain_add_tree(pdev->dev.of_node,
232 					       &qcom_ipcc_irq_ops, ipcc);
233 	if (!ipcc->irq_domain)
234 		return -ENOMEM;
235 
236 	ret = qcom_ipcc_setup_mbox(ipcc);
237 	if (ret)
238 		goto err_mbox;
239 
240 	ret = devm_request_irq(&pdev->dev, ipcc->irq, qcom_ipcc_irq_fn,
241 			       IRQF_TRIGGER_HIGH, "ipcc", ipcc);
242 	if (ret < 0) {
243 		dev_err(&pdev->dev, "Failed to register the irq: %d\n", ret);
244 		goto err_mbox;
245 	}
246 
247 	enable_irq_wake(ipcc->irq);
248 	platform_set_drvdata(pdev, ipcc);
249 
250 	return 0;
251 
252 err_mbox:
253 	irq_domain_remove(ipcc->irq_domain);
254 
255 	return ret;
256 }
257 
258 static int qcom_ipcc_remove(struct platform_device *pdev)
259 {
260 	struct qcom_ipcc *ipcc = platform_get_drvdata(pdev);
261 
262 	disable_irq_wake(ipcc->irq);
263 	irq_domain_remove(ipcc->irq_domain);
264 
265 	return 0;
266 }
267 
268 static const struct of_device_id qcom_ipcc_of_match[] = {
269 	{ .compatible = "qcom,ipcc"},
270 	{}
271 };
272 MODULE_DEVICE_TABLE(of, qcom_ipcc_of_match);
273 
274 static struct platform_driver qcom_ipcc_driver = {
275 	.probe = qcom_ipcc_probe,
276 	.remove = qcom_ipcc_remove,
277 	.driver = {
278 		.name = "qcom-ipcc",
279 		.of_match_table = qcom_ipcc_of_match,
280 	},
281 };
282 
283 static int __init qcom_ipcc_init(void)
284 {
285 	return platform_driver_register(&qcom_ipcc_driver);
286 }
287 arch_initcall(qcom_ipcc_init);
288 
289 MODULE_AUTHOR("Venkata Narendra Kumar Gutta <vnkgutta@codeaurora.org>");
290 MODULE_AUTHOR("Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>");
291 MODULE_DESCRIPTION("Qualcomm Technologies, Inc. IPCC driver");
292 MODULE_LICENSE("GPL v2");
293