1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/bitfield.h> 7 #include <linux/interrupt.h> 8 #include <linux/irq.h> 9 #include <linux/irqdomain.h> 10 #include <linux/mailbox_controller.h> 11 #include <linux/module.h> 12 #include <linux/platform_device.h> 13 14 #include <dt-bindings/mailbox/qcom-ipcc.h> 15 16 /* IPCC Register offsets */ 17 #define IPCC_REG_SEND_ID 0x0c 18 #define IPCC_REG_RECV_ID 0x10 19 #define IPCC_REG_RECV_SIGNAL_ENABLE 0x14 20 #define IPCC_REG_RECV_SIGNAL_DISABLE 0x18 21 #define IPCC_REG_RECV_SIGNAL_CLEAR 0x1c 22 #define IPCC_REG_CLIENT_CLEAR 0x38 23 24 #define IPCC_SIGNAL_ID_MASK GENMASK(15, 0) 25 #define IPCC_CLIENT_ID_MASK GENMASK(31, 16) 26 27 #define IPCC_NO_PENDING_IRQ GENMASK(31, 0) 28 29 /** 30 * struct qcom_ipcc_chan_info - Per-mailbox-channel info 31 * @client_id: The client-id to which the interrupt has to be triggered 32 * @signal_id: The signal-id to which the interrupt has to be triggered 33 */ 34 struct qcom_ipcc_chan_info { 35 u16 client_id; 36 u16 signal_id; 37 }; 38 39 /** 40 * struct qcom_ipcc - Holder for the mailbox driver 41 * @dev: Device associated with this instance 42 * @base: Base address of the IPCC frame associated to APSS 43 * @irq_domain: The irq_domain associated with this instance 44 * @chan: The mailbox channels array 45 * @mchan: The per-mailbox channel info array 46 * @mbox: The mailbox controller 47 * @irq: Summary irq 48 */ 49 struct qcom_ipcc { 50 struct device *dev; 51 void __iomem *base; 52 struct irq_domain *irq_domain; 53 struct mbox_chan *chans; 54 struct qcom_ipcc_chan_info *mchan; 55 struct mbox_controller mbox; 56 int num_chans; 57 int irq; 58 }; 59 60 static inline struct qcom_ipcc *to_qcom_ipcc(struct mbox_controller *mbox) 61 { 62 return container_of(mbox, struct qcom_ipcc, mbox); 63 } 64 65 static inline u32 qcom_ipcc_get_hwirq(u16 client_id, u16 signal_id) 66 { 67 return FIELD_PREP(IPCC_CLIENT_ID_MASK, client_id) | 68 FIELD_PREP(IPCC_SIGNAL_ID_MASK, signal_id); 69 } 70 71 static irqreturn_t qcom_ipcc_irq_fn(int irq, void *data) 72 { 73 struct qcom_ipcc *ipcc = data; 74 u32 hwirq; 75 int virq; 76 77 for (;;) { 78 hwirq = readl(ipcc->base + IPCC_REG_RECV_ID); 79 if (hwirq == IPCC_NO_PENDING_IRQ) 80 break; 81 82 virq = irq_find_mapping(ipcc->irq_domain, hwirq); 83 writel(hwirq, ipcc->base + IPCC_REG_RECV_SIGNAL_CLEAR); 84 generic_handle_irq(virq); 85 } 86 87 return IRQ_HANDLED; 88 } 89 90 static void qcom_ipcc_mask_irq(struct irq_data *irqd) 91 { 92 struct qcom_ipcc *ipcc = irq_data_get_irq_chip_data(irqd); 93 irq_hw_number_t hwirq = irqd_to_hwirq(irqd); 94 95 writel(hwirq, ipcc->base + IPCC_REG_RECV_SIGNAL_DISABLE); 96 } 97 98 static void qcom_ipcc_unmask_irq(struct irq_data *irqd) 99 { 100 struct qcom_ipcc *ipcc = irq_data_get_irq_chip_data(irqd); 101 irq_hw_number_t hwirq = irqd_to_hwirq(irqd); 102 103 writel(hwirq, ipcc->base + IPCC_REG_RECV_SIGNAL_ENABLE); 104 } 105 106 static struct irq_chip qcom_ipcc_irq_chip = { 107 .name = "ipcc", 108 .irq_mask = qcom_ipcc_mask_irq, 109 .irq_unmask = qcom_ipcc_unmask_irq, 110 .flags = IRQCHIP_SKIP_SET_WAKE, 111 }; 112 113 static int qcom_ipcc_domain_map(struct irq_domain *d, unsigned int irq, 114 irq_hw_number_t hw) 115 { 116 struct qcom_ipcc *ipcc = d->host_data; 117 118 irq_set_chip_and_handler(irq, &qcom_ipcc_irq_chip, handle_level_irq); 119 irq_set_chip_data(irq, ipcc); 120 irq_set_noprobe(irq); 121 122 return 0; 123 } 124 125 static int qcom_ipcc_domain_xlate(struct irq_domain *d, 126 struct device_node *node, const u32 *intspec, 127 unsigned int intsize, 128 unsigned long *out_hwirq, 129 unsigned int *out_type) 130 { 131 if (intsize != 3) 132 return -EINVAL; 133 134 *out_hwirq = qcom_ipcc_get_hwirq(intspec[0], intspec[1]); 135 *out_type = intspec[2] & IRQ_TYPE_SENSE_MASK; 136 137 return 0; 138 } 139 140 static const struct irq_domain_ops qcom_ipcc_irq_ops = { 141 .map = qcom_ipcc_domain_map, 142 .xlate = qcom_ipcc_domain_xlate, 143 }; 144 145 static int qcom_ipcc_mbox_send_data(struct mbox_chan *chan, void *data) 146 { 147 struct qcom_ipcc *ipcc = to_qcom_ipcc(chan->mbox); 148 struct qcom_ipcc_chan_info *mchan = chan->con_priv; 149 u32 hwirq; 150 151 hwirq = qcom_ipcc_get_hwirq(mchan->client_id, mchan->signal_id); 152 writel(hwirq, ipcc->base + IPCC_REG_SEND_ID); 153 154 return 0; 155 } 156 157 static void qcom_ipcc_mbox_shutdown(struct mbox_chan *chan) 158 { 159 chan->con_priv = NULL; 160 } 161 162 static struct mbox_chan *qcom_ipcc_mbox_xlate(struct mbox_controller *mbox, 163 const struct of_phandle_args *ph) 164 { 165 struct qcom_ipcc *ipcc = to_qcom_ipcc(mbox); 166 struct qcom_ipcc_chan_info *mchan; 167 struct mbox_chan *chan; 168 struct device *dev; 169 int chan_id; 170 171 dev = ipcc->dev; 172 173 if (ph->args_count != 2) 174 return ERR_PTR(-EINVAL); 175 176 for (chan_id = 0; chan_id < mbox->num_chans; chan_id++) { 177 chan = &ipcc->chans[chan_id]; 178 mchan = chan->con_priv; 179 180 if (!mchan) 181 break; 182 else if (mchan->client_id == ph->args[0] && 183 mchan->signal_id == ph->args[1]) 184 return ERR_PTR(-EBUSY); 185 } 186 187 if (chan_id >= mbox->num_chans) 188 return ERR_PTR(-EBUSY); 189 190 mchan = devm_kzalloc(dev, sizeof(*mchan), GFP_KERNEL); 191 if (!mchan) 192 return ERR_PTR(-ENOMEM); 193 194 mchan->client_id = ph->args[0]; 195 mchan->signal_id = ph->args[1]; 196 chan->con_priv = mchan; 197 198 return chan; 199 } 200 201 static const struct mbox_chan_ops ipcc_mbox_chan_ops = { 202 .send_data = qcom_ipcc_mbox_send_data, 203 .shutdown = qcom_ipcc_mbox_shutdown, 204 }; 205 206 static int qcom_ipcc_setup_mbox(struct qcom_ipcc *ipcc, 207 struct device_node *controller_dn) 208 { 209 struct of_phandle_args curr_ph; 210 struct device_node *client_dn; 211 struct mbox_controller *mbox; 212 struct device *dev = ipcc->dev; 213 int i, j, ret; 214 215 /* 216 * Find out the number of clients interested in this mailbox 217 * and create channels accordingly. 218 */ 219 ipcc->num_chans = 0; 220 for_each_node_with_property(client_dn, "mboxes") { 221 if (!of_device_is_available(client_dn)) 222 continue; 223 i = of_count_phandle_with_args(client_dn, 224 "mboxes", "#mbox-cells"); 225 for (j = 0; j < i; j++) { 226 ret = of_parse_phandle_with_args(client_dn, "mboxes", 227 "#mbox-cells", j, &curr_ph); 228 of_node_put(curr_ph.np); 229 if (!ret && curr_ph.np == controller_dn) { 230 ipcc->num_chans++; 231 break; 232 } 233 } 234 } 235 236 /* If no clients are found, skip registering as a mbox controller */ 237 if (!ipcc->num_chans) 238 return 0; 239 240 ipcc->chans = devm_kcalloc(dev, ipcc->num_chans, 241 sizeof(struct mbox_chan), GFP_KERNEL); 242 if (!ipcc->chans) 243 return -ENOMEM; 244 245 mbox = &ipcc->mbox; 246 mbox->dev = dev; 247 mbox->num_chans = ipcc->num_chans; 248 mbox->chans = ipcc->chans; 249 mbox->ops = &ipcc_mbox_chan_ops; 250 mbox->of_xlate = qcom_ipcc_mbox_xlate; 251 mbox->txdone_irq = false; 252 mbox->txdone_poll = false; 253 254 return devm_mbox_controller_register(dev, mbox); 255 } 256 257 static int qcom_ipcc_probe(struct platform_device *pdev) 258 { 259 struct qcom_ipcc *ipcc; 260 static int id; 261 char *name; 262 int ret; 263 264 ipcc = devm_kzalloc(&pdev->dev, sizeof(*ipcc), GFP_KERNEL); 265 if (!ipcc) 266 return -ENOMEM; 267 268 ipcc->dev = &pdev->dev; 269 270 ipcc->base = devm_platform_ioremap_resource(pdev, 0); 271 if (IS_ERR(ipcc->base)) 272 return PTR_ERR(ipcc->base); 273 274 ipcc->irq = platform_get_irq(pdev, 0); 275 if (ipcc->irq < 0) 276 return ipcc->irq; 277 278 name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "ipcc_%d", id++); 279 if (!name) 280 return -ENOMEM; 281 282 ipcc->irq_domain = irq_domain_add_tree(pdev->dev.of_node, 283 &qcom_ipcc_irq_ops, ipcc); 284 if (!ipcc->irq_domain) 285 return -ENOMEM; 286 287 ret = qcom_ipcc_setup_mbox(ipcc, pdev->dev.of_node); 288 if (ret) 289 goto err_mbox; 290 291 ret = devm_request_irq(&pdev->dev, ipcc->irq, qcom_ipcc_irq_fn, 292 IRQF_TRIGGER_HIGH | IRQF_NO_SUSPEND, name, ipcc); 293 if (ret < 0) { 294 dev_err(&pdev->dev, "Failed to register the irq: %d\n", ret); 295 goto err_req_irq; 296 } 297 298 platform_set_drvdata(pdev, ipcc); 299 300 return 0; 301 302 err_req_irq: 303 if (ipcc->num_chans) 304 mbox_controller_unregister(&ipcc->mbox); 305 err_mbox: 306 irq_domain_remove(ipcc->irq_domain); 307 308 return ret; 309 } 310 311 static int qcom_ipcc_remove(struct platform_device *pdev) 312 { 313 struct qcom_ipcc *ipcc = platform_get_drvdata(pdev); 314 315 disable_irq_wake(ipcc->irq); 316 irq_domain_remove(ipcc->irq_domain); 317 318 return 0; 319 } 320 321 static const struct of_device_id qcom_ipcc_of_match[] = { 322 { .compatible = "qcom,ipcc"}, 323 {} 324 }; 325 MODULE_DEVICE_TABLE(of, qcom_ipcc_of_match); 326 327 static struct platform_driver qcom_ipcc_driver = { 328 .probe = qcom_ipcc_probe, 329 .remove = qcom_ipcc_remove, 330 .driver = { 331 .name = "qcom-ipcc", 332 .of_match_table = qcom_ipcc_of_match, 333 .suppress_bind_attrs = true, 334 }, 335 }; 336 337 static int __init qcom_ipcc_init(void) 338 { 339 return platform_driver_register(&qcom_ipcc_driver); 340 } 341 arch_initcall(qcom_ipcc_init); 342 343 MODULE_AUTHOR("Venkata Narendra Kumar Gutta <vnkgutta@codeaurora.org>"); 344 MODULE_AUTHOR("Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>"); 345 MODULE_DESCRIPTION("Qualcomm Technologies, Inc. IPCC driver"); 346 MODULE_LICENSE("GPL v2"); 347