1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * OMAP mailbox driver 4 * 5 * Copyright (C) 2006-2009 Nokia Corporation. All rights reserved. 6 * Copyright (C) 2013-2016 Texas Instruments Incorporated - http://www.ti.com 7 * 8 * Contact: Hiroshi DOYU <Hiroshi.DOYU@nokia.com> 9 * Suman Anna <s-anna@ti.com> 10 */ 11 12 #include <linux/interrupt.h> 13 #include <linux/spinlock.h> 14 #include <linux/mutex.h> 15 #include <linux/slab.h> 16 #include <linux/kfifo.h> 17 #include <linux/err.h> 18 #include <linux/module.h> 19 #include <linux/of_device.h> 20 #include <linux/platform_device.h> 21 #include <linux/pm_runtime.h> 22 #include <linux/omap-mailbox.h> 23 #include <linux/mailbox_controller.h> 24 #include <linux/mailbox_client.h> 25 26 #include "mailbox.h" 27 28 #define MAILBOX_REVISION 0x000 29 #define MAILBOX_MESSAGE(m) (0x040 + 4 * (m)) 30 #define MAILBOX_FIFOSTATUS(m) (0x080 + 4 * (m)) 31 #define MAILBOX_MSGSTATUS(m) (0x0c0 + 4 * (m)) 32 33 #define OMAP2_MAILBOX_IRQSTATUS(u) (0x100 + 8 * (u)) 34 #define OMAP2_MAILBOX_IRQENABLE(u) (0x104 + 8 * (u)) 35 36 #define OMAP4_MAILBOX_IRQSTATUS(u) (0x104 + 0x10 * (u)) 37 #define OMAP4_MAILBOX_IRQENABLE(u) (0x108 + 0x10 * (u)) 38 #define OMAP4_MAILBOX_IRQENABLE_CLR(u) (0x10c + 0x10 * (u)) 39 40 #define MAILBOX_IRQSTATUS(type, u) (type ? OMAP4_MAILBOX_IRQSTATUS(u) : \ 41 OMAP2_MAILBOX_IRQSTATUS(u)) 42 #define MAILBOX_IRQENABLE(type, u) (type ? OMAP4_MAILBOX_IRQENABLE(u) : \ 43 OMAP2_MAILBOX_IRQENABLE(u)) 44 #define MAILBOX_IRQDISABLE(type, u) (type ? OMAP4_MAILBOX_IRQENABLE_CLR(u) \ 45 : OMAP2_MAILBOX_IRQENABLE(u)) 46 47 #define MAILBOX_IRQ_NEWMSG(m) (1 << (2 * (m))) 48 #define MAILBOX_IRQ_NOTFULL(m) (1 << (2 * (m) + 1)) 49 50 /* Interrupt register configuration types */ 51 #define MBOX_INTR_CFG_TYPE1 0 52 #define MBOX_INTR_CFG_TYPE2 1 53 54 struct omap_mbox_fifo { 55 unsigned long msg; 56 unsigned long fifo_stat; 57 unsigned long msg_stat; 58 unsigned long irqenable; 59 unsigned long irqstatus; 60 unsigned long irqdisable; 61 u32 intr_bit; 62 }; 63 64 struct omap_mbox_queue { 65 spinlock_t lock; 66 struct kfifo fifo; 67 struct work_struct work; 68 struct omap_mbox *mbox; 69 bool full; 70 }; 71 72 struct omap_mbox_match_data { 73 u32 intr_type; 74 }; 75 76 struct omap_mbox_device { 77 struct device *dev; 78 struct mutex cfg_lock; 79 void __iomem *mbox_base; 80 u32 *irq_ctx; 81 u32 num_users; 82 u32 num_fifos; 83 u32 intr_type; 84 struct omap_mbox **mboxes; 85 struct mbox_controller controller; 86 struct list_head elem; 87 }; 88 89 struct omap_mbox_fifo_info { 90 int tx_id; 91 int tx_usr; 92 int tx_irq; 93 94 int rx_id; 95 int rx_usr; 96 int rx_irq; 97 98 const char *name; 99 bool send_no_irq; 100 }; 101 102 struct omap_mbox { 103 const char *name; 104 int irq; 105 struct omap_mbox_queue *rxq; 106 struct device *dev; 107 struct omap_mbox_device *parent; 108 struct omap_mbox_fifo tx_fifo; 109 struct omap_mbox_fifo rx_fifo; 110 u32 intr_type; 111 struct mbox_chan *chan; 112 bool send_no_irq; 113 }; 114 115 /* global variables for the mailbox devices */ 116 static DEFINE_MUTEX(omap_mbox_devices_lock); 117 static LIST_HEAD(omap_mbox_devices); 118 119 static unsigned int mbox_kfifo_size = CONFIG_OMAP_MBOX_KFIFO_SIZE; 120 module_param(mbox_kfifo_size, uint, S_IRUGO); 121 MODULE_PARM_DESC(mbox_kfifo_size, "Size of omap's mailbox kfifo (bytes)"); 122 123 static struct omap_mbox *mbox_chan_to_omap_mbox(struct mbox_chan *chan) 124 { 125 if (!chan || !chan->con_priv) 126 return NULL; 127 128 return (struct omap_mbox *)chan->con_priv; 129 } 130 131 static inline 132 unsigned int mbox_read_reg(struct omap_mbox_device *mdev, size_t ofs) 133 { 134 return __raw_readl(mdev->mbox_base + ofs); 135 } 136 137 static inline 138 void mbox_write_reg(struct omap_mbox_device *mdev, u32 val, size_t ofs) 139 { 140 __raw_writel(val, mdev->mbox_base + ofs); 141 } 142 143 /* Mailbox FIFO handle functions */ 144 static mbox_msg_t mbox_fifo_read(struct omap_mbox *mbox) 145 { 146 struct omap_mbox_fifo *fifo = &mbox->rx_fifo; 147 148 return (mbox_msg_t)mbox_read_reg(mbox->parent, fifo->msg); 149 } 150 151 static void mbox_fifo_write(struct omap_mbox *mbox, mbox_msg_t msg) 152 { 153 struct omap_mbox_fifo *fifo = &mbox->tx_fifo; 154 155 mbox_write_reg(mbox->parent, msg, fifo->msg); 156 } 157 158 static int mbox_fifo_empty(struct omap_mbox *mbox) 159 { 160 struct omap_mbox_fifo *fifo = &mbox->rx_fifo; 161 162 return (mbox_read_reg(mbox->parent, fifo->msg_stat) == 0); 163 } 164 165 static int mbox_fifo_full(struct omap_mbox *mbox) 166 { 167 struct omap_mbox_fifo *fifo = &mbox->tx_fifo; 168 169 return mbox_read_reg(mbox->parent, fifo->fifo_stat); 170 } 171 172 /* Mailbox IRQ handle functions */ 173 static void ack_mbox_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq) 174 { 175 struct omap_mbox_fifo *fifo = (irq == IRQ_TX) ? 176 &mbox->tx_fifo : &mbox->rx_fifo; 177 u32 bit = fifo->intr_bit; 178 u32 irqstatus = fifo->irqstatus; 179 180 mbox_write_reg(mbox->parent, bit, irqstatus); 181 182 /* Flush posted write for irq status to avoid spurious interrupts */ 183 mbox_read_reg(mbox->parent, irqstatus); 184 } 185 186 static int is_mbox_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq) 187 { 188 struct omap_mbox_fifo *fifo = (irq == IRQ_TX) ? 189 &mbox->tx_fifo : &mbox->rx_fifo; 190 u32 bit = fifo->intr_bit; 191 u32 irqenable = fifo->irqenable; 192 u32 irqstatus = fifo->irqstatus; 193 194 u32 enable = mbox_read_reg(mbox->parent, irqenable); 195 u32 status = mbox_read_reg(mbox->parent, irqstatus); 196 197 return (int)(enable & status & bit); 198 } 199 200 static void _omap_mbox_enable_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq) 201 { 202 u32 l; 203 struct omap_mbox_fifo *fifo = (irq == IRQ_TX) ? 204 &mbox->tx_fifo : &mbox->rx_fifo; 205 u32 bit = fifo->intr_bit; 206 u32 irqenable = fifo->irqenable; 207 208 l = mbox_read_reg(mbox->parent, irqenable); 209 l |= bit; 210 mbox_write_reg(mbox->parent, l, irqenable); 211 } 212 213 static void _omap_mbox_disable_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq) 214 { 215 struct omap_mbox_fifo *fifo = (irq == IRQ_TX) ? 216 &mbox->tx_fifo : &mbox->rx_fifo; 217 u32 bit = fifo->intr_bit; 218 u32 irqdisable = fifo->irqdisable; 219 220 /* 221 * Read and update the interrupt configuration register for pre-OMAP4. 222 * OMAP4 and later SoCs have a dedicated interrupt disabling register. 223 */ 224 if (!mbox->intr_type) 225 bit = mbox_read_reg(mbox->parent, irqdisable) & ~bit; 226 227 mbox_write_reg(mbox->parent, bit, irqdisable); 228 } 229 230 void omap_mbox_enable_irq(struct mbox_chan *chan, omap_mbox_irq_t irq) 231 { 232 struct omap_mbox *mbox = mbox_chan_to_omap_mbox(chan); 233 234 if (WARN_ON(!mbox)) 235 return; 236 237 _omap_mbox_enable_irq(mbox, irq); 238 } 239 EXPORT_SYMBOL(omap_mbox_enable_irq); 240 241 void omap_mbox_disable_irq(struct mbox_chan *chan, omap_mbox_irq_t irq) 242 { 243 struct omap_mbox *mbox = mbox_chan_to_omap_mbox(chan); 244 245 if (WARN_ON(!mbox)) 246 return; 247 248 _omap_mbox_disable_irq(mbox, irq); 249 } 250 EXPORT_SYMBOL(omap_mbox_disable_irq); 251 252 /* 253 * Message receiver(workqueue) 254 */ 255 static void mbox_rx_work(struct work_struct *work) 256 { 257 struct omap_mbox_queue *mq = 258 container_of(work, struct omap_mbox_queue, work); 259 mbox_msg_t msg; 260 int len; 261 262 while (kfifo_len(&mq->fifo) >= sizeof(msg)) { 263 len = kfifo_out(&mq->fifo, (unsigned char *)&msg, sizeof(msg)); 264 WARN_ON(len != sizeof(msg)); 265 266 mbox_chan_received_data(mq->mbox->chan, (void *)msg); 267 spin_lock_irq(&mq->lock); 268 if (mq->full) { 269 mq->full = false; 270 _omap_mbox_enable_irq(mq->mbox, IRQ_RX); 271 } 272 spin_unlock_irq(&mq->lock); 273 } 274 } 275 276 /* 277 * Mailbox interrupt handler 278 */ 279 static void __mbox_tx_interrupt(struct omap_mbox *mbox) 280 { 281 _omap_mbox_disable_irq(mbox, IRQ_TX); 282 ack_mbox_irq(mbox, IRQ_TX); 283 mbox_chan_txdone(mbox->chan, 0); 284 } 285 286 static void __mbox_rx_interrupt(struct omap_mbox *mbox) 287 { 288 struct omap_mbox_queue *mq = mbox->rxq; 289 mbox_msg_t msg; 290 int len; 291 292 while (!mbox_fifo_empty(mbox)) { 293 if (unlikely(kfifo_avail(&mq->fifo) < sizeof(msg))) { 294 _omap_mbox_disable_irq(mbox, IRQ_RX); 295 mq->full = true; 296 goto nomem; 297 } 298 299 msg = mbox_fifo_read(mbox); 300 301 len = kfifo_in(&mq->fifo, (unsigned char *)&msg, sizeof(msg)); 302 WARN_ON(len != sizeof(msg)); 303 } 304 305 /* no more messages in the fifo. clear IRQ source. */ 306 ack_mbox_irq(mbox, IRQ_RX); 307 nomem: 308 schedule_work(&mbox->rxq->work); 309 } 310 311 static irqreturn_t mbox_interrupt(int irq, void *p) 312 { 313 struct omap_mbox *mbox = p; 314 315 if (is_mbox_irq(mbox, IRQ_TX)) 316 __mbox_tx_interrupt(mbox); 317 318 if (is_mbox_irq(mbox, IRQ_RX)) 319 __mbox_rx_interrupt(mbox); 320 321 return IRQ_HANDLED; 322 } 323 324 static struct omap_mbox_queue *mbox_queue_alloc(struct omap_mbox *mbox, 325 void (*work)(struct work_struct *)) 326 { 327 struct omap_mbox_queue *mq; 328 329 if (!work) 330 return NULL; 331 332 mq = kzalloc(sizeof(*mq), GFP_KERNEL); 333 if (!mq) 334 return NULL; 335 336 spin_lock_init(&mq->lock); 337 338 if (kfifo_alloc(&mq->fifo, mbox_kfifo_size, GFP_KERNEL)) 339 goto error; 340 341 INIT_WORK(&mq->work, work); 342 return mq; 343 344 error: 345 kfree(mq); 346 return NULL; 347 } 348 349 static void mbox_queue_free(struct omap_mbox_queue *q) 350 { 351 kfifo_free(&q->fifo); 352 kfree(q); 353 } 354 355 static int omap_mbox_startup(struct omap_mbox *mbox) 356 { 357 int ret = 0; 358 struct omap_mbox_queue *mq; 359 360 mq = mbox_queue_alloc(mbox, mbox_rx_work); 361 if (!mq) 362 return -ENOMEM; 363 mbox->rxq = mq; 364 mq->mbox = mbox; 365 366 ret = request_irq(mbox->irq, mbox_interrupt, IRQF_SHARED, 367 mbox->name, mbox); 368 if (unlikely(ret)) { 369 pr_err("failed to register mailbox interrupt:%d\n", ret); 370 goto fail_request_irq; 371 } 372 373 if (mbox->send_no_irq) 374 mbox->chan->txdone_method = TXDONE_BY_ACK; 375 376 _omap_mbox_enable_irq(mbox, IRQ_RX); 377 378 return 0; 379 380 fail_request_irq: 381 mbox_queue_free(mbox->rxq); 382 return ret; 383 } 384 385 static void omap_mbox_fini(struct omap_mbox *mbox) 386 { 387 _omap_mbox_disable_irq(mbox, IRQ_RX); 388 free_irq(mbox->irq, mbox); 389 flush_work(&mbox->rxq->work); 390 mbox_queue_free(mbox->rxq); 391 } 392 393 static struct omap_mbox *omap_mbox_device_find(struct omap_mbox_device *mdev, 394 const char *mbox_name) 395 { 396 struct omap_mbox *_mbox, *mbox = NULL; 397 struct omap_mbox **mboxes = mdev->mboxes; 398 int i; 399 400 if (!mboxes) 401 return NULL; 402 403 for (i = 0; (_mbox = mboxes[i]); i++) { 404 if (!strcmp(_mbox->name, mbox_name)) { 405 mbox = _mbox; 406 break; 407 } 408 } 409 return mbox; 410 } 411 412 struct mbox_chan *omap_mbox_request_channel(struct mbox_client *cl, 413 const char *chan_name) 414 { 415 struct device *dev = cl->dev; 416 struct omap_mbox *mbox = NULL; 417 struct omap_mbox_device *mdev; 418 struct mbox_chan *chan; 419 unsigned long flags; 420 int ret; 421 422 if (!dev) 423 return ERR_PTR(-ENODEV); 424 425 if (dev->of_node) { 426 pr_err("%s: please use mbox_request_channel(), this API is supported only for OMAP non-DT usage\n", 427 __func__); 428 return ERR_PTR(-ENODEV); 429 } 430 431 mutex_lock(&omap_mbox_devices_lock); 432 list_for_each_entry(mdev, &omap_mbox_devices, elem) { 433 mbox = omap_mbox_device_find(mdev, chan_name); 434 if (mbox) 435 break; 436 } 437 mutex_unlock(&omap_mbox_devices_lock); 438 439 if (!mbox || !mbox->chan) 440 return ERR_PTR(-ENOENT); 441 442 chan = mbox->chan; 443 spin_lock_irqsave(&chan->lock, flags); 444 chan->msg_free = 0; 445 chan->msg_count = 0; 446 chan->active_req = NULL; 447 chan->cl = cl; 448 init_completion(&chan->tx_complete); 449 spin_unlock_irqrestore(&chan->lock, flags); 450 451 ret = chan->mbox->ops->startup(chan); 452 if (ret) { 453 pr_err("Unable to startup the chan (%d)\n", ret); 454 mbox_free_channel(chan); 455 chan = ERR_PTR(ret); 456 } 457 458 return chan; 459 } 460 EXPORT_SYMBOL(omap_mbox_request_channel); 461 462 static struct class omap_mbox_class = { .name = "mbox", }; 463 464 static int omap_mbox_register(struct omap_mbox_device *mdev) 465 { 466 int ret; 467 int i; 468 struct omap_mbox **mboxes; 469 470 if (!mdev || !mdev->mboxes) 471 return -EINVAL; 472 473 mboxes = mdev->mboxes; 474 for (i = 0; mboxes[i]; i++) { 475 struct omap_mbox *mbox = mboxes[i]; 476 477 mbox->dev = device_create(&omap_mbox_class, mdev->dev, 478 0, mbox, "%s", mbox->name); 479 if (IS_ERR(mbox->dev)) { 480 ret = PTR_ERR(mbox->dev); 481 goto err_out; 482 } 483 } 484 485 mutex_lock(&omap_mbox_devices_lock); 486 list_add(&mdev->elem, &omap_mbox_devices); 487 mutex_unlock(&omap_mbox_devices_lock); 488 489 ret = devm_mbox_controller_register(mdev->dev, &mdev->controller); 490 491 err_out: 492 if (ret) { 493 while (i--) 494 device_unregister(mboxes[i]->dev); 495 } 496 return ret; 497 } 498 499 static int omap_mbox_unregister(struct omap_mbox_device *mdev) 500 { 501 int i; 502 struct omap_mbox **mboxes; 503 504 if (!mdev || !mdev->mboxes) 505 return -EINVAL; 506 507 mutex_lock(&omap_mbox_devices_lock); 508 list_del(&mdev->elem); 509 mutex_unlock(&omap_mbox_devices_lock); 510 511 mboxes = mdev->mboxes; 512 for (i = 0; mboxes[i]; i++) 513 device_unregister(mboxes[i]->dev); 514 return 0; 515 } 516 517 static int omap_mbox_chan_startup(struct mbox_chan *chan) 518 { 519 struct omap_mbox *mbox = mbox_chan_to_omap_mbox(chan); 520 struct omap_mbox_device *mdev = mbox->parent; 521 int ret = 0; 522 523 mutex_lock(&mdev->cfg_lock); 524 pm_runtime_get_sync(mdev->dev); 525 ret = omap_mbox_startup(mbox); 526 if (ret) 527 pm_runtime_put_sync(mdev->dev); 528 mutex_unlock(&mdev->cfg_lock); 529 return ret; 530 } 531 532 static void omap_mbox_chan_shutdown(struct mbox_chan *chan) 533 { 534 struct omap_mbox *mbox = mbox_chan_to_omap_mbox(chan); 535 struct omap_mbox_device *mdev = mbox->parent; 536 537 mutex_lock(&mdev->cfg_lock); 538 omap_mbox_fini(mbox); 539 pm_runtime_put_sync(mdev->dev); 540 mutex_unlock(&mdev->cfg_lock); 541 } 542 543 static int omap_mbox_chan_send_noirq(struct omap_mbox *mbox, void *data) 544 { 545 int ret = -EBUSY; 546 547 if (!mbox_fifo_full(mbox)) { 548 _omap_mbox_enable_irq(mbox, IRQ_RX); 549 mbox_fifo_write(mbox, (mbox_msg_t)data); 550 ret = 0; 551 _omap_mbox_disable_irq(mbox, IRQ_RX); 552 553 /* we must read and ack the interrupt directly from here */ 554 mbox_fifo_read(mbox); 555 ack_mbox_irq(mbox, IRQ_RX); 556 } 557 558 return ret; 559 } 560 561 static int omap_mbox_chan_send(struct omap_mbox *mbox, void *data) 562 { 563 int ret = -EBUSY; 564 565 if (!mbox_fifo_full(mbox)) { 566 mbox_fifo_write(mbox, (mbox_msg_t)data); 567 ret = 0; 568 } 569 570 /* always enable the interrupt */ 571 _omap_mbox_enable_irq(mbox, IRQ_TX); 572 return ret; 573 } 574 575 static int omap_mbox_chan_send_data(struct mbox_chan *chan, void *data) 576 { 577 struct omap_mbox *mbox = mbox_chan_to_omap_mbox(chan); 578 int ret; 579 580 if (!mbox) 581 return -EINVAL; 582 583 if (mbox->send_no_irq) 584 ret = omap_mbox_chan_send_noirq(mbox, data); 585 else 586 ret = omap_mbox_chan_send(mbox, data); 587 588 return ret; 589 } 590 591 static const struct mbox_chan_ops omap_mbox_chan_ops = { 592 .startup = omap_mbox_chan_startup, 593 .send_data = omap_mbox_chan_send_data, 594 .shutdown = omap_mbox_chan_shutdown, 595 }; 596 597 #ifdef CONFIG_PM_SLEEP 598 static int omap_mbox_suspend(struct device *dev) 599 { 600 struct omap_mbox_device *mdev = dev_get_drvdata(dev); 601 u32 usr, fifo, reg; 602 603 if (pm_runtime_status_suspended(dev)) 604 return 0; 605 606 for (fifo = 0; fifo < mdev->num_fifos; fifo++) { 607 if (mbox_read_reg(mdev, MAILBOX_MSGSTATUS(fifo))) { 608 dev_err(mdev->dev, "fifo %d has unexpected unread messages\n", 609 fifo); 610 return -EBUSY; 611 } 612 } 613 614 for (usr = 0; usr < mdev->num_users; usr++) { 615 reg = MAILBOX_IRQENABLE(mdev->intr_type, usr); 616 mdev->irq_ctx[usr] = mbox_read_reg(mdev, reg); 617 } 618 619 return 0; 620 } 621 622 static int omap_mbox_resume(struct device *dev) 623 { 624 struct omap_mbox_device *mdev = dev_get_drvdata(dev); 625 u32 usr, reg; 626 627 if (pm_runtime_status_suspended(dev)) 628 return 0; 629 630 for (usr = 0; usr < mdev->num_users; usr++) { 631 reg = MAILBOX_IRQENABLE(mdev->intr_type, usr); 632 mbox_write_reg(mdev, mdev->irq_ctx[usr], reg); 633 } 634 635 return 0; 636 } 637 #endif 638 639 static const struct dev_pm_ops omap_mbox_pm_ops = { 640 SET_SYSTEM_SLEEP_PM_OPS(omap_mbox_suspend, omap_mbox_resume) 641 }; 642 643 static const struct omap_mbox_match_data omap2_data = { MBOX_INTR_CFG_TYPE1 }; 644 static const struct omap_mbox_match_data omap4_data = { MBOX_INTR_CFG_TYPE2 }; 645 646 static const struct of_device_id omap_mailbox_of_match[] = { 647 { 648 .compatible = "ti,omap2-mailbox", 649 .data = &omap2_data, 650 }, 651 { 652 .compatible = "ti,omap3-mailbox", 653 .data = &omap2_data, 654 }, 655 { 656 .compatible = "ti,omap4-mailbox", 657 .data = &omap4_data, 658 }, 659 { 660 /* end */ 661 }, 662 }; 663 MODULE_DEVICE_TABLE(of, omap_mailbox_of_match); 664 665 static struct mbox_chan *omap_mbox_of_xlate(struct mbox_controller *controller, 666 const struct of_phandle_args *sp) 667 { 668 phandle phandle = sp->args[0]; 669 struct device_node *node; 670 struct omap_mbox_device *mdev; 671 struct omap_mbox *mbox; 672 673 mdev = container_of(controller, struct omap_mbox_device, controller); 674 if (WARN_ON(!mdev)) 675 return ERR_PTR(-EINVAL); 676 677 node = of_find_node_by_phandle(phandle); 678 if (!node) { 679 pr_err("%s: could not find node phandle 0x%x\n", 680 __func__, phandle); 681 return ERR_PTR(-ENODEV); 682 } 683 684 mbox = omap_mbox_device_find(mdev, node->name); 685 of_node_put(node); 686 return mbox ? mbox->chan : ERR_PTR(-ENOENT); 687 } 688 689 static int omap_mbox_probe(struct platform_device *pdev) 690 { 691 struct resource *mem; 692 int ret; 693 struct mbox_chan *chnls; 694 struct omap_mbox **list, *mbox, *mboxblk; 695 struct omap_mbox_fifo_info *finfo, *finfoblk; 696 struct omap_mbox_device *mdev; 697 struct omap_mbox_fifo *fifo; 698 struct device_node *node = pdev->dev.of_node; 699 struct device_node *child; 700 const struct omap_mbox_match_data *match_data; 701 u32 intr_type, info_count; 702 u32 num_users, num_fifos; 703 u32 tmp[3]; 704 u32 l; 705 int i; 706 707 if (!node) { 708 pr_err("%s: only DT-based devices are supported\n", __func__); 709 return -ENODEV; 710 } 711 712 match_data = of_device_get_match_data(&pdev->dev); 713 if (!match_data) 714 return -ENODEV; 715 intr_type = match_data->intr_type; 716 717 if (of_property_read_u32(node, "ti,mbox-num-users", &num_users)) 718 return -ENODEV; 719 720 if (of_property_read_u32(node, "ti,mbox-num-fifos", &num_fifos)) 721 return -ENODEV; 722 723 info_count = of_get_available_child_count(node); 724 if (!info_count) { 725 dev_err(&pdev->dev, "no available mbox devices found\n"); 726 return -ENODEV; 727 } 728 729 finfoblk = devm_kcalloc(&pdev->dev, info_count, sizeof(*finfoblk), 730 GFP_KERNEL); 731 if (!finfoblk) 732 return -ENOMEM; 733 734 finfo = finfoblk; 735 child = NULL; 736 for (i = 0; i < info_count; i++, finfo++) { 737 child = of_get_next_available_child(node, child); 738 ret = of_property_read_u32_array(child, "ti,mbox-tx", tmp, 739 ARRAY_SIZE(tmp)); 740 if (ret) 741 return ret; 742 finfo->tx_id = tmp[0]; 743 finfo->tx_irq = tmp[1]; 744 finfo->tx_usr = tmp[2]; 745 746 ret = of_property_read_u32_array(child, "ti,mbox-rx", tmp, 747 ARRAY_SIZE(tmp)); 748 if (ret) 749 return ret; 750 finfo->rx_id = tmp[0]; 751 finfo->rx_irq = tmp[1]; 752 finfo->rx_usr = tmp[2]; 753 754 finfo->name = child->name; 755 756 if (of_find_property(child, "ti,mbox-send-noirq", NULL)) 757 finfo->send_no_irq = true; 758 759 if (finfo->tx_id >= num_fifos || finfo->rx_id >= num_fifos || 760 finfo->tx_usr >= num_users || finfo->rx_usr >= num_users) 761 return -EINVAL; 762 } 763 764 mdev = devm_kzalloc(&pdev->dev, sizeof(*mdev), GFP_KERNEL); 765 if (!mdev) 766 return -ENOMEM; 767 768 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 769 mdev->mbox_base = devm_ioremap_resource(&pdev->dev, mem); 770 if (IS_ERR(mdev->mbox_base)) 771 return PTR_ERR(mdev->mbox_base); 772 773 mdev->irq_ctx = devm_kcalloc(&pdev->dev, num_users, sizeof(u32), 774 GFP_KERNEL); 775 if (!mdev->irq_ctx) 776 return -ENOMEM; 777 778 /* allocate one extra for marking end of list */ 779 list = devm_kcalloc(&pdev->dev, info_count + 1, sizeof(*list), 780 GFP_KERNEL); 781 if (!list) 782 return -ENOMEM; 783 784 chnls = devm_kcalloc(&pdev->dev, info_count + 1, sizeof(*chnls), 785 GFP_KERNEL); 786 if (!chnls) 787 return -ENOMEM; 788 789 mboxblk = devm_kcalloc(&pdev->dev, info_count, sizeof(*mbox), 790 GFP_KERNEL); 791 if (!mboxblk) 792 return -ENOMEM; 793 794 mbox = mboxblk; 795 finfo = finfoblk; 796 for (i = 0; i < info_count; i++, finfo++) { 797 fifo = &mbox->tx_fifo; 798 fifo->msg = MAILBOX_MESSAGE(finfo->tx_id); 799 fifo->fifo_stat = MAILBOX_FIFOSTATUS(finfo->tx_id); 800 fifo->intr_bit = MAILBOX_IRQ_NOTFULL(finfo->tx_id); 801 fifo->irqenable = MAILBOX_IRQENABLE(intr_type, finfo->tx_usr); 802 fifo->irqstatus = MAILBOX_IRQSTATUS(intr_type, finfo->tx_usr); 803 fifo->irqdisable = MAILBOX_IRQDISABLE(intr_type, finfo->tx_usr); 804 805 fifo = &mbox->rx_fifo; 806 fifo->msg = MAILBOX_MESSAGE(finfo->rx_id); 807 fifo->msg_stat = MAILBOX_MSGSTATUS(finfo->rx_id); 808 fifo->intr_bit = MAILBOX_IRQ_NEWMSG(finfo->rx_id); 809 fifo->irqenable = MAILBOX_IRQENABLE(intr_type, finfo->rx_usr); 810 fifo->irqstatus = MAILBOX_IRQSTATUS(intr_type, finfo->rx_usr); 811 fifo->irqdisable = MAILBOX_IRQDISABLE(intr_type, finfo->rx_usr); 812 813 mbox->send_no_irq = finfo->send_no_irq; 814 mbox->intr_type = intr_type; 815 816 mbox->parent = mdev; 817 mbox->name = finfo->name; 818 mbox->irq = platform_get_irq(pdev, finfo->tx_irq); 819 if (mbox->irq < 0) 820 return mbox->irq; 821 mbox->chan = &chnls[i]; 822 chnls[i].con_priv = mbox; 823 list[i] = mbox++; 824 } 825 826 mutex_init(&mdev->cfg_lock); 827 mdev->dev = &pdev->dev; 828 mdev->num_users = num_users; 829 mdev->num_fifos = num_fifos; 830 mdev->intr_type = intr_type; 831 mdev->mboxes = list; 832 833 /* OMAP does not have a Tx-Done IRQ, but rather a Tx-Ready IRQ */ 834 mdev->controller.txdone_irq = true; 835 mdev->controller.dev = mdev->dev; 836 mdev->controller.ops = &omap_mbox_chan_ops; 837 mdev->controller.chans = chnls; 838 mdev->controller.num_chans = info_count; 839 mdev->controller.of_xlate = omap_mbox_of_xlate; 840 ret = omap_mbox_register(mdev); 841 if (ret) 842 return ret; 843 844 platform_set_drvdata(pdev, mdev); 845 pm_runtime_enable(mdev->dev); 846 847 ret = pm_runtime_get_sync(mdev->dev); 848 if (ret < 0) { 849 pm_runtime_put_noidle(mdev->dev); 850 goto unregister; 851 } 852 853 /* 854 * just print the raw revision register, the format is not 855 * uniform across all SoCs 856 */ 857 l = mbox_read_reg(mdev, MAILBOX_REVISION); 858 dev_info(mdev->dev, "omap mailbox rev 0x%x\n", l); 859 860 ret = pm_runtime_put_sync(mdev->dev); 861 if (ret < 0) 862 goto unregister; 863 864 devm_kfree(&pdev->dev, finfoblk); 865 return 0; 866 867 unregister: 868 pm_runtime_disable(mdev->dev); 869 omap_mbox_unregister(mdev); 870 return ret; 871 } 872 873 static int omap_mbox_remove(struct platform_device *pdev) 874 { 875 struct omap_mbox_device *mdev = platform_get_drvdata(pdev); 876 877 pm_runtime_disable(mdev->dev); 878 omap_mbox_unregister(mdev); 879 880 return 0; 881 } 882 883 static struct platform_driver omap_mbox_driver = { 884 .probe = omap_mbox_probe, 885 .remove = omap_mbox_remove, 886 .driver = { 887 .name = "omap-mailbox", 888 .pm = &omap_mbox_pm_ops, 889 .of_match_table = of_match_ptr(omap_mailbox_of_match), 890 }, 891 }; 892 893 static int __init omap_mbox_init(void) 894 { 895 int err; 896 897 err = class_register(&omap_mbox_class); 898 if (err) 899 return err; 900 901 /* kfifo size sanity check: alignment and minimal size */ 902 mbox_kfifo_size = ALIGN(mbox_kfifo_size, sizeof(mbox_msg_t)); 903 mbox_kfifo_size = max_t(unsigned int, mbox_kfifo_size, 904 sizeof(mbox_msg_t)); 905 906 err = platform_driver_register(&omap_mbox_driver); 907 if (err) 908 class_unregister(&omap_mbox_class); 909 910 return err; 911 } 912 subsys_initcall(omap_mbox_init); 913 914 static void __exit omap_mbox_exit(void) 915 { 916 platform_driver_unregister(&omap_mbox_driver); 917 class_unregister(&omap_mbox_class); 918 } 919 module_exit(omap_mbox_exit); 920 921 MODULE_LICENSE("GPL v2"); 922 MODULE_DESCRIPTION("omap mailbox: interrupt driven messaging"); 923 MODULE_AUTHOR("Toshihiro Kobayashi"); 924 MODULE_AUTHOR("Hiroshi DOYU"); 925