1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // Copyright (c) 2018 MediaTek Inc. 4 5 #include <linux/bitops.h> 6 #include <linux/clk.h> 7 #include <linux/clk-provider.h> 8 #include <linux/dma-mapping.h> 9 #include <linux/errno.h> 10 #include <linux/interrupt.h> 11 #include <linux/io.h> 12 #include <linux/iopoll.h> 13 #include <linux/kernel.h> 14 #include <linux/module.h> 15 #include <linux/platform_device.h> 16 #include <linux/mailbox_controller.h> 17 #include <linux/mailbox/mtk-cmdq-mailbox.h> 18 #include <linux/of_device.h> 19 20 #define CMDQ_OP_CODE_MASK (0xff << CMDQ_OP_CODE_SHIFT) 21 #define CMDQ_NUM_CMD(t) (t->cmd_buf_size / CMDQ_INST_SIZE) 22 23 #define CMDQ_CURR_IRQ_STATUS 0x10 24 #define CMDQ_SYNC_TOKEN_UPDATE 0x68 25 #define CMDQ_THR_SLOT_CYCLES 0x30 26 #define CMDQ_THR_BASE 0x100 27 #define CMDQ_THR_SIZE 0x80 28 #define CMDQ_THR_WARM_RESET 0x00 29 #define CMDQ_THR_ENABLE_TASK 0x04 30 #define CMDQ_THR_SUSPEND_TASK 0x08 31 #define CMDQ_THR_CURR_STATUS 0x0c 32 #define CMDQ_THR_IRQ_STATUS 0x10 33 #define CMDQ_THR_IRQ_ENABLE 0x14 34 #define CMDQ_THR_CURR_ADDR 0x20 35 #define CMDQ_THR_END_ADDR 0x24 36 #define CMDQ_THR_WAIT_TOKEN 0x30 37 #define CMDQ_THR_PRIORITY 0x40 38 39 #define GCE_GCTL_VALUE 0x48 40 41 #define CMDQ_THR_ACTIVE_SLOT_CYCLES 0x3200 42 #define CMDQ_THR_ENABLED 0x1 43 #define CMDQ_THR_DISABLED 0x0 44 #define CMDQ_THR_SUSPEND 0x1 45 #define CMDQ_THR_RESUME 0x0 46 #define CMDQ_THR_STATUS_SUSPENDED BIT(1) 47 #define CMDQ_THR_DO_WARM_RESET BIT(0) 48 #define CMDQ_THR_IRQ_DONE 0x1 49 #define CMDQ_THR_IRQ_ERROR 0x12 50 #define CMDQ_THR_IRQ_EN (CMDQ_THR_IRQ_ERROR | CMDQ_THR_IRQ_DONE) 51 #define CMDQ_THR_IS_WAITING BIT(31) 52 53 #define CMDQ_JUMP_BY_OFFSET 0x10000000 54 #define CMDQ_JUMP_BY_PA 0x10000001 55 56 struct cmdq_thread { 57 struct mbox_chan *chan; 58 void __iomem *base; 59 struct list_head task_busy_list; 60 u32 priority; 61 }; 62 63 struct cmdq_task { 64 struct cmdq *cmdq; 65 struct list_head list_entry; 66 dma_addr_t pa_base; 67 struct cmdq_thread *thread; 68 struct cmdq_pkt *pkt; /* the packet sent from mailbox client */ 69 }; 70 71 struct cmdq { 72 struct mbox_controller mbox; 73 void __iomem *base; 74 int irq; 75 u32 thread_nr; 76 u32 irq_mask; 77 struct cmdq_thread *thread; 78 struct clk *clock; 79 bool suspended; 80 u8 shift_pa; 81 bool control_by_sw; 82 }; 83 84 struct gce_plat { 85 u32 thread_nr; 86 u8 shift; 87 bool control_by_sw; 88 }; 89 90 u8 cmdq_get_shift_pa(struct mbox_chan *chan) 91 { 92 struct cmdq *cmdq = container_of(chan->mbox, struct cmdq, mbox); 93 94 return cmdq->shift_pa; 95 } 96 EXPORT_SYMBOL(cmdq_get_shift_pa); 97 98 static int cmdq_thread_suspend(struct cmdq *cmdq, struct cmdq_thread *thread) 99 { 100 u32 status; 101 102 writel(CMDQ_THR_SUSPEND, thread->base + CMDQ_THR_SUSPEND_TASK); 103 104 /* If already disabled, treat as suspended successful. */ 105 if (!(readl(thread->base + CMDQ_THR_ENABLE_TASK) & CMDQ_THR_ENABLED)) 106 return 0; 107 108 if (readl_poll_timeout_atomic(thread->base + CMDQ_THR_CURR_STATUS, 109 status, status & CMDQ_THR_STATUS_SUSPENDED, 0, 10)) { 110 dev_err(cmdq->mbox.dev, "suspend GCE thread 0x%x failed\n", 111 (u32)(thread->base - cmdq->base)); 112 return -EFAULT; 113 } 114 115 return 0; 116 } 117 118 static void cmdq_thread_resume(struct cmdq_thread *thread) 119 { 120 writel(CMDQ_THR_RESUME, thread->base + CMDQ_THR_SUSPEND_TASK); 121 } 122 123 static void cmdq_init(struct cmdq *cmdq) 124 { 125 int i; 126 127 WARN_ON(clk_enable(cmdq->clock) < 0); 128 if (cmdq->control_by_sw) 129 writel(0x7, cmdq->base + GCE_GCTL_VALUE); 130 writel(CMDQ_THR_ACTIVE_SLOT_CYCLES, cmdq->base + CMDQ_THR_SLOT_CYCLES); 131 for (i = 0; i <= CMDQ_MAX_EVENT; i++) 132 writel(i, cmdq->base + CMDQ_SYNC_TOKEN_UPDATE); 133 clk_disable(cmdq->clock); 134 } 135 136 static int cmdq_thread_reset(struct cmdq *cmdq, struct cmdq_thread *thread) 137 { 138 u32 warm_reset; 139 140 writel(CMDQ_THR_DO_WARM_RESET, thread->base + CMDQ_THR_WARM_RESET); 141 if (readl_poll_timeout_atomic(thread->base + CMDQ_THR_WARM_RESET, 142 warm_reset, !(warm_reset & CMDQ_THR_DO_WARM_RESET), 143 0, 10)) { 144 dev_err(cmdq->mbox.dev, "reset GCE thread 0x%x failed\n", 145 (u32)(thread->base - cmdq->base)); 146 return -EFAULT; 147 } 148 149 return 0; 150 } 151 152 static void cmdq_thread_disable(struct cmdq *cmdq, struct cmdq_thread *thread) 153 { 154 cmdq_thread_reset(cmdq, thread); 155 writel(CMDQ_THR_DISABLED, thread->base + CMDQ_THR_ENABLE_TASK); 156 } 157 158 /* notify GCE to re-fetch commands by setting GCE thread PC */ 159 static void cmdq_thread_invalidate_fetched_data(struct cmdq_thread *thread) 160 { 161 writel(readl(thread->base + CMDQ_THR_CURR_ADDR), 162 thread->base + CMDQ_THR_CURR_ADDR); 163 } 164 165 static void cmdq_task_insert_into_thread(struct cmdq_task *task) 166 { 167 struct device *dev = task->cmdq->mbox.dev; 168 struct cmdq_thread *thread = task->thread; 169 struct cmdq_task *prev_task = list_last_entry( 170 &thread->task_busy_list, typeof(*task), list_entry); 171 u64 *prev_task_base = prev_task->pkt->va_base; 172 173 /* let previous task jump to this task */ 174 dma_sync_single_for_cpu(dev, prev_task->pa_base, 175 prev_task->pkt->cmd_buf_size, DMA_TO_DEVICE); 176 prev_task_base[CMDQ_NUM_CMD(prev_task->pkt) - 1] = 177 (u64)CMDQ_JUMP_BY_PA << 32 | 178 (task->pa_base >> task->cmdq->shift_pa); 179 dma_sync_single_for_device(dev, prev_task->pa_base, 180 prev_task->pkt->cmd_buf_size, DMA_TO_DEVICE); 181 182 cmdq_thread_invalidate_fetched_data(thread); 183 } 184 185 static bool cmdq_thread_is_in_wfe(struct cmdq_thread *thread) 186 { 187 return readl(thread->base + CMDQ_THR_WAIT_TOKEN) & CMDQ_THR_IS_WAITING; 188 } 189 190 static void cmdq_task_exec_done(struct cmdq_task *task, int sta) 191 { 192 struct cmdq_task_cb *cb = &task->pkt->async_cb; 193 struct cmdq_cb_data data; 194 195 WARN_ON(cb->cb == (cmdq_async_flush_cb)NULL); 196 data.sta = sta; 197 data.data = cb->data; 198 data.pkt = task->pkt; 199 if (cb->cb) 200 cb->cb(data); 201 202 mbox_chan_received_data(task->thread->chan, &data); 203 204 list_del(&task->list_entry); 205 } 206 207 static void cmdq_task_handle_error(struct cmdq_task *task) 208 { 209 struct cmdq_thread *thread = task->thread; 210 struct cmdq_task *next_task; 211 struct cmdq *cmdq = task->cmdq; 212 213 dev_err(cmdq->mbox.dev, "task 0x%p error\n", task); 214 WARN_ON(cmdq_thread_suspend(cmdq, thread) < 0); 215 next_task = list_first_entry_or_null(&thread->task_busy_list, 216 struct cmdq_task, list_entry); 217 if (next_task) 218 writel(next_task->pa_base >> cmdq->shift_pa, 219 thread->base + CMDQ_THR_CURR_ADDR); 220 cmdq_thread_resume(thread); 221 } 222 223 static void cmdq_thread_irq_handler(struct cmdq *cmdq, 224 struct cmdq_thread *thread) 225 { 226 struct cmdq_task *task, *tmp, *curr_task = NULL; 227 u32 curr_pa, irq_flag, task_end_pa; 228 bool err; 229 230 irq_flag = readl(thread->base + CMDQ_THR_IRQ_STATUS); 231 writel(~irq_flag, thread->base + CMDQ_THR_IRQ_STATUS); 232 233 /* 234 * When ISR call this function, another CPU core could run 235 * "release task" right before we acquire the spin lock, and thus 236 * reset / disable this GCE thread, so we need to check the enable 237 * bit of this GCE thread. 238 */ 239 if (!(readl(thread->base + CMDQ_THR_ENABLE_TASK) & CMDQ_THR_ENABLED)) 240 return; 241 242 if (irq_flag & CMDQ_THR_IRQ_ERROR) 243 err = true; 244 else if (irq_flag & CMDQ_THR_IRQ_DONE) 245 err = false; 246 else 247 return; 248 249 curr_pa = readl(thread->base + CMDQ_THR_CURR_ADDR) << cmdq->shift_pa; 250 251 list_for_each_entry_safe(task, tmp, &thread->task_busy_list, 252 list_entry) { 253 task_end_pa = task->pa_base + task->pkt->cmd_buf_size; 254 if (curr_pa >= task->pa_base && curr_pa < task_end_pa) 255 curr_task = task; 256 257 if (!curr_task || curr_pa == task_end_pa - CMDQ_INST_SIZE) { 258 cmdq_task_exec_done(task, 0); 259 kfree(task); 260 } else if (err) { 261 cmdq_task_exec_done(task, -ENOEXEC); 262 cmdq_task_handle_error(curr_task); 263 kfree(task); 264 } 265 266 if (curr_task) 267 break; 268 } 269 270 if (list_empty(&thread->task_busy_list)) { 271 cmdq_thread_disable(cmdq, thread); 272 clk_disable(cmdq->clock); 273 } 274 } 275 276 static irqreturn_t cmdq_irq_handler(int irq, void *dev) 277 { 278 struct cmdq *cmdq = dev; 279 unsigned long irq_status, flags = 0L; 280 int bit; 281 282 irq_status = readl(cmdq->base + CMDQ_CURR_IRQ_STATUS) & cmdq->irq_mask; 283 if (!(irq_status ^ cmdq->irq_mask)) 284 return IRQ_NONE; 285 286 for_each_clear_bit(bit, &irq_status, cmdq->thread_nr) { 287 struct cmdq_thread *thread = &cmdq->thread[bit]; 288 289 spin_lock_irqsave(&thread->chan->lock, flags); 290 cmdq_thread_irq_handler(cmdq, thread); 291 spin_unlock_irqrestore(&thread->chan->lock, flags); 292 } 293 294 return IRQ_HANDLED; 295 } 296 297 static int cmdq_suspend(struct device *dev) 298 { 299 struct cmdq *cmdq = dev_get_drvdata(dev); 300 struct cmdq_thread *thread; 301 int i; 302 bool task_running = false; 303 304 cmdq->suspended = true; 305 306 for (i = 0; i < cmdq->thread_nr; i++) { 307 thread = &cmdq->thread[i]; 308 if (!list_empty(&thread->task_busy_list)) { 309 task_running = true; 310 break; 311 } 312 } 313 314 if (task_running) 315 dev_warn(dev, "exist running task(s) in suspend\n"); 316 317 clk_unprepare(cmdq->clock); 318 319 return 0; 320 } 321 322 static int cmdq_resume(struct device *dev) 323 { 324 struct cmdq *cmdq = dev_get_drvdata(dev); 325 326 WARN_ON(clk_prepare(cmdq->clock) < 0); 327 cmdq->suspended = false; 328 return 0; 329 } 330 331 static int cmdq_remove(struct platform_device *pdev) 332 { 333 struct cmdq *cmdq = platform_get_drvdata(pdev); 334 335 clk_unprepare(cmdq->clock); 336 337 return 0; 338 } 339 340 static int cmdq_mbox_send_data(struct mbox_chan *chan, void *data) 341 { 342 struct cmdq_pkt *pkt = (struct cmdq_pkt *)data; 343 struct cmdq_thread *thread = (struct cmdq_thread *)chan->con_priv; 344 struct cmdq *cmdq = dev_get_drvdata(chan->mbox->dev); 345 struct cmdq_task *task; 346 unsigned long curr_pa, end_pa; 347 348 /* Client should not flush new tasks if suspended. */ 349 WARN_ON(cmdq->suspended); 350 351 task = kzalloc(sizeof(*task), GFP_ATOMIC); 352 if (!task) 353 return -ENOMEM; 354 355 task->cmdq = cmdq; 356 INIT_LIST_HEAD(&task->list_entry); 357 task->pa_base = pkt->pa_base; 358 task->thread = thread; 359 task->pkt = pkt; 360 361 if (list_empty(&thread->task_busy_list)) { 362 WARN_ON(clk_enable(cmdq->clock) < 0); 363 /* 364 * The thread reset will clear thread related register to 0, 365 * including pc, end, priority, irq, suspend and enable. Thus 366 * set CMDQ_THR_ENABLED to CMDQ_THR_ENABLE_TASK will enable 367 * thread and make it running. 368 */ 369 WARN_ON(cmdq_thread_reset(cmdq, thread) < 0); 370 371 writel(task->pa_base >> cmdq->shift_pa, 372 thread->base + CMDQ_THR_CURR_ADDR); 373 writel((task->pa_base + pkt->cmd_buf_size) >> cmdq->shift_pa, 374 thread->base + CMDQ_THR_END_ADDR); 375 376 writel(thread->priority, thread->base + CMDQ_THR_PRIORITY); 377 writel(CMDQ_THR_IRQ_EN, thread->base + CMDQ_THR_IRQ_ENABLE); 378 writel(CMDQ_THR_ENABLED, thread->base + CMDQ_THR_ENABLE_TASK); 379 } else { 380 WARN_ON(cmdq_thread_suspend(cmdq, thread) < 0); 381 curr_pa = readl(thread->base + CMDQ_THR_CURR_ADDR) << 382 cmdq->shift_pa; 383 end_pa = readl(thread->base + CMDQ_THR_END_ADDR) << 384 cmdq->shift_pa; 385 /* check boundary */ 386 if (curr_pa == end_pa - CMDQ_INST_SIZE || 387 curr_pa == end_pa) { 388 /* set to this task directly */ 389 writel(task->pa_base >> cmdq->shift_pa, 390 thread->base + CMDQ_THR_CURR_ADDR); 391 } else { 392 cmdq_task_insert_into_thread(task); 393 smp_mb(); /* modify jump before enable thread */ 394 } 395 writel((task->pa_base + pkt->cmd_buf_size) >> cmdq->shift_pa, 396 thread->base + CMDQ_THR_END_ADDR); 397 cmdq_thread_resume(thread); 398 } 399 list_move_tail(&task->list_entry, &thread->task_busy_list); 400 401 return 0; 402 } 403 404 static int cmdq_mbox_startup(struct mbox_chan *chan) 405 { 406 return 0; 407 } 408 409 static void cmdq_mbox_shutdown(struct mbox_chan *chan) 410 { 411 struct cmdq_thread *thread = (struct cmdq_thread *)chan->con_priv; 412 struct cmdq *cmdq = dev_get_drvdata(chan->mbox->dev); 413 struct cmdq_task *task, *tmp; 414 unsigned long flags; 415 416 spin_lock_irqsave(&thread->chan->lock, flags); 417 if (list_empty(&thread->task_busy_list)) 418 goto done; 419 420 WARN_ON(cmdq_thread_suspend(cmdq, thread) < 0); 421 422 /* make sure executed tasks have success callback */ 423 cmdq_thread_irq_handler(cmdq, thread); 424 if (list_empty(&thread->task_busy_list)) 425 goto done; 426 427 list_for_each_entry_safe(task, tmp, &thread->task_busy_list, 428 list_entry) { 429 cmdq_task_exec_done(task, -ECONNABORTED); 430 kfree(task); 431 } 432 433 cmdq_thread_disable(cmdq, thread); 434 clk_disable(cmdq->clock); 435 done: 436 /* 437 * The thread->task_busy_list empty means thread already disable. The 438 * cmdq_mbox_send_data() always reset thread which clear disable and 439 * suspend statue when first pkt send to channel, so there is no need 440 * to do any operation here, only unlock and leave. 441 */ 442 spin_unlock_irqrestore(&thread->chan->lock, flags); 443 } 444 445 static int cmdq_mbox_flush(struct mbox_chan *chan, unsigned long timeout) 446 { 447 struct cmdq_thread *thread = (struct cmdq_thread *)chan->con_priv; 448 struct cmdq_task_cb *cb; 449 struct cmdq_cb_data data; 450 struct cmdq *cmdq = dev_get_drvdata(chan->mbox->dev); 451 struct cmdq_task *task, *tmp; 452 unsigned long flags; 453 u32 enable; 454 455 spin_lock_irqsave(&thread->chan->lock, flags); 456 if (list_empty(&thread->task_busy_list)) 457 goto out; 458 459 WARN_ON(cmdq_thread_suspend(cmdq, thread) < 0); 460 if (!cmdq_thread_is_in_wfe(thread)) 461 goto wait; 462 463 list_for_each_entry_safe(task, tmp, &thread->task_busy_list, 464 list_entry) { 465 cb = &task->pkt->async_cb; 466 data.sta = -ECONNABORTED; 467 data.data = cb->data; 468 data.pkt = task->pkt; 469 if (cb->cb) 470 cb->cb(data); 471 472 mbox_chan_received_data(task->thread->chan, &data); 473 list_del(&task->list_entry); 474 kfree(task); 475 } 476 477 cmdq_thread_resume(thread); 478 cmdq_thread_disable(cmdq, thread); 479 clk_disable(cmdq->clock); 480 481 out: 482 spin_unlock_irqrestore(&thread->chan->lock, flags); 483 return 0; 484 485 wait: 486 cmdq_thread_resume(thread); 487 spin_unlock_irqrestore(&thread->chan->lock, flags); 488 if (readl_poll_timeout_atomic(thread->base + CMDQ_THR_ENABLE_TASK, 489 enable, enable == 0, 1, timeout)) { 490 dev_err(cmdq->mbox.dev, "Fail to wait GCE thread 0x%x done\n", 491 (u32)(thread->base - cmdq->base)); 492 493 return -EFAULT; 494 } 495 return 0; 496 } 497 498 static const struct mbox_chan_ops cmdq_mbox_chan_ops = { 499 .send_data = cmdq_mbox_send_data, 500 .startup = cmdq_mbox_startup, 501 .shutdown = cmdq_mbox_shutdown, 502 .flush = cmdq_mbox_flush, 503 }; 504 505 static struct mbox_chan *cmdq_xlate(struct mbox_controller *mbox, 506 const struct of_phandle_args *sp) 507 { 508 int ind = sp->args[0]; 509 struct cmdq_thread *thread; 510 511 if (ind >= mbox->num_chans) 512 return ERR_PTR(-EINVAL); 513 514 thread = (struct cmdq_thread *)mbox->chans[ind].con_priv; 515 thread->priority = sp->args[1]; 516 thread->chan = &mbox->chans[ind]; 517 518 return &mbox->chans[ind]; 519 } 520 521 static int cmdq_probe(struct platform_device *pdev) 522 { 523 struct device *dev = &pdev->dev; 524 struct resource *res; 525 struct cmdq *cmdq; 526 int err, i; 527 struct gce_plat *plat_data; 528 529 cmdq = devm_kzalloc(dev, sizeof(*cmdq), GFP_KERNEL); 530 if (!cmdq) 531 return -ENOMEM; 532 533 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 534 cmdq->base = devm_ioremap_resource(dev, res); 535 if (IS_ERR(cmdq->base)) 536 return PTR_ERR(cmdq->base); 537 538 cmdq->irq = platform_get_irq(pdev, 0); 539 if (cmdq->irq < 0) 540 return cmdq->irq; 541 542 plat_data = (struct gce_plat *)of_device_get_match_data(dev); 543 if (!plat_data) { 544 dev_err(dev, "failed to get match data\n"); 545 return -EINVAL; 546 } 547 548 cmdq->thread_nr = plat_data->thread_nr; 549 cmdq->shift_pa = plat_data->shift; 550 cmdq->control_by_sw = plat_data->control_by_sw; 551 cmdq->irq_mask = GENMASK(cmdq->thread_nr - 1, 0); 552 err = devm_request_irq(dev, cmdq->irq, cmdq_irq_handler, IRQF_SHARED, 553 "mtk_cmdq", cmdq); 554 if (err < 0) { 555 dev_err(dev, "failed to register ISR (%d)\n", err); 556 return err; 557 } 558 559 dev_dbg(dev, "cmdq device: addr:0x%p, va:0x%p, irq:%d\n", 560 dev, cmdq->base, cmdq->irq); 561 562 cmdq->clock = devm_clk_get(dev, "gce"); 563 if (IS_ERR(cmdq->clock)) { 564 dev_err(dev, "failed to get gce clk\n"); 565 return PTR_ERR(cmdq->clock); 566 } 567 568 cmdq->mbox.dev = dev; 569 cmdq->mbox.chans = devm_kcalloc(dev, cmdq->thread_nr, 570 sizeof(*cmdq->mbox.chans), GFP_KERNEL); 571 if (!cmdq->mbox.chans) 572 return -ENOMEM; 573 574 cmdq->mbox.num_chans = cmdq->thread_nr; 575 cmdq->mbox.ops = &cmdq_mbox_chan_ops; 576 cmdq->mbox.of_xlate = cmdq_xlate; 577 578 /* make use of TXDONE_BY_ACK */ 579 cmdq->mbox.txdone_irq = false; 580 cmdq->mbox.txdone_poll = false; 581 582 cmdq->thread = devm_kcalloc(dev, cmdq->thread_nr, 583 sizeof(*cmdq->thread), GFP_KERNEL); 584 if (!cmdq->thread) 585 return -ENOMEM; 586 587 for (i = 0; i < cmdq->thread_nr; i++) { 588 cmdq->thread[i].base = cmdq->base + CMDQ_THR_BASE + 589 CMDQ_THR_SIZE * i; 590 INIT_LIST_HEAD(&cmdq->thread[i].task_busy_list); 591 cmdq->mbox.chans[i].con_priv = (void *)&cmdq->thread[i]; 592 } 593 594 err = devm_mbox_controller_register(dev, &cmdq->mbox); 595 if (err < 0) { 596 dev_err(dev, "failed to register mailbox: %d\n", err); 597 return err; 598 } 599 600 platform_set_drvdata(pdev, cmdq); 601 WARN_ON(clk_prepare(cmdq->clock) < 0); 602 603 cmdq_init(cmdq); 604 605 return 0; 606 } 607 608 static const struct dev_pm_ops cmdq_pm_ops = { 609 .suspend = cmdq_suspend, 610 .resume = cmdq_resume, 611 }; 612 613 static const struct gce_plat gce_plat_v2 = {.thread_nr = 16}; 614 static const struct gce_plat gce_plat_v3 = {.thread_nr = 24}; 615 static const struct gce_plat gce_plat_v4 = {.thread_nr = 24, .shift = 3}; 616 static const struct gce_plat gce_plat_v5 = {.thread_nr = 24, .shift = 3, 617 .control_by_sw = true}; 618 619 static const struct of_device_id cmdq_of_ids[] = { 620 {.compatible = "mediatek,mt8173-gce", .data = (void *)&gce_plat_v2}, 621 {.compatible = "mediatek,mt8183-gce", .data = (void *)&gce_plat_v3}, 622 {.compatible = "mediatek,mt6779-gce", .data = (void *)&gce_plat_v4}, 623 {.compatible = "mediatek,mt8192-gce", .data = (void *)&gce_plat_v5}, 624 {.compatible = "mediatek,mt8195-gce", .data = (void *)&gce_plat_v4}, 625 {} 626 }; 627 628 static struct platform_driver cmdq_drv = { 629 .probe = cmdq_probe, 630 .remove = cmdq_remove, 631 .driver = { 632 .name = "mtk_cmdq", 633 .pm = &cmdq_pm_ops, 634 .of_match_table = cmdq_of_ids, 635 } 636 }; 637 638 static int __init cmdq_drv_init(void) 639 { 640 return platform_driver_register(&cmdq_drv); 641 } 642 643 static void __exit cmdq_drv_exit(void) 644 { 645 platform_driver_unregister(&cmdq_drv); 646 } 647 648 subsys_initcall(cmdq_drv_init); 649 module_exit(cmdq_drv_exit); 650 651 MODULE_LICENSE("GPL v2"); 652