1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // Copyright (c) 2018 MediaTek Inc. 4 5 #include <linux/bitops.h> 6 #include <linux/clk.h> 7 #include <linux/clk-provider.h> 8 #include <linux/dma-mapping.h> 9 #include <linux/errno.h> 10 #include <linux/interrupt.h> 11 #include <linux/io.h> 12 #include <linux/iopoll.h> 13 #include <linux/kernel.h> 14 #include <linux/module.h> 15 #include <linux/platform_device.h> 16 #include <linux/mailbox_controller.h> 17 #include <linux/mailbox/mtk-cmdq-mailbox.h> 18 #include <linux/of_device.h> 19 20 #define CMDQ_OP_CODE_MASK (0xff << CMDQ_OP_CODE_SHIFT) 21 #define CMDQ_NUM_CMD(t) (t->cmd_buf_size / CMDQ_INST_SIZE) 22 23 #define CMDQ_CURR_IRQ_STATUS 0x10 24 #define CMDQ_SYNC_TOKEN_UPDATE 0x68 25 #define CMDQ_THR_SLOT_CYCLES 0x30 26 #define CMDQ_THR_BASE 0x100 27 #define CMDQ_THR_SIZE 0x80 28 #define CMDQ_THR_WARM_RESET 0x00 29 #define CMDQ_THR_ENABLE_TASK 0x04 30 #define CMDQ_THR_SUSPEND_TASK 0x08 31 #define CMDQ_THR_CURR_STATUS 0x0c 32 #define CMDQ_THR_IRQ_STATUS 0x10 33 #define CMDQ_THR_IRQ_ENABLE 0x14 34 #define CMDQ_THR_CURR_ADDR 0x20 35 #define CMDQ_THR_END_ADDR 0x24 36 #define CMDQ_THR_WAIT_TOKEN 0x30 37 #define CMDQ_THR_PRIORITY 0x40 38 39 #define CMDQ_THR_ACTIVE_SLOT_CYCLES 0x3200 40 #define CMDQ_THR_ENABLED 0x1 41 #define CMDQ_THR_DISABLED 0x0 42 #define CMDQ_THR_SUSPEND 0x1 43 #define CMDQ_THR_RESUME 0x0 44 #define CMDQ_THR_STATUS_SUSPENDED BIT(1) 45 #define CMDQ_THR_DO_WARM_RESET BIT(0) 46 #define CMDQ_THR_IRQ_DONE 0x1 47 #define CMDQ_THR_IRQ_ERROR 0x12 48 #define CMDQ_THR_IRQ_EN (CMDQ_THR_IRQ_ERROR | CMDQ_THR_IRQ_DONE) 49 #define CMDQ_THR_IS_WAITING BIT(31) 50 51 #define CMDQ_JUMP_BY_OFFSET 0x10000000 52 #define CMDQ_JUMP_BY_PA 0x10000001 53 54 struct cmdq_thread { 55 struct mbox_chan *chan; 56 void __iomem *base; 57 struct list_head task_busy_list; 58 u32 priority; 59 }; 60 61 struct cmdq_task { 62 struct cmdq *cmdq; 63 struct list_head list_entry; 64 dma_addr_t pa_base; 65 struct cmdq_thread *thread; 66 struct cmdq_pkt *pkt; /* the packet sent from mailbox client */ 67 }; 68 69 struct cmdq { 70 struct mbox_controller mbox; 71 void __iomem *base; 72 int irq; 73 u32 thread_nr; 74 u32 irq_mask; 75 struct cmdq_thread *thread; 76 struct clk *clock; 77 bool suspended; 78 u8 shift_pa; 79 }; 80 81 struct gce_plat { 82 u32 thread_nr; 83 u8 shift; 84 }; 85 86 u8 cmdq_get_shift_pa(struct mbox_chan *chan) 87 { 88 struct cmdq *cmdq = container_of(chan->mbox, struct cmdq, mbox); 89 90 return cmdq->shift_pa; 91 } 92 EXPORT_SYMBOL(cmdq_get_shift_pa); 93 94 static int cmdq_thread_suspend(struct cmdq *cmdq, struct cmdq_thread *thread) 95 { 96 u32 status; 97 98 writel(CMDQ_THR_SUSPEND, thread->base + CMDQ_THR_SUSPEND_TASK); 99 100 /* If already disabled, treat as suspended successful. */ 101 if (!(readl(thread->base + CMDQ_THR_ENABLE_TASK) & CMDQ_THR_ENABLED)) 102 return 0; 103 104 if (readl_poll_timeout_atomic(thread->base + CMDQ_THR_CURR_STATUS, 105 status, status & CMDQ_THR_STATUS_SUSPENDED, 0, 10)) { 106 dev_err(cmdq->mbox.dev, "suspend GCE thread 0x%x failed\n", 107 (u32)(thread->base - cmdq->base)); 108 return -EFAULT; 109 } 110 111 return 0; 112 } 113 114 static void cmdq_thread_resume(struct cmdq_thread *thread) 115 { 116 writel(CMDQ_THR_RESUME, thread->base + CMDQ_THR_SUSPEND_TASK); 117 } 118 119 static void cmdq_init(struct cmdq *cmdq) 120 { 121 int i; 122 123 WARN_ON(clk_enable(cmdq->clock) < 0); 124 writel(CMDQ_THR_ACTIVE_SLOT_CYCLES, cmdq->base + CMDQ_THR_SLOT_CYCLES); 125 for (i = 0; i <= CMDQ_MAX_EVENT; i++) 126 writel(i, cmdq->base + CMDQ_SYNC_TOKEN_UPDATE); 127 clk_disable(cmdq->clock); 128 } 129 130 static int cmdq_thread_reset(struct cmdq *cmdq, struct cmdq_thread *thread) 131 { 132 u32 warm_reset; 133 134 writel(CMDQ_THR_DO_WARM_RESET, thread->base + CMDQ_THR_WARM_RESET); 135 if (readl_poll_timeout_atomic(thread->base + CMDQ_THR_WARM_RESET, 136 warm_reset, !(warm_reset & CMDQ_THR_DO_WARM_RESET), 137 0, 10)) { 138 dev_err(cmdq->mbox.dev, "reset GCE thread 0x%x failed\n", 139 (u32)(thread->base - cmdq->base)); 140 return -EFAULT; 141 } 142 143 return 0; 144 } 145 146 static void cmdq_thread_disable(struct cmdq *cmdq, struct cmdq_thread *thread) 147 { 148 cmdq_thread_reset(cmdq, thread); 149 writel(CMDQ_THR_DISABLED, thread->base + CMDQ_THR_ENABLE_TASK); 150 } 151 152 /* notify GCE to re-fetch commands by setting GCE thread PC */ 153 static void cmdq_thread_invalidate_fetched_data(struct cmdq_thread *thread) 154 { 155 writel(readl(thread->base + CMDQ_THR_CURR_ADDR), 156 thread->base + CMDQ_THR_CURR_ADDR); 157 } 158 159 static void cmdq_task_insert_into_thread(struct cmdq_task *task) 160 { 161 struct device *dev = task->cmdq->mbox.dev; 162 struct cmdq_thread *thread = task->thread; 163 struct cmdq_task *prev_task = list_last_entry( 164 &thread->task_busy_list, typeof(*task), list_entry); 165 u64 *prev_task_base = prev_task->pkt->va_base; 166 167 /* let previous task jump to this task */ 168 dma_sync_single_for_cpu(dev, prev_task->pa_base, 169 prev_task->pkt->cmd_buf_size, DMA_TO_DEVICE); 170 prev_task_base[CMDQ_NUM_CMD(prev_task->pkt) - 1] = 171 (u64)CMDQ_JUMP_BY_PA << 32 | task->pa_base; 172 dma_sync_single_for_device(dev, prev_task->pa_base, 173 prev_task->pkt->cmd_buf_size, DMA_TO_DEVICE); 174 175 cmdq_thread_invalidate_fetched_data(thread); 176 } 177 178 static bool cmdq_thread_is_in_wfe(struct cmdq_thread *thread) 179 { 180 return readl(thread->base + CMDQ_THR_WAIT_TOKEN) & CMDQ_THR_IS_WAITING; 181 } 182 183 static void cmdq_task_exec_done(struct cmdq_task *task, int sta) 184 { 185 struct cmdq_task_cb *cb = &task->pkt->async_cb; 186 struct cmdq_cb_data data; 187 188 WARN_ON(cb->cb == (cmdq_async_flush_cb)NULL); 189 data.sta = sta; 190 data.data = cb->data; 191 if (cb->cb) 192 cb->cb(data); 193 194 mbox_chan_received_data(task->thread->chan, &data); 195 196 list_del(&task->list_entry); 197 } 198 199 static void cmdq_task_handle_error(struct cmdq_task *task) 200 { 201 struct cmdq_thread *thread = task->thread; 202 struct cmdq_task *next_task; 203 struct cmdq *cmdq = task->cmdq; 204 205 dev_err(cmdq->mbox.dev, "task 0x%p error\n", task); 206 WARN_ON(cmdq_thread_suspend(cmdq, thread) < 0); 207 next_task = list_first_entry_or_null(&thread->task_busy_list, 208 struct cmdq_task, list_entry); 209 if (next_task) 210 writel(next_task->pa_base >> cmdq->shift_pa, 211 thread->base + CMDQ_THR_CURR_ADDR); 212 cmdq_thread_resume(thread); 213 } 214 215 static void cmdq_thread_irq_handler(struct cmdq *cmdq, 216 struct cmdq_thread *thread) 217 { 218 struct cmdq_task *task, *tmp, *curr_task = NULL; 219 u32 curr_pa, irq_flag, task_end_pa; 220 bool err; 221 222 irq_flag = readl(thread->base + CMDQ_THR_IRQ_STATUS); 223 writel(~irq_flag, thread->base + CMDQ_THR_IRQ_STATUS); 224 225 /* 226 * When ISR call this function, another CPU core could run 227 * "release task" right before we acquire the spin lock, and thus 228 * reset / disable this GCE thread, so we need to check the enable 229 * bit of this GCE thread. 230 */ 231 if (!(readl(thread->base + CMDQ_THR_ENABLE_TASK) & CMDQ_THR_ENABLED)) 232 return; 233 234 if (irq_flag & CMDQ_THR_IRQ_ERROR) 235 err = true; 236 else if (irq_flag & CMDQ_THR_IRQ_DONE) 237 err = false; 238 else 239 return; 240 241 curr_pa = readl(thread->base + CMDQ_THR_CURR_ADDR) << cmdq->shift_pa; 242 243 list_for_each_entry_safe(task, tmp, &thread->task_busy_list, 244 list_entry) { 245 task_end_pa = task->pa_base + task->pkt->cmd_buf_size; 246 if (curr_pa >= task->pa_base && curr_pa < task_end_pa) 247 curr_task = task; 248 249 if (!curr_task || curr_pa == task_end_pa - CMDQ_INST_SIZE) { 250 cmdq_task_exec_done(task, 0); 251 kfree(task); 252 } else if (err) { 253 cmdq_task_exec_done(task, -ENOEXEC); 254 cmdq_task_handle_error(curr_task); 255 kfree(task); 256 } 257 258 if (curr_task) 259 break; 260 } 261 262 if (list_empty(&thread->task_busy_list)) { 263 cmdq_thread_disable(cmdq, thread); 264 clk_disable(cmdq->clock); 265 } 266 } 267 268 static irqreturn_t cmdq_irq_handler(int irq, void *dev) 269 { 270 struct cmdq *cmdq = dev; 271 unsigned long irq_status, flags = 0L; 272 int bit; 273 274 irq_status = readl(cmdq->base + CMDQ_CURR_IRQ_STATUS) & cmdq->irq_mask; 275 if (!(irq_status ^ cmdq->irq_mask)) 276 return IRQ_NONE; 277 278 for_each_clear_bit(bit, &irq_status, cmdq->thread_nr) { 279 struct cmdq_thread *thread = &cmdq->thread[bit]; 280 281 spin_lock_irqsave(&thread->chan->lock, flags); 282 cmdq_thread_irq_handler(cmdq, thread); 283 spin_unlock_irqrestore(&thread->chan->lock, flags); 284 } 285 286 return IRQ_HANDLED; 287 } 288 289 static int cmdq_suspend(struct device *dev) 290 { 291 struct cmdq *cmdq = dev_get_drvdata(dev); 292 struct cmdq_thread *thread; 293 int i; 294 bool task_running = false; 295 296 cmdq->suspended = true; 297 298 for (i = 0; i < cmdq->thread_nr; i++) { 299 thread = &cmdq->thread[i]; 300 if (!list_empty(&thread->task_busy_list)) { 301 task_running = true; 302 break; 303 } 304 } 305 306 if (task_running) 307 dev_warn(dev, "exist running task(s) in suspend\n"); 308 309 clk_unprepare(cmdq->clock); 310 311 return 0; 312 } 313 314 static int cmdq_resume(struct device *dev) 315 { 316 struct cmdq *cmdq = dev_get_drvdata(dev); 317 318 WARN_ON(clk_prepare(cmdq->clock) < 0); 319 cmdq->suspended = false; 320 return 0; 321 } 322 323 static int cmdq_remove(struct platform_device *pdev) 324 { 325 struct cmdq *cmdq = platform_get_drvdata(pdev); 326 327 clk_unprepare(cmdq->clock); 328 329 return 0; 330 } 331 332 static int cmdq_mbox_send_data(struct mbox_chan *chan, void *data) 333 { 334 struct cmdq_pkt *pkt = (struct cmdq_pkt *)data; 335 struct cmdq_thread *thread = (struct cmdq_thread *)chan->con_priv; 336 struct cmdq *cmdq = dev_get_drvdata(chan->mbox->dev); 337 struct cmdq_task *task; 338 unsigned long curr_pa, end_pa; 339 340 /* Client should not flush new tasks if suspended. */ 341 WARN_ON(cmdq->suspended); 342 343 task = kzalloc(sizeof(*task), GFP_ATOMIC); 344 if (!task) 345 return -ENOMEM; 346 347 task->cmdq = cmdq; 348 INIT_LIST_HEAD(&task->list_entry); 349 task->pa_base = pkt->pa_base; 350 task->thread = thread; 351 task->pkt = pkt; 352 353 if (list_empty(&thread->task_busy_list)) { 354 WARN_ON(clk_enable(cmdq->clock) < 0); 355 /* 356 * The thread reset will clear thread related register to 0, 357 * including pc, end, priority, irq, suspend and enable. Thus 358 * set CMDQ_THR_ENABLED to CMDQ_THR_ENABLE_TASK will enable 359 * thread and make it running. 360 */ 361 WARN_ON(cmdq_thread_reset(cmdq, thread) < 0); 362 363 writel(task->pa_base >> cmdq->shift_pa, 364 thread->base + CMDQ_THR_CURR_ADDR); 365 writel((task->pa_base + pkt->cmd_buf_size) >> cmdq->shift_pa, 366 thread->base + CMDQ_THR_END_ADDR); 367 368 writel(thread->priority, thread->base + CMDQ_THR_PRIORITY); 369 writel(CMDQ_THR_IRQ_EN, thread->base + CMDQ_THR_IRQ_ENABLE); 370 writel(CMDQ_THR_ENABLED, thread->base + CMDQ_THR_ENABLE_TASK); 371 } else { 372 WARN_ON(cmdq_thread_suspend(cmdq, thread) < 0); 373 curr_pa = readl(thread->base + CMDQ_THR_CURR_ADDR) << 374 cmdq->shift_pa; 375 end_pa = readl(thread->base + CMDQ_THR_END_ADDR) << 376 cmdq->shift_pa; 377 /* check boundary */ 378 if (curr_pa == end_pa - CMDQ_INST_SIZE || 379 curr_pa == end_pa) { 380 /* set to this task directly */ 381 writel(task->pa_base >> cmdq->shift_pa, 382 thread->base + CMDQ_THR_CURR_ADDR); 383 } else { 384 cmdq_task_insert_into_thread(task); 385 smp_mb(); /* modify jump before enable thread */ 386 } 387 writel((task->pa_base + pkt->cmd_buf_size) >> cmdq->shift_pa, 388 thread->base + CMDQ_THR_END_ADDR); 389 cmdq_thread_resume(thread); 390 } 391 list_move_tail(&task->list_entry, &thread->task_busy_list); 392 393 return 0; 394 } 395 396 static int cmdq_mbox_startup(struct mbox_chan *chan) 397 { 398 return 0; 399 } 400 401 static void cmdq_mbox_shutdown(struct mbox_chan *chan) 402 { 403 struct cmdq_thread *thread = (struct cmdq_thread *)chan->con_priv; 404 struct cmdq *cmdq = dev_get_drvdata(chan->mbox->dev); 405 struct cmdq_task *task, *tmp; 406 unsigned long flags; 407 408 spin_lock_irqsave(&thread->chan->lock, flags); 409 if (list_empty(&thread->task_busy_list)) 410 goto done; 411 412 WARN_ON(cmdq_thread_suspend(cmdq, thread) < 0); 413 414 /* make sure executed tasks have success callback */ 415 cmdq_thread_irq_handler(cmdq, thread); 416 if (list_empty(&thread->task_busy_list)) 417 goto done; 418 419 list_for_each_entry_safe(task, tmp, &thread->task_busy_list, 420 list_entry) { 421 cmdq_task_exec_done(task, -ECONNABORTED); 422 kfree(task); 423 } 424 425 cmdq_thread_disable(cmdq, thread); 426 clk_disable(cmdq->clock); 427 done: 428 /* 429 * The thread->task_busy_list empty means thread already disable. The 430 * cmdq_mbox_send_data() always reset thread which clear disable and 431 * suspend statue when first pkt send to channel, so there is no need 432 * to do any operation here, only unlock and leave. 433 */ 434 spin_unlock_irqrestore(&thread->chan->lock, flags); 435 } 436 437 static int cmdq_mbox_flush(struct mbox_chan *chan, unsigned long timeout) 438 { 439 struct cmdq_thread *thread = (struct cmdq_thread *)chan->con_priv; 440 struct cmdq_task_cb *cb; 441 struct cmdq_cb_data data; 442 struct cmdq *cmdq = dev_get_drvdata(chan->mbox->dev); 443 struct cmdq_task *task, *tmp; 444 unsigned long flags; 445 u32 enable; 446 447 spin_lock_irqsave(&thread->chan->lock, flags); 448 if (list_empty(&thread->task_busy_list)) 449 goto out; 450 451 WARN_ON(cmdq_thread_suspend(cmdq, thread) < 0); 452 if (!cmdq_thread_is_in_wfe(thread)) 453 goto wait; 454 455 list_for_each_entry_safe(task, tmp, &thread->task_busy_list, 456 list_entry) { 457 data.sta = -ECONNABORTED; 458 data.data = cb->data; 459 cb = &task->pkt->async_cb; 460 if (cb->cb) 461 cb->cb(data); 462 463 mbox_chan_received_data(task->thread->chan, &data); 464 list_del(&task->list_entry); 465 kfree(task); 466 } 467 468 cmdq_thread_resume(thread); 469 cmdq_thread_disable(cmdq, thread); 470 clk_disable(cmdq->clock); 471 472 out: 473 spin_unlock_irqrestore(&thread->chan->lock, flags); 474 return 0; 475 476 wait: 477 cmdq_thread_resume(thread); 478 spin_unlock_irqrestore(&thread->chan->lock, flags); 479 if (readl_poll_timeout_atomic(thread->base + CMDQ_THR_ENABLE_TASK, 480 enable, enable == 0, 1, timeout)) { 481 dev_err(cmdq->mbox.dev, "Fail to wait GCE thread 0x%x done\n", 482 (u32)(thread->base - cmdq->base)); 483 484 return -EFAULT; 485 } 486 return 0; 487 } 488 489 static const struct mbox_chan_ops cmdq_mbox_chan_ops = { 490 .send_data = cmdq_mbox_send_data, 491 .startup = cmdq_mbox_startup, 492 .shutdown = cmdq_mbox_shutdown, 493 .flush = cmdq_mbox_flush, 494 }; 495 496 static struct mbox_chan *cmdq_xlate(struct mbox_controller *mbox, 497 const struct of_phandle_args *sp) 498 { 499 int ind = sp->args[0]; 500 struct cmdq_thread *thread; 501 502 if (ind >= mbox->num_chans) 503 return ERR_PTR(-EINVAL); 504 505 thread = (struct cmdq_thread *)mbox->chans[ind].con_priv; 506 thread->priority = sp->args[1]; 507 thread->chan = &mbox->chans[ind]; 508 509 return &mbox->chans[ind]; 510 } 511 512 static int cmdq_probe(struct platform_device *pdev) 513 { 514 struct device *dev = &pdev->dev; 515 struct resource *res; 516 struct cmdq *cmdq; 517 int err, i; 518 struct gce_plat *plat_data; 519 520 cmdq = devm_kzalloc(dev, sizeof(*cmdq), GFP_KERNEL); 521 if (!cmdq) 522 return -ENOMEM; 523 524 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 525 cmdq->base = devm_ioremap_resource(dev, res); 526 if (IS_ERR(cmdq->base)) 527 return PTR_ERR(cmdq->base); 528 529 cmdq->irq = platform_get_irq(pdev, 0); 530 if (cmdq->irq < 0) 531 return cmdq->irq; 532 533 plat_data = (struct gce_plat *)of_device_get_match_data(dev); 534 if (!plat_data) { 535 dev_err(dev, "failed to get match data\n"); 536 return -EINVAL; 537 } 538 539 cmdq->thread_nr = plat_data->thread_nr; 540 cmdq->shift_pa = plat_data->shift; 541 cmdq->irq_mask = GENMASK(cmdq->thread_nr - 1, 0); 542 err = devm_request_irq(dev, cmdq->irq, cmdq_irq_handler, IRQF_SHARED, 543 "mtk_cmdq", cmdq); 544 if (err < 0) { 545 dev_err(dev, "failed to register ISR (%d)\n", err); 546 return err; 547 } 548 549 dev_dbg(dev, "cmdq device: addr:0x%p, va:0x%p, irq:%d\n", 550 dev, cmdq->base, cmdq->irq); 551 552 cmdq->clock = devm_clk_get(dev, "gce"); 553 if (IS_ERR(cmdq->clock)) { 554 dev_err(dev, "failed to get gce clk\n"); 555 return PTR_ERR(cmdq->clock); 556 } 557 558 cmdq->mbox.dev = dev; 559 cmdq->mbox.chans = devm_kcalloc(dev, cmdq->thread_nr, 560 sizeof(*cmdq->mbox.chans), GFP_KERNEL); 561 if (!cmdq->mbox.chans) 562 return -ENOMEM; 563 564 cmdq->mbox.num_chans = cmdq->thread_nr; 565 cmdq->mbox.ops = &cmdq_mbox_chan_ops; 566 cmdq->mbox.of_xlate = cmdq_xlate; 567 568 /* make use of TXDONE_BY_ACK */ 569 cmdq->mbox.txdone_irq = false; 570 cmdq->mbox.txdone_poll = false; 571 572 cmdq->thread = devm_kcalloc(dev, cmdq->thread_nr, 573 sizeof(*cmdq->thread), GFP_KERNEL); 574 if (!cmdq->thread) 575 return -ENOMEM; 576 577 for (i = 0; i < cmdq->thread_nr; i++) { 578 cmdq->thread[i].base = cmdq->base + CMDQ_THR_BASE + 579 CMDQ_THR_SIZE * i; 580 INIT_LIST_HEAD(&cmdq->thread[i].task_busy_list); 581 cmdq->mbox.chans[i].con_priv = (void *)&cmdq->thread[i]; 582 } 583 584 err = devm_mbox_controller_register(dev, &cmdq->mbox); 585 if (err < 0) { 586 dev_err(dev, "failed to register mailbox: %d\n", err); 587 return err; 588 } 589 590 platform_set_drvdata(pdev, cmdq); 591 WARN_ON(clk_prepare(cmdq->clock) < 0); 592 593 cmdq_init(cmdq); 594 595 return 0; 596 } 597 598 static const struct dev_pm_ops cmdq_pm_ops = { 599 .suspend = cmdq_suspend, 600 .resume = cmdq_resume, 601 }; 602 603 static const struct gce_plat gce_plat_v2 = {.thread_nr = 16}; 604 static const struct gce_plat gce_plat_v3 = {.thread_nr = 24}; 605 static const struct gce_plat gce_plat_v4 = {.thread_nr = 24, .shift = 3}; 606 607 static const struct of_device_id cmdq_of_ids[] = { 608 {.compatible = "mediatek,mt8173-gce", .data = (void *)&gce_plat_v2}, 609 {.compatible = "mediatek,mt8183-gce", .data = (void *)&gce_plat_v3}, 610 {.compatible = "mediatek,mt6779-gce", .data = (void *)&gce_plat_v4}, 611 {} 612 }; 613 614 static struct platform_driver cmdq_drv = { 615 .probe = cmdq_probe, 616 .remove = cmdq_remove, 617 .driver = { 618 .name = "mtk_cmdq", 619 .pm = &cmdq_pm_ops, 620 .of_match_table = cmdq_of_ids, 621 } 622 }; 623 624 static int __init cmdq_drv_init(void) 625 { 626 return platform_driver_register(&cmdq_drv); 627 } 628 629 static void __exit cmdq_drv_exit(void) 630 { 631 platform_driver_unregister(&cmdq_drv); 632 } 633 634 subsys_initcall(cmdq_drv_init); 635 module_exit(cmdq_drv_exit); 636 637 MODULE_LICENSE("GPL v2"); 638