xref: /openbmc/linux/drivers/mailbox/Kconfig (revision be7f8012) 
1# SPDX-License-Identifier: GPL-2.0-only
2menuconfig MAILBOX
3	bool "Mailbox Hardware Support"
4	help
5	  Mailbox is a framework to control hardware communication between
6	  on-chip processors through queued messages and interrupt driven
7	  signals. Say Y if your platform supports hardware mailboxes.
8
9if MAILBOX
10
11config APPLE_MAILBOX
12	tristate "Apple Mailbox driver"
13	depends on ARCH_APPLE || (ARM64 && COMPILE_TEST)
14	default ARCH_APPLE
15	help
16	  Apple SoCs have various co-processors required for certain
17	  peripherals to work (NVMe, display controller, etc.). This
18	  driver adds support for the mailbox controller used to
19	  communicate with those.
20
21	  Say Y here if you have a Apple SoC.
22
23config ARM_MHU
24	tristate "ARM MHU Mailbox"
25	depends on ARM_AMBA
26	help
27	  Say Y here if you want to build the ARM MHU controller driver.
28	  The controller has 3 mailbox channels, the last of which can be
29	  used in Secure mode only.
30
31config ARM_MHU_V2
32	tristate "ARM MHUv2 Mailbox"
33	depends on ARM_AMBA
34	help
35	  Say Y here if you want to build the ARM MHUv2 controller driver,
36	  which provides unidirectional mailboxes between processing elements.
37
38config IMX_MBOX
39	tristate "i.MX Mailbox"
40	depends on ARCH_MXC || COMPILE_TEST
41	help
42	  Mailbox implementation for i.MX Messaging Unit (MU).
43
44config PLATFORM_MHU
45	tristate "Platform MHU Mailbox"
46	depends on OF
47	depends on HAS_IOMEM
48	help
49	  Say Y here if you want to build a platform specific variant MHU
50	  controller driver.
51	  The controller has a maximum of 3 mailbox channels, the last of
52	  which can be used in Secure mode only.
53
54config PL320_MBOX
55	bool "ARM PL320 Mailbox"
56	depends on ARM_AMBA
57	help
58	  An implementation of the ARM PL320 Interprocessor Communication
59	  Mailbox (IPCM), tailored for the Calxeda Highbank. It is used to
60	  send short messages between Highbank's A9 cores and the EnergyCore
61	  Management Engine, primarily for cpufreq. Say Y here if you want
62	  to use the PL320 IPCM support.
63
64config ARMADA_37XX_RWTM_MBOX
65	tristate "Armada 37xx rWTM BIU Mailbox"
66	depends on ARCH_MVEBU || COMPILE_TEST
67	depends on OF
68	help
69	  Mailbox implementation for communication with the the firmware
70	  running on the Cortex-M3 rWTM secure processor of the Armada 37xx
71	  SOC. Say Y here if you are building for such a device (for example
72	  the Turris Mox router).
73
74config OMAP2PLUS_MBOX
75	tristate "OMAP2+ Mailbox framework support"
76	depends on ARCH_OMAP2PLUS || ARCH_K3
77	help
78	  Mailbox implementation for OMAP family chips with hardware for
79	  interprocessor communication involving DSP, IVA1.0 and IVA2 in
80	  OMAP2/3; or IPU, IVA HD and DSP in OMAP4/5. Say Y here if you
81	  want to use OMAP2+ Mailbox framework support.
82
83config OMAP_MBOX_KFIFO_SIZE
84	int "Mailbox kfifo default buffer size (bytes)"
85	depends on OMAP2PLUS_MBOX
86	default 256
87	help
88	  Specify the default size of mailbox's kfifo buffers (bytes).
89	  This can also be changed at runtime (via the mbox_kfifo_size
90	  module parameter).
91
92config ROCKCHIP_MBOX
93	bool "Rockchip Soc Integrated Mailbox Support"
94	depends on ARCH_ROCKCHIP || COMPILE_TEST
95	help
96	  This driver provides support for inter-processor communication
97	  between CPU cores and MCU processor on Some Rockchip SOCs.
98	  Please check it that the Soc you use have Mailbox hardware.
99	  Say Y here if you want to use the Rockchip Mailbox support.
100
101config PCC
102	bool "Platform Communication Channel Driver"
103	depends on ACPI
104	default n
105	help
106	  ACPI 5.0+ spec defines a generic mode of communication
107	  between the OS and a platform such as the BMC. This medium
108	  (PCC) is typically used by CPPC (ACPI CPU Performance management),
109	  RAS (ACPI reliability protocol) and MPST (ACPI Memory power
110	  states). Select this driver if your platform implements the
111	  PCC clients mentioned above.
112
113config ALTERA_MBOX
114	tristate "Altera Mailbox"
115	depends on HAS_IOMEM
116	help
117	  An implementation of the Altera Mailbox soft core. It is used
118	  to send message between processors. Say Y here if you want to use the
119	  Altera mailbox support.
120
121config BCM2835_MBOX
122	tristate "BCM2835 Mailbox"
123	depends on ARCH_BCM2835
124	help
125	  An implementation of the BCM2385 Mailbox.  It is used to invoke
126	  the services of the Videocore. Say Y here if you want to use the
127	  BCM2835 Mailbox.
128
129config STI_MBOX
130	tristate "STI Mailbox framework support"
131	depends on ARCH_STI && OF
132	help
133	  Mailbox implementation for STMicroelectonics family chips with
134	  hardware for interprocessor communication.
135
136config TI_MESSAGE_MANAGER
137	tristate "Texas Instruments Message Manager Driver"
138	depends on ARCH_KEYSTONE || ARCH_K3
139	default ARCH_K3
140	help
141	  An implementation of Message Manager slave driver for Keystone
142	  and K3 architecture SoCs from Texas Instruments. Message Manager
143	  is a communication entity found on few of Texas Instrument's keystone
144	  and K3 architecture SoCs. These may be used for communication between
145	  multiple processors within the SoC. Select this driver if your
146	  platform has support for the hardware block.
147
148config HI3660_MBOX
149	tristate "Hi3660 Mailbox" if EXPERT
150	depends on (ARCH_HISI || COMPILE_TEST)
151	depends on OF
152	default ARCH_HISI
153	help
154	  An implementation of the hi3660 mailbox. It is used to send message
155	  between application processors and other processors/MCU/DSP. Select
156	  Y here if you want to use Hi3660 mailbox controller.
157
158config HI6220_MBOX
159	tristate "Hi6220 Mailbox" if EXPERT
160	depends on (ARCH_HISI || COMPILE_TEST)
161	depends on OF
162	default ARCH_HISI
163	help
164	  An implementation of the hi6220 mailbox. It is used to send message
165	  between application processors and MCU. Say Y here if you want to
166	  build Hi6220 mailbox controller driver.
167
168config MAILBOX_TEST
169	tristate "Mailbox Test Client"
170	depends on OF
171	depends on HAS_IOMEM
172	help
173	  Test client to help with testing new Controller driver
174	  implementations.
175
176config POLARFIRE_SOC_MAILBOX
177	tristate "PolarFire SoC (MPFS) Mailbox"
178	depends on HAS_IOMEM
179	depends on ARCH_MICROCHIP_POLARFIRE || COMPILE_TEST
180	help
181	  This driver adds support for the PolarFire SoC (MPFS) mailbox controller.
182
183	  To compile this driver as a module, choose M here. the
184	  module will be called mailbox-mpfs.
185
186	  If unsure, say N.
187
188config QCOM_APCS_IPC
189	tristate "Qualcomm APCS IPC driver"
190	depends on ARCH_QCOM || COMPILE_TEST
191	help
192	  Say y here to enable support for the APCS IPC mailbox driver,
193	  providing an interface for invoking the inter-process communication
194	  signals from the application processor to other masters.
195
196config TEGRA_HSP_MBOX
197	bool "Tegra HSP (Hardware Synchronization Primitives) Driver"
198	depends on ARCH_TEGRA
199	help
200	  The Tegra HSP driver is used for the interprocessor communication
201	  between different remote processors and host processors on Tegra186
202	  and later SoCs. Say Y here if you want to have this support.
203	  If unsure say N.
204
205config XGENE_SLIMPRO_MBOX
206	tristate "APM SoC X-Gene SLIMpro Mailbox Controller"
207	depends on ARCH_XGENE
208	help
209	  An implementation of the APM X-Gene Interprocessor Communication
210	  Mailbox (IPCM) between the ARM 64-bit cores and SLIMpro controller.
211	  It is used to send short messages between ARM64-bit cores and
212	  the SLIMpro Management Engine, primarily for PM. Say Y here if you
213	  want to use the APM X-Gene SLIMpro IPCM support.
214
215config BCM_PDC_MBOX
216	tristate "Broadcom FlexSparx DMA Mailbox"
217	depends on ARCH_BCM_IPROC || COMPILE_TEST
218	help
219	  Mailbox implementation for the Broadcom FlexSparx DMA ring manager,
220	  which provides access to various offload engines on Broadcom
221	  SoCs, including FA2/FA+ on Northstar Plus and PDC on Northstar 2.
222
223config BCM_FLEXRM_MBOX
224	tristate "Broadcom FlexRM Mailbox"
225	depends on ARM64
226	depends on ARCH_BCM_IPROC || COMPILE_TEST
227	select GENERIC_MSI_IRQ
228	default m if ARCH_BCM_IPROC
229	help
230	  Mailbox implementation of the Broadcom FlexRM ring manager,
231	  which provides access to various offload engines on Broadcom
232	  SoCs. Say Y here if you want to use the Broadcom FlexRM.
233
234config STM32_IPCC
235	tristate "STM32 IPCC Mailbox"
236	depends on MACH_STM32MP157 || COMPILE_TEST
237	help
238	  Mailbox implementation for STMicroelectonics STM32 family chips
239	  with hardware for Inter-Processor Communication Controller (IPCC)
240	  between processors. Say Y here if you want to have this support.
241
242config MTK_ADSP_MBOX
243	tristate "MediaTek ADSP Mailbox Controller"
244	depends on ARCH_MEDIATEK || COMPILE_TEST
245	help
246          Say yes here to add support for "MediaTek ADSP Mailbox Controller.
247          This mailbox driver is used to send notification or short message
248          between processors with ADSP. It will place the message to share
249	  buffer and will access the ipc control.
250
251config MTK_CMDQ_MBOX
252	tristate "MediaTek CMDQ Mailbox Support"
253	depends on ARCH_MEDIATEK || COMPILE_TEST
254	select MTK_INFRACFG
255	help
256	  Say yes here to add support for the MediaTek Command Queue (CMDQ)
257	  mailbox driver. The CMDQ is used to help read/write registers with
258	  critical time limitation, such as updating display configuration
259	  during the vblank.
260
261config ZYNQMP_IPI_MBOX
262	tristate "Xilinx ZynqMP IPI Mailbox"
263	depends on ARCH_ZYNQMP && OF
264	help
265	  Say yes here to add support for Xilinx IPI mailbox driver.
266	  This mailbox driver is used to send notification or short message
267	  between processors with Xilinx ZynqMP IPI. It will place the
268	  message to the IPI buffer and will access the IPI control
269	  registers to kick the other processor or enquire status.
270
271config SUN6I_MSGBOX
272	tristate "Allwinner sun6i/sun8i/sun9i/sun50i Message Box"
273	depends on ARCH_SUNXI || COMPILE_TEST
274	default ARCH_SUNXI
275	help
276	  Mailbox implementation for the hardware message box present in
277	  various Allwinner SoCs. This mailbox is used for communication
278	  between the application CPUs and the power management coprocessor.
279
280config SPRD_MBOX
281	tristate "Spreadtrum Mailbox"
282	depends on ARCH_SPRD || COMPILE_TEST
283	help
284	  Mailbox driver implementation for the Spreadtrum platform. It is used
285	  to send message between application processors and MCU. Say Y here if
286	  you want to build the Spreatrum mailbox controller driver.
287
288config QCOM_IPCC
289	tristate "Qualcomm Technologies, Inc. IPCC driver"
290	depends on ARCH_QCOM || COMPILE_TEST
291	help
292	  Qualcomm Technologies, Inc. Inter-Processor Communication Controller
293	  (IPCC) driver for MSM devices. The driver provides mailbox support for
294	  sending interrupts to the clients. On the other hand, the driver also
295	  acts as an interrupt controller for receiving interrupts from clients.
296	  Say Y here if you want to build this driver.
297
298endif
299