1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2017-2022 Linaro Ltd
4 * Copyright (c) 2010-2012, The Linux Foundation. All rights reserved.
5 * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
6 */
7 #include <linux/bits.h>
8 #include <linux/bitfield.h>
9 #include <linux/led-class-multicolor.h>
10 #include <linux/module.h>
11 #include <linux/of.h>
12 #include <linux/platform_device.h>
13 #include <linux/pwm.h>
14 #include <linux/regmap.h>
15 #include <linux/slab.h>
16
17 #define LPG_SUBTYPE_REG 0x05
18 #define LPG_SUBTYPE_LPG 0x2
19 #define LPG_SUBTYPE_PWM 0xb
20 #define LPG_SUBTYPE_HI_RES_PWM 0xc
21 #define LPG_SUBTYPE_LPG_LITE 0x11
22 #define LPG_PATTERN_CONFIG_REG 0x40
23 #define LPG_SIZE_CLK_REG 0x41
24 #define PWM_CLK_SELECT_MASK GENMASK(1, 0)
25 #define PWM_CLK_SELECT_HI_RES_MASK GENMASK(2, 0)
26 #define PWM_SIZE_HI_RES_MASK GENMASK(6, 4)
27 #define LPG_PREDIV_CLK_REG 0x42
28 #define PWM_FREQ_PRE_DIV_MASK GENMASK(6, 5)
29 #define PWM_FREQ_EXP_MASK GENMASK(2, 0)
30 #define PWM_TYPE_CONFIG_REG 0x43
31 #define PWM_VALUE_REG 0x44
32 #define PWM_ENABLE_CONTROL_REG 0x46
33 #define PWM_SYNC_REG 0x47
34 #define LPG_RAMP_DURATION_REG 0x50
35 #define LPG_HI_PAUSE_REG 0x52
36 #define LPG_LO_PAUSE_REG 0x54
37 #define LPG_HI_IDX_REG 0x56
38 #define LPG_LO_IDX_REG 0x57
39 #define PWM_SEC_ACCESS_REG 0xd0
40 #define PWM_DTEST_REG(x) (0xe2 + (x) - 1)
41
42 #define TRI_LED_SRC_SEL 0x45
43 #define TRI_LED_EN_CTL 0x46
44 #define TRI_LED_ATC_CTL 0x47
45
46 #define LPG_LUT_REG(x) (0x40 + (x) * 2)
47 #define RAMP_CONTROL_REG 0xc8
48
49 #define LPG_RESOLUTION_9BIT BIT(9)
50 #define LPG_RESOLUTION_15BIT BIT(15)
51 #define LPG_MAX_M 7
52 #define LPG_MAX_PREDIV 6
53
54 struct lpg_channel;
55 struct lpg_data;
56
57 /**
58 * struct lpg - LPG device context
59 * @dev: pointer to LPG device
60 * @map: regmap for register access
61 * @lock: used to synchronize LED and pwm callback requests
62 * @pwm: PWM-chip object, if operating in PWM mode
63 * @data: reference to version specific data
64 * @lut_base: base address of the LUT block (optional)
65 * @lut_size: number of entries in the LUT block
66 * @lut_bitmap: allocation bitmap for LUT entries
67 * @triled_base: base address of the TRILED block (optional)
68 * @triled_src: power-source for the TRILED
69 * @triled_has_atc_ctl: true if there is TRI_LED_ATC_CTL register
70 * @triled_has_src_sel: true if there is TRI_LED_SRC_SEL register
71 * @channels: list of PWM channels
72 * @num_channels: number of @channels
73 */
74 struct lpg {
75 struct device *dev;
76 struct regmap *map;
77
78 struct mutex lock;
79
80 struct pwm_chip pwm;
81
82 const struct lpg_data *data;
83
84 u32 lut_base;
85 u32 lut_size;
86 unsigned long *lut_bitmap;
87
88 u32 triled_base;
89 u32 triled_src;
90 bool triled_has_atc_ctl;
91 bool triled_has_src_sel;
92
93 struct lpg_channel *channels;
94 unsigned int num_channels;
95 };
96
97 /**
98 * struct lpg_channel - per channel data
99 * @lpg: reference to parent lpg
100 * @base: base address of the PWM channel
101 * @triled_mask: mask in TRILED to enable this channel
102 * @lut_mask: mask in LUT to start pattern generator for this channel
103 * @subtype: PMIC hardware block subtype
104 * @in_use: channel is exposed to LED framework
105 * @color: color of the LED attached to this channel
106 * @dtest_line: DTEST line for output, or 0 if disabled
107 * @dtest_value: DTEST line configuration
108 * @pwm_value: duty (in microseconds) of the generated pulses, overridden by LUT
109 * @enabled: output enabled?
110 * @period: period (in nanoseconds) of the generated pulses
111 * @clk_sel: reference clock frequency selector
112 * @pre_div_sel: divider selector of the reference clock
113 * @pre_div_exp: exponential divider of the reference clock
114 * @pwm_resolution_sel: pwm resolution selector
115 * @ramp_enabled: duty cycle is driven by iterating over lookup table
116 * @ramp_ping_pong: reverse through pattern, rather than wrapping to start
117 * @ramp_oneshot: perform only a single pass over the pattern
118 * @ramp_reverse: iterate over pattern backwards
119 * @ramp_tick_ms: length (in milliseconds) of one step in the pattern
120 * @ramp_lo_pause_ms: pause (in milliseconds) before iterating over pattern
121 * @ramp_hi_pause_ms: pause (in milliseconds) after iterating over pattern
122 * @pattern_lo_idx: start index of associated pattern
123 * @pattern_hi_idx: last index of associated pattern
124 */
125 struct lpg_channel {
126 struct lpg *lpg;
127
128 u32 base;
129 unsigned int triled_mask;
130 unsigned int lut_mask;
131 unsigned int subtype;
132
133 bool in_use;
134
135 int color;
136
137 u32 dtest_line;
138 u32 dtest_value;
139
140 u16 pwm_value;
141 bool enabled;
142
143 u64 period;
144 unsigned int clk_sel;
145 unsigned int pre_div_sel;
146 unsigned int pre_div_exp;
147 unsigned int pwm_resolution_sel;
148
149 bool ramp_enabled;
150 bool ramp_ping_pong;
151 bool ramp_oneshot;
152 bool ramp_reverse;
153 unsigned short ramp_tick_ms;
154 unsigned long ramp_lo_pause_ms;
155 unsigned long ramp_hi_pause_ms;
156
157 unsigned int pattern_lo_idx;
158 unsigned int pattern_hi_idx;
159 };
160
161 /**
162 * struct lpg_led - logical LED object
163 * @lpg: lpg context reference
164 * @cdev: LED class device
165 * @mcdev: Multicolor LED class device
166 * @num_channels: number of @channels
167 * @channels: list of channels associated with the LED
168 */
169 struct lpg_led {
170 struct lpg *lpg;
171
172 struct led_classdev cdev;
173 struct led_classdev_mc mcdev;
174
175 unsigned int num_channels;
176 struct lpg_channel *channels[];
177 };
178
179 /**
180 * struct lpg_channel_data - per channel initialization data
181 * @base: base address for PWM channel registers
182 * @triled_mask: bitmask for controlling this channel in TRILED
183 */
184 struct lpg_channel_data {
185 unsigned int base;
186 u8 triled_mask;
187 };
188
189 /**
190 * struct lpg_data - initialization data
191 * @lut_base: base address of LUT block
192 * @lut_size: number of entries in LUT
193 * @triled_base: base address of TRILED
194 * @triled_has_atc_ctl: true if there is TRI_LED_ATC_CTL register
195 * @triled_has_src_sel: true if there is TRI_LED_SRC_SEL register
196 * @num_channels: number of channels in LPG
197 * @channels: list of channel initialization data
198 */
199 struct lpg_data {
200 unsigned int lut_base;
201 unsigned int lut_size;
202 unsigned int triled_base;
203 bool triled_has_atc_ctl;
204 bool triled_has_src_sel;
205 int num_channels;
206 const struct lpg_channel_data *channels;
207 };
208
triled_set(struct lpg * lpg,unsigned int mask,unsigned int enable)209 static int triled_set(struct lpg *lpg, unsigned int mask, unsigned int enable)
210 {
211 /* Skip if we don't have a triled block */
212 if (!lpg->triled_base)
213 return 0;
214
215 return regmap_update_bits(lpg->map, lpg->triled_base + TRI_LED_EN_CTL,
216 mask, enable);
217 }
218
lpg_lut_store(struct lpg * lpg,struct led_pattern * pattern,size_t len,unsigned int * lo_idx,unsigned int * hi_idx)219 static int lpg_lut_store(struct lpg *lpg, struct led_pattern *pattern,
220 size_t len, unsigned int *lo_idx, unsigned int *hi_idx)
221 {
222 unsigned int idx;
223 u16 val;
224 int i;
225
226 idx = bitmap_find_next_zero_area(lpg->lut_bitmap, lpg->lut_size,
227 0, len, 0);
228 if (idx >= lpg->lut_size)
229 return -ENOMEM;
230
231 for (i = 0; i < len; i++) {
232 val = pattern[i].brightness;
233
234 regmap_bulk_write(lpg->map, lpg->lut_base + LPG_LUT_REG(idx + i),
235 &val, sizeof(val));
236 }
237
238 bitmap_set(lpg->lut_bitmap, idx, len);
239
240 *lo_idx = idx;
241 *hi_idx = idx + len - 1;
242
243 return 0;
244 }
245
lpg_lut_free(struct lpg * lpg,unsigned int lo_idx,unsigned int hi_idx)246 static void lpg_lut_free(struct lpg *lpg, unsigned int lo_idx, unsigned int hi_idx)
247 {
248 int len;
249
250 len = hi_idx - lo_idx + 1;
251 if (len == 1)
252 return;
253
254 bitmap_clear(lpg->lut_bitmap, lo_idx, len);
255 }
256
lpg_lut_sync(struct lpg * lpg,unsigned int mask)257 static int lpg_lut_sync(struct lpg *lpg, unsigned int mask)
258 {
259 return regmap_write(lpg->map, lpg->lut_base + RAMP_CONTROL_REG, mask);
260 }
261
262 static const unsigned int lpg_clk_rates[] = {0, 1024, 32768, 19200000};
263 static const unsigned int lpg_clk_rates_hi_res[] = {0, 1024, 32768, 19200000, 76800000};
264 static const unsigned int lpg_pre_divs[] = {1, 3, 5, 6};
265 static const unsigned int lpg_pwm_resolution[] = {9};
266 static const unsigned int lpg_pwm_resolution_hi_res[] = {8, 9, 10, 11, 12, 13, 14, 15};
267
lpg_calc_freq(struct lpg_channel * chan,uint64_t period)268 static int lpg_calc_freq(struct lpg_channel *chan, uint64_t period)
269 {
270 unsigned int i, pwm_resolution_count, best_pwm_resolution_sel = 0;
271 const unsigned int *clk_rate_arr, *pwm_resolution_arr;
272 unsigned int clk_sel, clk_len, best_clk = 0;
273 unsigned int div, best_div = 0;
274 unsigned int m, best_m = 0;
275 unsigned int resolution;
276 unsigned int error;
277 unsigned int best_err = UINT_MAX;
278 u64 max_period, min_period;
279 u64 best_period = 0;
280 u64 max_res;
281
282 /*
283 * The PWM period is determined by:
284 *
285 * resolution * pre_div * 2^M
286 * period = --------------------------
287 * refclk
288 *
289 * Resolution = 2^9 bits for PWM or
290 * 2^{8, 9, 10, 11, 12, 13, 14, 15} bits for high resolution PWM
291 * pre_div = {1, 3, 5, 6} and
292 * M = [0..7].
293 *
294 * This allows for periods between 27uS and 384s for PWM channels and periods between
295 * 3uS and 24576s for high resolution PWMs.
296 * The PWM framework wants a period of equal or lower length than requested,
297 * reject anything below minimum period.
298 */
299
300 if (chan->subtype == LPG_SUBTYPE_HI_RES_PWM) {
301 clk_rate_arr = lpg_clk_rates_hi_res;
302 clk_len = ARRAY_SIZE(lpg_clk_rates_hi_res);
303 pwm_resolution_arr = lpg_pwm_resolution_hi_res;
304 pwm_resolution_count = ARRAY_SIZE(lpg_pwm_resolution_hi_res);
305 max_res = LPG_RESOLUTION_15BIT;
306 } else {
307 clk_rate_arr = lpg_clk_rates;
308 clk_len = ARRAY_SIZE(lpg_clk_rates);
309 pwm_resolution_arr = lpg_pwm_resolution;
310 pwm_resolution_count = ARRAY_SIZE(lpg_pwm_resolution);
311 max_res = LPG_RESOLUTION_9BIT;
312 }
313
314 min_period = div64_u64((u64)NSEC_PER_SEC * (1 << pwm_resolution_arr[0]),
315 clk_rate_arr[clk_len - 1]);
316 if (period <= min_period)
317 return -EINVAL;
318
319 /* Limit period to largest possible value, to avoid overflows */
320 max_period = div64_u64((u64)NSEC_PER_SEC * max_res * LPG_MAX_PREDIV * (1 << LPG_MAX_M),
321 1024);
322 if (period > max_period)
323 period = max_period;
324
325 /*
326 * Search for the pre_div, refclk, resolution and M by solving the rewritten formula
327 * for each refclk, resolution and pre_div value:
328 *
329 * period * refclk
330 * M = log2 -------------------------------------
331 * NSEC_PER_SEC * pre_div * resolution
332 */
333
334 for (i = 0; i < pwm_resolution_count; i++) {
335 resolution = 1 << pwm_resolution_arr[i];
336 for (clk_sel = 1; clk_sel < clk_len; clk_sel++) {
337 u64 numerator = period * clk_rate_arr[clk_sel];
338
339 for (div = 0; div < ARRAY_SIZE(lpg_pre_divs); div++) {
340 u64 denominator = (u64)NSEC_PER_SEC * lpg_pre_divs[div] *
341 resolution;
342 u64 actual;
343 u64 ratio;
344
345 if (numerator < denominator)
346 continue;
347
348 ratio = div64_u64(numerator, denominator);
349 m = ilog2(ratio);
350 if (m > LPG_MAX_M)
351 m = LPG_MAX_M;
352
353 actual = DIV_ROUND_UP_ULL(denominator * (1 << m),
354 clk_rate_arr[clk_sel]);
355 error = period - actual;
356 if (error < best_err) {
357 best_err = error;
358 best_div = div;
359 best_m = m;
360 best_clk = clk_sel;
361 best_period = actual;
362 best_pwm_resolution_sel = i;
363 }
364 }
365 }
366 }
367 chan->clk_sel = best_clk;
368 chan->pre_div_sel = best_div;
369 chan->pre_div_exp = best_m;
370 chan->period = best_period;
371 chan->pwm_resolution_sel = best_pwm_resolution_sel;
372 return 0;
373 }
374
lpg_calc_duty(struct lpg_channel * chan,uint64_t duty)375 static void lpg_calc_duty(struct lpg_channel *chan, uint64_t duty)
376 {
377 unsigned int max;
378 unsigned int val;
379 unsigned int clk_rate;
380
381 if (chan->subtype == LPG_SUBTYPE_HI_RES_PWM) {
382 max = LPG_RESOLUTION_15BIT - 1;
383 clk_rate = lpg_clk_rates_hi_res[chan->clk_sel];
384 } else {
385 max = LPG_RESOLUTION_9BIT - 1;
386 clk_rate = lpg_clk_rates[chan->clk_sel];
387 }
388
389 val = div64_u64(duty * clk_rate,
390 (u64)NSEC_PER_SEC * lpg_pre_divs[chan->pre_div_sel] * (1 << chan->pre_div_exp));
391
392 chan->pwm_value = min(val, max);
393 }
394
lpg_apply_freq(struct lpg_channel * chan)395 static void lpg_apply_freq(struct lpg_channel *chan)
396 {
397 unsigned long val;
398 struct lpg *lpg = chan->lpg;
399
400 if (!chan->enabled)
401 return;
402
403 val = chan->clk_sel;
404
405 /* Specify resolution, based on the subtype of the channel */
406 switch (chan->subtype) {
407 case LPG_SUBTYPE_LPG:
408 val |= GENMASK(5, 4);
409 break;
410 case LPG_SUBTYPE_PWM:
411 val |= BIT(2);
412 break;
413 case LPG_SUBTYPE_HI_RES_PWM:
414 val |= FIELD_PREP(PWM_SIZE_HI_RES_MASK, chan->pwm_resolution_sel);
415 break;
416 case LPG_SUBTYPE_LPG_LITE:
417 default:
418 val |= BIT(4);
419 break;
420 }
421
422 regmap_write(lpg->map, chan->base + LPG_SIZE_CLK_REG, val);
423
424 val = FIELD_PREP(PWM_FREQ_PRE_DIV_MASK, chan->pre_div_sel) |
425 FIELD_PREP(PWM_FREQ_EXP_MASK, chan->pre_div_exp);
426 regmap_write(lpg->map, chan->base + LPG_PREDIV_CLK_REG, val);
427 }
428
429 #define LPG_ENABLE_GLITCH_REMOVAL BIT(5)
430
lpg_enable_glitch(struct lpg_channel * chan)431 static void lpg_enable_glitch(struct lpg_channel *chan)
432 {
433 struct lpg *lpg = chan->lpg;
434
435 regmap_update_bits(lpg->map, chan->base + PWM_TYPE_CONFIG_REG,
436 LPG_ENABLE_GLITCH_REMOVAL, 0);
437 }
438
lpg_disable_glitch(struct lpg_channel * chan)439 static void lpg_disable_glitch(struct lpg_channel *chan)
440 {
441 struct lpg *lpg = chan->lpg;
442
443 regmap_update_bits(lpg->map, chan->base + PWM_TYPE_CONFIG_REG,
444 LPG_ENABLE_GLITCH_REMOVAL,
445 LPG_ENABLE_GLITCH_REMOVAL);
446 }
447
lpg_apply_pwm_value(struct lpg_channel * chan)448 static void lpg_apply_pwm_value(struct lpg_channel *chan)
449 {
450 struct lpg *lpg = chan->lpg;
451 u16 val = chan->pwm_value;
452
453 if (!chan->enabled)
454 return;
455
456 regmap_bulk_write(lpg->map, chan->base + PWM_VALUE_REG, &val, sizeof(val));
457 }
458
459 #define LPG_PATTERN_CONFIG_LO_TO_HI BIT(4)
460 #define LPG_PATTERN_CONFIG_REPEAT BIT(3)
461 #define LPG_PATTERN_CONFIG_TOGGLE BIT(2)
462 #define LPG_PATTERN_CONFIG_PAUSE_HI BIT(1)
463 #define LPG_PATTERN_CONFIG_PAUSE_LO BIT(0)
464
lpg_apply_lut_control(struct lpg_channel * chan)465 static void lpg_apply_lut_control(struct lpg_channel *chan)
466 {
467 struct lpg *lpg = chan->lpg;
468 unsigned int hi_pause;
469 unsigned int lo_pause;
470 unsigned int conf = 0;
471 unsigned int lo_idx = chan->pattern_lo_idx;
472 unsigned int hi_idx = chan->pattern_hi_idx;
473 u16 step = chan->ramp_tick_ms;
474
475 if (!chan->ramp_enabled || chan->pattern_lo_idx == chan->pattern_hi_idx)
476 return;
477
478 hi_pause = DIV_ROUND_UP(chan->ramp_hi_pause_ms, step);
479 lo_pause = DIV_ROUND_UP(chan->ramp_lo_pause_ms, step);
480
481 if (!chan->ramp_reverse)
482 conf |= LPG_PATTERN_CONFIG_LO_TO_HI;
483 if (!chan->ramp_oneshot)
484 conf |= LPG_PATTERN_CONFIG_REPEAT;
485 if (chan->ramp_ping_pong)
486 conf |= LPG_PATTERN_CONFIG_TOGGLE;
487 if (chan->ramp_hi_pause_ms)
488 conf |= LPG_PATTERN_CONFIG_PAUSE_HI;
489 if (chan->ramp_lo_pause_ms)
490 conf |= LPG_PATTERN_CONFIG_PAUSE_LO;
491
492 regmap_write(lpg->map, chan->base + LPG_PATTERN_CONFIG_REG, conf);
493 regmap_write(lpg->map, chan->base + LPG_HI_IDX_REG, hi_idx);
494 regmap_write(lpg->map, chan->base + LPG_LO_IDX_REG, lo_idx);
495
496 regmap_bulk_write(lpg->map, chan->base + LPG_RAMP_DURATION_REG, &step, sizeof(step));
497 regmap_write(lpg->map, chan->base + LPG_HI_PAUSE_REG, hi_pause);
498 regmap_write(lpg->map, chan->base + LPG_LO_PAUSE_REG, lo_pause);
499 }
500
501 #define LPG_ENABLE_CONTROL_OUTPUT BIT(7)
502 #define LPG_ENABLE_CONTROL_BUFFER_TRISTATE BIT(5)
503 #define LPG_ENABLE_CONTROL_SRC_PWM BIT(2)
504 #define LPG_ENABLE_CONTROL_RAMP_GEN BIT(1)
505
lpg_apply_control(struct lpg_channel * chan)506 static void lpg_apply_control(struct lpg_channel *chan)
507 {
508 unsigned int ctrl;
509 struct lpg *lpg = chan->lpg;
510
511 ctrl = LPG_ENABLE_CONTROL_BUFFER_TRISTATE;
512
513 if (chan->enabled)
514 ctrl |= LPG_ENABLE_CONTROL_OUTPUT;
515
516 if (chan->pattern_lo_idx != chan->pattern_hi_idx)
517 ctrl |= LPG_ENABLE_CONTROL_RAMP_GEN;
518 else
519 ctrl |= LPG_ENABLE_CONTROL_SRC_PWM;
520
521 regmap_write(lpg->map, chan->base + PWM_ENABLE_CONTROL_REG, ctrl);
522
523 /*
524 * Due to LPG hardware bug, in the PWM mode, having enabled PWM,
525 * We have to write PWM values one more time.
526 */
527 if (chan->enabled)
528 lpg_apply_pwm_value(chan);
529 }
530
531 #define LPG_SYNC_PWM BIT(0)
532
lpg_apply_sync(struct lpg_channel * chan)533 static void lpg_apply_sync(struct lpg_channel *chan)
534 {
535 struct lpg *lpg = chan->lpg;
536
537 regmap_write(lpg->map, chan->base + PWM_SYNC_REG, LPG_SYNC_PWM);
538 }
539
lpg_parse_dtest(struct lpg * lpg)540 static int lpg_parse_dtest(struct lpg *lpg)
541 {
542 struct lpg_channel *chan;
543 struct device_node *np = lpg->dev->of_node;
544 int count;
545 int ret;
546 int i;
547
548 count = of_property_count_u32_elems(np, "qcom,dtest");
549 if (count == -EINVAL) {
550 return 0;
551 } else if (count < 0) {
552 ret = count;
553 goto err_malformed;
554 } else if (count != lpg->data->num_channels * 2) {
555 dev_err(lpg->dev, "qcom,dtest needs to be %d items\n",
556 lpg->data->num_channels * 2);
557 return -EINVAL;
558 }
559
560 for (i = 0; i < lpg->data->num_channels; i++) {
561 chan = &lpg->channels[i];
562
563 ret = of_property_read_u32_index(np, "qcom,dtest", i * 2,
564 &chan->dtest_line);
565 if (ret)
566 goto err_malformed;
567
568 ret = of_property_read_u32_index(np, "qcom,dtest", i * 2 + 1,
569 &chan->dtest_value);
570 if (ret)
571 goto err_malformed;
572 }
573
574 return 0;
575
576 err_malformed:
577 dev_err(lpg->dev, "malformed qcom,dtest\n");
578 return ret;
579 }
580
lpg_apply_dtest(struct lpg_channel * chan)581 static void lpg_apply_dtest(struct lpg_channel *chan)
582 {
583 struct lpg *lpg = chan->lpg;
584
585 if (!chan->dtest_line)
586 return;
587
588 regmap_write(lpg->map, chan->base + PWM_SEC_ACCESS_REG, 0xa5);
589 regmap_write(lpg->map, chan->base + PWM_DTEST_REG(chan->dtest_line),
590 chan->dtest_value);
591 }
592
lpg_apply(struct lpg_channel * chan)593 static void lpg_apply(struct lpg_channel *chan)
594 {
595 lpg_disable_glitch(chan);
596 lpg_apply_freq(chan);
597 lpg_apply_pwm_value(chan);
598 lpg_apply_control(chan);
599 lpg_apply_sync(chan);
600 lpg_apply_lut_control(chan);
601 lpg_enable_glitch(chan);
602 }
603
lpg_brightness_set(struct lpg_led * led,struct led_classdev * cdev,struct mc_subled * subleds)604 static void lpg_brightness_set(struct lpg_led *led, struct led_classdev *cdev,
605 struct mc_subled *subleds)
606 {
607 enum led_brightness brightness;
608 struct lpg_channel *chan;
609 unsigned int triled_enabled = 0;
610 unsigned int triled_mask = 0;
611 unsigned int lut_mask = 0;
612 unsigned int duty;
613 struct lpg *lpg = led->lpg;
614 int i;
615
616 for (i = 0; i < led->num_channels; i++) {
617 chan = led->channels[i];
618 brightness = subleds[i].brightness;
619
620 if (brightness == LED_OFF) {
621 chan->enabled = false;
622 chan->ramp_enabled = false;
623 } else if (chan->pattern_lo_idx != chan->pattern_hi_idx) {
624 lpg_calc_freq(chan, NSEC_PER_MSEC);
625
626 chan->enabled = true;
627 chan->ramp_enabled = true;
628
629 lut_mask |= chan->lut_mask;
630 triled_enabled |= chan->triled_mask;
631 } else {
632 lpg_calc_freq(chan, NSEC_PER_MSEC);
633
634 duty = div_u64(brightness * chan->period, cdev->max_brightness);
635 lpg_calc_duty(chan, duty);
636 chan->enabled = true;
637 chan->ramp_enabled = false;
638
639 triled_enabled |= chan->triled_mask;
640 }
641
642 triled_mask |= chan->triled_mask;
643
644 lpg_apply(chan);
645 }
646
647 /* Toggle triled lines */
648 if (triled_mask)
649 triled_set(lpg, triled_mask, triled_enabled);
650
651 /* Trigger start of ramp generator(s) */
652 if (lut_mask)
653 lpg_lut_sync(lpg, lut_mask);
654 }
655
lpg_brightness_single_set(struct led_classdev * cdev,enum led_brightness value)656 static int lpg_brightness_single_set(struct led_classdev *cdev,
657 enum led_brightness value)
658 {
659 struct lpg_led *led = container_of(cdev, struct lpg_led, cdev);
660 struct mc_subled info;
661
662 mutex_lock(&led->lpg->lock);
663
664 info.brightness = value;
665 lpg_brightness_set(led, cdev, &info);
666
667 mutex_unlock(&led->lpg->lock);
668
669 return 0;
670 }
671
lpg_brightness_mc_set(struct led_classdev * cdev,enum led_brightness value)672 static int lpg_brightness_mc_set(struct led_classdev *cdev,
673 enum led_brightness value)
674 {
675 struct led_classdev_mc *mc = lcdev_to_mccdev(cdev);
676 struct lpg_led *led = container_of(mc, struct lpg_led, mcdev);
677
678 mutex_lock(&led->lpg->lock);
679
680 led_mc_calc_color_components(mc, value);
681 lpg_brightness_set(led, cdev, mc->subled_info);
682
683 mutex_unlock(&led->lpg->lock);
684
685 return 0;
686 }
687
lpg_blink_set(struct lpg_led * led,unsigned long * delay_on,unsigned long * delay_off)688 static int lpg_blink_set(struct lpg_led *led,
689 unsigned long *delay_on, unsigned long *delay_off)
690 {
691 struct lpg_channel *chan;
692 unsigned int period;
693 unsigned int triled_mask = 0;
694 struct lpg *lpg = led->lpg;
695 u64 duty;
696 int i;
697
698 if (!*delay_on && !*delay_off) {
699 *delay_on = 500;
700 *delay_off = 500;
701 }
702
703 duty = *delay_on * NSEC_PER_MSEC;
704 period = (*delay_on + *delay_off) * NSEC_PER_MSEC;
705
706 for (i = 0; i < led->num_channels; i++) {
707 chan = led->channels[i];
708
709 lpg_calc_freq(chan, period);
710 lpg_calc_duty(chan, duty);
711
712 chan->enabled = true;
713 chan->ramp_enabled = false;
714
715 triled_mask |= chan->triled_mask;
716
717 lpg_apply(chan);
718 }
719
720 /* Enable triled lines */
721 triled_set(lpg, triled_mask, triled_mask);
722
723 chan = led->channels[0];
724 duty = div_u64(chan->pwm_value * chan->period, LPG_RESOLUTION_9BIT);
725 *delay_on = div_u64(duty, NSEC_PER_MSEC);
726 *delay_off = div_u64(chan->period - duty, NSEC_PER_MSEC);
727
728 return 0;
729 }
730
lpg_blink_single_set(struct led_classdev * cdev,unsigned long * delay_on,unsigned long * delay_off)731 static int lpg_blink_single_set(struct led_classdev *cdev,
732 unsigned long *delay_on, unsigned long *delay_off)
733 {
734 struct lpg_led *led = container_of(cdev, struct lpg_led, cdev);
735 int ret;
736
737 mutex_lock(&led->lpg->lock);
738
739 ret = lpg_blink_set(led, delay_on, delay_off);
740
741 mutex_unlock(&led->lpg->lock);
742
743 return ret;
744 }
745
lpg_blink_mc_set(struct led_classdev * cdev,unsigned long * delay_on,unsigned long * delay_off)746 static int lpg_blink_mc_set(struct led_classdev *cdev,
747 unsigned long *delay_on, unsigned long *delay_off)
748 {
749 struct led_classdev_mc *mc = lcdev_to_mccdev(cdev);
750 struct lpg_led *led = container_of(mc, struct lpg_led, mcdev);
751 int ret;
752
753 mutex_lock(&led->lpg->lock);
754
755 ret = lpg_blink_set(led, delay_on, delay_off);
756
757 mutex_unlock(&led->lpg->lock);
758
759 return ret;
760 }
761
lpg_pattern_set(struct lpg_led * led,struct led_pattern * led_pattern,u32 len,int repeat)762 static int lpg_pattern_set(struct lpg_led *led, struct led_pattern *led_pattern,
763 u32 len, int repeat)
764 {
765 struct lpg_channel *chan;
766 struct lpg *lpg = led->lpg;
767 struct led_pattern *pattern;
768 unsigned int brightness_a;
769 unsigned int brightness_b;
770 unsigned int actual_len;
771 unsigned int hi_pause;
772 unsigned int lo_pause;
773 unsigned int delta_t;
774 unsigned int lo_idx;
775 unsigned int hi_idx;
776 unsigned int i;
777 bool ping_pong = true;
778 int ret = -EINVAL;
779
780 /* Hardware only support oneshot or indefinite loops */
781 if (repeat != -1 && repeat != 1)
782 return -EINVAL;
783
784 /*
785 * The standardized leds-trigger-pattern format defines that the
786 * brightness of the LED follows a linear transition from one entry
787 * in the pattern to the next, over the given delta_t time. It
788 * describes that the way to perform instant transitions a zero-length
789 * entry should be added following a pattern entry.
790 *
791 * The LPG hardware is only able to perform the latter (no linear
792 * transitions), so require each entry in the pattern to be followed by
793 * a zero-length transition.
794 */
795 if (len % 2)
796 return -EINVAL;
797
798 pattern = kcalloc(len / 2, sizeof(*pattern), GFP_KERNEL);
799 if (!pattern)
800 return -ENOMEM;
801
802 for (i = 0; i < len; i += 2) {
803 if (led_pattern[i].brightness != led_pattern[i + 1].brightness)
804 goto out_free_pattern;
805 if (led_pattern[i + 1].delta_t != 0)
806 goto out_free_pattern;
807
808 pattern[i / 2].brightness = led_pattern[i].brightness;
809 pattern[i / 2].delta_t = led_pattern[i].delta_t;
810 }
811
812 len /= 2;
813
814 /*
815 * Specifying a pattern of length 1 causes the hardware to iterate
816 * through the entire LUT, so prohibit this.
817 */
818 if (len < 2)
819 goto out_free_pattern;
820
821 /*
822 * The LPG plays patterns with at a fixed pace, a "low pause" can be
823 * used to stretch the first delay of the pattern and a "high pause"
824 * the last one.
825 *
826 * In order to save space the pattern can be played in "ping pong"
827 * mode, in which the pattern is first played forward, then "high
828 * pause" is applied, then the pattern is played backwards and finally
829 * the "low pause" is applied.
830 *
831 * The middle elements of the pattern are used to determine delta_t and
832 * the "low pause" and "high pause" multipliers are derrived from this.
833 *
834 * The first element in the pattern is used to determine "low pause".
835 *
836 * If the specified pattern is a palindrome the ping pong mode is
837 * enabled. In this scenario the delta_t of the middle entry (i.e. the
838 * last in the programmed pattern) determines the "high pause".
839 */
840
841 /* Detect palindromes and use "ping pong" to reduce LUT usage */
842 for (i = 0; i < len / 2; i++) {
843 brightness_a = pattern[i].brightness;
844 brightness_b = pattern[len - i - 1].brightness;
845
846 if (brightness_a != brightness_b) {
847 ping_pong = false;
848 break;
849 }
850 }
851
852 /* The pattern length to be written to the LUT */
853 if (ping_pong)
854 actual_len = (len + 1) / 2;
855 else
856 actual_len = len;
857
858 /*
859 * Validate that all delta_t in the pattern are the same, with the
860 * exception of the middle element in case of ping_pong.
861 */
862 delta_t = pattern[1].delta_t;
863 for (i = 2; i < len; i++) {
864 if (pattern[i].delta_t != delta_t) {
865 /*
866 * Allow last entry in the full or shortened pattern to
867 * specify hi pause. Reject other variations.
868 */
869 if (i != actual_len - 1)
870 goto out_free_pattern;
871 }
872 }
873
874 /* LPG_RAMP_DURATION_REG is a 9bit */
875 if (delta_t >= BIT(9))
876 goto out_free_pattern;
877
878 /* Find "low pause" and "high pause" in the pattern */
879 lo_pause = pattern[0].delta_t;
880 hi_pause = pattern[actual_len - 1].delta_t;
881
882 mutex_lock(&lpg->lock);
883 ret = lpg_lut_store(lpg, pattern, actual_len, &lo_idx, &hi_idx);
884 if (ret < 0)
885 goto out_unlock;
886
887 for (i = 0; i < led->num_channels; i++) {
888 chan = led->channels[i];
889
890 chan->ramp_tick_ms = delta_t;
891 chan->ramp_ping_pong = ping_pong;
892 chan->ramp_oneshot = repeat != -1;
893
894 chan->ramp_lo_pause_ms = lo_pause;
895 chan->ramp_hi_pause_ms = hi_pause;
896
897 chan->pattern_lo_idx = lo_idx;
898 chan->pattern_hi_idx = hi_idx;
899 }
900
901 out_unlock:
902 mutex_unlock(&lpg->lock);
903 out_free_pattern:
904 kfree(pattern);
905
906 return ret;
907 }
908
lpg_pattern_single_set(struct led_classdev * cdev,struct led_pattern * pattern,u32 len,int repeat)909 static int lpg_pattern_single_set(struct led_classdev *cdev,
910 struct led_pattern *pattern, u32 len,
911 int repeat)
912 {
913 struct lpg_led *led = container_of(cdev, struct lpg_led, cdev);
914 int ret;
915
916 ret = lpg_pattern_set(led, pattern, len, repeat);
917 if (ret < 0)
918 return ret;
919
920 lpg_brightness_single_set(cdev, LED_FULL);
921
922 return 0;
923 }
924
lpg_pattern_mc_set(struct led_classdev * cdev,struct led_pattern * pattern,u32 len,int repeat)925 static int lpg_pattern_mc_set(struct led_classdev *cdev,
926 struct led_pattern *pattern, u32 len,
927 int repeat)
928 {
929 struct led_classdev_mc *mc = lcdev_to_mccdev(cdev);
930 struct lpg_led *led = container_of(mc, struct lpg_led, mcdev);
931 int ret;
932
933 ret = lpg_pattern_set(led, pattern, len, repeat);
934 if (ret < 0)
935 return ret;
936
937 led_mc_calc_color_components(mc, LED_FULL);
938 lpg_brightness_set(led, cdev, mc->subled_info);
939
940 return 0;
941 }
942
lpg_pattern_clear(struct lpg_led * led)943 static int lpg_pattern_clear(struct lpg_led *led)
944 {
945 struct lpg_channel *chan;
946 struct lpg *lpg = led->lpg;
947 int i;
948
949 mutex_lock(&lpg->lock);
950
951 chan = led->channels[0];
952 lpg_lut_free(lpg, chan->pattern_lo_idx, chan->pattern_hi_idx);
953
954 for (i = 0; i < led->num_channels; i++) {
955 chan = led->channels[i];
956 chan->pattern_lo_idx = 0;
957 chan->pattern_hi_idx = 0;
958 }
959
960 mutex_unlock(&lpg->lock);
961
962 return 0;
963 }
964
lpg_pattern_single_clear(struct led_classdev * cdev)965 static int lpg_pattern_single_clear(struct led_classdev *cdev)
966 {
967 struct lpg_led *led = container_of(cdev, struct lpg_led, cdev);
968
969 return lpg_pattern_clear(led);
970 }
971
lpg_pattern_mc_clear(struct led_classdev * cdev)972 static int lpg_pattern_mc_clear(struct led_classdev *cdev)
973 {
974 struct led_classdev_mc *mc = lcdev_to_mccdev(cdev);
975 struct lpg_led *led = container_of(mc, struct lpg_led, mcdev);
976
977 return lpg_pattern_clear(led);
978 }
979
lpg_pwm_request(struct pwm_chip * chip,struct pwm_device * pwm)980 static int lpg_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
981 {
982 struct lpg *lpg = container_of(chip, struct lpg, pwm);
983 struct lpg_channel *chan = &lpg->channels[pwm->hwpwm];
984
985 return chan->in_use ? -EBUSY : 0;
986 }
987
988 /*
989 * Limitations:
990 * - Updating both duty and period is not done atomically, so the output signal
991 * will momentarily be a mix of the settings.
992 * - Changed parameters takes effect immediately.
993 * - A disabled channel outputs a logical 0.
994 */
lpg_pwm_apply(struct pwm_chip * chip,struct pwm_device * pwm,const struct pwm_state * state)995 static int lpg_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
996 const struct pwm_state *state)
997 {
998 struct lpg *lpg = container_of(chip, struct lpg, pwm);
999 struct lpg_channel *chan = &lpg->channels[pwm->hwpwm];
1000 int ret = 0;
1001
1002 if (state->polarity != PWM_POLARITY_NORMAL)
1003 return -EINVAL;
1004
1005 mutex_lock(&lpg->lock);
1006
1007 if (state->enabled) {
1008 ret = lpg_calc_freq(chan, state->period);
1009 if (ret < 0)
1010 goto out_unlock;
1011
1012 lpg_calc_duty(chan, state->duty_cycle);
1013 }
1014 chan->enabled = state->enabled;
1015
1016 lpg_apply(chan);
1017
1018 triled_set(lpg, chan->triled_mask, chan->enabled ? chan->triled_mask : 0);
1019
1020 out_unlock:
1021 mutex_unlock(&lpg->lock);
1022
1023 return ret;
1024 }
1025
lpg_pwm_get_state(struct pwm_chip * chip,struct pwm_device * pwm,struct pwm_state * state)1026 static int lpg_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
1027 struct pwm_state *state)
1028 {
1029 struct lpg *lpg = container_of(chip, struct lpg, pwm);
1030 struct lpg_channel *chan = &lpg->channels[pwm->hwpwm];
1031 unsigned int resolution;
1032 unsigned int pre_div;
1033 unsigned int refclk;
1034 unsigned int val;
1035 unsigned int m;
1036 u16 pwm_value;
1037 int ret;
1038
1039 ret = regmap_read(lpg->map, chan->base + LPG_SIZE_CLK_REG, &val);
1040 if (ret)
1041 return ret;
1042
1043 if (chan->subtype == LPG_SUBTYPE_HI_RES_PWM) {
1044 refclk = lpg_clk_rates_hi_res[FIELD_GET(PWM_CLK_SELECT_HI_RES_MASK, val)];
1045 resolution = lpg_pwm_resolution_hi_res[FIELD_GET(PWM_SIZE_HI_RES_MASK, val)];
1046 } else {
1047 refclk = lpg_clk_rates[FIELD_GET(PWM_CLK_SELECT_MASK, val)];
1048 resolution = 9;
1049 }
1050
1051 if (refclk) {
1052 ret = regmap_read(lpg->map, chan->base + LPG_PREDIV_CLK_REG, &val);
1053 if (ret)
1054 return ret;
1055
1056 pre_div = lpg_pre_divs[FIELD_GET(PWM_FREQ_PRE_DIV_MASK, val)];
1057 m = FIELD_GET(PWM_FREQ_EXP_MASK, val);
1058
1059 ret = regmap_bulk_read(lpg->map, chan->base + PWM_VALUE_REG, &pwm_value, sizeof(pwm_value));
1060 if (ret)
1061 return ret;
1062
1063 state->period = DIV_ROUND_UP_ULL((u64)NSEC_PER_SEC * (1 << resolution) *
1064 pre_div * (1 << m), refclk);
1065 state->duty_cycle = DIV_ROUND_UP_ULL((u64)NSEC_PER_SEC * pwm_value * pre_div * (1 << m), refclk);
1066 } else {
1067 state->period = 0;
1068 state->duty_cycle = 0;
1069 }
1070
1071 ret = regmap_read(lpg->map, chan->base + PWM_ENABLE_CONTROL_REG, &val);
1072 if (ret)
1073 return ret;
1074
1075 state->enabled = FIELD_GET(LPG_ENABLE_CONTROL_OUTPUT, val);
1076 state->polarity = PWM_POLARITY_NORMAL;
1077
1078 if (state->duty_cycle > state->period)
1079 state->duty_cycle = state->period;
1080
1081 return 0;
1082 }
1083
1084 static const struct pwm_ops lpg_pwm_ops = {
1085 .request = lpg_pwm_request,
1086 .apply = lpg_pwm_apply,
1087 .get_state = lpg_pwm_get_state,
1088 .owner = THIS_MODULE,
1089 };
1090
lpg_add_pwm(struct lpg * lpg)1091 static int lpg_add_pwm(struct lpg *lpg)
1092 {
1093 int ret;
1094
1095 lpg->pwm.dev = lpg->dev;
1096 lpg->pwm.npwm = lpg->num_channels;
1097 lpg->pwm.ops = &lpg_pwm_ops;
1098
1099 ret = pwmchip_add(&lpg->pwm);
1100 if (ret)
1101 dev_err(lpg->dev, "failed to add PWM chip: ret %d\n", ret);
1102
1103 return ret;
1104 }
1105
lpg_parse_channel(struct lpg * lpg,struct device_node * np,struct lpg_channel ** channel)1106 static int lpg_parse_channel(struct lpg *lpg, struct device_node *np,
1107 struct lpg_channel **channel)
1108 {
1109 struct lpg_channel *chan;
1110 u32 color = LED_COLOR_ID_GREEN;
1111 u32 reg;
1112 int ret;
1113
1114 ret = of_property_read_u32(np, "reg", ®);
1115 if (ret || !reg || reg > lpg->num_channels) {
1116 dev_err(lpg->dev, "invalid \"reg\" of %pOFn\n", np);
1117 return -EINVAL;
1118 }
1119
1120 chan = &lpg->channels[reg - 1];
1121 chan->in_use = true;
1122
1123 ret = of_property_read_u32(np, "color", &color);
1124 if (ret < 0 && ret != -EINVAL) {
1125 dev_err(lpg->dev, "failed to parse \"color\" of %pOF\n", np);
1126 return ret;
1127 }
1128
1129 chan->color = color;
1130
1131 *channel = chan;
1132
1133 return 0;
1134 }
1135
lpg_add_led(struct lpg * lpg,struct device_node * np)1136 static int lpg_add_led(struct lpg *lpg, struct device_node *np)
1137 {
1138 struct led_init_data init_data = {};
1139 struct led_classdev *cdev;
1140 struct device_node *child;
1141 struct mc_subled *info;
1142 struct lpg_led *led;
1143 const char *state;
1144 int num_channels;
1145 u32 color = 0;
1146 int ret;
1147 int i;
1148
1149 ret = of_property_read_u32(np, "color", &color);
1150 if (ret < 0 && ret != -EINVAL) {
1151 dev_err(lpg->dev, "failed to parse \"color\" of %pOF\n", np);
1152 return ret;
1153 }
1154
1155 if (color == LED_COLOR_ID_RGB)
1156 num_channels = of_get_available_child_count(np);
1157 else
1158 num_channels = 1;
1159
1160 led = devm_kzalloc(lpg->dev, struct_size(led, channels, num_channels), GFP_KERNEL);
1161 if (!led)
1162 return -ENOMEM;
1163
1164 led->lpg = lpg;
1165 led->num_channels = num_channels;
1166
1167 if (color == LED_COLOR_ID_RGB) {
1168 info = devm_kcalloc(lpg->dev, num_channels, sizeof(*info), GFP_KERNEL);
1169 if (!info)
1170 return -ENOMEM;
1171 i = 0;
1172 for_each_available_child_of_node(np, child) {
1173 ret = lpg_parse_channel(lpg, child, &led->channels[i]);
1174 if (ret < 0) {
1175 of_node_put(child);
1176 return ret;
1177 }
1178
1179 info[i].color_index = led->channels[i]->color;
1180 info[i].intensity = 0;
1181 i++;
1182 }
1183
1184 led->mcdev.subled_info = info;
1185 led->mcdev.num_colors = num_channels;
1186
1187 cdev = &led->mcdev.led_cdev;
1188 cdev->brightness_set_blocking = lpg_brightness_mc_set;
1189 cdev->blink_set = lpg_blink_mc_set;
1190
1191 /* Register pattern accessors only if we have a LUT block */
1192 if (lpg->lut_base) {
1193 cdev->pattern_set = lpg_pattern_mc_set;
1194 cdev->pattern_clear = lpg_pattern_mc_clear;
1195 }
1196 } else {
1197 ret = lpg_parse_channel(lpg, np, &led->channels[0]);
1198 if (ret < 0)
1199 return ret;
1200
1201 cdev = &led->cdev;
1202 cdev->brightness_set_blocking = lpg_brightness_single_set;
1203 cdev->blink_set = lpg_blink_single_set;
1204
1205 /* Register pattern accessors only if we have a LUT block */
1206 if (lpg->lut_base) {
1207 cdev->pattern_set = lpg_pattern_single_set;
1208 cdev->pattern_clear = lpg_pattern_single_clear;
1209 }
1210 }
1211
1212 cdev->default_trigger = of_get_property(np, "linux,default-trigger", NULL);
1213 cdev->max_brightness = LPG_RESOLUTION_9BIT - 1;
1214
1215 if (!of_property_read_string(np, "default-state", &state) &&
1216 !strcmp(state, "on"))
1217 cdev->brightness = cdev->max_brightness;
1218 else
1219 cdev->brightness = LED_OFF;
1220
1221 cdev->brightness_set_blocking(cdev, cdev->brightness);
1222
1223 init_data.fwnode = of_fwnode_handle(np);
1224
1225 if (color == LED_COLOR_ID_RGB)
1226 ret = devm_led_classdev_multicolor_register_ext(lpg->dev, &led->mcdev, &init_data);
1227 else
1228 ret = devm_led_classdev_register_ext(lpg->dev, &led->cdev, &init_data);
1229 if (ret)
1230 dev_err(lpg->dev, "unable to register %s\n", cdev->name);
1231
1232 return ret;
1233 }
1234
lpg_init_channels(struct lpg * lpg)1235 static int lpg_init_channels(struct lpg *lpg)
1236 {
1237 const struct lpg_data *data = lpg->data;
1238 struct lpg_channel *chan;
1239 int i;
1240
1241 lpg->num_channels = data->num_channels;
1242 lpg->channels = devm_kcalloc(lpg->dev, data->num_channels,
1243 sizeof(struct lpg_channel), GFP_KERNEL);
1244 if (!lpg->channels)
1245 return -ENOMEM;
1246
1247 for (i = 0; i < data->num_channels; i++) {
1248 chan = &lpg->channels[i];
1249
1250 chan->lpg = lpg;
1251 chan->base = data->channels[i].base;
1252 chan->triled_mask = data->channels[i].triled_mask;
1253 chan->lut_mask = BIT(i);
1254
1255 regmap_read(lpg->map, chan->base + LPG_SUBTYPE_REG, &chan->subtype);
1256 }
1257
1258 return 0;
1259 }
1260
lpg_init_triled(struct lpg * lpg)1261 static int lpg_init_triled(struct lpg *lpg)
1262 {
1263 struct device_node *np = lpg->dev->of_node;
1264 int ret;
1265
1266 /* Skip initialization if we don't have a triled block */
1267 if (!lpg->data->triled_base)
1268 return 0;
1269
1270 lpg->triled_base = lpg->data->triled_base;
1271 lpg->triled_has_atc_ctl = lpg->data->triled_has_atc_ctl;
1272 lpg->triled_has_src_sel = lpg->data->triled_has_src_sel;
1273
1274 if (lpg->triled_has_src_sel) {
1275 ret = of_property_read_u32(np, "qcom,power-source", &lpg->triled_src);
1276 if (ret || lpg->triled_src == 2 || lpg->triled_src > 3) {
1277 dev_err(lpg->dev, "invalid power source\n");
1278 return -EINVAL;
1279 }
1280 }
1281
1282 /* Disable automatic trickle charge LED */
1283 if (lpg->triled_has_atc_ctl)
1284 regmap_write(lpg->map, lpg->triled_base + TRI_LED_ATC_CTL, 0);
1285
1286 /* Configure power source */
1287 if (lpg->triled_has_src_sel)
1288 regmap_write(lpg->map, lpg->triled_base + TRI_LED_SRC_SEL, lpg->triled_src);
1289
1290 /* Default all outputs to off */
1291 regmap_write(lpg->map, lpg->triled_base + TRI_LED_EN_CTL, 0);
1292
1293 return 0;
1294 }
1295
lpg_init_lut(struct lpg * lpg)1296 static int lpg_init_lut(struct lpg *lpg)
1297 {
1298 const struct lpg_data *data = lpg->data;
1299
1300 if (!data->lut_base)
1301 return 0;
1302
1303 lpg->lut_base = data->lut_base;
1304 lpg->lut_size = data->lut_size;
1305
1306 lpg->lut_bitmap = devm_bitmap_zalloc(lpg->dev, lpg->lut_size, GFP_KERNEL);
1307 if (!lpg->lut_bitmap)
1308 return -ENOMEM;
1309
1310 return 0;
1311 }
1312
lpg_probe(struct platform_device * pdev)1313 static int lpg_probe(struct platform_device *pdev)
1314 {
1315 struct device_node *np;
1316 struct lpg *lpg;
1317 int ret;
1318 int i;
1319
1320 lpg = devm_kzalloc(&pdev->dev, sizeof(*lpg), GFP_KERNEL);
1321 if (!lpg)
1322 return -ENOMEM;
1323
1324 lpg->data = of_device_get_match_data(&pdev->dev);
1325 if (!lpg->data)
1326 return -EINVAL;
1327
1328 platform_set_drvdata(pdev, lpg);
1329
1330 lpg->dev = &pdev->dev;
1331 mutex_init(&lpg->lock);
1332
1333 lpg->map = dev_get_regmap(pdev->dev.parent, NULL);
1334 if (!lpg->map)
1335 return dev_err_probe(&pdev->dev, -ENXIO, "parent regmap unavailable\n");
1336
1337 ret = lpg_init_channels(lpg);
1338 if (ret < 0)
1339 return ret;
1340
1341 ret = lpg_parse_dtest(lpg);
1342 if (ret < 0)
1343 return ret;
1344
1345 ret = lpg_init_triled(lpg);
1346 if (ret < 0)
1347 return ret;
1348
1349 ret = lpg_init_lut(lpg);
1350 if (ret < 0)
1351 return ret;
1352
1353 for_each_available_child_of_node(pdev->dev.of_node, np) {
1354 ret = lpg_add_led(lpg, np);
1355 if (ret) {
1356 of_node_put(np);
1357 return ret;
1358 }
1359 }
1360
1361 for (i = 0; i < lpg->num_channels; i++)
1362 lpg_apply_dtest(&lpg->channels[i]);
1363
1364 return lpg_add_pwm(lpg);
1365 }
1366
lpg_remove(struct platform_device * pdev)1367 static int lpg_remove(struct platform_device *pdev)
1368 {
1369 struct lpg *lpg = platform_get_drvdata(pdev);
1370
1371 pwmchip_remove(&lpg->pwm);
1372
1373 return 0;
1374 }
1375
1376 static const struct lpg_data pm8916_pwm_data = {
1377 .num_channels = 1,
1378 .channels = (const struct lpg_channel_data[]) {
1379 { .base = 0xbc00 },
1380 },
1381 };
1382
1383 static const struct lpg_data pm8941_lpg_data = {
1384 .lut_base = 0xb000,
1385 .lut_size = 64,
1386
1387 .triled_base = 0xd000,
1388 .triled_has_atc_ctl = true,
1389 .triled_has_src_sel = true,
1390
1391 .num_channels = 8,
1392 .channels = (const struct lpg_channel_data[]) {
1393 { .base = 0xb100 },
1394 { .base = 0xb200 },
1395 { .base = 0xb300 },
1396 { .base = 0xb400 },
1397 { .base = 0xb500, .triled_mask = BIT(5) },
1398 { .base = 0xb600, .triled_mask = BIT(6) },
1399 { .base = 0xb700, .triled_mask = BIT(7) },
1400 { .base = 0xb800 },
1401 },
1402 };
1403
1404 static const struct lpg_data pm8994_lpg_data = {
1405 .lut_base = 0xb000,
1406 .lut_size = 64,
1407
1408 .num_channels = 6,
1409 .channels = (const struct lpg_channel_data[]) {
1410 { .base = 0xb100 },
1411 { .base = 0xb200 },
1412 { .base = 0xb300 },
1413 { .base = 0xb400 },
1414 { .base = 0xb500 },
1415 { .base = 0xb600 },
1416 },
1417 };
1418
1419 /* PMI632 uses SDAM instead of LUT for pattern */
1420 static const struct lpg_data pmi632_lpg_data = {
1421 .triled_base = 0xd000,
1422
1423 .num_channels = 5,
1424 .channels = (const struct lpg_channel_data[]) {
1425 { .base = 0xb300, .triled_mask = BIT(7) },
1426 { .base = 0xb400, .triled_mask = BIT(6) },
1427 { .base = 0xb500, .triled_mask = BIT(5) },
1428 { .base = 0xb600 },
1429 { .base = 0xb700 },
1430 },
1431 };
1432
1433 static const struct lpg_data pmi8994_lpg_data = {
1434 .lut_base = 0xb000,
1435 .lut_size = 24,
1436
1437 .triled_base = 0xd000,
1438 .triled_has_atc_ctl = true,
1439 .triled_has_src_sel = true,
1440
1441 .num_channels = 4,
1442 .channels = (const struct lpg_channel_data[]) {
1443 { .base = 0xb100, .triled_mask = BIT(5) },
1444 { .base = 0xb200, .triled_mask = BIT(6) },
1445 { .base = 0xb300, .triled_mask = BIT(7) },
1446 { .base = 0xb400 },
1447 },
1448 };
1449
1450 static const struct lpg_data pmi8998_lpg_data = {
1451 .lut_base = 0xb000,
1452 .lut_size = 49,
1453
1454 .triled_base = 0xd000,
1455
1456 .num_channels = 6,
1457 .channels = (const struct lpg_channel_data[]) {
1458 { .base = 0xb100 },
1459 { .base = 0xb200 },
1460 { .base = 0xb300, .triled_mask = BIT(5) },
1461 { .base = 0xb400, .triled_mask = BIT(6) },
1462 { .base = 0xb500, .triled_mask = BIT(7) },
1463 { .base = 0xb600 },
1464 },
1465 };
1466
1467 static const struct lpg_data pm8150b_lpg_data = {
1468 .lut_base = 0xb000,
1469 .lut_size = 24,
1470
1471 .triled_base = 0xd000,
1472
1473 .num_channels = 2,
1474 .channels = (const struct lpg_channel_data[]) {
1475 { .base = 0xb100, .triled_mask = BIT(7) },
1476 { .base = 0xb200, .triled_mask = BIT(6) },
1477 },
1478 };
1479
1480 static const struct lpg_data pm8150l_lpg_data = {
1481 .lut_base = 0xb000,
1482 .lut_size = 48,
1483
1484 .triled_base = 0xd000,
1485
1486 .num_channels = 5,
1487 .channels = (const struct lpg_channel_data[]) {
1488 { .base = 0xb100, .triled_mask = BIT(7) },
1489 { .base = 0xb200, .triled_mask = BIT(6) },
1490 { .base = 0xb300, .triled_mask = BIT(5) },
1491 { .base = 0xbc00 },
1492 { .base = 0xbd00 },
1493
1494 },
1495 };
1496
1497 static const struct lpg_data pm8350c_pwm_data = {
1498 .triled_base = 0xef00,
1499
1500 .num_channels = 4,
1501 .channels = (const struct lpg_channel_data[]) {
1502 { .base = 0xe800, .triled_mask = BIT(7) },
1503 { .base = 0xe900, .triled_mask = BIT(6) },
1504 { .base = 0xea00, .triled_mask = BIT(5) },
1505 { .base = 0xeb00 },
1506 },
1507 };
1508
1509 static const struct lpg_data pmk8550_pwm_data = {
1510 .num_channels = 2,
1511 .channels = (const struct lpg_channel_data[]) {
1512 { .base = 0xe800 },
1513 { .base = 0xe900 },
1514 },
1515 };
1516
1517 static const struct of_device_id lpg_of_table[] = {
1518 { .compatible = "qcom,pm8150b-lpg", .data = &pm8150b_lpg_data },
1519 { .compatible = "qcom,pm8150l-lpg", .data = &pm8150l_lpg_data },
1520 { .compatible = "qcom,pm8350c-pwm", .data = &pm8350c_pwm_data },
1521 { .compatible = "qcom,pm8916-pwm", .data = &pm8916_pwm_data },
1522 { .compatible = "qcom,pm8941-lpg", .data = &pm8941_lpg_data },
1523 { .compatible = "qcom,pm8994-lpg", .data = &pm8994_lpg_data },
1524 { .compatible = "qcom,pmi632-lpg", .data = &pmi632_lpg_data },
1525 { .compatible = "qcom,pmi8994-lpg", .data = &pmi8994_lpg_data },
1526 { .compatible = "qcom,pmi8998-lpg", .data = &pmi8998_lpg_data },
1527 { .compatible = "qcom,pmc8180c-lpg", .data = &pm8150l_lpg_data },
1528 { .compatible = "qcom,pmk8550-pwm", .data = &pmk8550_pwm_data },
1529 {}
1530 };
1531 MODULE_DEVICE_TABLE(of, lpg_of_table);
1532
1533 static struct platform_driver lpg_driver = {
1534 .probe = lpg_probe,
1535 .remove = lpg_remove,
1536 .driver = {
1537 .name = "qcom-spmi-lpg",
1538 .of_match_table = lpg_of_table,
1539 },
1540 };
1541 module_platform_driver(lpg_driver);
1542
1543 MODULE_DESCRIPTION("Qualcomm LPG LED driver");
1544 MODULE_LICENSE("GPL v2");
1545