1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Intel Lightning Mountain SoC LED Serial Shift Output Controller driver 4 * 5 * Copyright (c) 2020 Intel Corporation. 6 */ 7 8 #include <linux/bitfield.h> 9 #include <linux/clk.h> 10 #include <linux/gpio.h> 11 #include <linux/init.h> 12 #include <linux/kernel.h> 13 #include <linux/leds.h> 14 #include <linux/mfd/syscon.h> 15 #include <linux/module.h> 16 #include <linux/platform_device.h> 17 #include <linux/property.h> 18 #include <linux/regmap.h> 19 #include <linux/sizes.h> 20 #include <linux/uaccess.h> 21 22 #define SSO_DEV_NAME "lgm-sso" 23 24 #define LED_BLINK_H8_0 0x0 25 #define LED_BLINK_H8_1 0x4 26 #define GET_FREQ_OFFSET(pin, src) (((pin) * 6) + ((src) * 2)) 27 #define GET_SRC_OFFSET(pinc) (((pin) * 6) + 4) 28 29 #define DUTY_CYCLE(x) (0x8 + ((x) * 4)) 30 #define SSO_CON0 0x2B0 31 #define SSO_CON0_RZFL BIT(26) 32 #define SSO_CON0_BLINK_R BIT(30) 33 #define SSO_CON0_SWU BIT(31) 34 35 #define SSO_CON1 0x2B4 36 #define SSO_CON1_FCDSC GENMASK(21, 20) /* Fixed Divider Shift Clock */ 37 #define SSO_CON1_FPID GENMASK(24, 23) 38 #define SSO_CON1_GPTD GENMASK(26, 25) 39 #define SSO_CON1_US GENMASK(31, 30) 40 41 #define SSO_CPU 0x2B8 42 #define SSO_CON2 0x2C4 43 #define SSO_CON3 0x2C8 44 45 /* Driver MACRO */ 46 #define MAX_PIN_NUM_PER_BANK SZ_32 47 #define MAX_GROUP_NUM SZ_4 48 #define PINS_PER_GROUP SZ_8 49 #define FPID_FREQ_RANK_MAX SZ_4 50 #define SSO_LED_MAX_NUM SZ_32 51 #define MAX_FREQ_RANK 10 52 #define DEF_GPTC_CLK_RATE 200000000 53 #define SSO_DEF_BRIGHTNESS LED_HALF 54 #define DATA_CLK_EDGE 0 /* 0-rising, 1-falling */ 55 56 static const u32 freq_div_tbl[] = {4000, 2000, 1000, 800}; 57 static const int freq_tbl[] = {2, 4, 8, 10, 50000, 100000, 200000, 250000}; 58 static const int shift_clk_freq_tbl[] = {25000000, 12500000, 6250000, 3125000}; 59 60 /* 61 * Update Source to update the SOUTs 62 * SW - Software has to update the SWU bit 63 * GPTC - General Purpose timer is used as clock source 64 * FPID - Divided FSC clock (FPID) is used as clock source 65 */ 66 enum { 67 US_SW = 0, 68 US_GPTC = 1, 69 US_FPID = 2 70 }; 71 72 enum { 73 MAX_FPID_FREQ_RANK = 5, /* 1 to 4 */ 74 MAX_GPTC_FREQ_RANK = 9, /* 5 to 8 */ 75 MAX_GPTC_HS_FREQ_RANK = 10, /* 9 to 10 */ 76 }; 77 78 enum { 79 LED_GRP0_PIN_MAX = 24, 80 LED_GRP1_PIN_MAX = 29, 81 LED_GRP2_PIN_MAX = 32, 82 }; 83 84 enum { 85 LED_GRP0_0_23, 86 LED_GRP1_24_28, 87 LED_GRP2_29_31, 88 LED_GROUP_MAX, 89 }; 90 91 enum { 92 CLK_SRC_FPID = 0, 93 CLK_SRC_GPTC = 1, 94 CLK_SRC_GPTC_HS = 2, 95 }; 96 97 struct sso_led_priv; 98 99 struct sso_led_desc { 100 const char *name; 101 const char *default_trigger; 102 unsigned int brightness; 103 unsigned int blink_rate; 104 unsigned int retain_state_suspended:1; 105 unsigned int retain_state_shutdown:1; 106 unsigned int panic_indicator:1; 107 unsigned int hw_blink:1; 108 unsigned int hw_trig:1; 109 unsigned int blinking:1; 110 int freq_idx; 111 u32 pin; 112 }; 113 114 struct sso_led { 115 struct list_head list; 116 struct led_classdev cdev; 117 struct gpio_desc *gpiod; 118 struct sso_led_desc desc; 119 struct sso_led_priv *priv; 120 }; 121 122 struct sso_gpio { 123 struct gpio_chip chip; 124 int shift_clk_freq; 125 int edge; 126 int freq; 127 u32 pins; 128 u32 alloc_bitmap; 129 }; 130 131 struct sso_led_priv { 132 struct regmap *mmap; 133 struct device *dev; 134 struct platform_device *pdev; 135 struct clk *gclk; 136 struct clk *fpid_clk; 137 u32 fpid_clkrate; 138 u32 gptc_clkrate; 139 u32 freq[MAX_FREQ_RANK]; 140 struct list_head led_list; 141 struct sso_gpio gpio; 142 }; 143 144 static int sso_get_blink_rate_idx(struct sso_led_priv *priv, u32 rate) 145 { 146 int i; 147 148 for (i = 0; i < MAX_FREQ_RANK; i++) { 149 if (rate <= priv->freq[i]) 150 return i; 151 } 152 153 return -1; 154 } 155 156 static unsigned int sso_led_pin_to_group(u32 pin) 157 { 158 if (pin < LED_GRP0_PIN_MAX) 159 return LED_GRP0_0_23; 160 else if (pin < LED_GRP1_PIN_MAX) 161 return LED_GRP1_24_28; 162 else 163 return LED_GRP2_29_31; 164 } 165 166 static u32 sso_led_get_freq_src(int freq_idx) 167 { 168 if (freq_idx < MAX_FPID_FREQ_RANK) 169 return CLK_SRC_FPID; 170 else if (freq_idx < MAX_GPTC_FREQ_RANK) 171 return CLK_SRC_GPTC; 172 else 173 return CLK_SRC_GPTC_HS; 174 } 175 176 static u32 sso_led_pin_blink_off(u32 pin, unsigned int group) 177 { 178 if (group == LED_GRP2_29_31) 179 return pin - LED_GRP1_PIN_MAX; 180 else if (group == LED_GRP1_24_28) 181 return pin - LED_GRP0_PIN_MAX; 182 else /* led 0 - 23 in led 32 location */ 183 return SSO_LED_MAX_NUM - LED_GRP1_PIN_MAX; 184 } 185 186 static struct sso_led 187 *cdev_to_sso_led_data(struct led_classdev *led_cdev) 188 { 189 return container_of(led_cdev, struct sso_led, cdev); 190 } 191 192 static void sso_led_freq_set(struct sso_led_priv *priv, u32 pin, int freq_idx) 193 { 194 u32 reg, off, freq_src, val_freq; 195 u32 low, high, val; 196 unsigned int group; 197 198 if (!freq_idx) 199 return; 200 201 group = sso_led_pin_to_group(pin); 202 freq_src = sso_led_get_freq_src(freq_idx); 203 off = sso_led_pin_blink_off(pin, group); 204 205 if (group == LED_GRP0_0_23) 206 return; 207 else if (group == LED_GRP1_24_28) 208 reg = LED_BLINK_H8_0; 209 else 210 reg = LED_BLINK_H8_1; 211 212 if (freq_src == CLK_SRC_FPID) 213 val_freq = freq_idx - 1; 214 else if (freq_src == CLK_SRC_GPTC) 215 val_freq = freq_idx - MAX_FPID_FREQ_RANK; 216 217 /* set blink rate idx */ 218 if (freq_src != CLK_SRC_GPTC_HS) { 219 low = GET_FREQ_OFFSET(off, freq_src); 220 high = low + 2; 221 val = val_freq << high; 222 regmap_update_bits(priv->mmap, reg, GENMASK(high, low), val); 223 } 224 225 /* select clock source */ 226 low = GET_SRC_OFFSET(off); 227 high = low + 2; 228 val = freq_src << high; 229 regmap_update_bits(priv->mmap, reg, GENMASK(high, low), val); 230 } 231 232 static void sso_led_brightness_set(struct led_classdev *led_cdev, 233 enum led_brightness brightness) 234 { 235 struct sso_led_priv *priv; 236 struct sso_led_desc *desc; 237 struct sso_led *led; 238 int val; 239 240 led = cdev_to_sso_led_data(led_cdev); 241 priv = led->priv; 242 desc = &led->desc; 243 244 desc->brightness = brightness; 245 regmap_write(priv->mmap, DUTY_CYCLE(desc->pin), brightness); 246 247 if (brightness == LED_OFF) 248 val = 0; 249 else 250 val = 1; 251 252 /* HW blink off */ 253 if (desc->hw_blink && !val && desc->blinking) { 254 desc->blinking = 0; 255 regmap_update_bits(priv->mmap, SSO_CON2, BIT(desc->pin), 0); 256 } else if (desc->hw_blink && val && !desc->blinking) { 257 desc->blinking = 1; 258 regmap_update_bits(priv->mmap, SSO_CON2, BIT(desc->pin), 259 1 << desc->pin); 260 } 261 262 if (!desc->hw_trig && led->gpiod) 263 gpiod_set_value(led->gpiod, val); 264 } 265 266 static enum led_brightness sso_led_brightness_get(struct led_classdev *led_cdev) 267 { 268 struct sso_led *led = cdev_to_sso_led_data(led_cdev); 269 270 return (enum led_brightness)led->desc.brightness; 271 } 272 273 static int 274 delay_to_freq_idx(struct sso_led *led, unsigned long *delay_on, 275 unsigned long *delay_off) 276 { 277 struct sso_led_priv *priv = led->priv; 278 unsigned long delay; 279 int freq_idx; 280 u32 freq; 281 282 if (!*delay_on && !*delay_off) { 283 *delay_on = *delay_off = (1000 / priv->freq[0]) / 2; 284 return 0; 285 } 286 287 delay = *delay_on + *delay_off; 288 freq = 1000 / delay; 289 290 freq_idx = sso_get_blink_rate_idx(priv, freq); 291 if (freq_idx == -1) 292 freq_idx = MAX_FREQ_RANK - 1; 293 294 delay = 1000 / priv->freq[freq_idx]; 295 *delay_on = *delay_off = delay / 2; 296 297 if (!*delay_on) 298 *delay_on = *delay_off = 1; 299 300 return freq_idx; 301 } 302 303 static int 304 sso_led_blink_set(struct led_classdev *led_cdev, unsigned long *delay_on, 305 unsigned long *delay_off) 306 { 307 struct sso_led_priv *priv; 308 struct sso_led *led; 309 int freq_idx; 310 311 led = cdev_to_sso_led_data(led_cdev); 312 priv = led->priv; 313 freq_idx = delay_to_freq_idx(led, delay_on, delay_off); 314 315 sso_led_freq_set(priv, led->desc.pin, freq_idx); 316 regmap_update_bits(priv->mmap, SSO_CON2, BIT(led->desc.pin), 317 1 << led->desc.pin); 318 led->desc.freq_idx = freq_idx; 319 led->desc.blink_rate = priv->freq[freq_idx]; 320 led->desc.blinking = 1; 321 322 return 1; 323 } 324 325 static void sso_led_hw_cfg(struct sso_led_priv *priv, struct sso_led *led) 326 { 327 struct sso_led_desc *desc = &led->desc; 328 329 /* set freq */ 330 if (desc->hw_blink) { 331 sso_led_freq_set(priv, desc->pin, desc->freq_idx); 332 regmap_update_bits(priv->mmap, SSO_CON2, BIT(desc->pin), 333 1 << desc->pin); 334 } 335 336 if (desc->hw_trig) 337 regmap_update_bits(priv->mmap, SSO_CON3, BIT(desc->pin), 338 1 << desc->pin); 339 340 /* set brightness */ 341 regmap_write(priv->mmap, DUTY_CYCLE(desc->pin), desc->brightness); 342 343 /* enable output */ 344 if (!desc->hw_trig && desc->brightness) 345 gpiod_set_value(led->gpiod, 1); 346 } 347 348 static int sso_create_led(struct sso_led_priv *priv, struct sso_led *led, 349 struct fwnode_handle *child) 350 { 351 struct sso_led_desc *desc = &led->desc; 352 struct led_init_data init_data; 353 int err; 354 355 init_data.fwnode = child; 356 init_data.devicename = SSO_DEV_NAME; 357 init_data.default_label = ":"; 358 359 led->cdev.default_trigger = desc->default_trigger; 360 led->cdev.brightness_set = sso_led_brightness_set; 361 led->cdev.brightness_get = sso_led_brightness_get; 362 led->cdev.brightness = desc->brightness; 363 led->cdev.max_brightness = LED_FULL; 364 365 if (desc->retain_state_shutdown) 366 led->cdev.flags |= LED_RETAIN_AT_SHUTDOWN; 367 if (desc->retain_state_suspended) 368 led->cdev.flags |= LED_CORE_SUSPENDRESUME; 369 if (desc->panic_indicator) 370 led->cdev.flags |= LED_PANIC_INDICATOR; 371 372 if (desc->hw_blink) 373 led->cdev.blink_set = sso_led_blink_set; 374 375 sso_led_hw_cfg(priv, led); 376 377 err = devm_led_classdev_register_ext(priv->dev, &led->cdev, &init_data); 378 if (err) 379 return err; 380 381 list_add(&led->list, &priv->led_list); 382 383 return 0; 384 } 385 386 static void sso_init_freq(struct sso_led_priv *priv) 387 { 388 int i; 389 390 priv->freq[0] = 0; 391 for (i = 1; i < MAX_FREQ_RANK; i++) { 392 if (i < MAX_FPID_FREQ_RANK) { 393 priv->freq[i] = priv->fpid_clkrate / freq_div_tbl[i - 1]; 394 } else if (i < MAX_GPTC_FREQ_RANK) { 395 priv->freq[i] = priv->gptc_clkrate / 396 freq_div_tbl[i - MAX_FPID_FREQ_RANK]; 397 } else if (i < MAX_GPTC_HS_FREQ_RANK) { 398 priv->freq[i] = priv->gptc_clkrate; 399 } 400 } 401 } 402 403 static int sso_gpio_request(struct gpio_chip *chip, unsigned int offset) 404 { 405 struct sso_led_priv *priv = gpiochip_get_data(chip); 406 407 if (priv->gpio.alloc_bitmap & BIT(offset)) 408 return -EINVAL; 409 410 priv->gpio.alloc_bitmap |= BIT(offset); 411 regmap_write(priv->mmap, DUTY_CYCLE(offset), 0xFF); 412 413 return 0; 414 } 415 416 static void sso_gpio_free(struct gpio_chip *chip, unsigned int offset) 417 { 418 struct sso_led_priv *priv = gpiochip_get_data(chip); 419 420 priv->gpio.alloc_bitmap &= ~BIT(offset); 421 regmap_write(priv->mmap, DUTY_CYCLE(offset), 0x0); 422 } 423 424 static int sso_gpio_get_dir(struct gpio_chip *chip, unsigned int offset) 425 { 426 return GPIOF_DIR_OUT; 427 } 428 429 static int 430 sso_gpio_dir_out(struct gpio_chip *chip, unsigned int offset, int value) 431 { 432 struct sso_led_priv *priv = gpiochip_get_data(chip); 433 bool bit = !!value; 434 435 regmap_update_bits(priv->mmap, SSO_CPU, BIT(offset), bit << offset); 436 if (!priv->gpio.freq) 437 regmap_update_bits(priv->mmap, SSO_CON0, SSO_CON0_SWU, 438 SSO_CON0_SWU); 439 440 return 0; 441 } 442 443 static int sso_gpio_get(struct gpio_chip *chip, unsigned int offset) 444 { 445 struct sso_led_priv *priv = gpiochip_get_data(chip); 446 u32 reg_val; 447 448 regmap_read(priv->mmap, SSO_CPU, ®_val); 449 450 return !!(reg_val & BIT(offset)); 451 } 452 453 static void sso_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) 454 { 455 struct sso_led_priv *priv = gpiochip_get_data(chip); 456 457 regmap_update_bits(priv->mmap, SSO_CPU, BIT(offset), value << offset); 458 if (!priv->gpio.freq) 459 regmap_update_bits(priv->mmap, SSO_CON0, SSO_CON0_SWU, 460 SSO_CON0_SWU); 461 } 462 463 static int sso_gpio_gc_init(struct device *dev, struct sso_led_priv *priv) 464 { 465 struct gpio_chip *gc = &priv->gpio.chip; 466 467 gc->request = sso_gpio_request; 468 gc->free = sso_gpio_free; 469 gc->get_direction = sso_gpio_get_dir; 470 gc->direction_output = sso_gpio_dir_out; 471 gc->get = sso_gpio_get; 472 gc->set = sso_gpio_set; 473 474 gc->label = "lgm-sso"; 475 gc->base = -1; 476 /* To exclude pins from control, use "gpio-reserved-ranges" */ 477 gc->ngpio = priv->gpio.pins; 478 gc->parent = dev; 479 gc->owner = THIS_MODULE; 480 gc->of_node = dev->of_node; 481 482 return devm_gpiochip_add_data(dev, gc, priv); 483 } 484 485 static int sso_gpio_get_freq_idx(int freq) 486 { 487 int idx; 488 489 for (idx = 0; idx < ARRAY_SIZE(freq_tbl); idx++) { 490 if (freq <= freq_tbl[idx]) 491 return idx; 492 } 493 494 return -1; 495 } 496 497 static void sso_register_shift_clk(struct sso_led_priv *priv) 498 { 499 int idx, size = ARRAY_SIZE(shift_clk_freq_tbl); 500 u32 val = 0; 501 502 for (idx = 0; idx < size; idx++) { 503 if (shift_clk_freq_tbl[idx] <= priv->gpio.shift_clk_freq) { 504 val = idx; 505 break; 506 } 507 } 508 509 if (idx == size) 510 dev_warn(priv->dev, "%s: Invalid freq %d\n", 511 __func__, priv->gpio.shift_clk_freq); 512 513 regmap_update_bits(priv->mmap, SSO_CON1, SSO_CON1_FCDSC, 514 FIELD_PREP(SSO_CON1_FCDSC, val)); 515 } 516 517 static int sso_gpio_freq_set(struct sso_led_priv *priv) 518 { 519 int freq_idx; 520 u32 val; 521 522 freq_idx = sso_gpio_get_freq_idx(priv->gpio.freq); 523 if (freq_idx == -1) 524 freq_idx = ARRAY_SIZE(freq_tbl) - 1; 525 526 val = freq_idx % FPID_FREQ_RANK_MAX; 527 528 if (!priv->gpio.freq) { 529 regmap_update_bits(priv->mmap, SSO_CON0, SSO_CON0_BLINK_R, 0); 530 regmap_update_bits(priv->mmap, SSO_CON1, SSO_CON1_US, 531 FIELD_PREP(SSO_CON1_US, US_SW)); 532 } else if (freq_idx < FPID_FREQ_RANK_MAX) { 533 regmap_update_bits(priv->mmap, SSO_CON0, SSO_CON0_BLINK_R, 534 SSO_CON0_BLINK_R); 535 regmap_update_bits(priv->mmap, SSO_CON1, SSO_CON1_US, 536 FIELD_PREP(SSO_CON1_US, US_FPID)); 537 regmap_update_bits(priv->mmap, SSO_CON1, SSO_CON1_FPID, 538 FIELD_PREP(SSO_CON1_FPID, val)); 539 } else { 540 regmap_update_bits(priv->mmap, SSO_CON0, SSO_CON0_BLINK_R, 541 SSO_CON0_BLINK_R); 542 regmap_update_bits(priv->mmap, SSO_CON1, SSO_CON1_US, 543 FIELD_PREP(SSO_CON1_US, US_GPTC)); 544 regmap_update_bits(priv->mmap, SSO_CON1, SSO_CON1_GPTD, 545 FIELD_PREP(SSO_CON1_GPTD, val)); 546 } 547 548 return 0; 549 } 550 551 static int sso_gpio_hw_init(struct sso_led_priv *priv) 552 { 553 u32 activate; 554 int i, err; 555 556 /* Clear all duty cycles */ 557 for (i = 0; i < priv->gpio.pins; i++) { 558 err = regmap_write(priv->mmap, DUTY_CYCLE(i), 0); 559 if (err) 560 return err; 561 } 562 563 /* 4 groups for total 32 pins */ 564 for (i = 1; i <= MAX_GROUP_NUM; i++) { 565 activate = !!(i * PINS_PER_GROUP <= priv->gpio.pins || 566 priv->gpio.pins > (i - 1) * PINS_PER_GROUP); 567 err = regmap_update_bits(priv->mmap, SSO_CON1, BIT(i - 1), 568 activate << (i - 1)); 569 if (err) 570 return err; 571 } 572 573 /* NO HW directly controlled pin by default */ 574 err = regmap_write(priv->mmap, SSO_CON3, 0); 575 if (err) 576 return err; 577 578 /* NO BLINK for all pins */ 579 err = regmap_write(priv->mmap, SSO_CON2, 0); 580 if (err) 581 return err; 582 583 /* OUTPUT 0 by default */ 584 err = regmap_write(priv->mmap, SSO_CPU, 0); 585 if (err) 586 return err; 587 588 /* update edge */ 589 err = regmap_update_bits(priv->mmap, SSO_CON0, SSO_CON0_RZFL, 590 FIELD_PREP(SSO_CON0_RZFL, priv->gpio.edge)); 591 if (err) 592 return err; 593 594 /* Set GPIO update rate */ 595 sso_gpio_freq_set(priv); 596 597 /* Register shift clock */ 598 sso_register_shift_clk(priv); 599 600 return 0; 601 } 602 603 static void sso_led_shutdown(struct sso_led *led) 604 { 605 struct sso_led_priv *priv = led->priv; 606 607 /* unregister led */ 608 devm_led_classdev_unregister(priv->dev, &led->cdev); 609 610 /* clear HW control bit */ 611 if (led->desc.hw_trig) 612 regmap_update_bits(priv->mmap, SSO_CON3, BIT(led->desc.pin), 0); 613 614 if (led->gpiod) 615 devm_gpiod_put(priv->dev, led->gpiod); 616 617 led->priv = NULL; 618 } 619 620 static int 621 __sso_led_dt_parse(struct sso_led_priv *priv, struct fwnode_handle *fw_ssoled) 622 { 623 struct fwnode_handle *fwnode_child; 624 struct device *dev = priv->dev; 625 struct sso_led_desc *desc; 626 struct sso_led *led; 627 struct list_head *p; 628 const char *tmp; 629 u32 prop; 630 int ret; 631 632 fwnode_for_each_child_node(fw_ssoled, fwnode_child) { 633 led = devm_kzalloc(dev, sizeof(*led), GFP_KERNEL); 634 if (!led) 635 return -ENOMEM; 636 637 INIT_LIST_HEAD(&led->list); 638 led->priv = priv; 639 desc = &led->desc; 640 641 led->gpiod = devm_fwnode_get_gpiod_from_child(dev, NULL, 642 fwnode_child, 643 GPIOD_ASIS, NULL); 644 if (IS_ERR(led->gpiod)) { 645 dev_err(dev, "led: get gpio fail!\n"); 646 goto __dt_err; 647 } 648 649 fwnode_property_read_string(fwnode_child, 650 "linux,default-trigger", 651 &desc->default_trigger); 652 653 if (fwnode_property_present(fwnode_child, 654 "retain-state-suspended")) 655 desc->retain_state_suspended = 1; 656 657 if (fwnode_property_present(fwnode_child, 658 "retain-state-shutdown")) 659 desc->retain_state_shutdown = 1; 660 661 if (fwnode_property_present(fwnode_child, "panic-indicator")) 662 desc->panic_indicator = 1; 663 664 ret = fwnode_property_read_u32(fwnode_child, "reg", &prop); 665 if (ret != 0 || prop >= SSO_LED_MAX_NUM) { 666 dev_err(dev, "invalid LED pin:%u\n", prop); 667 goto __dt_err; 668 } 669 desc->pin = prop; 670 671 if (fwnode_property_present(fwnode_child, "intel,sso-hw-blink")) 672 desc->hw_blink = 1; 673 674 desc->hw_trig = fwnode_property_read_bool(fwnode_child, 675 "intel,sso-hw-trigger"); 676 if (desc->hw_trig) { 677 desc->default_trigger = NULL; 678 desc->retain_state_shutdown = 0; 679 desc->retain_state_suspended = 0; 680 desc->panic_indicator = 0; 681 desc->hw_blink = 0; 682 } 683 684 if (fwnode_property_read_u32(fwnode_child, 685 "intel,sso-blink-rate-hz", &prop)) { 686 /* default first freq rate */ 687 desc->freq_idx = 0; 688 desc->blink_rate = priv->freq[desc->freq_idx]; 689 } else { 690 desc->freq_idx = sso_get_blink_rate_idx(priv, prop); 691 if (desc->freq_idx == -1) 692 desc->freq_idx = MAX_FREQ_RANK - 1; 693 694 desc->blink_rate = priv->freq[desc->freq_idx]; 695 } 696 697 if (!fwnode_property_read_string(fwnode_child, "default-state", &tmp)) { 698 if (!strcmp(tmp, "on")) 699 desc->brightness = LED_FULL; 700 } 701 702 if (sso_create_led(priv, led, fwnode_child)) 703 goto __dt_err; 704 } 705 fwnode_handle_put(fw_ssoled); 706 707 return 0; 708 __dt_err: 709 fwnode_handle_put(fw_ssoled); 710 /* unregister leds */ 711 list_for_each(p, &priv->led_list) { 712 led = list_entry(p, struct sso_led, list); 713 sso_led_shutdown(led); 714 } 715 716 return -EINVAL; 717 } 718 719 static int sso_led_dt_parse(struct sso_led_priv *priv) 720 { 721 struct fwnode_handle *fwnode = dev_fwnode(priv->dev); 722 struct fwnode_handle *fw_ssoled; 723 struct device *dev = priv->dev; 724 int count; 725 int ret; 726 727 count = device_get_child_node_count(dev); 728 if (!count) 729 return 0; 730 731 fw_ssoled = fwnode_get_named_child_node(fwnode, "ssoled"); 732 if (fw_ssoled) { 733 ret = __sso_led_dt_parse(priv, fw_ssoled); 734 if (ret) 735 return ret; 736 } 737 738 return 0; 739 } 740 741 static int sso_probe_gpios(struct sso_led_priv *priv) 742 { 743 struct device *dev = priv->dev; 744 int ret; 745 746 if (device_property_read_u32(dev, "ngpios", &priv->gpio.pins)) 747 priv->gpio.pins = MAX_PIN_NUM_PER_BANK; 748 749 if (priv->gpio.pins > MAX_PIN_NUM_PER_BANK) 750 return -EINVAL; 751 752 if (device_property_read_u32(dev, "intel,sso-update-rate-hz", 753 &priv->gpio.freq)) 754 priv->gpio.freq = 0; 755 756 priv->gpio.edge = DATA_CLK_EDGE; 757 priv->gpio.shift_clk_freq = -1; 758 759 ret = sso_gpio_hw_init(priv); 760 if (ret) 761 return ret; 762 763 return sso_gpio_gc_init(dev, priv); 764 } 765 766 static void sso_clk_disable(void *data) 767 { 768 struct sso_led_priv *priv = data; 769 770 clk_disable_unprepare(priv->fpid_clk); 771 clk_disable_unprepare(priv->gclk); 772 } 773 774 static int intel_sso_led_probe(struct platform_device *pdev) 775 { 776 struct device *dev = &pdev->dev; 777 struct sso_led_priv *priv; 778 int ret; 779 780 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 781 if (!priv) 782 return -ENOMEM; 783 784 priv->pdev = pdev; 785 priv->dev = dev; 786 787 /* gate clock */ 788 priv->gclk = devm_clk_get(dev, "sso"); 789 if (IS_ERR(priv->gclk)) { 790 dev_err(dev, "get sso gate clock failed!\n"); 791 return PTR_ERR(priv->gclk); 792 } 793 794 ret = clk_prepare_enable(priv->gclk); 795 if (ret) { 796 dev_err(dev, "Failed to prepate/enable sso gate clock!\n"); 797 return ret; 798 } 799 800 priv->fpid_clk = devm_clk_get(dev, "fpid"); 801 if (IS_ERR(priv->fpid_clk)) { 802 dev_err(dev, "Failed to get fpid clock!\n"); 803 return PTR_ERR(priv->fpid_clk); 804 } 805 806 ret = clk_prepare_enable(priv->fpid_clk); 807 if (ret) { 808 dev_err(dev, "Failed to prepare/enable fpid clock!\n"); 809 return ret; 810 } 811 priv->fpid_clkrate = clk_get_rate(priv->fpid_clk); 812 813 ret = devm_add_action_or_reset(dev, sso_clk_disable, priv); 814 if (ret) { 815 dev_err(dev, "Failed to devm_add_action_or_reset, %d\n", ret); 816 return ret; 817 } 818 819 priv->mmap = syscon_node_to_regmap(dev->of_node); 820 if (IS_ERR(priv->mmap)) { 821 dev_err(dev, "Failed to map iomem!\n"); 822 return PTR_ERR(priv->mmap); 823 } 824 825 ret = sso_probe_gpios(priv); 826 if (ret) { 827 regmap_exit(priv->mmap); 828 return ret; 829 } 830 831 INIT_LIST_HEAD(&priv->led_list); 832 833 platform_set_drvdata(pdev, priv); 834 sso_init_freq(priv); 835 836 priv->gptc_clkrate = DEF_GPTC_CLK_RATE; 837 838 ret = sso_led_dt_parse(priv); 839 if (ret) { 840 regmap_exit(priv->mmap); 841 return ret; 842 } 843 dev_info(priv->dev, "sso LED init success!\n"); 844 845 return 0; 846 } 847 848 static int intel_sso_led_remove(struct platform_device *pdev) 849 { 850 struct sso_led_priv *priv; 851 struct list_head *pos, *n; 852 struct sso_led *led; 853 854 priv = platform_get_drvdata(pdev); 855 856 list_for_each_safe(pos, n, &priv->led_list) { 857 list_del(pos); 858 led = list_entry(pos, struct sso_led, list); 859 sso_led_shutdown(led); 860 } 861 862 clk_disable_unprepare(priv->fpid_clk); 863 clk_disable_unprepare(priv->gclk); 864 regmap_exit(priv->mmap); 865 866 return 0; 867 } 868 869 static const struct of_device_id of_sso_led_match[] = { 870 { .compatible = "intel,lgm-ssoled" }, 871 {} 872 }; 873 874 MODULE_DEVICE_TABLE(of, of_sso_led_match); 875 876 static struct platform_driver intel_sso_led_driver = { 877 .probe = intel_sso_led_probe, 878 .remove = intel_sso_led_remove, 879 .driver = { 880 .name = "lgm-ssoled", 881 .of_match_table = of_match_ptr(of_sso_led_match), 882 }, 883 }; 884 885 module_platform_driver(intel_sso_led_driver); 886 887 MODULE_DESCRIPTION("Intel SSO LED/GPIO driver"); 888 MODULE_LICENSE("GPL v2"); 889