1 /* 2 * NETJet mISDN driver 3 * 4 * Author Karsten Keil <keil@isdn4linux.de> 5 * 6 * Copyright 2009 by Karsten Keil <keil@isdn4linux.de> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 20 * 21 */ 22 23 #include <linux/interrupt.h> 24 #include <linux/module.h> 25 #include <linux/pci.h> 26 #include <linux/delay.h> 27 #include <linux/mISDNhw.h> 28 #include <linux/slab.h> 29 #include "ipac.h" 30 #include "iohelper.h" 31 #include "netjet.h" 32 #include <linux/isdn/hdlc.h> 33 34 #define NETJET_REV "2.0" 35 36 enum nj_types { 37 NETJET_S_TJ300, 38 NETJET_S_TJ320, 39 ENTERNOW__TJ320, 40 }; 41 42 struct tiger_dma { 43 size_t size; 44 u32 *start; 45 int idx; 46 u32 dmastart; 47 u32 dmairq; 48 u32 dmaend; 49 u32 dmacur; 50 }; 51 52 struct tiger_hw; 53 54 struct tiger_ch { 55 struct bchannel bch; 56 struct tiger_hw *nj; 57 int idx; 58 int free; 59 int lastrx; 60 u16 rxstate; 61 u16 txstate; 62 struct isdnhdlc_vars hsend; 63 struct isdnhdlc_vars hrecv; 64 u8 *hsbuf; 65 u8 *hrbuf; 66 }; 67 68 #define TX_INIT 0x0001 69 #define TX_IDLE 0x0002 70 #define TX_RUN 0x0004 71 #define TX_UNDERRUN 0x0100 72 #define RX_OVERRUN 0x0100 73 74 #define LOG_SIZE 64 75 76 struct tiger_hw { 77 struct list_head list; 78 struct pci_dev *pdev; 79 char name[MISDN_MAX_IDLEN]; 80 enum nj_types typ; 81 int irq; 82 u32 irqcnt; 83 u32 base; 84 size_t base_s; 85 dma_addr_t dma; 86 void *dma_p; 87 spinlock_t lock; /* lock HW */ 88 struct isac_hw isac; 89 struct tiger_dma send; 90 struct tiger_dma recv; 91 struct tiger_ch bc[2]; 92 u8 ctrlreg; 93 u8 dmactrl; 94 u8 auxd; 95 u8 last_is0; 96 u8 irqmask0; 97 char log[LOG_SIZE]; 98 }; 99 100 static LIST_HEAD(Cards); 101 static DEFINE_RWLOCK(card_lock); /* protect Cards */ 102 static u32 debug; 103 static int nj_cnt; 104 105 static void 106 _set_debug(struct tiger_hw *card) 107 { 108 card->isac.dch.debug = debug; 109 card->bc[0].bch.debug = debug; 110 card->bc[1].bch.debug = debug; 111 } 112 113 static int 114 set_debug(const char *val, const struct kernel_param *kp) 115 { 116 int ret; 117 struct tiger_hw *card; 118 119 ret = param_set_uint(val, kp); 120 if (!ret) { 121 read_lock(&card_lock); 122 list_for_each_entry(card, &Cards, list) 123 _set_debug(card); 124 read_unlock(&card_lock); 125 } 126 return ret; 127 } 128 129 MODULE_AUTHOR("Karsten Keil"); 130 MODULE_LICENSE("GPL v2"); 131 MODULE_VERSION(NETJET_REV); 132 module_param_call(debug, set_debug, param_get_uint, &debug, S_IRUGO | S_IWUSR); 133 MODULE_PARM_DESC(debug, "Netjet debug mask"); 134 135 static void 136 nj_disable_hwirq(struct tiger_hw *card) 137 { 138 outb(0, card->base + NJ_IRQMASK0); 139 outb(0, card->base + NJ_IRQMASK1); 140 } 141 142 143 static u8 144 ReadISAC_nj(void *p, u8 offset) 145 { 146 struct tiger_hw *card = p; 147 u8 ret; 148 149 card->auxd &= 0xfc; 150 card->auxd |= (offset >> 4) & 3; 151 outb(card->auxd, card->base + NJ_AUXDATA); 152 ret = inb(card->base + NJ_ISAC_OFF + ((offset & 0x0f) << 2)); 153 return ret; 154 } 155 156 static void 157 WriteISAC_nj(void *p, u8 offset, u8 value) 158 { 159 struct tiger_hw *card = p; 160 161 card->auxd &= 0xfc; 162 card->auxd |= (offset >> 4) & 3; 163 outb(card->auxd, card->base + NJ_AUXDATA); 164 outb(value, card->base + NJ_ISAC_OFF + ((offset & 0x0f) << 2)); 165 } 166 167 static void 168 ReadFiFoISAC_nj(void *p, u8 offset, u8 *data, int size) 169 { 170 struct tiger_hw *card = p; 171 172 card->auxd &= 0xfc; 173 outb(card->auxd, card->base + NJ_AUXDATA); 174 insb(card->base + NJ_ISAC_OFF, data, size); 175 } 176 177 static void 178 WriteFiFoISAC_nj(void *p, u8 offset, u8 *data, int size) 179 { 180 struct tiger_hw *card = p; 181 182 card->auxd &= 0xfc; 183 outb(card->auxd, card->base + NJ_AUXDATA); 184 outsb(card->base + NJ_ISAC_OFF, data, size); 185 } 186 187 static void 188 fill_mem(struct tiger_ch *bc, u32 idx, u32 cnt, u32 fill) 189 { 190 struct tiger_hw *card = bc->bch.hw; 191 u32 mask = 0xff, val; 192 193 pr_debug("%s: B%1d fill %02x len %d idx %d/%d\n", card->name, 194 bc->bch.nr, fill, cnt, idx, card->send.idx); 195 if (bc->bch.nr & 2) { 196 fill <<= 8; 197 mask <<= 8; 198 } 199 mask ^= 0xffffffff; 200 while (cnt--) { 201 val = card->send.start[idx]; 202 val &= mask; 203 val |= fill; 204 card->send.start[idx++] = val; 205 if (idx >= card->send.size) 206 idx = 0; 207 } 208 } 209 210 static int 211 mode_tiger(struct tiger_ch *bc, u32 protocol) 212 { 213 struct tiger_hw *card = bc->bch.hw; 214 215 pr_debug("%s: B%1d protocol %x-->%x\n", card->name, 216 bc->bch.nr, bc->bch.state, protocol); 217 switch (protocol) { 218 case ISDN_P_NONE: 219 if (bc->bch.state == ISDN_P_NONE) 220 break; 221 fill_mem(bc, 0, card->send.size, 0xff); 222 bc->bch.state = protocol; 223 /* only stop dma and interrupts if both channels NULL */ 224 if ((card->bc[0].bch.state == ISDN_P_NONE) && 225 (card->bc[1].bch.state == ISDN_P_NONE)) { 226 card->dmactrl = 0; 227 outb(card->dmactrl, card->base + NJ_DMACTRL); 228 outb(0, card->base + NJ_IRQMASK0); 229 } 230 test_and_clear_bit(FLG_HDLC, &bc->bch.Flags); 231 test_and_clear_bit(FLG_TRANSPARENT, &bc->bch.Flags); 232 bc->txstate = 0; 233 bc->rxstate = 0; 234 bc->lastrx = -1; 235 break; 236 case ISDN_P_B_RAW: 237 test_and_set_bit(FLG_TRANSPARENT, &bc->bch.Flags); 238 bc->bch.state = protocol; 239 bc->idx = 0; 240 bc->free = card->send.size / 2; 241 bc->rxstate = 0; 242 bc->txstate = TX_INIT | TX_IDLE; 243 bc->lastrx = -1; 244 if (!card->dmactrl) { 245 card->dmactrl = 1; 246 outb(card->dmactrl, card->base + NJ_DMACTRL); 247 outb(0x0f, card->base + NJ_IRQMASK0); 248 } 249 break; 250 case ISDN_P_B_HDLC: 251 test_and_set_bit(FLG_HDLC, &bc->bch.Flags); 252 bc->bch.state = protocol; 253 bc->idx = 0; 254 bc->free = card->send.size / 2; 255 bc->rxstate = 0; 256 bc->txstate = TX_INIT | TX_IDLE; 257 isdnhdlc_rcv_init(&bc->hrecv, 0); 258 isdnhdlc_out_init(&bc->hsend, 0); 259 bc->lastrx = -1; 260 if (!card->dmactrl) { 261 card->dmactrl = 1; 262 outb(card->dmactrl, card->base + NJ_DMACTRL); 263 outb(0x0f, card->base + NJ_IRQMASK0); 264 } 265 break; 266 default: 267 pr_info("%s: %s protocol %x not handled\n", card->name, 268 __func__, protocol); 269 return -ENOPROTOOPT; 270 } 271 card->send.dmacur = inl(card->base + NJ_DMA_READ_ADR); 272 card->recv.dmacur = inl(card->base + NJ_DMA_WRITE_ADR); 273 card->send.idx = (card->send.dmacur - card->send.dmastart) >> 2; 274 card->recv.idx = (card->recv.dmacur - card->recv.dmastart) >> 2; 275 pr_debug("%s: %s ctrl %x irq %02x/%02x idx %d/%d\n", 276 card->name, __func__, 277 inb(card->base + NJ_DMACTRL), 278 inb(card->base + NJ_IRQMASK0), 279 inb(card->base + NJ_IRQSTAT0), 280 card->send.idx, 281 card->recv.idx); 282 return 0; 283 } 284 285 static void 286 nj_reset(struct tiger_hw *card) 287 { 288 outb(0xff, card->base + NJ_CTRL); /* Reset On */ 289 mdelay(1); 290 291 /* now edge triggered for TJ320 GE 13/07/00 */ 292 /* see comment in IRQ function */ 293 if (card->typ == NETJET_S_TJ320) /* TJ320 */ 294 card->ctrlreg = 0x40; /* Reset Off and status read clear */ 295 else 296 card->ctrlreg = 0x00; /* Reset Off and status read clear */ 297 outb(card->ctrlreg, card->base + NJ_CTRL); 298 mdelay(10); 299 300 /* configure AUX pins (all output except ISAC IRQ pin) */ 301 card->auxd = 0; 302 card->dmactrl = 0; 303 outb(~NJ_ISACIRQ, card->base + NJ_AUXCTRL); 304 outb(NJ_ISACIRQ, card->base + NJ_IRQMASK1); 305 outb(card->auxd, card->base + NJ_AUXDATA); 306 } 307 308 static int 309 inittiger(struct tiger_hw *card) 310 { 311 int i; 312 313 card->dma_p = pci_alloc_consistent(card->pdev, NJ_DMA_SIZE, 314 &card->dma); 315 if (!card->dma_p) { 316 pr_info("%s: No DMA memory\n", card->name); 317 return -ENOMEM; 318 } 319 if ((u64)card->dma > 0xffffffff) { 320 pr_info("%s: DMA outside 32 bit\n", card->name); 321 return -ENOMEM; 322 } 323 for (i = 0; i < 2; i++) { 324 card->bc[i].hsbuf = kmalloc(NJ_DMA_TXSIZE, GFP_ATOMIC); 325 if (!card->bc[i].hsbuf) { 326 pr_info("%s: no B%d send buffer\n", card->name, i + 1); 327 return -ENOMEM; 328 } 329 card->bc[i].hrbuf = kmalloc(NJ_DMA_RXSIZE, GFP_ATOMIC); 330 if (!card->bc[i].hrbuf) { 331 pr_info("%s: no B%d recv buffer\n", card->name, i + 1); 332 return -ENOMEM; 333 } 334 } 335 memset(card->dma_p, 0xff, NJ_DMA_SIZE); 336 337 card->send.start = card->dma_p; 338 card->send.dmastart = (u32)card->dma; 339 card->send.dmaend = card->send.dmastart + 340 (4 * (NJ_DMA_TXSIZE - 1)); 341 card->send.dmairq = card->send.dmastart + 342 (4 * ((NJ_DMA_TXSIZE / 2) - 1)); 343 card->send.size = NJ_DMA_TXSIZE; 344 345 if (debug & DEBUG_HW) 346 pr_notice("%s: send buffer phy %#x - %#x - %#x virt %p" 347 " size %zu u32\n", card->name, 348 card->send.dmastart, card->send.dmairq, 349 card->send.dmaend, card->send.start, card->send.size); 350 351 outl(card->send.dmastart, card->base + NJ_DMA_READ_START); 352 outl(card->send.dmairq, card->base + NJ_DMA_READ_IRQ); 353 outl(card->send.dmaend, card->base + NJ_DMA_READ_END); 354 355 card->recv.start = card->dma_p + (NJ_DMA_SIZE / 2); 356 card->recv.dmastart = (u32)card->dma + (NJ_DMA_SIZE / 2); 357 card->recv.dmaend = card->recv.dmastart + 358 (4 * (NJ_DMA_RXSIZE - 1)); 359 card->recv.dmairq = card->recv.dmastart + 360 (4 * ((NJ_DMA_RXSIZE / 2) - 1)); 361 card->recv.size = NJ_DMA_RXSIZE; 362 363 if (debug & DEBUG_HW) 364 pr_notice("%s: recv buffer phy %#x - %#x - %#x virt %p" 365 " size %zu u32\n", card->name, 366 card->recv.dmastart, card->recv.dmairq, 367 card->recv.dmaend, card->recv.start, card->recv.size); 368 369 outl(card->recv.dmastart, card->base + NJ_DMA_WRITE_START); 370 outl(card->recv.dmairq, card->base + NJ_DMA_WRITE_IRQ); 371 outl(card->recv.dmaend, card->base + NJ_DMA_WRITE_END); 372 return 0; 373 } 374 375 static void 376 read_dma(struct tiger_ch *bc, u32 idx, int cnt) 377 { 378 struct tiger_hw *card = bc->bch.hw; 379 int i, stat; 380 u32 val; 381 u8 *p, *pn; 382 383 if (bc->lastrx == idx) { 384 bc->rxstate |= RX_OVERRUN; 385 pr_info("%s: B%1d overrun at idx %d\n", card->name, 386 bc->bch.nr, idx); 387 } 388 bc->lastrx = idx; 389 if (test_bit(FLG_RX_OFF, &bc->bch.Flags)) { 390 bc->bch.dropcnt += cnt; 391 return; 392 } 393 stat = bchannel_get_rxbuf(&bc->bch, cnt); 394 /* only transparent use the count here, HDLC overun is detected later */ 395 if (stat == -ENOMEM) { 396 pr_warning("%s.B%d: No memory for %d bytes\n", 397 card->name, bc->bch.nr, cnt); 398 return; 399 } 400 if (test_bit(FLG_TRANSPARENT, &bc->bch.Flags)) 401 p = skb_put(bc->bch.rx_skb, cnt); 402 else 403 p = bc->hrbuf; 404 405 for (i = 0; i < cnt; i++) { 406 val = card->recv.start[idx++]; 407 if (bc->bch.nr & 2) 408 val >>= 8; 409 if (idx >= card->recv.size) 410 idx = 0; 411 p[i] = val & 0xff; 412 } 413 414 if (test_bit(FLG_TRANSPARENT, &bc->bch.Flags)) { 415 recv_Bchannel(&bc->bch, 0, false); 416 return; 417 } 418 419 pn = bc->hrbuf; 420 while (cnt > 0) { 421 stat = isdnhdlc_decode(&bc->hrecv, pn, cnt, &i, 422 bc->bch.rx_skb->data, bc->bch.maxlen); 423 if (stat > 0) { /* valid frame received */ 424 p = skb_put(bc->bch.rx_skb, stat); 425 if (debug & DEBUG_HW_BFIFO) { 426 snprintf(card->log, LOG_SIZE, 427 "B%1d-recv %s %d ", bc->bch.nr, 428 card->name, stat); 429 print_hex_dump_bytes(card->log, 430 DUMP_PREFIX_OFFSET, p, 431 stat); 432 } 433 recv_Bchannel(&bc->bch, 0, false); 434 stat = bchannel_get_rxbuf(&bc->bch, bc->bch.maxlen); 435 if (stat < 0) { 436 pr_warning("%s.B%d: No memory for %d bytes\n", 437 card->name, bc->bch.nr, cnt); 438 return; 439 } 440 } else if (stat == -HDLC_CRC_ERROR) { 441 pr_info("%s: B%1d receive frame CRC error\n", 442 card->name, bc->bch.nr); 443 } else if (stat == -HDLC_FRAMING_ERROR) { 444 pr_info("%s: B%1d receive framing error\n", 445 card->name, bc->bch.nr); 446 } else if (stat == -HDLC_LENGTH_ERROR) { 447 pr_info("%s: B%1d receive frame too long (> %d)\n", 448 card->name, bc->bch.nr, bc->bch.maxlen); 449 } 450 pn += i; 451 cnt -= i; 452 } 453 } 454 455 static void 456 recv_tiger(struct tiger_hw *card, u8 irq_stat) 457 { 458 u32 idx; 459 int cnt = card->recv.size / 2; 460 461 /* Note receive is via the WRITE DMA channel */ 462 card->last_is0 &= ~NJ_IRQM0_WR_MASK; 463 card->last_is0 |= (irq_stat & NJ_IRQM0_WR_MASK); 464 465 if (irq_stat & NJ_IRQM0_WR_END) 466 idx = cnt - 1; 467 else 468 idx = card->recv.size - 1; 469 470 if (test_bit(FLG_ACTIVE, &card->bc[0].bch.Flags)) 471 read_dma(&card->bc[0], idx, cnt); 472 if (test_bit(FLG_ACTIVE, &card->bc[1].bch.Flags)) 473 read_dma(&card->bc[1], idx, cnt); 474 } 475 476 /* sync with current DMA address at start or after exception */ 477 static void 478 resync(struct tiger_ch *bc, struct tiger_hw *card) 479 { 480 card->send.dmacur = inl(card->base | NJ_DMA_READ_ADR); 481 card->send.idx = (card->send.dmacur - card->send.dmastart) >> 2; 482 if (bc->free > card->send.size / 2) 483 bc->free = card->send.size / 2; 484 /* currently we simple sync to the next complete free area 485 * this hast the advantage that we have always maximum time to 486 * handle TX irq 487 */ 488 if (card->send.idx < ((card->send.size / 2) - 1)) 489 bc->idx = (card->recv.size / 2) - 1; 490 else 491 bc->idx = card->recv.size - 1; 492 bc->txstate = TX_RUN; 493 pr_debug("%s: %s B%1d free %d idx %d/%d\n", card->name, 494 __func__, bc->bch.nr, bc->free, bc->idx, card->send.idx); 495 } 496 497 static int bc_next_frame(struct tiger_ch *); 498 499 static void 500 fill_hdlc_flag(struct tiger_ch *bc) 501 { 502 struct tiger_hw *card = bc->bch.hw; 503 int count, i; 504 u32 m, v; 505 u8 *p; 506 507 if (bc->free == 0) 508 return; 509 pr_debug("%s: %s B%1d %d state %x idx %d/%d\n", card->name, 510 __func__, bc->bch.nr, bc->free, bc->txstate, 511 bc->idx, card->send.idx); 512 if (bc->txstate & (TX_IDLE | TX_INIT | TX_UNDERRUN)) 513 resync(bc, card); 514 count = isdnhdlc_encode(&bc->hsend, NULL, 0, &i, 515 bc->hsbuf, bc->free); 516 pr_debug("%s: B%1d hdlc encoded %d flags\n", card->name, 517 bc->bch.nr, count); 518 bc->free -= count; 519 p = bc->hsbuf; 520 m = (bc->bch.nr & 1) ? 0xffffff00 : 0xffff00ff; 521 for (i = 0; i < count; i++) { 522 if (bc->idx >= card->send.size) 523 bc->idx = 0; 524 v = card->send.start[bc->idx]; 525 v &= m; 526 v |= (bc->bch.nr & 1) ? (u32)(p[i]) : ((u32)(p[i])) << 8; 527 card->send.start[bc->idx++] = v; 528 } 529 if (debug & DEBUG_HW_BFIFO) { 530 snprintf(card->log, LOG_SIZE, "B%1d-send %s %d ", 531 bc->bch.nr, card->name, count); 532 print_hex_dump_bytes(card->log, DUMP_PREFIX_OFFSET, p, count); 533 } 534 } 535 536 static void 537 fill_dma(struct tiger_ch *bc) 538 { 539 struct tiger_hw *card = bc->bch.hw; 540 int count, i, fillempty = 0; 541 u32 m, v, n = 0; 542 u8 *p; 543 544 if (bc->free == 0) 545 return; 546 if (!bc->bch.tx_skb) { 547 if (!test_bit(FLG_TX_EMPTY, &bc->bch.Flags)) 548 return; 549 fillempty = 1; 550 count = card->send.size >> 1; 551 p = bc->bch.fill; 552 } else { 553 count = bc->bch.tx_skb->len - bc->bch.tx_idx; 554 if (count <= 0) 555 return; 556 pr_debug("%s: %s B%1d %d/%d/%d/%d state %x idx %d/%d\n", 557 card->name, __func__, bc->bch.nr, count, bc->free, 558 bc->bch.tx_idx, bc->bch.tx_skb->len, bc->txstate, 559 bc->idx, card->send.idx); 560 p = bc->bch.tx_skb->data + bc->bch.tx_idx; 561 } 562 if (bc->txstate & (TX_IDLE | TX_INIT | TX_UNDERRUN)) 563 resync(bc, card); 564 if (test_bit(FLG_HDLC, &bc->bch.Flags) && !fillempty) { 565 count = isdnhdlc_encode(&bc->hsend, p, count, &i, 566 bc->hsbuf, bc->free); 567 pr_debug("%s: B%1d hdlc encoded %d in %d\n", card->name, 568 bc->bch.nr, i, count); 569 bc->bch.tx_idx += i; 570 bc->free -= count; 571 p = bc->hsbuf; 572 } else { 573 if (count > bc->free) 574 count = bc->free; 575 if (!fillempty) 576 bc->bch.tx_idx += count; 577 bc->free -= count; 578 } 579 m = (bc->bch.nr & 1) ? 0xffffff00 : 0xffff00ff; 580 if (fillempty) { 581 n = p[0]; 582 if (!(bc->bch.nr & 1)) 583 n <<= 8; 584 for (i = 0; i < count; i++) { 585 if (bc->idx >= card->send.size) 586 bc->idx = 0; 587 v = card->send.start[bc->idx]; 588 v &= m; 589 v |= n; 590 card->send.start[bc->idx++] = v; 591 } 592 } else { 593 for (i = 0; i < count; i++) { 594 if (bc->idx >= card->send.size) 595 bc->idx = 0; 596 v = card->send.start[bc->idx]; 597 v &= m; 598 n = p[i]; 599 v |= (bc->bch.nr & 1) ? n : n << 8; 600 card->send.start[bc->idx++] = v; 601 } 602 } 603 if (debug & DEBUG_HW_BFIFO) { 604 snprintf(card->log, LOG_SIZE, "B%1d-send %s %d ", 605 bc->bch.nr, card->name, count); 606 print_hex_dump_bytes(card->log, DUMP_PREFIX_OFFSET, p, count); 607 } 608 if (bc->free) 609 bc_next_frame(bc); 610 } 611 612 613 static int 614 bc_next_frame(struct tiger_ch *bc) 615 { 616 int ret = 1; 617 618 if (bc->bch.tx_skb && bc->bch.tx_idx < bc->bch.tx_skb->len) { 619 fill_dma(bc); 620 } else { 621 if (bc->bch.tx_skb) 622 dev_kfree_skb(bc->bch.tx_skb); 623 if (get_next_bframe(&bc->bch)) { 624 fill_dma(bc); 625 test_and_clear_bit(FLG_TX_EMPTY, &bc->bch.Flags); 626 } else if (test_bit(FLG_TX_EMPTY, &bc->bch.Flags)) { 627 fill_dma(bc); 628 } else if (test_bit(FLG_FILLEMPTY, &bc->bch.Flags)) { 629 test_and_set_bit(FLG_TX_EMPTY, &bc->bch.Flags); 630 ret = 0; 631 } else { 632 ret = 0; 633 } 634 } 635 return ret; 636 } 637 638 static void 639 send_tiger_bc(struct tiger_hw *card, struct tiger_ch *bc) 640 { 641 int ret; 642 643 bc->free += card->send.size / 2; 644 if (bc->free >= card->send.size) { 645 if (!(bc->txstate & (TX_UNDERRUN | TX_INIT))) { 646 pr_info("%s: B%1d TX underrun state %x\n", card->name, 647 bc->bch.nr, bc->txstate); 648 bc->txstate |= TX_UNDERRUN; 649 } 650 bc->free = card->send.size; 651 } 652 ret = bc_next_frame(bc); 653 if (!ret) { 654 if (test_bit(FLG_HDLC, &bc->bch.Flags)) { 655 fill_hdlc_flag(bc); 656 return; 657 } 658 pr_debug("%s: B%1d TX no data free %d idx %d/%d\n", card->name, 659 bc->bch.nr, bc->free, bc->idx, card->send.idx); 660 if (!(bc->txstate & (TX_IDLE | TX_INIT))) { 661 fill_mem(bc, bc->idx, bc->free, 0xff); 662 if (bc->free == card->send.size) 663 bc->txstate |= TX_IDLE; 664 } 665 } 666 } 667 668 static void 669 send_tiger(struct tiger_hw *card, u8 irq_stat) 670 { 671 int i; 672 673 /* Note send is via the READ DMA channel */ 674 if ((irq_stat & card->last_is0) & NJ_IRQM0_RD_MASK) { 675 pr_info("%s: tiger warn write double dma %x/%x\n", 676 card->name, irq_stat, card->last_is0); 677 return; 678 } else { 679 card->last_is0 &= ~NJ_IRQM0_RD_MASK; 680 card->last_is0 |= (irq_stat & NJ_IRQM0_RD_MASK); 681 } 682 for (i = 0; i < 2; i++) { 683 if (test_bit(FLG_ACTIVE, &card->bc[i].bch.Flags)) 684 send_tiger_bc(card, &card->bc[i]); 685 } 686 } 687 688 static irqreturn_t 689 nj_irq(int intno, void *dev_id) 690 { 691 struct tiger_hw *card = dev_id; 692 u8 val, s1val, s0val; 693 694 spin_lock(&card->lock); 695 s0val = inb(card->base | NJ_IRQSTAT0); 696 s1val = inb(card->base | NJ_IRQSTAT1); 697 if ((s1val & NJ_ISACIRQ) && (s0val == 0)) { 698 /* shared IRQ */ 699 spin_unlock(&card->lock); 700 return IRQ_NONE; 701 } 702 pr_debug("%s: IRQSTAT0 %02x IRQSTAT1 %02x\n", card->name, s0val, s1val); 703 card->irqcnt++; 704 if (!(s1val & NJ_ISACIRQ)) { 705 val = ReadISAC_nj(card, ISAC_ISTA); 706 if (val) 707 mISDNisac_irq(&card->isac, val); 708 } 709 710 if (s0val) 711 /* write to clear */ 712 outb(s0val, card->base | NJ_IRQSTAT0); 713 else 714 goto end; 715 s1val = s0val; 716 /* set bits in sval to indicate which page is free */ 717 card->recv.dmacur = inl(card->base | NJ_DMA_WRITE_ADR); 718 card->recv.idx = (card->recv.dmacur - card->recv.dmastart) >> 2; 719 if (card->recv.dmacur < card->recv.dmairq) 720 s0val = 0x08; /* the 2nd write area is free */ 721 else 722 s0val = 0x04; /* the 1st write area is free */ 723 724 card->send.dmacur = inl(card->base | NJ_DMA_READ_ADR); 725 card->send.idx = (card->send.dmacur - card->send.dmastart) >> 2; 726 if (card->send.dmacur < card->send.dmairq) 727 s0val |= 0x02; /* the 2nd read area is free */ 728 else 729 s0val |= 0x01; /* the 1st read area is free */ 730 731 pr_debug("%s: DMA Status %02x/%02x/%02x %d/%d\n", card->name, 732 s1val, s0val, card->last_is0, 733 card->recv.idx, card->send.idx); 734 /* test if we have a DMA interrupt */ 735 if (s0val != card->last_is0) { 736 if ((s0val & NJ_IRQM0_RD_MASK) != 737 (card->last_is0 & NJ_IRQM0_RD_MASK)) 738 /* got a write dma int */ 739 send_tiger(card, s0val); 740 if ((s0val & NJ_IRQM0_WR_MASK) != 741 (card->last_is0 & NJ_IRQM0_WR_MASK)) 742 /* got a read dma int */ 743 recv_tiger(card, s0val); 744 } 745 end: 746 spin_unlock(&card->lock); 747 return IRQ_HANDLED; 748 } 749 750 static int 751 nj_l2l1B(struct mISDNchannel *ch, struct sk_buff *skb) 752 { 753 int ret = -EINVAL; 754 struct bchannel *bch = container_of(ch, struct bchannel, ch); 755 struct tiger_ch *bc = container_of(bch, struct tiger_ch, bch); 756 struct tiger_hw *card = bch->hw; 757 struct mISDNhead *hh = mISDN_HEAD_P(skb); 758 unsigned long flags; 759 760 switch (hh->prim) { 761 case PH_DATA_REQ: 762 spin_lock_irqsave(&card->lock, flags); 763 ret = bchannel_senddata(bch, skb); 764 if (ret > 0) { /* direct TX */ 765 fill_dma(bc); 766 ret = 0; 767 } 768 spin_unlock_irqrestore(&card->lock, flags); 769 return ret; 770 case PH_ACTIVATE_REQ: 771 spin_lock_irqsave(&card->lock, flags); 772 if (!test_and_set_bit(FLG_ACTIVE, &bch->Flags)) 773 ret = mode_tiger(bc, ch->protocol); 774 else 775 ret = 0; 776 spin_unlock_irqrestore(&card->lock, flags); 777 if (!ret) 778 _queue_data(ch, PH_ACTIVATE_IND, MISDN_ID_ANY, 0, 779 NULL, GFP_KERNEL); 780 break; 781 case PH_DEACTIVATE_REQ: 782 spin_lock_irqsave(&card->lock, flags); 783 mISDN_clear_bchannel(bch); 784 mode_tiger(bc, ISDN_P_NONE); 785 spin_unlock_irqrestore(&card->lock, flags); 786 _queue_data(ch, PH_DEACTIVATE_IND, MISDN_ID_ANY, 0, 787 NULL, GFP_KERNEL); 788 ret = 0; 789 break; 790 } 791 if (!ret) 792 dev_kfree_skb(skb); 793 return ret; 794 } 795 796 static int 797 channel_bctrl(struct tiger_ch *bc, struct mISDN_ctrl_req *cq) 798 { 799 return mISDN_ctrl_bchannel(&bc->bch, cq); 800 } 801 802 static int 803 nj_bctrl(struct mISDNchannel *ch, u32 cmd, void *arg) 804 { 805 struct bchannel *bch = container_of(ch, struct bchannel, ch); 806 struct tiger_ch *bc = container_of(bch, struct tiger_ch, bch); 807 struct tiger_hw *card = bch->hw; 808 int ret = -EINVAL; 809 u_long flags; 810 811 pr_debug("%s: %s cmd:%x %p\n", card->name, __func__, cmd, arg); 812 switch (cmd) { 813 case CLOSE_CHANNEL: 814 test_and_clear_bit(FLG_OPEN, &bch->Flags); 815 cancel_work_sync(&bch->workq); 816 spin_lock_irqsave(&card->lock, flags); 817 mISDN_clear_bchannel(bch); 818 mode_tiger(bc, ISDN_P_NONE); 819 spin_unlock_irqrestore(&card->lock, flags); 820 ch->protocol = ISDN_P_NONE; 821 ch->peer = NULL; 822 module_put(THIS_MODULE); 823 ret = 0; 824 break; 825 case CONTROL_CHANNEL: 826 ret = channel_bctrl(bc, arg); 827 break; 828 default: 829 pr_info("%s: %s unknown prim(%x)\n", card->name, __func__, cmd); 830 } 831 return ret; 832 } 833 834 static int 835 channel_ctrl(struct tiger_hw *card, struct mISDN_ctrl_req *cq) 836 { 837 int ret = 0; 838 839 switch (cq->op) { 840 case MISDN_CTRL_GETOP: 841 cq->op = MISDN_CTRL_LOOP | MISDN_CTRL_L1_TIMER3; 842 break; 843 case MISDN_CTRL_LOOP: 844 /* cq->channel: 0 disable, 1 B1 loop 2 B2 loop, 3 both */ 845 if (cq->channel < 0 || cq->channel > 3) { 846 ret = -EINVAL; 847 break; 848 } 849 ret = card->isac.ctrl(&card->isac, HW_TESTLOOP, cq->channel); 850 break; 851 case MISDN_CTRL_L1_TIMER3: 852 ret = card->isac.ctrl(&card->isac, HW_TIMER3_VALUE, cq->p1); 853 break; 854 default: 855 pr_info("%s: %s unknown Op %x\n", card->name, __func__, cq->op); 856 ret = -EINVAL; 857 break; 858 } 859 return ret; 860 } 861 862 static int 863 open_bchannel(struct tiger_hw *card, struct channel_req *rq) 864 { 865 struct bchannel *bch; 866 867 if (rq->adr.channel == 0 || rq->adr.channel > 2) 868 return -EINVAL; 869 if (rq->protocol == ISDN_P_NONE) 870 return -EINVAL; 871 bch = &card->bc[rq->adr.channel - 1].bch; 872 if (test_and_set_bit(FLG_OPEN, &bch->Flags)) 873 return -EBUSY; /* b-channel can be only open once */ 874 test_and_clear_bit(FLG_FILLEMPTY, &bch->Flags); 875 bch->ch.protocol = rq->protocol; 876 rq->ch = &bch->ch; 877 return 0; 878 } 879 880 /* 881 * device control function 882 */ 883 static int 884 nj_dctrl(struct mISDNchannel *ch, u32 cmd, void *arg) 885 { 886 struct mISDNdevice *dev = container_of(ch, struct mISDNdevice, D); 887 struct dchannel *dch = container_of(dev, struct dchannel, dev); 888 struct tiger_hw *card = dch->hw; 889 struct channel_req *rq; 890 int err = 0; 891 892 pr_debug("%s: %s cmd:%x %p\n", card->name, __func__, cmd, arg); 893 switch (cmd) { 894 case OPEN_CHANNEL: 895 rq = arg; 896 if (rq->protocol == ISDN_P_TE_S0) 897 err = card->isac.open(&card->isac, rq); 898 else 899 err = open_bchannel(card, rq); 900 if (err) 901 break; 902 if (!try_module_get(THIS_MODULE)) 903 pr_info("%s: cannot get module\n", card->name); 904 break; 905 case CLOSE_CHANNEL: 906 pr_debug("%s: dev(%d) close from %p\n", card->name, dch->dev.id, 907 __builtin_return_address(0)); 908 module_put(THIS_MODULE); 909 break; 910 case CONTROL_CHANNEL: 911 err = channel_ctrl(card, arg); 912 break; 913 default: 914 pr_debug("%s: %s unknown command %x\n", 915 card->name, __func__, cmd); 916 return -EINVAL; 917 } 918 return err; 919 } 920 921 static int 922 nj_init_card(struct tiger_hw *card) 923 { 924 u_long flags; 925 int ret; 926 927 spin_lock_irqsave(&card->lock, flags); 928 nj_disable_hwirq(card); 929 spin_unlock_irqrestore(&card->lock, flags); 930 931 card->irq = card->pdev->irq; 932 if (request_irq(card->irq, nj_irq, IRQF_SHARED, card->name, card)) { 933 pr_info("%s: couldn't get interrupt %d\n", 934 card->name, card->irq); 935 card->irq = -1; 936 return -EIO; 937 } 938 939 spin_lock_irqsave(&card->lock, flags); 940 nj_reset(card); 941 ret = card->isac.init(&card->isac); 942 if (ret) 943 goto error; 944 ret = inittiger(card); 945 if (ret) 946 goto error; 947 mode_tiger(&card->bc[0], ISDN_P_NONE); 948 mode_tiger(&card->bc[1], ISDN_P_NONE); 949 error: 950 spin_unlock_irqrestore(&card->lock, flags); 951 return ret; 952 } 953 954 955 static void 956 nj_release(struct tiger_hw *card) 957 { 958 u_long flags; 959 int i; 960 961 if (card->base_s) { 962 spin_lock_irqsave(&card->lock, flags); 963 nj_disable_hwirq(card); 964 mode_tiger(&card->bc[0], ISDN_P_NONE); 965 mode_tiger(&card->bc[1], ISDN_P_NONE); 966 card->isac.release(&card->isac); 967 spin_unlock_irqrestore(&card->lock, flags); 968 release_region(card->base, card->base_s); 969 card->base_s = 0; 970 } 971 if (card->irq > 0) 972 free_irq(card->irq, card); 973 if (card->isac.dch.dev.dev.class) 974 mISDN_unregister_device(&card->isac.dch.dev); 975 976 for (i = 0; i < 2; i++) { 977 mISDN_freebchannel(&card->bc[i].bch); 978 kfree(card->bc[i].hsbuf); 979 kfree(card->bc[i].hrbuf); 980 } 981 if (card->dma_p) 982 pci_free_consistent(card->pdev, NJ_DMA_SIZE, 983 card->dma_p, card->dma); 984 write_lock_irqsave(&card_lock, flags); 985 list_del(&card->list); 986 write_unlock_irqrestore(&card_lock, flags); 987 pci_clear_master(card->pdev); 988 pci_disable_device(card->pdev); 989 pci_set_drvdata(card->pdev, NULL); 990 kfree(card); 991 } 992 993 994 static int 995 nj_setup(struct tiger_hw *card) 996 { 997 card->base = pci_resource_start(card->pdev, 0); 998 card->base_s = pci_resource_len(card->pdev, 0); 999 if (!request_region(card->base, card->base_s, card->name)) { 1000 pr_info("%s: NETjet config port %#x-%#x already in use\n", 1001 card->name, card->base, 1002 (u32)(card->base + card->base_s - 1)); 1003 card->base_s = 0; 1004 return -EIO; 1005 } 1006 ASSIGN_FUNC(nj, ISAC, card->isac); 1007 return 0; 1008 } 1009 1010 1011 static int 1012 setup_instance(struct tiger_hw *card) 1013 { 1014 int i, err; 1015 u_long flags; 1016 1017 snprintf(card->name, MISDN_MAX_IDLEN - 1, "netjet.%d", nj_cnt + 1); 1018 write_lock_irqsave(&card_lock, flags); 1019 list_add_tail(&card->list, &Cards); 1020 write_unlock_irqrestore(&card_lock, flags); 1021 1022 _set_debug(card); 1023 card->isac.name = card->name; 1024 spin_lock_init(&card->lock); 1025 card->isac.hwlock = &card->lock; 1026 mISDNisac_init(&card->isac, card); 1027 1028 card->isac.dch.dev.Bprotocols = (1 << (ISDN_P_B_RAW & ISDN_P_B_MASK)) | 1029 (1 << (ISDN_P_B_HDLC & ISDN_P_B_MASK)); 1030 card->isac.dch.dev.D.ctrl = nj_dctrl; 1031 for (i = 0; i < 2; i++) { 1032 card->bc[i].bch.nr = i + 1; 1033 set_channelmap(i + 1, card->isac.dch.dev.channelmap); 1034 mISDN_initbchannel(&card->bc[i].bch, MAX_DATA_MEM, 1035 NJ_DMA_RXSIZE >> 1); 1036 card->bc[i].bch.hw = card; 1037 card->bc[i].bch.ch.send = nj_l2l1B; 1038 card->bc[i].bch.ch.ctrl = nj_bctrl; 1039 card->bc[i].bch.ch.nr = i + 1; 1040 list_add(&card->bc[i].bch.ch.list, 1041 &card->isac.dch.dev.bchannels); 1042 card->bc[i].bch.hw = card; 1043 } 1044 err = nj_setup(card); 1045 if (err) 1046 goto error; 1047 err = mISDN_register_device(&card->isac.dch.dev, &card->pdev->dev, 1048 card->name); 1049 if (err) 1050 goto error; 1051 err = nj_init_card(card); 1052 if (!err) { 1053 nj_cnt++; 1054 pr_notice("Netjet %d cards installed\n", nj_cnt); 1055 return 0; 1056 } 1057 error: 1058 nj_release(card); 1059 return err; 1060 } 1061 1062 static int 1063 nj_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 1064 { 1065 int err = -ENOMEM; 1066 int cfg; 1067 struct tiger_hw *card; 1068 1069 if (pdev->subsystem_vendor == 0x8086 && 1070 pdev->subsystem_device == 0x0003) { 1071 pr_notice("Netjet: Digium X100P/X101P not handled\n"); 1072 return -ENODEV; 1073 } 1074 1075 if (pdev->subsystem_vendor == 0x55 && 1076 pdev->subsystem_device == 0x02) { 1077 pr_notice("Netjet: Enter!Now not handled yet\n"); 1078 return -ENODEV; 1079 } 1080 1081 if (pdev->subsystem_vendor == 0xb100 && 1082 pdev->subsystem_device == 0x0003) { 1083 pr_notice("Netjet: Digium TDM400P not handled yet\n"); 1084 return -ENODEV; 1085 } 1086 1087 card = kzalloc(sizeof(struct tiger_hw), GFP_ATOMIC); 1088 if (!card) { 1089 pr_info("No kmem for Netjet\n"); 1090 return err; 1091 } 1092 1093 card->pdev = pdev; 1094 1095 err = pci_enable_device(pdev); 1096 if (err) { 1097 kfree(card); 1098 return err; 1099 } 1100 1101 printk(KERN_INFO "nj_probe(mISDN): found adapter at %s\n", 1102 pci_name(pdev)); 1103 1104 pci_set_master(pdev); 1105 1106 /* the TJ300 and TJ320 must be detected, the IRQ handling is different 1107 * unfortunately the chips use the same device ID, but the TJ320 has 1108 * the bit20 in status PCI cfg register set 1109 */ 1110 pci_read_config_dword(pdev, 0x04, &cfg); 1111 if (cfg & 0x00100000) 1112 card->typ = NETJET_S_TJ320; 1113 else 1114 card->typ = NETJET_S_TJ300; 1115 1116 card->base = pci_resource_start(pdev, 0); 1117 card->irq = pdev->irq; 1118 pci_set_drvdata(pdev, card); 1119 err = setup_instance(card); 1120 if (err) 1121 pci_set_drvdata(pdev, NULL); 1122 1123 return err; 1124 } 1125 1126 1127 static void nj_remove(struct pci_dev *pdev) 1128 { 1129 struct tiger_hw *card = pci_get_drvdata(pdev); 1130 1131 if (card) 1132 nj_release(card); 1133 else 1134 pr_info("%s drvdata already removed\n", __func__); 1135 } 1136 1137 /* We cannot select cards with PCI_SUB... IDs, since here are cards with 1138 * SUB IDs set to PCI_ANY_ID, so we need to match all and reject 1139 * known other cards which not work with this driver - see probe function */ 1140 static const struct pci_device_id nj_pci_ids[] = { 1141 { PCI_VENDOR_ID_TIGERJET, PCI_DEVICE_ID_TIGERJET_300, 1142 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 1143 { } 1144 }; 1145 MODULE_DEVICE_TABLE(pci, nj_pci_ids); 1146 1147 static struct pci_driver nj_driver = { 1148 .name = "netjet", 1149 .probe = nj_probe, 1150 .remove = nj_remove, 1151 .id_table = nj_pci_ids, 1152 }; 1153 1154 static int __init nj_init(void) 1155 { 1156 int err; 1157 1158 pr_notice("Netjet PCI driver Rev. %s\n", NETJET_REV); 1159 err = pci_register_driver(&nj_driver); 1160 return err; 1161 } 1162 1163 static void __exit nj_cleanup(void) 1164 { 1165 pci_unregister_driver(&nj_driver); 1166 } 1167 1168 module_init(nj_init); 1169 module_exit(nj_cleanup); 1170