1 /* 2 * isac.c ISAC specific routines 3 * 4 * Author Karsten Keil <keil@isdn4linux.de> 5 * 6 * Copyright 2009 by Karsten Keil <keil@isdn4linux.de> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 20 * 21 */ 22 23 #include <linux/irqreturn.h> 24 #include <linux/slab.h> 25 #include <linux/module.h> 26 #include <linux/mISDNhw.h> 27 #include "ipac.h" 28 29 30 #define DBUSY_TIMER_VALUE 80 31 #define ARCOFI_USE 1 32 33 #define ISAC_REV "2.0" 34 35 MODULE_AUTHOR("Karsten Keil"); 36 MODULE_VERSION(ISAC_REV); 37 MODULE_LICENSE("GPL v2"); 38 39 #define ReadISAC(is, o) (is->read_reg(is->dch.hw, o + is->off)) 40 #define WriteISAC(is, o, v) (is->write_reg(is->dch.hw, o + is->off, v)) 41 #define ReadHSCX(h, o) (h->ip->read_reg(h->ip->hw, h->off + o)) 42 #define WriteHSCX(h, o, v) (h->ip->write_reg(h->ip->hw, h->off + o, v)) 43 #define ReadIPAC(ip, o) (ip->read_reg(ip->hw, o)) 44 #define WriteIPAC(ip, o, v) (ip->write_reg(ip->hw, o, v)) 45 46 static inline void 47 ph_command(struct isac_hw *isac, u8 command) 48 { 49 pr_debug("%s: ph_command %x\n", isac->name, command); 50 if (isac->type & IPAC_TYPE_ISACX) 51 WriteISAC(isac, ISACX_CIX0, (command << 4) | 0xE); 52 else 53 WriteISAC(isac, ISAC_CIX0, (command << 2) | 3); 54 } 55 56 static void 57 isac_ph_state_change(struct isac_hw *isac) 58 { 59 switch (isac->state) { 60 case (ISAC_IND_RS): 61 case (ISAC_IND_EI): 62 ph_command(isac, ISAC_CMD_DUI); 63 } 64 schedule_event(&isac->dch, FLG_PHCHANGE); 65 } 66 67 static void 68 isac_ph_state_bh(struct dchannel *dch) 69 { 70 struct isac_hw *isac = container_of(dch, struct isac_hw, dch); 71 72 switch (isac->state) { 73 case ISAC_IND_RS: 74 case ISAC_IND_EI: 75 dch->state = 0; 76 l1_event(dch->l1, HW_RESET_IND); 77 break; 78 case ISAC_IND_DID: 79 dch->state = 3; 80 l1_event(dch->l1, HW_DEACT_CNF); 81 break; 82 case ISAC_IND_DR: 83 case ISAC_IND_DR6: 84 dch->state = 3; 85 l1_event(dch->l1, HW_DEACT_IND); 86 break; 87 case ISAC_IND_PU: 88 dch->state = 4; 89 l1_event(dch->l1, HW_POWERUP_IND); 90 break; 91 case ISAC_IND_RSY: 92 if (dch->state <= 5) { 93 dch->state = 5; 94 l1_event(dch->l1, ANYSIGNAL); 95 } else { 96 dch->state = 8; 97 l1_event(dch->l1, LOSTFRAMING); 98 } 99 break; 100 case ISAC_IND_ARD: 101 dch->state = 6; 102 l1_event(dch->l1, INFO2); 103 break; 104 case ISAC_IND_AI8: 105 dch->state = 7; 106 l1_event(dch->l1, INFO4_P8); 107 break; 108 case ISAC_IND_AI10: 109 dch->state = 7; 110 l1_event(dch->l1, INFO4_P10); 111 break; 112 } 113 pr_debug("%s: TE newstate %x\n", isac->name, dch->state); 114 } 115 116 static void 117 isac_empty_fifo(struct isac_hw *isac, int count) 118 { 119 u8 *ptr; 120 121 pr_debug("%s: %s %d\n", isac->name, __func__, count); 122 123 if (!isac->dch.rx_skb) { 124 isac->dch.rx_skb = mI_alloc_skb(isac->dch.maxlen, GFP_ATOMIC); 125 if (!isac->dch.rx_skb) { 126 pr_info("%s: D receive out of memory\n", isac->name); 127 WriteISAC(isac, ISAC_CMDR, 0x80); 128 return; 129 } 130 } 131 if ((isac->dch.rx_skb->len + count) >= isac->dch.maxlen) { 132 pr_debug("%s: %s overrun %d\n", isac->name, __func__, 133 isac->dch.rx_skb->len + count); 134 WriteISAC(isac, ISAC_CMDR, 0x80); 135 return; 136 } 137 ptr = skb_put(isac->dch.rx_skb, count); 138 isac->read_fifo(isac->dch.hw, isac->off, ptr, count); 139 WriteISAC(isac, ISAC_CMDR, 0x80); 140 if (isac->dch.debug & DEBUG_HW_DFIFO) { 141 char pfx[MISDN_MAX_IDLEN + 16]; 142 143 snprintf(pfx, MISDN_MAX_IDLEN + 15, "D-recv %s %d ", 144 isac->name, count); 145 print_hex_dump_bytes(pfx, DUMP_PREFIX_OFFSET, ptr, count); 146 } 147 } 148 149 static void 150 isac_fill_fifo(struct isac_hw *isac) 151 { 152 int count, more; 153 u8 *ptr; 154 155 if (!isac->dch.tx_skb) 156 return; 157 count = isac->dch.tx_skb->len - isac->dch.tx_idx; 158 if (count <= 0) 159 return; 160 161 more = 0; 162 if (count > 32) { 163 more = !0; 164 count = 32; 165 } 166 pr_debug("%s: %s %d\n", isac->name, __func__, count); 167 ptr = isac->dch.tx_skb->data + isac->dch.tx_idx; 168 isac->dch.tx_idx += count; 169 isac->write_fifo(isac->dch.hw, isac->off, ptr, count); 170 WriteISAC(isac, ISAC_CMDR, more ? 0x8 : 0xa); 171 if (test_and_set_bit(FLG_BUSY_TIMER, &isac->dch.Flags)) { 172 pr_debug("%s: %s dbusytimer running\n", isac->name, __func__); 173 del_timer(&isac->dch.timer); 174 } 175 init_timer(&isac->dch.timer); 176 isac->dch.timer.expires = jiffies + ((DBUSY_TIMER_VALUE * HZ)/1000); 177 add_timer(&isac->dch.timer); 178 if (isac->dch.debug & DEBUG_HW_DFIFO) { 179 char pfx[MISDN_MAX_IDLEN + 16]; 180 181 snprintf(pfx, MISDN_MAX_IDLEN + 15, "D-send %s %d ", 182 isac->name, count); 183 print_hex_dump_bytes(pfx, DUMP_PREFIX_OFFSET, ptr, count); 184 } 185 } 186 187 static void 188 isac_rme_irq(struct isac_hw *isac) 189 { 190 u8 val, count; 191 192 val = ReadISAC(isac, ISAC_RSTA); 193 if ((val & 0x70) != 0x20) { 194 if (val & 0x40) { 195 pr_debug("%s: ISAC RDO\n", isac->name); 196 #ifdef ERROR_STATISTIC 197 isac->dch.err_rx++; 198 #endif 199 } 200 if (!(val & 0x20)) { 201 pr_debug("%s: ISAC CRC error\n", isac->name); 202 #ifdef ERROR_STATISTIC 203 isac->dch.err_crc++; 204 #endif 205 } 206 WriteISAC(isac, ISAC_CMDR, 0x80); 207 if (isac->dch.rx_skb) 208 dev_kfree_skb(isac->dch.rx_skb); 209 isac->dch.rx_skb = NULL; 210 } else { 211 count = ReadISAC(isac, ISAC_RBCL) & 0x1f; 212 if (count == 0) 213 count = 32; 214 isac_empty_fifo(isac, count); 215 recv_Dchannel(&isac->dch); 216 } 217 } 218 219 static void 220 isac_xpr_irq(struct isac_hw *isac) 221 { 222 if (test_and_clear_bit(FLG_BUSY_TIMER, &isac->dch.Flags)) 223 del_timer(&isac->dch.timer); 224 if (isac->dch.tx_skb && isac->dch.tx_idx < isac->dch.tx_skb->len) { 225 isac_fill_fifo(isac); 226 } else { 227 if (isac->dch.tx_skb) 228 dev_kfree_skb(isac->dch.tx_skb); 229 if (get_next_dframe(&isac->dch)) 230 isac_fill_fifo(isac); 231 } 232 } 233 234 static void 235 isac_retransmit(struct isac_hw *isac) 236 { 237 if (test_and_clear_bit(FLG_BUSY_TIMER, &isac->dch.Flags)) 238 del_timer(&isac->dch.timer); 239 if (test_bit(FLG_TX_BUSY, &isac->dch.Flags)) { 240 /* Restart frame */ 241 isac->dch.tx_idx = 0; 242 isac_fill_fifo(isac); 243 } else if (isac->dch.tx_skb) { /* should not happen */ 244 pr_info("%s: tx_skb exist but not busy\n", isac->name); 245 test_and_set_bit(FLG_TX_BUSY, &isac->dch.Flags); 246 isac->dch.tx_idx = 0; 247 isac_fill_fifo(isac); 248 } else { 249 pr_info("%s: ISAC XDU no TX_BUSY\n", isac->name); 250 if (get_next_dframe(&isac->dch)) 251 isac_fill_fifo(isac); 252 } 253 } 254 255 static void 256 isac_mos_irq(struct isac_hw *isac) 257 { 258 u8 val; 259 int ret; 260 261 val = ReadISAC(isac, ISAC_MOSR); 262 pr_debug("%s: ISAC MOSR %02x\n", isac->name, val); 263 #if ARCOFI_USE 264 if (val & 0x08) { 265 if (!isac->mon_rx) { 266 isac->mon_rx = kmalloc(MAX_MON_FRAME, GFP_ATOMIC); 267 if (!isac->mon_rx) { 268 pr_info("%s: ISAC MON RX out of memory!\n", 269 isac->name); 270 isac->mocr &= 0xf0; 271 isac->mocr |= 0x0a; 272 WriteISAC(isac, ISAC_MOCR, isac->mocr); 273 goto afterMONR0; 274 } else 275 isac->mon_rxp = 0; 276 } 277 if (isac->mon_rxp >= MAX_MON_FRAME) { 278 isac->mocr &= 0xf0; 279 isac->mocr |= 0x0a; 280 WriteISAC(isac, ISAC_MOCR, isac->mocr); 281 isac->mon_rxp = 0; 282 pr_debug("%s: ISAC MON RX overflow!\n", isac->name); 283 goto afterMONR0; 284 } 285 isac->mon_rx[isac->mon_rxp++] = ReadISAC(isac, ISAC_MOR0); 286 pr_debug("%s: ISAC MOR0 %02x\n", isac->name, 287 isac->mon_rx[isac->mon_rxp - 1]); 288 if (isac->mon_rxp == 1) { 289 isac->mocr |= 0x04; 290 WriteISAC(isac, ISAC_MOCR, isac->mocr); 291 } 292 } 293 afterMONR0: 294 if (val & 0x80) { 295 if (!isac->mon_rx) { 296 isac->mon_rx = kmalloc(MAX_MON_FRAME, GFP_ATOMIC); 297 if (!isac->mon_rx) { 298 pr_info("%s: ISAC MON RX out of memory!\n", 299 isac->name); 300 isac->mocr &= 0x0f; 301 isac->mocr |= 0xa0; 302 WriteISAC(isac, ISAC_MOCR, isac->mocr); 303 goto afterMONR1; 304 } else 305 isac->mon_rxp = 0; 306 } 307 if (isac->mon_rxp >= MAX_MON_FRAME) { 308 isac->mocr &= 0x0f; 309 isac->mocr |= 0xa0; 310 WriteISAC(isac, ISAC_MOCR, isac->mocr); 311 isac->mon_rxp = 0; 312 pr_debug("%s: ISAC MON RX overflow!\n", isac->name); 313 goto afterMONR1; 314 } 315 isac->mon_rx[isac->mon_rxp++] = ReadISAC(isac, ISAC_MOR1); 316 pr_debug("%s: ISAC MOR1 %02x\n", isac->name, 317 isac->mon_rx[isac->mon_rxp - 1]); 318 isac->mocr |= 0x40; 319 WriteISAC(isac, ISAC_MOCR, isac->mocr); 320 } 321 afterMONR1: 322 if (val & 0x04) { 323 isac->mocr &= 0xf0; 324 WriteISAC(isac, ISAC_MOCR, isac->mocr); 325 isac->mocr |= 0x0a; 326 WriteISAC(isac, ISAC_MOCR, isac->mocr); 327 if (isac->monitor) { 328 ret = isac->monitor(isac->dch.hw, MONITOR_RX_0, 329 isac->mon_rx, isac->mon_rxp); 330 if (ret) 331 kfree(isac->mon_rx); 332 } else { 333 pr_info("%s: MONITOR 0 received %d but no user\n", 334 isac->name, isac->mon_rxp); 335 kfree(isac->mon_rx); 336 } 337 isac->mon_rx = NULL; 338 isac->mon_rxp = 0; 339 } 340 if (val & 0x40) { 341 isac->mocr &= 0x0f; 342 WriteISAC(isac, ISAC_MOCR, isac->mocr); 343 isac->mocr |= 0xa0; 344 WriteISAC(isac, ISAC_MOCR, isac->mocr); 345 if (isac->monitor) { 346 ret = isac->monitor(isac->dch.hw, MONITOR_RX_1, 347 isac->mon_rx, isac->mon_rxp); 348 if (ret) 349 kfree(isac->mon_rx); 350 } else { 351 pr_info("%s: MONITOR 1 received %d but no user\n", 352 isac->name, isac->mon_rxp); 353 kfree(isac->mon_rx); 354 } 355 isac->mon_rx = NULL; 356 isac->mon_rxp = 0; 357 } 358 if (val & 0x02) { 359 if ((!isac->mon_tx) || (isac->mon_txc && 360 (isac->mon_txp >= isac->mon_txc) && !(val & 0x08))) { 361 isac->mocr &= 0xf0; 362 WriteISAC(isac, ISAC_MOCR, isac->mocr); 363 isac->mocr |= 0x0a; 364 WriteISAC(isac, ISAC_MOCR, isac->mocr); 365 if (isac->mon_txc && (isac->mon_txp >= isac->mon_txc)) { 366 if (isac->monitor) 367 isac->monitor(isac->dch.hw, 368 MONITOR_TX_0, NULL, 0); 369 } 370 kfree(isac->mon_tx); 371 isac->mon_tx = NULL; 372 isac->mon_txc = 0; 373 isac->mon_txp = 0; 374 goto AfterMOX0; 375 } 376 if (isac->mon_txc && (isac->mon_txp >= isac->mon_txc)) { 377 if (isac->monitor) 378 isac->monitor(isac->dch.hw, 379 MONITOR_TX_0, NULL, 0); 380 kfree(isac->mon_tx); 381 isac->mon_tx = NULL; 382 isac->mon_txc = 0; 383 isac->mon_txp = 0; 384 goto AfterMOX0; 385 } 386 WriteISAC(isac, ISAC_MOX0, isac->mon_tx[isac->mon_txp++]); 387 pr_debug("%s: ISAC %02x -> MOX0\n", isac->name, 388 isac->mon_tx[isac->mon_txp - 1]); 389 } 390 AfterMOX0: 391 if (val & 0x20) { 392 if ((!isac->mon_tx) || (isac->mon_txc && 393 (isac->mon_txp >= isac->mon_txc) && !(val & 0x80))) { 394 isac->mocr &= 0x0f; 395 WriteISAC(isac, ISAC_MOCR, isac->mocr); 396 isac->mocr |= 0xa0; 397 WriteISAC(isac, ISAC_MOCR, isac->mocr); 398 if (isac->mon_txc && (isac->mon_txp >= isac->mon_txc)) { 399 if (isac->monitor) 400 isac->monitor(isac->dch.hw, 401 MONITOR_TX_1, NULL, 0); 402 } 403 kfree(isac->mon_tx); 404 isac->mon_tx = NULL; 405 isac->mon_txc = 0; 406 isac->mon_txp = 0; 407 goto AfterMOX1; 408 } 409 if (isac->mon_txc && (isac->mon_txp >= isac->mon_txc)) { 410 if (isac->monitor) 411 isac->monitor(isac->dch.hw, 412 MONITOR_TX_1, NULL, 0); 413 kfree(isac->mon_tx); 414 isac->mon_tx = NULL; 415 isac->mon_txc = 0; 416 isac->mon_txp = 0; 417 goto AfterMOX1; 418 } 419 WriteISAC(isac, ISAC_MOX1, isac->mon_tx[isac->mon_txp++]); 420 pr_debug("%s: ISAC %02x -> MOX1\n", isac->name, 421 isac->mon_tx[isac->mon_txp - 1]); 422 } 423 AfterMOX1: 424 val = 0; /* dummy to avoid warning */ 425 #endif 426 } 427 428 static void 429 isac_cisq_irq(struct isac_hw *isac) { 430 u8 val; 431 432 val = ReadISAC(isac, ISAC_CIR0); 433 pr_debug("%s: ISAC CIR0 %02X\n", isac->name, val); 434 if (val & 2) { 435 pr_debug("%s: ph_state change %x->%x\n", isac->name, 436 isac->state, (val >> 2) & 0xf); 437 isac->state = (val >> 2) & 0xf; 438 isac_ph_state_change(isac); 439 } 440 if (val & 1) { 441 val = ReadISAC(isac, ISAC_CIR1); 442 pr_debug("%s: ISAC CIR1 %02X\n", isac->name, val); 443 } 444 } 445 446 static void 447 isacsx_cic_irq(struct isac_hw *isac) 448 { 449 u8 val; 450 451 val = ReadISAC(isac, ISACX_CIR0); 452 pr_debug("%s: ISACX CIR0 %02X\n", isac->name, val); 453 if (val & ISACX_CIR0_CIC0) { 454 pr_debug("%s: ph_state change %x->%x\n", isac->name, 455 isac->state, val >> 4); 456 isac->state = val >> 4; 457 isac_ph_state_change(isac); 458 } 459 } 460 461 static void 462 isacsx_rme_irq(struct isac_hw *isac) 463 { 464 int count; 465 u8 val; 466 467 val = ReadISAC(isac, ISACX_RSTAD); 468 if ((val & (ISACX_RSTAD_VFR | 469 ISACX_RSTAD_RDO | 470 ISACX_RSTAD_CRC | 471 ISACX_RSTAD_RAB)) 472 != (ISACX_RSTAD_VFR | ISACX_RSTAD_CRC)) { 473 pr_debug("%s: RSTAD %#x, dropped\n", isac->name, val); 474 #ifdef ERROR_STATISTIC 475 if (val & ISACX_RSTAD_CRC) 476 isac->dch.err_rx++; 477 else 478 isac->dch.err_crc++; 479 #endif 480 WriteISAC(isac, ISACX_CMDRD, ISACX_CMDRD_RMC); 481 if (isac->dch.rx_skb) 482 dev_kfree_skb(isac->dch.rx_skb); 483 isac->dch.rx_skb = NULL; 484 } else { 485 count = ReadISAC(isac, ISACX_RBCLD) & 0x1f; 486 if (count == 0) 487 count = 32; 488 isac_empty_fifo(isac, count); 489 if (isac->dch.rx_skb) { 490 skb_trim(isac->dch.rx_skb, isac->dch.rx_skb->len - 1); 491 pr_debug("%s: dchannel received %d\n", isac->name, 492 isac->dch.rx_skb->len); 493 recv_Dchannel(&isac->dch); 494 } 495 } 496 } 497 498 irqreturn_t 499 mISDNisac_irq(struct isac_hw *isac, u8 val) 500 { 501 if (unlikely(!val)) 502 return IRQ_NONE; 503 pr_debug("%s: ISAC interrupt %02x\n", isac->name, val); 504 if (isac->type & IPAC_TYPE_ISACX) { 505 if (val & ISACX__CIC) 506 isacsx_cic_irq(isac); 507 if (val & ISACX__ICD) { 508 val = ReadISAC(isac, ISACX_ISTAD); 509 pr_debug("%s: ISTAD %02x\n", isac->name, val); 510 if (val & ISACX_D_XDU) { 511 pr_debug("%s: ISAC XDU\n", isac->name); 512 #ifdef ERROR_STATISTIC 513 isac->dch.err_tx++; 514 #endif 515 isac_retransmit(isac); 516 } 517 if (val & ISACX_D_XMR) { 518 pr_debug("%s: ISAC XMR\n", isac->name); 519 #ifdef ERROR_STATISTIC 520 isac->dch.err_tx++; 521 #endif 522 isac_retransmit(isac); 523 } 524 if (val & ISACX_D_XPR) 525 isac_xpr_irq(isac); 526 if (val & ISACX_D_RFO) { 527 pr_debug("%s: ISAC RFO\n", isac->name); 528 WriteISAC(isac, ISACX_CMDRD, ISACX_CMDRD_RMC); 529 } 530 if (val & ISACX_D_RME) 531 isacsx_rme_irq(isac); 532 if (val & ISACX_D_RPF) 533 isac_empty_fifo(isac, 0x20); 534 } 535 } else { 536 if (val & 0x80) /* RME */ 537 isac_rme_irq(isac); 538 if (val & 0x40) /* RPF */ 539 isac_empty_fifo(isac, 32); 540 if (val & 0x10) /* XPR */ 541 isac_xpr_irq(isac); 542 if (val & 0x04) /* CISQ */ 543 isac_cisq_irq(isac); 544 if (val & 0x20) /* RSC - never */ 545 pr_debug("%s: ISAC RSC interrupt\n", isac->name); 546 if (val & 0x02) /* SIN - never */ 547 pr_debug("%s: ISAC SIN interrupt\n", isac->name); 548 if (val & 0x01) { /* EXI */ 549 val = ReadISAC(isac, ISAC_EXIR); 550 pr_debug("%s: ISAC EXIR %02x\n", isac->name, val); 551 if (val & 0x80) /* XMR */ 552 pr_debug("%s: ISAC XMR\n", isac->name); 553 if (val & 0x40) { /* XDU */ 554 pr_debug("%s: ISAC XDU\n", isac->name); 555 #ifdef ERROR_STATISTIC 556 isac->dch.err_tx++; 557 #endif 558 isac_retransmit(isac); 559 } 560 if (val & 0x04) /* MOS */ 561 isac_mos_irq(isac); 562 } 563 } 564 return IRQ_HANDLED; 565 } 566 EXPORT_SYMBOL(mISDNisac_irq); 567 568 static int 569 isac_l1hw(struct mISDNchannel *ch, struct sk_buff *skb) 570 { 571 struct mISDNdevice *dev = container_of(ch, struct mISDNdevice, D); 572 struct dchannel *dch = container_of(dev, struct dchannel, dev); 573 struct isac_hw *isac = container_of(dch, struct isac_hw, dch); 574 int ret = -EINVAL; 575 struct mISDNhead *hh = mISDN_HEAD_P(skb); 576 u32 id; 577 u_long flags; 578 579 switch (hh->prim) { 580 case PH_DATA_REQ: 581 spin_lock_irqsave(isac->hwlock, flags); 582 ret = dchannel_senddata(dch, skb); 583 if (ret > 0) { /* direct TX */ 584 id = hh->id; /* skb can be freed */ 585 isac_fill_fifo(isac); 586 ret = 0; 587 spin_unlock_irqrestore(isac->hwlock, flags); 588 queue_ch_frame(ch, PH_DATA_CNF, id, NULL); 589 } else 590 spin_unlock_irqrestore(isac->hwlock, flags); 591 return ret; 592 case PH_ACTIVATE_REQ: 593 ret = l1_event(dch->l1, hh->prim); 594 break; 595 case PH_DEACTIVATE_REQ: 596 test_and_clear_bit(FLG_L2_ACTIVATED, &dch->Flags); 597 ret = l1_event(dch->l1, hh->prim); 598 break; 599 } 600 601 if (!ret) 602 dev_kfree_skb(skb); 603 return ret; 604 } 605 606 static int 607 isac_ctrl(struct isac_hw *isac, u32 cmd, unsigned long para) 608 { 609 u8 tl = 0; 610 unsigned long flags; 611 int ret = 0; 612 613 switch (cmd) { 614 case HW_TESTLOOP: 615 spin_lock_irqsave(isac->hwlock, flags); 616 if (!(isac->type & IPAC_TYPE_ISACX)) { 617 /* TODO: implement for IPAC_TYPE_ISACX */ 618 if (para & 1) /* B1 */ 619 tl |= 0x0c; 620 else if (para & 2) /* B2 */ 621 tl |= 0x3; 622 /* we only support IOM2 mode */ 623 WriteISAC(isac, ISAC_SPCR, tl); 624 if (tl) 625 WriteISAC(isac, ISAC_ADF1, 0x8); 626 else 627 WriteISAC(isac, ISAC_ADF1, 0x0); 628 } 629 spin_unlock_irqrestore(isac->hwlock, flags); 630 break; 631 case HW_TIMER3_VALUE: 632 ret = l1_event(isac->dch.l1, HW_TIMER3_VALUE | (para & 0xff)); 633 break; 634 default: 635 pr_debug("%s: %s unknown command %x %lx\n", isac->name, 636 __func__, cmd, para); 637 ret = -1; 638 } 639 return ret; 640 } 641 642 static int 643 isac_l1cmd(struct dchannel *dch, u32 cmd) 644 { 645 struct isac_hw *isac = container_of(dch, struct isac_hw, dch); 646 u_long flags; 647 648 pr_debug("%s: cmd(%x) state(%02x)\n", isac->name, cmd, isac->state); 649 switch (cmd) { 650 case INFO3_P8: 651 spin_lock_irqsave(isac->hwlock, flags); 652 ph_command(isac, ISAC_CMD_AR8); 653 spin_unlock_irqrestore(isac->hwlock, flags); 654 break; 655 case INFO3_P10: 656 spin_lock_irqsave(isac->hwlock, flags); 657 ph_command(isac, ISAC_CMD_AR10); 658 spin_unlock_irqrestore(isac->hwlock, flags); 659 break; 660 case HW_RESET_REQ: 661 spin_lock_irqsave(isac->hwlock, flags); 662 if ((isac->state == ISAC_IND_EI) || 663 (isac->state == ISAC_IND_DR) || 664 (isac->state == ISAC_IND_DR6) || 665 (isac->state == ISAC_IND_RS)) 666 ph_command(isac, ISAC_CMD_TIM); 667 else 668 ph_command(isac, ISAC_CMD_RS); 669 spin_unlock_irqrestore(isac->hwlock, flags); 670 break; 671 case HW_DEACT_REQ: 672 skb_queue_purge(&dch->squeue); 673 if (dch->tx_skb) { 674 dev_kfree_skb(dch->tx_skb); 675 dch->tx_skb = NULL; 676 } 677 dch->tx_idx = 0; 678 if (dch->rx_skb) { 679 dev_kfree_skb(dch->rx_skb); 680 dch->rx_skb = NULL; 681 } 682 test_and_clear_bit(FLG_TX_BUSY, &dch->Flags); 683 if (test_and_clear_bit(FLG_BUSY_TIMER, &dch->Flags)) 684 del_timer(&dch->timer); 685 break; 686 case HW_POWERUP_REQ: 687 spin_lock_irqsave(isac->hwlock, flags); 688 ph_command(isac, ISAC_CMD_TIM); 689 spin_unlock_irqrestore(isac->hwlock, flags); 690 break; 691 case PH_ACTIVATE_IND: 692 test_and_set_bit(FLG_ACTIVE, &dch->Flags); 693 _queue_data(&dch->dev.D, cmd, MISDN_ID_ANY, 0, NULL, 694 GFP_ATOMIC); 695 break; 696 case PH_DEACTIVATE_IND: 697 test_and_clear_bit(FLG_ACTIVE, &dch->Flags); 698 _queue_data(&dch->dev.D, cmd, MISDN_ID_ANY, 0, NULL, 699 GFP_ATOMIC); 700 break; 701 default: 702 pr_debug("%s: %s unknown command %x\n", isac->name, 703 __func__, cmd); 704 return -1; 705 } 706 return 0; 707 } 708 709 static void 710 isac_release(struct isac_hw *isac) 711 { 712 if (isac->type & IPAC_TYPE_ISACX) 713 WriteISAC(isac, ISACX_MASK, 0xff); 714 else 715 WriteISAC(isac, ISAC_MASK, 0xff); 716 if (isac->dch.timer.function != NULL) { 717 del_timer(&isac->dch.timer); 718 isac->dch.timer.function = NULL; 719 } 720 kfree(isac->mon_rx); 721 isac->mon_rx = NULL; 722 kfree(isac->mon_tx); 723 isac->mon_tx = NULL; 724 if (isac->dch.l1) 725 l1_event(isac->dch.l1, CLOSE_CHANNEL); 726 mISDN_freedchannel(&isac->dch); 727 } 728 729 static void 730 dbusy_timer_handler(struct isac_hw *isac) 731 { 732 int rbch, star; 733 u_long flags; 734 735 if (test_bit(FLG_BUSY_TIMER, &isac->dch.Flags)) { 736 spin_lock_irqsave(isac->hwlock, flags); 737 rbch = ReadISAC(isac, ISAC_RBCH); 738 star = ReadISAC(isac, ISAC_STAR); 739 pr_debug("%s: D-Channel Busy RBCH %02x STAR %02x\n", 740 isac->name, rbch, star); 741 if (rbch & ISAC_RBCH_XAC) /* D-Channel Busy */ 742 test_and_set_bit(FLG_L1_BUSY, &isac->dch.Flags); 743 else { 744 /* discard frame; reset transceiver */ 745 test_and_clear_bit(FLG_BUSY_TIMER, &isac->dch.Flags); 746 if (isac->dch.tx_idx) 747 isac->dch.tx_idx = 0; 748 else 749 pr_info("%s: ISAC D-Channel Busy no tx_idx\n", 750 isac->name); 751 /* Transmitter reset */ 752 WriteISAC(isac, ISAC_CMDR, 0x01); 753 } 754 spin_unlock_irqrestore(isac->hwlock, flags); 755 } 756 } 757 758 static int 759 open_dchannel_caller(struct isac_hw *isac, struct channel_req *rq, void *caller) 760 { 761 pr_debug("%s: %s dev(%d) open from %p\n", isac->name, __func__, 762 isac->dch.dev.id, caller); 763 if (rq->protocol != ISDN_P_TE_S0) 764 return -EINVAL; 765 if (rq->adr.channel == 1) 766 /* E-Channel not supported */ 767 return -EINVAL; 768 rq->ch = &isac->dch.dev.D; 769 rq->ch->protocol = rq->protocol; 770 if (isac->dch.state == 7) 771 _queue_data(rq->ch, PH_ACTIVATE_IND, MISDN_ID_ANY, 772 0, NULL, GFP_KERNEL); 773 return 0; 774 } 775 776 static int 777 open_dchannel(struct isac_hw *isac, struct channel_req *rq) 778 { 779 return open_dchannel_caller(isac, rq, __builtin_return_address(0)); 780 } 781 782 static const char *ISACVer[] = 783 {"2086/2186 V1.1", "2085 B1", "2085 B2", 784 "2085 V2.3"}; 785 786 static int 787 isac_init(struct isac_hw *isac) 788 { 789 u8 val; 790 int err = 0; 791 792 if (!isac->dch.l1) { 793 err = create_l1(&isac->dch, isac_l1cmd); 794 if (err) 795 return err; 796 } 797 isac->mon_tx = NULL; 798 isac->mon_rx = NULL; 799 setup_timer(&isac->dch.timer, (void *)dbusy_timer_handler, 800 (long)isac); 801 isac->mocr = 0xaa; 802 if (isac->type & IPAC_TYPE_ISACX) { 803 /* Disable all IRQ */ 804 WriteISAC(isac, ISACX_MASK, 0xff); 805 val = ReadISAC(isac, ISACX_STARD); 806 pr_debug("%s: ISACX STARD %x\n", isac->name, val); 807 val = ReadISAC(isac, ISACX_ISTAD); 808 pr_debug("%s: ISACX ISTAD %x\n", isac->name, val); 809 val = ReadISAC(isac, ISACX_ISTA); 810 pr_debug("%s: ISACX ISTA %x\n", isac->name, val); 811 /* clear LDD */ 812 WriteISAC(isac, ISACX_TR_CONF0, 0x00); 813 /* enable transmitter */ 814 WriteISAC(isac, ISACX_TR_CONF2, 0x00); 815 /* transparent mode 0, RAC, stop/go */ 816 WriteISAC(isac, ISACX_MODED, 0xc9); 817 /* all HDLC IRQ unmasked */ 818 val = ReadISAC(isac, ISACX_ID); 819 if (isac->dch.debug & DEBUG_HW) 820 pr_notice("%s: ISACX Design ID %x\n", 821 isac->name, val & 0x3f); 822 val = ReadISAC(isac, ISACX_CIR0); 823 pr_debug("%s: ISACX CIR0 %02X\n", isac->name, val); 824 isac->state = val >> 4; 825 isac_ph_state_change(isac); 826 ph_command(isac, ISAC_CMD_RS); 827 WriteISAC(isac, ISACX_MASK, IPACX__ON); 828 WriteISAC(isac, ISACX_MASKD, 0x00); 829 } else { /* old isac */ 830 WriteISAC(isac, ISAC_MASK, 0xff); 831 val = ReadISAC(isac, ISAC_STAR); 832 pr_debug("%s: ISAC STAR %x\n", isac->name, val); 833 val = ReadISAC(isac, ISAC_MODE); 834 pr_debug("%s: ISAC MODE %x\n", isac->name, val); 835 val = ReadISAC(isac, ISAC_ADF2); 836 pr_debug("%s: ISAC ADF2 %x\n", isac->name, val); 837 val = ReadISAC(isac, ISAC_ISTA); 838 pr_debug("%s: ISAC ISTA %x\n", isac->name, val); 839 if (val & 0x01) { 840 val = ReadISAC(isac, ISAC_EXIR); 841 pr_debug("%s: ISAC EXIR %x\n", isac->name, val); 842 } 843 val = ReadISAC(isac, ISAC_RBCH); 844 if (isac->dch.debug & DEBUG_HW) 845 pr_notice("%s: ISAC version (%x): %s\n", isac->name, 846 val, ISACVer[(val >> 5) & 3]); 847 isac->type |= ((val >> 5) & 3); 848 if (!isac->adf2) 849 isac->adf2 = 0x80; 850 if (!(isac->adf2 & 0x80)) { /* only IOM 2 Mode */ 851 pr_info("%s: only support IOM2 mode but adf2=%02x\n", 852 isac->name, isac->adf2); 853 isac_release(isac); 854 return -EINVAL; 855 } 856 WriteISAC(isac, ISAC_ADF2, isac->adf2); 857 WriteISAC(isac, ISAC_SQXR, 0x2f); 858 WriteISAC(isac, ISAC_SPCR, 0x00); 859 WriteISAC(isac, ISAC_STCR, 0x70); 860 WriteISAC(isac, ISAC_MODE, 0xc9); 861 WriteISAC(isac, ISAC_TIMR, 0x00); 862 WriteISAC(isac, ISAC_ADF1, 0x00); 863 val = ReadISAC(isac, ISAC_CIR0); 864 pr_debug("%s: ISAC CIR0 %x\n", isac->name, val); 865 isac->state = (val >> 2) & 0xf; 866 isac_ph_state_change(isac); 867 ph_command(isac, ISAC_CMD_RS); 868 WriteISAC(isac, ISAC_MASK, 0); 869 } 870 return err; 871 } 872 873 int 874 mISDNisac_init(struct isac_hw *isac, void *hw) 875 { 876 mISDN_initdchannel(&isac->dch, MAX_DFRAME_LEN_L1, isac_ph_state_bh); 877 isac->dch.hw = hw; 878 isac->dch.dev.D.send = isac_l1hw; 879 isac->init = isac_init; 880 isac->release = isac_release; 881 isac->ctrl = isac_ctrl; 882 isac->open = open_dchannel; 883 isac->dch.dev.Dprotocols = (1 << ISDN_P_TE_S0); 884 isac->dch.dev.nrbchan = 2; 885 return 0; 886 } 887 EXPORT_SYMBOL(mISDNisac_init); 888 889 static void 890 waitforCEC(struct hscx_hw *hx) 891 { 892 u8 starb, to = 50; 893 894 while (to) { 895 starb = ReadHSCX(hx, IPAC_STARB); 896 if (!(starb & 0x04)) 897 break; 898 udelay(1); 899 to--; 900 } 901 if (to < 50) 902 pr_debug("%s: B%1d CEC %d us\n", hx->ip->name, hx->bch.nr, 903 50 - to); 904 if (!to) 905 pr_info("%s: B%1d CEC timeout\n", hx->ip->name, hx->bch.nr); 906 } 907 908 909 static void 910 waitforXFW(struct hscx_hw *hx) 911 { 912 u8 starb, to = 50; 913 914 while (to) { 915 starb = ReadHSCX(hx, IPAC_STARB); 916 if ((starb & 0x44) == 0x40) 917 break; 918 udelay(1); 919 to--; 920 } 921 if (to < 50) 922 pr_debug("%s: B%1d XFW %d us\n", hx->ip->name, hx->bch.nr, 923 50 - to); 924 if (!to) 925 pr_info("%s: B%1d XFW timeout\n", hx->ip->name, hx->bch.nr); 926 } 927 928 static void 929 hscx_cmdr(struct hscx_hw *hx, u8 cmd) 930 { 931 if (hx->ip->type & IPAC_TYPE_IPACX) 932 WriteHSCX(hx, IPACX_CMDRB, cmd); 933 else { 934 waitforCEC(hx); 935 WriteHSCX(hx, IPAC_CMDRB, cmd); 936 } 937 } 938 939 static void 940 hscx_empty_fifo(struct hscx_hw *hscx, u8 count) 941 { 942 u8 *p; 943 int maxlen; 944 945 pr_debug("%s: B%1d %d\n", hscx->ip->name, hscx->bch.nr, count); 946 if (test_bit(FLG_RX_OFF, &hscx->bch.Flags)) { 947 hscx->bch.dropcnt += count; 948 hscx_cmdr(hscx, 0x80); /* RMC */ 949 return; 950 } 951 maxlen = bchannel_get_rxbuf(&hscx->bch, count); 952 if (maxlen < 0) { 953 hscx_cmdr(hscx, 0x80); /* RMC */ 954 if (hscx->bch.rx_skb) 955 skb_trim(hscx->bch.rx_skb, 0); 956 pr_warning("%s.B%d: No bufferspace for %d bytes\n", 957 hscx->ip->name, hscx->bch.nr, count); 958 return; 959 } 960 p = skb_put(hscx->bch.rx_skb, count); 961 962 if (hscx->ip->type & IPAC_TYPE_IPACX) 963 hscx->ip->read_fifo(hscx->ip->hw, 964 hscx->off + IPACX_RFIFOB, p, count); 965 else 966 hscx->ip->read_fifo(hscx->ip->hw, 967 hscx->off, p, count); 968 969 hscx_cmdr(hscx, 0x80); /* RMC */ 970 971 if (hscx->bch.debug & DEBUG_HW_BFIFO) { 972 snprintf(hscx->log, 64, "B%1d-recv %s %d ", 973 hscx->bch.nr, hscx->ip->name, count); 974 print_hex_dump_bytes(hscx->log, DUMP_PREFIX_OFFSET, p, count); 975 } 976 } 977 978 static void 979 hscx_fill_fifo(struct hscx_hw *hscx) 980 { 981 int count, more; 982 u8 *p; 983 984 if (!hscx->bch.tx_skb) { 985 if (!test_bit(FLG_TX_EMPTY, &hscx->bch.Flags)) 986 return; 987 count = hscx->fifo_size; 988 more = 1; 989 p = hscx->log; 990 memset(p, hscx->bch.fill[0], count); 991 } else { 992 count = hscx->bch.tx_skb->len - hscx->bch.tx_idx; 993 if (count <= 0) 994 return; 995 p = hscx->bch.tx_skb->data + hscx->bch.tx_idx; 996 997 more = test_bit(FLG_TRANSPARENT, &hscx->bch.Flags) ? 1 : 0; 998 if (count > hscx->fifo_size) { 999 count = hscx->fifo_size; 1000 more = 1; 1001 } 1002 pr_debug("%s: B%1d %d/%d/%d\n", hscx->ip->name, hscx->bch.nr, 1003 count, hscx->bch.tx_idx, hscx->bch.tx_skb->len); 1004 hscx->bch.tx_idx += count; 1005 } 1006 if (hscx->ip->type & IPAC_TYPE_IPACX) 1007 hscx->ip->write_fifo(hscx->ip->hw, 1008 hscx->off + IPACX_XFIFOB, p, count); 1009 else { 1010 waitforXFW(hscx); 1011 hscx->ip->write_fifo(hscx->ip->hw, 1012 hscx->off, p, count); 1013 } 1014 hscx_cmdr(hscx, more ? 0x08 : 0x0a); 1015 1016 if (hscx->bch.tx_skb && (hscx->bch.debug & DEBUG_HW_BFIFO)) { 1017 snprintf(hscx->log, 64, "B%1d-send %s %d ", 1018 hscx->bch.nr, hscx->ip->name, count); 1019 print_hex_dump_bytes(hscx->log, DUMP_PREFIX_OFFSET, p, count); 1020 } 1021 } 1022 1023 static void 1024 hscx_xpr(struct hscx_hw *hx) 1025 { 1026 if (hx->bch.tx_skb && hx->bch.tx_idx < hx->bch.tx_skb->len) { 1027 hscx_fill_fifo(hx); 1028 } else { 1029 if (hx->bch.tx_skb) 1030 dev_kfree_skb(hx->bch.tx_skb); 1031 if (get_next_bframe(&hx->bch)) { 1032 hscx_fill_fifo(hx); 1033 test_and_clear_bit(FLG_TX_EMPTY, &hx->bch.Flags); 1034 } else if (test_bit(FLG_TX_EMPTY, &hx->bch.Flags)) { 1035 hscx_fill_fifo(hx); 1036 } 1037 } 1038 } 1039 1040 static void 1041 ipac_rme(struct hscx_hw *hx) 1042 { 1043 int count; 1044 u8 rstab; 1045 1046 if (hx->ip->type & IPAC_TYPE_IPACX) 1047 rstab = ReadHSCX(hx, IPACX_RSTAB); 1048 else 1049 rstab = ReadHSCX(hx, IPAC_RSTAB); 1050 pr_debug("%s: B%1d RSTAB %02x\n", hx->ip->name, hx->bch.nr, rstab); 1051 if ((rstab & 0xf0) != 0xa0) { 1052 /* !(VFR && !RDO && CRC && !RAB) */ 1053 if (!(rstab & 0x80)) { 1054 if (hx->bch.debug & DEBUG_HW_BCHANNEL) 1055 pr_notice("%s: B%1d invalid frame\n", 1056 hx->ip->name, hx->bch.nr); 1057 } 1058 if (rstab & 0x40) { 1059 if (hx->bch.debug & DEBUG_HW_BCHANNEL) 1060 pr_notice("%s: B%1d RDO proto=%x\n", 1061 hx->ip->name, hx->bch.nr, 1062 hx->bch.state); 1063 } 1064 if (!(rstab & 0x20)) { 1065 if (hx->bch.debug & DEBUG_HW_BCHANNEL) 1066 pr_notice("%s: B%1d CRC error\n", 1067 hx->ip->name, hx->bch.nr); 1068 } 1069 hscx_cmdr(hx, 0x80); /* Do RMC */ 1070 return; 1071 } 1072 if (hx->ip->type & IPAC_TYPE_IPACX) 1073 count = ReadHSCX(hx, IPACX_RBCLB); 1074 else 1075 count = ReadHSCX(hx, IPAC_RBCLB); 1076 count &= (hx->fifo_size - 1); 1077 if (count == 0) 1078 count = hx->fifo_size; 1079 hscx_empty_fifo(hx, count); 1080 if (!hx->bch.rx_skb) 1081 return; 1082 if (hx->bch.rx_skb->len < 2) { 1083 pr_debug("%s: B%1d frame to short %d\n", 1084 hx->ip->name, hx->bch.nr, hx->bch.rx_skb->len); 1085 skb_trim(hx->bch.rx_skb, 0); 1086 } else { 1087 skb_trim(hx->bch.rx_skb, hx->bch.rx_skb->len - 1); 1088 recv_Bchannel(&hx->bch, 0, false); 1089 } 1090 } 1091 1092 static void 1093 ipac_irq(struct hscx_hw *hx, u8 ista) 1094 { 1095 u8 istab, m, exirb = 0; 1096 1097 if (hx->ip->type & IPAC_TYPE_IPACX) 1098 istab = ReadHSCX(hx, IPACX_ISTAB); 1099 else if (hx->ip->type & IPAC_TYPE_IPAC) { 1100 istab = ReadHSCX(hx, IPAC_ISTAB); 1101 m = (hx->bch.nr & 1) ? IPAC__EXA : IPAC__EXB; 1102 if (m & ista) { 1103 exirb = ReadHSCX(hx, IPAC_EXIRB); 1104 pr_debug("%s: B%1d EXIRB %02x\n", hx->ip->name, 1105 hx->bch.nr, exirb); 1106 } 1107 } else if (hx->bch.nr & 2) { /* HSCX B */ 1108 if (ista & (HSCX__EXA | HSCX__ICA)) 1109 ipac_irq(&hx->ip->hscx[0], ista); 1110 if (ista & HSCX__EXB) { 1111 exirb = ReadHSCX(hx, IPAC_EXIRB); 1112 pr_debug("%s: B%1d EXIRB %02x\n", hx->ip->name, 1113 hx->bch.nr, exirb); 1114 } 1115 istab = ista & 0xF8; 1116 } else { /* HSCX A */ 1117 istab = ReadHSCX(hx, IPAC_ISTAB); 1118 if (ista & HSCX__EXA) { 1119 exirb = ReadHSCX(hx, IPAC_EXIRB); 1120 pr_debug("%s: B%1d EXIRB %02x\n", hx->ip->name, 1121 hx->bch.nr, exirb); 1122 } 1123 istab = istab & 0xF8; 1124 } 1125 if (exirb & IPAC_B_XDU) 1126 istab |= IPACX_B_XDU; 1127 if (exirb & IPAC_B_RFO) 1128 istab |= IPACX_B_RFO; 1129 pr_debug("%s: B%1d ISTAB %02x\n", hx->ip->name, hx->bch.nr, istab); 1130 1131 if (!test_bit(FLG_ACTIVE, &hx->bch.Flags)) 1132 return; 1133 1134 if (istab & IPACX_B_RME) 1135 ipac_rme(hx); 1136 1137 if (istab & IPACX_B_RPF) { 1138 hscx_empty_fifo(hx, hx->fifo_size); 1139 if (test_bit(FLG_TRANSPARENT, &hx->bch.Flags)) 1140 recv_Bchannel(&hx->bch, 0, false); 1141 } 1142 1143 if (istab & IPACX_B_RFO) { 1144 pr_debug("%s: B%1d RFO error\n", hx->ip->name, hx->bch.nr); 1145 hscx_cmdr(hx, 0x40); /* RRES */ 1146 } 1147 1148 if (istab & IPACX_B_XPR) 1149 hscx_xpr(hx); 1150 1151 if (istab & IPACX_B_XDU) { 1152 if (test_bit(FLG_TRANSPARENT, &hx->bch.Flags)) { 1153 if (test_bit(FLG_FILLEMPTY, &hx->bch.Flags)) 1154 test_and_set_bit(FLG_TX_EMPTY, &hx->bch.Flags); 1155 hscx_xpr(hx); 1156 return; 1157 } 1158 pr_debug("%s: B%1d XDU error at len %d\n", hx->ip->name, 1159 hx->bch.nr, hx->bch.tx_idx); 1160 hx->bch.tx_idx = 0; 1161 hscx_cmdr(hx, 0x01); /* XRES */ 1162 } 1163 } 1164 1165 irqreturn_t 1166 mISDNipac_irq(struct ipac_hw *ipac, int maxloop) 1167 { 1168 int cnt = maxloop + 1; 1169 u8 ista, istad; 1170 struct isac_hw *isac = &ipac->isac; 1171 1172 if (ipac->type & IPAC_TYPE_IPACX) { 1173 ista = ReadIPAC(ipac, ISACX_ISTA); 1174 while (ista && --cnt) { 1175 pr_debug("%s: ISTA %02x\n", ipac->name, ista); 1176 if (ista & IPACX__ICA) 1177 ipac_irq(&ipac->hscx[0], ista); 1178 if (ista & IPACX__ICB) 1179 ipac_irq(&ipac->hscx[1], ista); 1180 if (ista & (ISACX__ICD | ISACX__CIC)) 1181 mISDNisac_irq(&ipac->isac, ista); 1182 ista = ReadIPAC(ipac, ISACX_ISTA); 1183 } 1184 } else if (ipac->type & IPAC_TYPE_IPAC) { 1185 ista = ReadIPAC(ipac, IPAC_ISTA); 1186 while (ista && --cnt) { 1187 pr_debug("%s: ISTA %02x\n", ipac->name, ista); 1188 if (ista & (IPAC__ICD | IPAC__EXD)) { 1189 istad = ReadISAC(isac, ISAC_ISTA); 1190 pr_debug("%s: ISTAD %02x\n", ipac->name, istad); 1191 if (istad & IPAC_D_TIN2) 1192 pr_debug("%s TIN2 irq\n", ipac->name); 1193 if (ista & IPAC__EXD) 1194 istad |= 1; /* ISAC EXI */ 1195 mISDNisac_irq(isac, istad); 1196 } 1197 if (ista & (IPAC__ICA | IPAC__EXA)) 1198 ipac_irq(&ipac->hscx[0], ista); 1199 if (ista & (IPAC__ICB | IPAC__EXB)) 1200 ipac_irq(&ipac->hscx[1], ista); 1201 ista = ReadIPAC(ipac, IPAC_ISTA); 1202 } 1203 } else if (ipac->type & IPAC_TYPE_HSCX) { 1204 while (--cnt) { 1205 ista = ReadIPAC(ipac, IPAC_ISTAB + ipac->hscx[1].off); 1206 pr_debug("%s: B2 ISTA %02x\n", ipac->name, ista); 1207 if (ista) 1208 ipac_irq(&ipac->hscx[1], ista); 1209 istad = ReadISAC(isac, ISAC_ISTA); 1210 pr_debug("%s: ISTAD %02x\n", ipac->name, istad); 1211 if (istad) 1212 mISDNisac_irq(isac, istad); 1213 if (0 == (ista | istad)) 1214 break; 1215 } 1216 } 1217 if (cnt > maxloop) /* only for ISAC/HSCX without PCI IRQ test */ 1218 return IRQ_NONE; 1219 if (cnt < maxloop) 1220 pr_debug("%s: %d irqloops cpu%d\n", ipac->name, 1221 maxloop - cnt, smp_processor_id()); 1222 if (maxloop && !cnt) 1223 pr_notice("%s: %d IRQ LOOP cpu%d\n", ipac->name, 1224 maxloop, smp_processor_id()); 1225 return IRQ_HANDLED; 1226 } 1227 EXPORT_SYMBOL(mISDNipac_irq); 1228 1229 static int 1230 hscx_mode(struct hscx_hw *hscx, u32 bprotocol) 1231 { 1232 pr_debug("%s: HSCX %c protocol %x-->%x ch %d\n", hscx->ip->name, 1233 '@' + hscx->bch.nr, hscx->bch.state, bprotocol, hscx->bch.nr); 1234 if (hscx->ip->type & IPAC_TYPE_IPACX) { 1235 if (hscx->bch.nr & 1) { /* B1 and ICA */ 1236 WriteIPAC(hscx->ip, ISACX_BCHA_TSDP_BC1, 0x80); 1237 WriteIPAC(hscx->ip, ISACX_BCHA_CR, 0x88); 1238 } else { /* B2 and ICB */ 1239 WriteIPAC(hscx->ip, ISACX_BCHB_TSDP_BC1, 0x81); 1240 WriteIPAC(hscx->ip, ISACX_BCHB_CR, 0x88); 1241 } 1242 switch (bprotocol) { 1243 case ISDN_P_NONE: /* init */ 1244 WriteHSCX(hscx, IPACX_MODEB, 0xC0); /* rec off */ 1245 WriteHSCX(hscx, IPACX_EXMB, 0x30); /* std adj. */ 1246 WriteHSCX(hscx, IPACX_MASKB, 0xFF); /* ints off */ 1247 hscx_cmdr(hscx, 0x41); 1248 test_and_clear_bit(FLG_HDLC, &hscx->bch.Flags); 1249 test_and_clear_bit(FLG_TRANSPARENT, &hscx->bch.Flags); 1250 break; 1251 case ISDN_P_B_RAW: 1252 WriteHSCX(hscx, IPACX_MODEB, 0x88); /* ex trans */ 1253 WriteHSCX(hscx, IPACX_EXMB, 0x00); /* trans */ 1254 hscx_cmdr(hscx, 0x41); 1255 WriteHSCX(hscx, IPACX_MASKB, IPACX_B_ON); 1256 test_and_set_bit(FLG_TRANSPARENT, &hscx->bch.Flags); 1257 break; 1258 case ISDN_P_B_HDLC: 1259 WriteHSCX(hscx, IPACX_MODEB, 0xC0); /* trans */ 1260 WriteHSCX(hscx, IPACX_EXMB, 0x00); /* hdlc,crc */ 1261 hscx_cmdr(hscx, 0x41); 1262 WriteHSCX(hscx, IPACX_MASKB, IPACX_B_ON); 1263 test_and_set_bit(FLG_HDLC, &hscx->bch.Flags); 1264 break; 1265 default: 1266 pr_info("%s: protocol not known %x\n", hscx->ip->name, 1267 bprotocol); 1268 return -ENOPROTOOPT; 1269 } 1270 } else if (hscx->ip->type & IPAC_TYPE_IPAC) { /* IPAC */ 1271 WriteHSCX(hscx, IPAC_CCR1, 0x82); 1272 WriteHSCX(hscx, IPAC_CCR2, 0x30); 1273 WriteHSCX(hscx, IPAC_XCCR, 0x07); 1274 WriteHSCX(hscx, IPAC_RCCR, 0x07); 1275 WriteHSCX(hscx, IPAC_TSAX, hscx->slot); 1276 WriteHSCX(hscx, IPAC_TSAR, hscx->slot); 1277 switch (bprotocol) { 1278 case ISDN_P_NONE: 1279 WriteHSCX(hscx, IPAC_TSAX, 0x1F); 1280 WriteHSCX(hscx, IPAC_TSAR, 0x1F); 1281 WriteHSCX(hscx, IPAC_MODEB, 0x84); 1282 WriteHSCX(hscx, IPAC_CCR1, 0x82); 1283 WriteHSCX(hscx, IPAC_MASKB, 0xFF); /* ints off */ 1284 test_and_clear_bit(FLG_HDLC, &hscx->bch.Flags); 1285 test_and_clear_bit(FLG_TRANSPARENT, &hscx->bch.Flags); 1286 break; 1287 case ISDN_P_B_RAW: 1288 WriteHSCX(hscx, IPAC_MODEB, 0xe4); /* ex trans */ 1289 WriteHSCX(hscx, IPAC_CCR1, 0x82); 1290 hscx_cmdr(hscx, 0x41); 1291 WriteHSCX(hscx, IPAC_MASKB, 0); 1292 test_and_set_bit(FLG_TRANSPARENT, &hscx->bch.Flags); 1293 break; 1294 case ISDN_P_B_HDLC: 1295 WriteHSCX(hscx, IPAC_MODEB, 0x8c); 1296 WriteHSCX(hscx, IPAC_CCR1, 0x8a); 1297 hscx_cmdr(hscx, 0x41); 1298 WriteHSCX(hscx, IPAC_MASKB, 0); 1299 test_and_set_bit(FLG_HDLC, &hscx->bch.Flags); 1300 break; 1301 default: 1302 pr_info("%s: protocol not known %x\n", hscx->ip->name, 1303 bprotocol); 1304 return -ENOPROTOOPT; 1305 } 1306 } else if (hscx->ip->type & IPAC_TYPE_HSCX) { /* HSCX */ 1307 WriteHSCX(hscx, IPAC_CCR1, 0x85); 1308 WriteHSCX(hscx, IPAC_CCR2, 0x30); 1309 WriteHSCX(hscx, IPAC_XCCR, 0x07); 1310 WriteHSCX(hscx, IPAC_RCCR, 0x07); 1311 WriteHSCX(hscx, IPAC_TSAX, hscx->slot); 1312 WriteHSCX(hscx, IPAC_TSAR, hscx->slot); 1313 switch (bprotocol) { 1314 case ISDN_P_NONE: 1315 WriteHSCX(hscx, IPAC_TSAX, 0x1F); 1316 WriteHSCX(hscx, IPAC_TSAR, 0x1F); 1317 WriteHSCX(hscx, IPAC_MODEB, 0x84); 1318 WriteHSCX(hscx, IPAC_CCR1, 0x85); 1319 WriteHSCX(hscx, IPAC_MASKB, 0xFF); /* ints off */ 1320 test_and_clear_bit(FLG_HDLC, &hscx->bch.Flags); 1321 test_and_clear_bit(FLG_TRANSPARENT, &hscx->bch.Flags); 1322 break; 1323 case ISDN_P_B_RAW: 1324 WriteHSCX(hscx, IPAC_MODEB, 0xe4); /* ex trans */ 1325 WriteHSCX(hscx, IPAC_CCR1, 0x85); 1326 hscx_cmdr(hscx, 0x41); 1327 WriteHSCX(hscx, IPAC_MASKB, 0); 1328 test_and_set_bit(FLG_TRANSPARENT, &hscx->bch.Flags); 1329 break; 1330 case ISDN_P_B_HDLC: 1331 WriteHSCX(hscx, IPAC_MODEB, 0x8c); 1332 WriteHSCX(hscx, IPAC_CCR1, 0x8d); 1333 hscx_cmdr(hscx, 0x41); 1334 WriteHSCX(hscx, IPAC_MASKB, 0); 1335 test_and_set_bit(FLG_HDLC, &hscx->bch.Flags); 1336 break; 1337 default: 1338 pr_info("%s: protocol not known %x\n", hscx->ip->name, 1339 bprotocol); 1340 return -ENOPROTOOPT; 1341 } 1342 } else 1343 return -EINVAL; 1344 hscx->bch.state = bprotocol; 1345 return 0; 1346 } 1347 1348 static int 1349 hscx_l2l1(struct mISDNchannel *ch, struct sk_buff *skb) 1350 { 1351 struct bchannel *bch = container_of(ch, struct bchannel, ch); 1352 struct hscx_hw *hx = container_of(bch, struct hscx_hw, bch); 1353 int ret = -EINVAL; 1354 struct mISDNhead *hh = mISDN_HEAD_P(skb); 1355 unsigned long flags; 1356 1357 switch (hh->prim) { 1358 case PH_DATA_REQ: 1359 spin_lock_irqsave(hx->ip->hwlock, flags); 1360 ret = bchannel_senddata(bch, skb); 1361 if (ret > 0) { /* direct TX */ 1362 ret = 0; 1363 hscx_fill_fifo(hx); 1364 } 1365 spin_unlock_irqrestore(hx->ip->hwlock, flags); 1366 return ret; 1367 case PH_ACTIVATE_REQ: 1368 spin_lock_irqsave(hx->ip->hwlock, flags); 1369 if (!test_and_set_bit(FLG_ACTIVE, &bch->Flags)) 1370 ret = hscx_mode(hx, ch->protocol); 1371 else 1372 ret = 0; 1373 spin_unlock_irqrestore(hx->ip->hwlock, flags); 1374 if (!ret) 1375 _queue_data(ch, PH_ACTIVATE_IND, MISDN_ID_ANY, 0, 1376 NULL, GFP_KERNEL); 1377 break; 1378 case PH_DEACTIVATE_REQ: 1379 spin_lock_irqsave(hx->ip->hwlock, flags); 1380 mISDN_clear_bchannel(bch); 1381 hscx_mode(hx, ISDN_P_NONE); 1382 spin_unlock_irqrestore(hx->ip->hwlock, flags); 1383 _queue_data(ch, PH_DEACTIVATE_IND, MISDN_ID_ANY, 0, 1384 NULL, GFP_KERNEL); 1385 ret = 0; 1386 break; 1387 default: 1388 pr_info("%s: %s unknown prim(%x,%x)\n", 1389 hx->ip->name, __func__, hh->prim, hh->id); 1390 ret = -EINVAL; 1391 } 1392 if (!ret) 1393 dev_kfree_skb(skb); 1394 return ret; 1395 } 1396 1397 static int 1398 channel_bctrl(struct bchannel *bch, struct mISDN_ctrl_req *cq) 1399 { 1400 return mISDN_ctrl_bchannel(bch, cq); 1401 } 1402 1403 static int 1404 hscx_bctrl(struct mISDNchannel *ch, u32 cmd, void *arg) 1405 { 1406 struct bchannel *bch = container_of(ch, struct bchannel, ch); 1407 struct hscx_hw *hx = container_of(bch, struct hscx_hw, bch); 1408 int ret = -EINVAL; 1409 u_long flags; 1410 1411 pr_debug("%s: %s cmd:%x %p\n", hx->ip->name, __func__, cmd, arg); 1412 switch (cmd) { 1413 case CLOSE_CHANNEL: 1414 test_and_clear_bit(FLG_OPEN, &bch->Flags); 1415 cancel_work_sync(&bch->workq); 1416 spin_lock_irqsave(hx->ip->hwlock, flags); 1417 mISDN_clear_bchannel(bch); 1418 hscx_mode(hx, ISDN_P_NONE); 1419 spin_unlock_irqrestore(hx->ip->hwlock, flags); 1420 ch->protocol = ISDN_P_NONE; 1421 ch->peer = NULL; 1422 module_put(hx->ip->owner); 1423 ret = 0; 1424 break; 1425 case CONTROL_CHANNEL: 1426 ret = channel_bctrl(bch, arg); 1427 break; 1428 default: 1429 pr_info("%s: %s unknown prim(%x)\n", 1430 hx->ip->name, __func__, cmd); 1431 } 1432 return ret; 1433 } 1434 1435 static void 1436 free_ipac(struct ipac_hw *ipac) 1437 { 1438 isac_release(&ipac->isac); 1439 } 1440 1441 static const char *HSCXVer[] = 1442 {"A1", "?1", "A2", "?3", "A3", "V2.1", "?6", "?7", 1443 "?8", "?9", "?10", "?11", "?12", "?13", "?14", "???"}; 1444 1445 1446 1447 static void 1448 hscx_init(struct hscx_hw *hx) 1449 { 1450 u8 val; 1451 1452 WriteHSCX(hx, IPAC_RAH2, 0xFF); 1453 WriteHSCX(hx, IPAC_XBCH, 0x00); 1454 WriteHSCX(hx, IPAC_RLCR, 0x00); 1455 1456 if (hx->ip->type & IPAC_TYPE_HSCX) { 1457 WriteHSCX(hx, IPAC_CCR1, 0x85); 1458 val = ReadHSCX(hx, HSCX_VSTR); 1459 pr_debug("%s: HSCX VSTR %02x\n", hx->ip->name, val); 1460 if (hx->bch.debug & DEBUG_HW) 1461 pr_notice("%s: HSCX version %s\n", hx->ip->name, 1462 HSCXVer[val & 0x0f]); 1463 } else 1464 WriteHSCX(hx, IPAC_CCR1, 0x82); 1465 WriteHSCX(hx, IPAC_CCR2, 0x30); 1466 WriteHSCX(hx, IPAC_XCCR, 0x07); 1467 WriteHSCX(hx, IPAC_RCCR, 0x07); 1468 } 1469 1470 static int 1471 ipac_init(struct ipac_hw *ipac) 1472 { 1473 u8 val; 1474 1475 if (ipac->type & IPAC_TYPE_HSCX) { 1476 hscx_init(&ipac->hscx[0]); 1477 hscx_init(&ipac->hscx[1]); 1478 val = ReadIPAC(ipac, IPAC_ID); 1479 } else if (ipac->type & IPAC_TYPE_IPAC) { 1480 hscx_init(&ipac->hscx[0]); 1481 hscx_init(&ipac->hscx[1]); 1482 WriteIPAC(ipac, IPAC_MASK, IPAC__ON); 1483 val = ReadIPAC(ipac, IPAC_CONF); 1484 /* conf is default 0, but can be overwritten by card setup */ 1485 pr_debug("%s: IPAC CONF %02x/%02x\n", ipac->name, 1486 val, ipac->conf); 1487 WriteIPAC(ipac, IPAC_CONF, ipac->conf); 1488 val = ReadIPAC(ipac, IPAC_ID); 1489 if (ipac->hscx[0].bch.debug & DEBUG_HW) 1490 pr_notice("%s: IPAC Design ID %02x\n", ipac->name, val); 1491 } 1492 /* nothing special for IPACX to do here */ 1493 return isac_init(&ipac->isac); 1494 } 1495 1496 static int 1497 open_bchannel(struct ipac_hw *ipac, struct channel_req *rq) 1498 { 1499 struct bchannel *bch; 1500 1501 if (rq->adr.channel == 0 || rq->adr.channel > 2) 1502 return -EINVAL; 1503 if (rq->protocol == ISDN_P_NONE) 1504 return -EINVAL; 1505 bch = &ipac->hscx[rq->adr.channel - 1].bch; 1506 if (test_and_set_bit(FLG_OPEN, &bch->Flags)) 1507 return -EBUSY; /* b-channel can be only open once */ 1508 test_and_clear_bit(FLG_FILLEMPTY, &bch->Flags); 1509 bch->ch.protocol = rq->protocol; 1510 rq->ch = &bch->ch; 1511 return 0; 1512 } 1513 1514 static int 1515 channel_ctrl(struct ipac_hw *ipac, struct mISDN_ctrl_req *cq) 1516 { 1517 int ret = 0; 1518 1519 switch (cq->op) { 1520 case MISDN_CTRL_GETOP: 1521 cq->op = MISDN_CTRL_LOOP | MISDN_CTRL_L1_TIMER3; 1522 break; 1523 case MISDN_CTRL_LOOP: 1524 /* cq->channel: 0 disable, 1 B1 loop 2 B2 loop, 3 both */ 1525 if (cq->channel < 0 || cq->channel > 3) { 1526 ret = -EINVAL; 1527 break; 1528 } 1529 ret = ipac->ctrl(ipac, HW_TESTLOOP, cq->channel); 1530 break; 1531 case MISDN_CTRL_L1_TIMER3: 1532 ret = ipac->isac.ctrl(&ipac->isac, HW_TIMER3_VALUE, cq->p1); 1533 break; 1534 default: 1535 pr_info("%s: unknown CTRL OP %x\n", ipac->name, cq->op); 1536 ret = -EINVAL; 1537 break; 1538 } 1539 return ret; 1540 } 1541 1542 static int 1543 ipac_dctrl(struct mISDNchannel *ch, u32 cmd, void *arg) 1544 { 1545 struct mISDNdevice *dev = container_of(ch, struct mISDNdevice, D); 1546 struct dchannel *dch = container_of(dev, struct dchannel, dev); 1547 struct isac_hw *isac = container_of(dch, struct isac_hw, dch); 1548 struct ipac_hw *ipac = container_of(isac, struct ipac_hw, isac); 1549 struct channel_req *rq; 1550 int err = 0; 1551 1552 pr_debug("%s: DCTRL: %x %p\n", ipac->name, cmd, arg); 1553 switch (cmd) { 1554 case OPEN_CHANNEL: 1555 rq = arg; 1556 if (rq->protocol == ISDN_P_TE_S0) 1557 err = open_dchannel_caller(isac, rq, __builtin_return_address(0)); 1558 else 1559 err = open_bchannel(ipac, rq); 1560 if (err) 1561 break; 1562 if (!try_module_get(ipac->owner)) 1563 pr_info("%s: cannot get module\n", ipac->name); 1564 break; 1565 case CLOSE_CHANNEL: 1566 pr_debug("%s: dev(%d) close from %p\n", ipac->name, 1567 dch->dev.id, __builtin_return_address(0)); 1568 module_put(ipac->owner); 1569 break; 1570 case CONTROL_CHANNEL: 1571 err = channel_ctrl(ipac, arg); 1572 break; 1573 default: 1574 pr_debug("%s: unknown DCTRL command %x\n", ipac->name, cmd); 1575 return -EINVAL; 1576 } 1577 return err; 1578 } 1579 1580 u32 1581 mISDNipac_init(struct ipac_hw *ipac, void *hw) 1582 { 1583 u32 ret; 1584 u8 i; 1585 1586 ipac->hw = hw; 1587 if (ipac->isac.dch.debug & DEBUG_HW) 1588 pr_notice("%s: ipac type %x\n", ipac->name, ipac->type); 1589 if (ipac->type & IPAC_TYPE_HSCX) { 1590 ipac->isac.type = IPAC_TYPE_ISAC; 1591 ipac->hscx[0].off = 0; 1592 ipac->hscx[1].off = 0x40; 1593 ipac->hscx[0].fifo_size = 32; 1594 ipac->hscx[1].fifo_size = 32; 1595 } else if (ipac->type & IPAC_TYPE_IPAC) { 1596 ipac->isac.type = IPAC_TYPE_IPAC | IPAC_TYPE_ISAC; 1597 ipac->hscx[0].off = 0; 1598 ipac->hscx[1].off = 0x40; 1599 ipac->hscx[0].fifo_size = 64; 1600 ipac->hscx[1].fifo_size = 64; 1601 } else if (ipac->type & IPAC_TYPE_IPACX) { 1602 ipac->isac.type = IPAC_TYPE_IPACX | IPAC_TYPE_ISACX; 1603 ipac->hscx[0].off = IPACX_OFF_ICA; 1604 ipac->hscx[1].off = IPACX_OFF_ICB; 1605 ipac->hscx[0].fifo_size = 64; 1606 ipac->hscx[1].fifo_size = 64; 1607 } else 1608 return 0; 1609 1610 mISDNisac_init(&ipac->isac, hw); 1611 1612 ipac->isac.dch.dev.D.ctrl = ipac_dctrl; 1613 1614 for (i = 0; i < 2; i++) { 1615 ipac->hscx[i].bch.nr = i + 1; 1616 set_channelmap(i + 1, ipac->isac.dch.dev.channelmap); 1617 list_add(&ipac->hscx[i].bch.ch.list, 1618 &ipac->isac.dch.dev.bchannels); 1619 mISDN_initbchannel(&ipac->hscx[i].bch, MAX_DATA_MEM, 1620 ipac->hscx[i].fifo_size); 1621 ipac->hscx[i].bch.ch.nr = i + 1; 1622 ipac->hscx[i].bch.ch.send = &hscx_l2l1; 1623 ipac->hscx[i].bch.ch.ctrl = hscx_bctrl; 1624 ipac->hscx[i].bch.hw = hw; 1625 ipac->hscx[i].ip = ipac; 1626 /* default values for IOM time slots 1627 * can be overwritten by card */ 1628 ipac->hscx[i].slot = (i == 0) ? 0x2f : 0x03; 1629 } 1630 1631 ipac->init = ipac_init; 1632 ipac->release = free_ipac; 1633 1634 ret = (1 << (ISDN_P_B_RAW & ISDN_P_B_MASK)) | 1635 (1 << (ISDN_P_B_HDLC & ISDN_P_B_MASK)); 1636 return ret; 1637 } 1638 EXPORT_SYMBOL(mISDNipac_init); 1639 1640 static int __init 1641 isac_mod_init(void) 1642 { 1643 pr_notice("mISDNipac module version %s\n", ISAC_REV); 1644 return 0; 1645 } 1646 1647 static void __exit 1648 isac_mod_cleanup(void) 1649 { 1650 pr_notice("mISDNipac module unloaded\n"); 1651 } 1652 module_init(isac_mod_init); 1653 module_exit(isac_mod_cleanup); 1654