1 /* 2 * hfcmulti.c low level driver for hfc-4s/hfc-8s/hfc-e1 based cards 3 * 4 * Author Andreas Eversberg (jolly@eversberg.eu) 5 * ported to mqueue mechanism: 6 * Peter Sprenger (sprengermoving-bytes.de) 7 * 8 * inspired by existing hfc-pci driver: 9 * Copyright 1999 by Werner Cornelius (werner@isdn-development.de) 10 * Copyright 2008 by Karsten Keil (kkeil@suse.de) 11 * Copyright 2008 by Andreas Eversberg (jolly@eversberg.eu) 12 * 13 * This program is free software; you can redistribute it and/or modify 14 * it under the terms of the GNU General Public License as published by 15 * the Free Software Foundation; either version 2, or (at your option) 16 * any later version. 17 * 18 * This program is distributed in the hope that it will be useful, 19 * but WITHOUT ANY WARRANTY; without even the implied warranty of 20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 * GNU General Public License for more details. 22 * 23 * You should have received a copy of the GNU General Public License 24 * along with this program; if not, write to the Free Software 25 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 26 * 27 * 28 * Thanks to Cologne Chip AG for this great controller! 29 */ 30 31 /* 32 * module parameters: 33 * type: 34 * By default (0), the card is automatically detected. 35 * Or use the following combinations: 36 * Bit 0-7 = 0x00001 = HFC-E1 (1 port) 37 * or Bit 0-7 = 0x00004 = HFC-4S (4 ports) 38 * or Bit 0-7 = 0x00008 = HFC-8S (8 ports) 39 * Bit 8 = 0x00100 = uLaw (instead of aLaw) 40 * Bit 9 = 0x00200 = Disable DTMF detect on all B-channels via hardware 41 * Bit 10 = spare 42 * Bit 11 = 0x00800 = Force PCM bus into slave mode. (otherwhise auto) 43 * or Bit 12 = 0x01000 = Force PCM bus into master mode. (otherwhise auto) 44 * Bit 13 = spare 45 * Bit 14 = 0x04000 = Use external ram (128K) 46 * Bit 15 = 0x08000 = Use external ram (512K) 47 * Bit 16 = 0x10000 = Use 64 timeslots instead of 32 48 * or Bit 17 = 0x20000 = Use 128 timeslots instead of anything else 49 * Bit 18 = spare 50 * Bit 19 = 0x80000 = Send the Watchdog a Signal (Dual E1 with Watchdog) 51 * (all other bits are reserved and shall be 0) 52 * example: 0x20204 one HFC-4S with dtmf detection and 128 timeslots on PCM 53 * bus (PCM master) 54 * 55 * port: (optional or required for all ports on all installed cards) 56 * HFC-4S/HFC-8S only bits: 57 * Bit 0 = 0x001 = Use master clock for this S/T interface 58 * (ony once per chip). 59 * Bit 1 = 0x002 = transmitter line setup (non capacitive mode) 60 * Don't use this unless you know what you are doing! 61 * Bit 2 = 0x004 = Disable E-channel. (No E-channel processing) 62 * example: 0x0001,0x0000,0x0000,0x0000 one HFC-4S with master clock 63 * received from port 1 64 * 65 * HFC-E1 only bits: 66 * Bit 0 = 0x0001 = interface: 0=copper, 1=optical 67 * Bit 1 = 0x0002 = reserved (later for 32 B-channels transparent mode) 68 * Bit 2 = 0x0004 = Report LOS 69 * Bit 3 = 0x0008 = Report AIS 70 * Bit 4 = 0x0010 = Report SLIP 71 * Bit 5 = 0x0020 = Report RDI 72 * Bit 8 = 0x0100 = Turn off CRC-4 Multiframe Mode, use double frame 73 * mode instead. 74 * Bit 9 = 0x0200 = Force get clock from interface, even in NT mode. 75 * or Bit 10 = 0x0400 = Force put clock to interface, even in TE mode. 76 * Bit 11 = 0x0800 = Use direct RX clock for PCM sync rather than PLL. 77 * (E1 only) 78 * Bit 12-13 = 0xX000 = elastic jitter buffer (1-3), Set both bits to 0 79 * for default. 80 * (all other bits are reserved and shall be 0) 81 * 82 * debug: 83 * NOTE: only one debug value must be given for all cards 84 * enable debugging (see hfc_multi.h for debug options) 85 * 86 * poll: 87 * NOTE: only one poll value must be given for all cards 88 * Give the number of samples for each fifo process. 89 * By default 128 is used. Decrease to reduce delay, increase to 90 * reduce cpu load. If unsure, don't mess with it! 91 * Valid is 8, 16, 32, 64, 128, 256. 92 * 93 * pcm: 94 * NOTE: only one pcm value must be given for every card. 95 * The PCM bus id tells the mISDNdsp module about the connected PCM bus. 96 * By default (0), the PCM bus id is 100 for the card that is PCM master. 97 * If multiple cards are PCM master (because they are not interconnected), 98 * each card with PCM master will have increasing PCM id. 99 * All PCM busses with the same ID are expected to be connected and have 100 * common time slots slots. 101 * Only one chip of the PCM bus must be master, the others slave. 102 * -1 means no support of PCM bus not even. 103 * Omit this value, if all cards are interconnected or none is connected. 104 * If unsure, don't give this parameter. 105 * 106 * dslot: 107 * NOTE: only one dslot value must be given for every card. 108 * Also this value must be given for non-E1 cards. If omitted, the E1 109 * card has D-channel on time slot 16, which is default. 110 * If 1..15 or 17..31, an alternate time slot is used for D-channel. 111 * In this case, the application must be able to handle this. 112 * If -1 is given, the D-channel is disabled and all 31 slots can be used 113 * for B-channel. (only for specific applications) 114 * If you don't know how to use it, you don't need it! 115 * 116 * iomode: 117 * NOTE: only one mode value must be given for every card. 118 * -> See hfc_multi.h for HFC_IO_MODE_* values 119 * By default, the IO mode is pci memory IO (MEMIO). 120 * Some cards require specific IO mode, so it cannot be changed. 121 * It may be useful to set IO mode to register io (REGIO) to solve 122 * PCI bridge problems. 123 * If unsure, don't give this parameter. 124 * 125 * clockdelay_nt: 126 * NOTE: only one clockdelay_nt value must be given once for all cards. 127 * Give the value of the clock control register (A_ST_CLK_DLY) 128 * of the S/T interfaces in NT mode. 129 * This register is needed for the TBR3 certification, so don't change it. 130 * 131 * clockdelay_te: 132 * NOTE: only one clockdelay_te value must be given once 133 * Give the value of the clock control register (A_ST_CLK_DLY) 134 * of the S/T interfaces in TE mode. 135 * This register is needed for the TBR3 certification, so don't change it. 136 * 137 * clock: 138 * NOTE: only one clock value must be given once 139 * Selects interface with clock source for mISDN and applications. 140 * Set to card number starting with 1. Set to -1 to disable. 141 * By default, the first card is used as clock source. 142 * 143 * hwid: 144 * NOTE: only one hwid value must be given once 145 * Enable special embedded devices with XHFC controllers. 146 */ 147 148 /* 149 * debug register access (never use this, it will flood your system log) 150 * #define HFC_REGISTER_DEBUG 151 */ 152 153 #define HFC_MULTI_VERSION "2.03" 154 155 #include <linux/interrupt.h> 156 #include <linux/module.h> 157 #include <linux/slab.h> 158 #include <linux/pci.h> 159 #include <linux/delay.h> 160 #include <linux/mISDNhw.h> 161 #include <linux/mISDNdsp.h> 162 163 /* 164 #define IRQCOUNT_DEBUG 165 #define IRQ_DEBUG 166 */ 167 168 #include "hfc_multi.h" 169 #ifdef ECHOPREP 170 #include "gaintab.h" 171 #endif 172 173 #define MAX_CARDS 8 174 #define MAX_PORTS (8 * MAX_CARDS) 175 176 static LIST_HEAD(HFClist); 177 static spinlock_t HFClock; /* global hfc list lock */ 178 179 static void ph_state_change(struct dchannel *); 180 181 static struct hfc_multi *syncmaster; 182 static int plxsd_master; /* if we have a master card (yet) */ 183 static spinlock_t plx_lock; /* may not acquire other lock inside */ 184 185 #define TYP_E1 1 186 #define TYP_4S 4 187 #define TYP_8S 8 188 189 static int poll_timer = 6; /* default = 128 samples = 16ms */ 190 /* number of POLL_TIMER interrupts for G2 timeout (ca 1s) */ 191 static int nt_t1_count[] = { 3840, 1920, 960, 480, 240, 120, 60, 30 }; 192 #define CLKDEL_TE 0x0f /* CLKDEL in TE mode */ 193 #define CLKDEL_NT 0x6c /* CLKDEL in NT mode 194 (0x60 MUST be included!) */ 195 196 #define DIP_4S 0x1 /* DIP Switches for Beronet 1S/2S/4S cards */ 197 #define DIP_8S 0x2 /* DIP Switches for Beronet 8S+ cards */ 198 #define DIP_E1 0x3 /* DIP Switches for Beronet E1 cards */ 199 200 /* 201 * module stuff 202 */ 203 204 static uint type[MAX_CARDS]; 205 static int pcm[MAX_CARDS]; 206 static int dslot[MAX_CARDS]; 207 static uint iomode[MAX_CARDS]; 208 static uint port[MAX_PORTS]; 209 static uint debug; 210 static uint poll; 211 static int clock; 212 static uint timer; 213 static uint clockdelay_te = CLKDEL_TE; 214 static uint clockdelay_nt = CLKDEL_NT; 215 #define HWID_NONE 0 216 #define HWID_MINIP4 1 217 #define HWID_MINIP8 2 218 #define HWID_MINIP16 3 219 static uint hwid = HWID_NONE; 220 221 static int HFC_cnt, Port_cnt, PCM_cnt = 99; 222 223 MODULE_AUTHOR("Andreas Eversberg"); 224 MODULE_LICENSE("GPL"); 225 MODULE_VERSION(HFC_MULTI_VERSION); 226 module_param(debug, uint, S_IRUGO | S_IWUSR); 227 module_param(poll, uint, S_IRUGO | S_IWUSR); 228 module_param(clock, int, S_IRUGO | S_IWUSR); 229 module_param(timer, uint, S_IRUGO | S_IWUSR); 230 module_param(clockdelay_te, uint, S_IRUGO | S_IWUSR); 231 module_param(clockdelay_nt, uint, S_IRUGO | S_IWUSR); 232 module_param_array(type, uint, NULL, S_IRUGO | S_IWUSR); 233 module_param_array(pcm, int, NULL, S_IRUGO | S_IWUSR); 234 module_param_array(dslot, int, NULL, S_IRUGO | S_IWUSR); 235 module_param_array(iomode, uint, NULL, S_IRUGO | S_IWUSR); 236 module_param_array(port, uint, NULL, S_IRUGO | S_IWUSR); 237 module_param(hwid, uint, S_IRUGO | S_IWUSR); /* The hardware ID */ 238 239 #ifdef HFC_REGISTER_DEBUG 240 #define HFC_outb(hc, reg, val) \ 241 (hc->HFC_outb(hc, reg, val, __func__, __LINE__)) 242 #define HFC_outb_nodebug(hc, reg, val) \ 243 (hc->HFC_outb_nodebug(hc, reg, val, __func__, __LINE__)) 244 #define HFC_inb(hc, reg) \ 245 (hc->HFC_inb(hc, reg, __func__, __LINE__)) 246 #define HFC_inb_nodebug(hc, reg) \ 247 (hc->HFC_inb_nodebug(hc, reg, __func__, __LINE__)) 248 #define HFC_inw(hc, reg) \ 249 (hc->HFC_inw(hc, reg, __func__, __LINE__)) 250 #define HFC_inw_nodebug(hc, reg) \ 251 (hc->HFC_inw_nodebug(hc, reg, __func__, __LINE__)) 252 #define HFC_wait(hc) \ 253 (hc->HFC_wait(hc, __func__, __LINE__)) 254 #define HFC_wait_nodebug(hc) \ 255 (hc->HFC_wait_nodebug(hc, __func__, __LINE__)) 256 #else 257 #define HFC_outb(hc, reg, val) (hc->HFC_outb(hc, reg, val)) 258 #define HFC_outb_nodebug(hc, reg, val) (hc->HFC_outb_nodebug(hc, reg, val)) 259 #define HFC_inb(hc, reg) (hc->HFC_inb(hc, reg)) 260 #define HFC_inb_nodebug(hc, reg) (hc->HFC_inb_nodebug(hc, reg)) 261 #define HFC_inw(hc, reg) (hc->HFC_inw(hc, reg)) 262 #define HFC_inw_nodebug(hc, reg) (hc->HFC_inw_nodebug(hc, reg)) 263 #define HFC_wait(hc) (hc->HFC_wait(hc)) 264 #define HFC_wait_nodebug(hc) (hc->HFC_wait_nodebug(hc)) 265 #endif 266 267 #ifdef CONFIG_MISDN_HFCMULTI_8xx 268 #include "hfc_multi_8xx.h" 269 #endif 270 271 /* HFC_IO_MODE_PCIMEM */ 272 static void 273 #ifdef HFC_REGISTER_DEBUG 274 HFC_outb_pcimem(struct hfc_multi *hc, u_char reg, u_char val, 275 const char *function, int line) 276 #else 277 HFC_outb_pcimem(struct hfc_multi *hc, u_char reg, u_char val) 278 #endif 279 { 280 writeb(val, hc->pci_membase + reg); 281 } 282 static u_char 283 #ifdef HFC_REGISTER_DEBUG 284 HFC_inb_pcimem(struct hfc_multi *hc, u_char reg, const char *function, int line) 285 #else 286 HFC_inb_pcimem(struct hfc_multi *hc, u_char reg) 287 #endif 288 { 289 return readb(hc->pci_membase + reg); 290 } 291 static u_short 292 #ifdef HFC_REGISTER_DEBUG 293 HFC_inw_pcimem(struct hfc_multi *hc, u_char reg, const char *function, int line) 294 #else 295 HFC_inw_pcimem(struct hfc_multi *hc, u_char reg) 296 #endif 297 { 298 return readw(hc->pci_membase + reg); 299 } 300 static void 301 #ifdef HFC_REGISTER_DEBUG 302 HFC_wait_pcimem(struct hfc_multi *hc, const char *function, int line) 303 #else 304 HFC_wait_pcimem(struct hfc_multi *hc) 305 #endif 306 { 307 while (readb(hc->pci_membase + R_STATUS) & V_BUSY) 308 cpu_relax(); 309 } 310 311 /* HFC_IO_MODE_REGIO */ 312 static void 313 #ifdef HFC_REGISTER_DEBUG 314 HFC_outb_regio(struct hfc_multi *hc, u_char reg, u_char val, 315 const char *function, int line) 316 #else 317 HFC_outb_regio(struct hfc_multi *hc, u_char reg, u_char val) 318 #endif 319 { 320 outb(reg, hc->pci_iobase + 4); 321 outb(val, hc->pci_iobase); 322 } 323 static u_char 324 #ifdef HFC_REGISTER_DEBUG 325 HFC_inb_regio(struct hfc_multi *hc, u_char reg, const char *function, int line) 326 #else 327 HFC_inb_regio(struct hfc_multi *hc, u_char reg) 328 #endif 329 { 330 outb(reg, hc->pci_iobase + 4); 331 return inb(hc->pci_iobase); 332 } 333 static u_short 334 #ifdef HFC_REGISTER_DEBUG 335 HFC_inw_regio(struct hfc_multi *hc, u_char reg, const char *function, int line) 336 #else 337 HFC_inw_regio(struct hfc_multi *hc, u_char reg) 338 #endif 339 { 340 outb(reg, hc->pci_iobase + 4); 341 return inw(hc->pci_iobase); 342 } 343 static void 344 #ifdef HFC_REGISTER_DEBUG 345 HFC_wait_regio(struct hfc_multi *hc, const char *function, int line) 346 #else 347 HFC_wait_regio(struct hfc_multi *hc) 348 #endif 349 { 350 outb(R_STATUS, hc->pci_iobase + 4); 351 while (inb(hc->pci_iobase) & V_BUSY) 352 cpu_relax(); 353 } 354 355 #ifdef HFC_REGISTER_DEBUG 356 static void 357 HFC_outb_debug(struct hfc_multi *hc, u_char reg, u_char val, 358 const char *function, int line) 359 { 360 char regname[256] = "", bits[9] = "xxxxxxxx"; 361 int i; 362 363 i = -1; 364 while (hfc_register_names[++i].name) { 365 if (hfc_register_names[i].reg == reg) 366 strcat(regname, hfc_register_names[i].name); 367 } 368 if (regname[0] == '\0') 369 strcpy(regname, "register"); 370 371 bits[7] = '0' + (!!(val & 1)); 372 bits[6] = '0' + (!!(val & 2)); 373 bits[5] = '0' + (!!(val & 4)); 374 bits[4] = '0' + (!!(val & 8)); 375 bits[3] = '0' + (!!(val & 16)); 376 bits[2] = '0' + (!!(val & 32)); 377 bits[1] = '0' + (!!(val & 64)); 378 bits[0] = '0' + (!!(val & 128)); 379 printk(KERN_DEBUG 380 "HFC_outb(chip %d, %02x=%s, 0x%02x=%s); in %s() line %d\n", 381 hc->id, reg, regname, val, bits, function, line); 382 HFC_outb_nodebug(hc, reg, val); 383 } 384 static u_char 385 HFC_inb_debug(struct hfc_multi *hc, u_char reg, const char *function, int line) 386 { 387 char regname[256] = "", bits[9] = "xxxxxxxx"; 388 u_char val = HFC_inb_nodebug(hc, reg); 389 int i; 390 391 i = 0; 392 while (hfc_register_names[i++].name) 393 ; 394 while (hfc_register_names[++i].name) { 395 if (hfc_register_names[i].reg == reg) 396 strcat(regname, hfc_register_names[i].name); 397 } 398 if (regname[0] == '\0') 399 strcpy(regname, "register"); 400 401 bits[7] = '0' + (!!(val & 1)); 402 bits[6] = '0' + (!!(val & 2)); 403 bits[5] = '0' + (!!(val & 4)); 404 bits[4] = '0' + (!!(val & 8)); 405 bits[3] = '0' + (!!(val & 16)); 406 bits[2] = '0' + (!!(val & 32)); 407 bits[1] = '0' + (!!(val & 64)); 408 bits[0] = '0' + (!!(val & 128)); 409 printk(KERN_DEBUG 410 "HFC_inb(chip %d, %02x=%s) = 0x%02x=%s; in %s() line %d\n", 411 hc->id, reg, regname, val, bits, function, line); 412 return val; 413 } 414 static u_short 415 HFC_inw_debug(struct hfc_multi *hc, u_char reg, const char *function, int line) 416 { 417 char regname[256] = ""; 418 u_short val = HFC_inw_nodebug(hc, reg); 419 int i; 420 421 i = 0; 422 while (hfc_register_names[i++].name) 423 ; 424 while (hfc_register_names[++i].name) { 425 if (hfc_register_names[i].reg == reg) 426 strcat(regname, hfc_register_names[i].name); 427 } 428 if (regname[0] == '\0') 429 strcpy(regname, "register"); 430 431 printk(KERN_DEBUG 432 "HFC_inw(chip %d, %02x=%s) = 0x%04x; in %s() line %d\n", 433 hc->id, reg, regname, val, function, line); 434 return val; 435 } 436 static void 437 HFC_wait_debug(struct hfc_multi *hc, const char *function, int line) 438 { 439 printk(KERN_DEBUG "HFC_wait(chip %d); in %s() line %d\n", 440 hc->id, function, line); 441 HFC_wait_nodebug(hc); 442 } 443 #endif 444 445 /* write fifo data (REGIO) */ 446 static void 447 write_fifo_regio(struct hfc_multi *hc, u_char *data, int len) 448 { 449 outb(A_FIFO_DATA0, (hc->pci_iobase)+4); 450 while (len>>2) { 451 outl(cpu_to_le32(*(u32 *)data), hc->pci_iobase); 452 data += 4; 453 len -= 4; 454 } 455 while (len>>1) { 456 outw(cpu_to_le16(*(u16 *)data), hc->pci_iobase); 457 data += 2; 458 len -= 2; 459 } 460 while (len) { 461 outb(*data, hc->pci_iobase); 462 data++; 463 len--; 464 } 465 } 466 /* write fifo data (PCIMEM) */ 467 static void 468 write_fifo_pcimem(struct hfc_multi *hc, u_char *data, int len) 469 { 470 while (len>>2) { 471 writel(cpu_to_le32(*(u32 *)data), 472 hc->pci_membase + A_FIFO_DATA0); 473 data += 4; 474 len -= 4; 475 } 476 while (len>>1) { 477 writew(cpu_to_le16(*(u16 *)data), 478 hc->pci_membase + A_FIFO_DATA0); 479 data += 2; 480 len -= 2; 481 } 482 while (len) { 483 writeb(*data, hc->pci_membase + A_FIFO_DATA0); 484 data++; 485 len--; 486 } 487 } 488 489 /* read fifo data (REGIO) */ 490 static void 491 read_fifo_regio(struct hfc_multi *hc, u_char *data, int len) 492 { 493 outb(A_FIFO_DATA0, (hc->pci_iobase)+4); 494 while (len>>2) { 495 *(u32 *)data = le32_to_cpu(inl(hc->pci_iobase)); 496 data += 4; 497 len -= 4; 498 } 499 while (len>>1) { 500 *(u16 *)data = le16_to_cpu(inw(hc->pci_iobase)); 501 data += 2; 502 len -= 2; 503 } 504 while (len) { 505 *data = inb(hc->pci_iobase); 506 data++; 507 len--; 508 } 509 } 510 511 /* read fifo data (PCIMEM) */ 512 static void 513 read_fifo_pcimem(struct hfc_multi *hc, u_char *data, int len) 514 { 515 while (len>>2) { 516 *(u32 *)data = 517 le32_to_cpu(readl(hc->pci_membase + A_FIFO_DATA0)); 518 data += 4; 519 len -= 4; 520 } 521 while (len>>1) { 522 *(u16 *)data = 523 le16_to_cpu(readw(hc->pci_membase + A_FIFO_DATA0)); 524 data += 2; 525 len -= 2; 526 } 527 while (len) { 528 *data = readb(hc->pci_membase + A_FIFO_DATA0); 529 data++; 530 len--; 531 } 532 } 533 534 static void 535 enable_hwirq(struct hfc_multi *hc) 536 { 537 hc->hw.r_irq_ctrl |= V_GLOB_IRQ_EN; 538 HFC_outb(hc, R_IRQ_CTRL, hc->hw.r_irq_ctrl); 539 } 540 541 static void 542 disable_hwirq(struct hfc_multi *hc) 543 { 544 hc->hw.r_irq_ctrl &= ~((u_char)V_GLOB_IRQ_EN); 545 HFC_outb(hc, R_IRQ_CTRL, hc->hw.r_irq_ctrl); 546 } 547 548 #define NUM_EC 2 549 #define MAX_TDM_CHAN 32 550 551 552 inline void 553 enablepcibridge(struct hfc_multi *c) 554 { 555 HFC_outb(c, R_BRG_PCM_CFG, (0x0 << 6) | 0x3); /* was _io before */ 556 } 557 558 inline void 559 disablepcibridge(struct hfc_multi *c) 560 { 561 HFC_outb(c, R_BRG_PCM_CFG, (0x0 << 6) | 0x2); /* was _io before */ 562 } 563 564 inline unsigned char 565 readpcibridge(struct hfc_multi *hc, unsigned char address) 566 { 567 unsigned short cipv; 568 unsigned char data; 569 570 if (!hc->pci_iobase) 571 return 0; 572 573 /* slow down a PCI read access by 1 PCI clock cycle */ 574 HFC_outb(hc, R_CTRL, 0x4); /*was _io before*/ 575 576 if (address == 0) 577 cipv = 0x4000; 578 else 579 cipv = 0x5800; 580 581 /* select local bridge port address by writing to CIP port */ 582 /* data = HFC_inb(c, cipv); * was _io before */ 583 outw(cipv, hc->pci_iobase + 4); 584 data = inb(hc->pci_iobase); 585 586 /* restore R_CTRL for normal PCI read cycle speed */ 587 HFC_outb(hc, R_CTRL, 0x0); /* was _io before */ 588 589 return data; 590 } 591 592 inline void 593 writepcibridge(struct hfc_multi *hc, unsigned char address, unsigned char data) 594 { 595 unsigned short cipv; 596 unsigned int datav; 597 598 if (!hc->pci_iobase) 599 return; 600 601 if (address == 0) 602 cipv = 0x4000; 603 else 604 cipv = 0x5800; 605 606 /* select local bridge port address by writing to CIP port */ 607 outw(cipv, hc->pci_iobase + 4); 608 /* define a 32 bit dword with 4 identical bytes for write sequence */ 609 datav = data | ((__u32) data << 8) | ((__u32) data << 16) | 610 ((__u32) data << 24); 611 612 /* 613 * write this 32 bit dword to the bridge data port 614 * this will initiate a write sequence of up to 4 writes to the same 615 * address on the local bus interface the number of write accesses 616 * is undefined but >=1 and depends on the next PCI transaction 617 * during write sequence on the local bus 618 */ 619 outl(datav, hc->pci_iobase); 620 } 621 622 inline void 623 cpld_set_reg(struct hfc_multi *hc, unsigned char reg) 624 { 625 /* Do data pin read low byte */ 626 HFC_outb(hc, R_GPIO_OUT1, reg); 627 } 628 629 inline void 630 cpld_write_reg(struct hfc_multi *hc, unsigned char reg, unsigned char val) 631 { 632 cpld_set_reg(hc, reg); 633 634 enablepcibridge(hc); 635 writepcibridge(hc, 1, val); 636 disablepcibridge(hc); 637 638 return; 639 } 640 641 inline unsigned char 642 cpld_read_reg(struct hfc_multi *hc, unsigned char reg) 643 { 644 unsigned char bytein; 645 646 cpld_set_reg(hc, reg); 647 648 /* Do data pin read low byte */ 649 HFC_outb(hc, R_GPIO_OUT1, reg); 650 651 enablepcibridge(hc); 652 bytein = readpcibridge(hc, 1); 653 disablepcibridge(hc); 654 655 return bytein; 656 } 657 658 inline void 659 vpm_write_address(struct hfc_multi *hc, unsigned short addr) 660 { 661 cpld_write_reg(hc, 0, 0xff & addr); 662 cpld_write_reg(hc, 1, 0x01 & (addr >> 8)); 663 } 664 665 inline unsigned short 666 vpm_read_address(struct hfc_multi *c) 667 { 668 unsigned short addr; 669 unsigned short highbit; 670 671 addr = cpld_read_reg(c, 0); 672 highbit = cpld_read_reg(c, 1); 673 674 addr = addr | (highbit << 8); 675 676 return addr & 0x1ff; 677 } 678 679 inline unsigned char 680 vpm_in(struct hfc_multi *c, int which, unsigned short addr) 681 { 682 unsigned char res; 683 684 vpm_write_address(c, addr); 685 686 if (!which) 687 cpld_set_reg(c, 2); 688 else 689 cpld_set_reg(c, 3); 690 691 enablepcibridge(c); 692 res = readpcibridge(c, 1); 693 disablepcibridge(c); 694 695 cpld_set_reg(c, 0); 696 697 return res; 698 } 699 700 inline void 701 vpm_out(struct hfc_multi *c, int which, unsigned short addr, 702 unsigned char data) 703 { 704 vpm_write_address(c, addr); 705 706 enablepcibridge(c); 707 708 if (!which) 709 cpld_set_reg(c, 2); 710 else 711 cpld_set_reg(c, 3); 712 713 writepcibridge(c, 1, data); 714 715 cpld_set_reg(c, 0); 716 717 disablepcibridge(c); 718 719 { 720 unsigned char regin; 721 regin = vpm_in(c, which, addr); 722 if (regin != data) 723 printk(KERN_DEBUG "Wrote 0x%x to register 0x%x but got back " 724 "0x%x\n", data, addr, regin); 725 } 726 727 } 728 729 730 static void 731 vpm_init(struct hfc_multi *wc) 732 { 733 unsigned char reg; 734 unsigned int mask; 735 unsigned int i, x, y; 736 unsigned int ver; 737 738 for (x = 0; x < NUM_EC; x++) { 739 /* Setup GPIO's */ 740 if (!x) { 741 ver = vpm_in(wc, x, 0x1a0); 742 printk(KERN_DEBUG "VPM: Chip %d: ver %02x\n", x, ver); 743 } 744 745 for (y = 0; y < 4; y++) { 746 vpm_out(wc, x, 0x1a8 + y, 0x00); /* GPIO out */ 747 vpm_out(wc, x, 0x1ac + y, 0x00); /* GPIO dir */ 748 vpm_out(wc, x, 0x1b0 + y, 0x00); /* GPIO sel */ 749 } 750 751 /* Setup TDM path - sets fsync and tdm_clk as inputs */ 752 reg = vpm_in(wc, x, 0x1a3); /* misc_con */ 753 vpm_out(wc, x, 0x1a3, reg & ~2); 754 755 /* Setup Echo length (256 taps) */ 756 vpm_out(wc, x, 0x022, 1); 757 vpm_out(wc, x, 0x023, 0xff); 758 759 /* Setup timeslots */ 760 vpm_out(wc, x, 0x02f, 0x00); 761 mask = 0x02020202 << (x * 4); 762 763 /* Setup the tdm channel masks for all chips */ 764 for (i = 0; i < 4; i++) 765 vpm_out(wc, x, 0x33 - i, (mask >> (i << 3)) & 0xff); 766 767 /* Setup convergence rate */ 768 printk(KERN_DEBUG "VPM: A-law mode\n"); 769 reg = 0x00 | 0x10 | 0x01; 770 vpm_out(wc, x, 0x20, reg); 771 printk(KERN_DEBUG "VPM reg 0x20 is %x\n", reg); 772 /*vpm_out(wc, x, 0x20, (0x00 | 0x08 | 0x20 | 0x10)); */ 773 774 vpm_out(wc, x, 0x24, 0x02); 775 reg = vpm_in(wc, x, 0x24); 776 printk(KERN_DEBUG "NLP Thresh is set to %d (0x%x)\n", reg, reg); 777 778 /* Initialize echo cans */ 779 for (i = 0; i < MAX_TDM_CHAN; i++) { 780 if (mask & (0x00000001 << i)) 781 vpm_out(wc, x, i, 0x00); 782 } 783 784 /* 785 * ARM arch at least disallows a udelay of 786 * more than 2ms... it gives a fake "__bad_udelay" 787 * reference at link-time. 788 * long delays in kernel code are pretty sucky anyway 789 * for now work around it using 5 x 2ms instead of 1 x 10ms 790 */ 791 792 udelay(2000); 793 udelay(2000); 794 udelay(2000); 795 udelay(2000); 796 udelay(2000); 797 798 /* Put in bypass mode */ 799 for (i = 0; i < MAX_TDM_CHAN; i++) { 800 if (mask & (0x00000001 << i)) 801 vpm_out(wc, x, i, 0x01); 802 } 803 804 /* Enable bypass */ 805 for (i = 0; i < MAX_TDM_CHAN; i++) { 806 if (mask & (0x00000001 << i)) 807 vpm_out(wc, x, 0x78 + i, 0x01); 808 } 809 810 } 811 } 812 813 #ifdef UNUSED 814 static void 815 vpm_check(struct hfc_multi *hctmp) 816 { 817 unsigned char gpi2; 818 819 gpi2 = HFC_inb(hctmp, R_GPI_IN2); 820 821 if ((gpi2 & 0x3) != 0x3) 822 printk(KERN_DEBUG "Got interrupt 0x%x from VPM!\n", gpi2); 823 } 824 #endif /* UNUSED */ 825 826 827 /* 828 * Interface to enable/disable the HW Echocan 829 * 830 * these functions are called within a spin_lock_irqsave on 831 * the channel instance lock, so we are not disturbed by irqs 832 * 833 * we can later easily change the interface to make other 834 * things configurable, for now we configure the taps 835 * 836 */ 837 838 static void 839 vpm_echocan_on(struct hfc_multi *hc, int ch, int taps) 840 { 841 unsigned int timeslot; 842 unsigned int unit; 843 struct bchannel *bch = hc->chan[ch].bch; 844 #ifdef TXADJ 845 int txadj = -4; 846 struct sk_buff *skb; 847 #endif 848 if (hc->chan[ch].protocol != ISDN_P_B_RAW) 849 return; 850 851 if (!bch) 852 return; 853 854 #ifdef TXADJ 855 skb = _alloc_mISDN_skb(PH_CONTROL_IND, HFC_VOL_CHANGE_TX, 856 sizeof(int), &txadj, GFP_ATOMIC); 857 if (skb) 858 recv_Bchannel_skb(bch, skb); 859 #endif 860 861 timeslot = ((ch/4)*8) + ((ch%4)*4) + 1; 862 unit = ch % 4; 863 864 printk(KERN_NOTICE "vpm_echocan_on called taps [%d] on timeslot %d\n", 865 taps, timeslot); 866 867 vpm_out(hc, unit, timeslot, 0x7e); 868 } 869 870 static void 871 vpm_echocan_off(struct hfc_multi *hc, int ch) 872 { 873 unsigned int timeslot; 874 unsigned int unit; 875 struct bchannel *bch = hc->chan[ch].bch; 876 #ifdef TXADJ 877 int txadj = 0; 878 struct sk_buff *skb; 879 #endif 880 881 if (hc->chan[ch].protocol != ISDN_P_B_RAW) 882 return; 883 884 if (!bch) 885 return; 886 887 #ifdef TXADJ 888 skb = _alloc_mISDN_skb(PH_CONTROL_IND, HFC_VOL_CHANGE_TX, 889 sizeof(int), &txadj, GFP_ATOMIC); 890 if (skb) 891 recv_Bchannel_skb(bch, skb); 892 #endif 893 894 timeslot = ((ch/4)*8) + ((ch%4)*4) + 1; 895 unit = ch % 4; 896 897 printk(KERN_NOTICE "vpm_echocan_off called on timeslot %d\n", 898 timeslot); 899 /* FILLME */ 900 vpm_out(hc, unit, timeslot, 0x01); 901 } 902 903 904 /* 905 * Speech Design resync feature 906 * NOTE: This is called sometimes outside interrupt handler. 907 * We must lock irqsave, so no other interrupt (other card) will occur! 908 * Also multiple interrupts may nest, so must lock each access (lists, card)! 909 */ 910 static inline void 911 hfcmulti_resync(struct hfc_multi *locked, struct hfc_multi *newmaster, int rm) 912 { 913 struct hfc_multi *hc, *next, *pcmmaster = NULL; 914 void __iomem *plx_acc_32; 915 u_int pv; 916 u_long flags; 917 918 spin_lock_irqsave(&HFClock, flags); 919 spin_lock(&plx_lock); /* must be locked inside other locks */ 920 921 if (debug & DEBUG_HFCMULTI_PLXSD) 922 printk(KERN_DEBUG "%s: RESYNC(syncmaster=0x%p)\n", 923 __func__, syncmaster); 924 925 /* select new master */ 926 if (newmaster) { 927 if (debug & DEBUG_HFCMULTI_PLXSD) 928 printk(KERN_DEBUG "using provided controller\n"); 929 } else { 930 list_for_each_entry_safe(hc, next, &HFClist, list) { 931 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) { 932 if (hc->syncronized) { 933 newmaster = hc; 934 break; 935 } 936 } 937 } 938 } 939 940 /* Disable sync of all cards */ 941 list_for_each_entry_safe(hc, next, &HFClist, list) { 942 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) { 943 plx_acc_32 = hc->plx_membase + PLX_GPIOC; 944 pv = readl(plx_acc_32); 945 pv &= ~PLX_SYNC_O_EN; 946 writel(pv, plx_acc_32); 947 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip)) { 948 pcmmaster = hc; 949 if (hc->ctype == HFC_TYPE_E1) { 950 if (debug & DEBUG_HFCMULTI_PLXSD) 951 printk(KERN_DEBUG 952 "Schedule SYNC_I\n"); 953 hc->e1_resync |= 1; /* get SYNC_I */ 954 } 955 } 956 } 957 } 958 959 if (newmaster) { 960 hc = newmaster; 961 if (debug & DEBUG_HFCMULTI_PLXSD) 962 printk(KERN_DEBUG "id=%d (0x%p) = syncronized with " 963 "interface.\n", hc->id, hc); 964 /* Enable new sync master */ 965 plx_acc_32 = hc->plx_membase + PLX_GPIOC; 966 pv = readl(plx_acc_32); 967 pv |= PLX_SYNC_O_EN; 968 writel(pv, plx_acc_32); 969 /* switch to jatt PLL, if not disabled by RX_SYNC */ 970 if (hc->ctype == HFC_TYPE_E1 971 && !test_bit(HFC_CHIP_RX_SYNC, &hc->chip)) { 972 if (debug & DEBUG_HFCMULTI_PLXSD) 973 printk(KERN_DEBUG "Schedule jatt PLL\n"); 974 hc->e1_resync |= 2; /* switch to jatt */ 975 } 976 } else { 977 if (pcmmaster) { 978 hc = pcmmaster; 979 if (debug & DEBUG_HFCMULTI_PLXSD) 980 printk(KERN_DEBUG 981 "id=%d (0x%p) = PCM master syncronized " 982 "with QUARTZ\n", hc->id, hc); 983 if (hc->ctype == HFC_TYPE_E1) { 984 /* Use the crystal clock for the PCM 985 master card */ 986 if (debug & DEBUG_HFCMULTI_PLXSD) 987 printk(KERN_DEBUG 988 "Schedule QUARTZ for HFC-E1\n"); 989 hc->e1_resync |= 4; /* switch quartz */ 990 } else { 991 if (debug & DEBUG_HFCMULTI_PLXSD) 992 printk(KERN_DEBUG 993 "QUARTZ is automatically " 994 "enabled by HFC-%dS\n", hc->ctype); 995 } 996 plx_acc_32 = hc->plx_membase + PLX_GPIOC; 997 pv = readl(plx_acc_32); 998 pv |= PLX_SYNC_O_EN; 999 writel(pv, plx_acc_32); 1000 } else 1001 if (!rm) 1002 printk(KERN_ERR "%s no pcm master, this MUST " 1003 "not happen!\n", __func__); 1004 } 1005 syncmaster = newmaster; 1006 1007 spin_unlock(&plx_lock); 1008 spin_unlock_irqrestore(&HFClock, flags); 1009 } 1010 1011 /* This must be called AND hc must be locked irqsave!!! */ 1012 inline void 1013 plxsd_checksync(struct hfc_multi *hc, int rm) 1014 { 1015 if (hc->syncronized) { 1016 if (syncmaster == NULL) { 1017 if (debug & DEBUG_HFCMULTI_PLXSD) 1018 printk(KERN_DEBUG "%s: GOT sync on card %d" 1019 " (id=%d)\n", __func__, hc->id + 1, 1020 hc->id); 1021 hfcmulti_resync(hc, hc, rm); 1022 } 1023 } else { 1024 if (syncmaster == hc) { 1025 if (debug & DEBUG_HFCMULTI_PLXSD) 1026 printk(KERN_DEBUG "%s: LOST sync on card %d" 1027 " (id=%d)\n", __func__, hc->id + 1, 1028 hc->id); 1029 hfcmulti_resync(hc, NULL, rm); 1030 } 1031 } 1032 } 1033 1034 1035 /* 1036 * free hardware resources used by driver 1037 */ 1038 static void 1039 release_io_hfcmulti(struct hfc_multi *hc) 1040 { 1041 void __iomem *plx_acc_32; 1042 u_int pv; 1043 u_long plx_flags; 1044 1045 if (debug & DEBUG_HFCMULTI_INIT) 1046 printk(KERN_DEBUG "%s: entered\n", __func__); 1047 1048 /* soft reset also masks all interrupts */ 1049 hc->hw.r_cirm |= V_SRES; 1050 HFC_outb(hc, R_CIRM, hc->hw.r_cirm); 1051 udelay(1000); 1052 hc->hw.r_cirm &= ~V_SRES; 1053 HFC_outb(hc, R_CIRM, hc->hw.r_cirm); 1054 udelay(1000); /* instead of 'wait' that may cause locking */ 1055 1056 /* release Speech Design card, if PLX was initialized */ 1057 if (test_bit(HFC_CHIP_PLXSD, &hc->chip) && hc->plx_membase) { 1058 if (debug & DEBUG_HFCMULTI_PLXSD) 1059 printk(KERN_DEBUG "%s: release PLXSD card %d\n", 1060 __func__, hc->id + 1); 1061 spin_lock_irqsave(&plx_lock, plx_flags); 1062 plx_acc_32 = hc->plx_membase + PLX_GPIOC; 1063 writel(PLX_GPIOC_INIT, plx_acc_32); 1064 pv = readl(plx_acc_32); 1065 /* Termination off */ 1066 pv &= ~PLX_TERM_ON; 1067 /* Disconnect the PCM */ 1068 pv |= PLX_SLAVE_EN_N; 1069 pv &= ~PLX_MASTER_EN; 1070 pv &= ~PLX_SYNC_O_EN; 1071 /* Put the DSP in Reset */ 1072 pv &= ~PLX_DSP_RES_N; 1073 writel(pv, plx_acc_32); 1074 if (debug & DEBUG_HFCMULTI_INIT) 1075 printk(KERN_DEBUG "%s: PCM off: PLX_GPIO=%x\n", 1076 __func__, pv); 1077 spin_unlock_irqrestore(&plx_lock, plx_flags); 1078 } 1079 1080 /* disable memory mapped ports / io ports */ 1081 test_and_clear_bit(HFC_CHIP_PLXSD, &hc->chip); /* prevent resync */ 1082 if (hc->pci_dev) 1083 pci_write_config_word(hc->pci_dev, PCI_COMMAND, 0); 1084 if (hc->pci_membase) 1085 iounmap(hc->pci_membase); 1086 if (hc->plx_membase) 1087 iounmap(hc->plx_membase); 1088 if (hc->pci_iobase) 1089 release_region(hc->pci_iobase, 8); 1090 if (hc->xhfc_membase) 1091 iounmap((void *)hc->xhfc_membase); 1092 1093 if (hc->pci_dev) { 1094 pci_disable_device(hc->pci_dev); 1095 pci_set_drvdata(hc->pci_dev, NULL); 1096 } 1097 if (debug & DEBUG_HFCMULTI_INIT) 1098 printk(KERN_DEBUG "%s: done\n", __func__); 1099 } 1100 1101 /* 1102 * function called to reset the HFC chip. A complete software reset of chip 1103 * and fifos is done. All configuration of the chip is done. 1104 */ 1105 1106 static int 1107 init_chip(struct hfc_multi *hc) 1108 { 1109 u_long flags, val, val2 = 0, rev; 1110 int i, err = 0; 1111 u_char r_conf_en, rval; 1112 void __iomem *plx_acc_32; 1113 u_int pv; 1114 u_long plx_flags, hfc_flags; 1115 int plx_count; 1116 struct hfc_multi *pos, *next, *plx_last_hc; 1117 1118 spin_lock_irqsave(&hc->lock, flags); 1119 /* reset all registers */ 1120 memset(&hc->hw, 0, sizeof(struct hfcm_hw)); 1121 1122 /* revision check */ 1123 if (debug & DEBUG_HFCMULTI_INIT) 1124 printk(KERN_DEBUG "%s: entered\n", __func__); 1125 val = HFC_inb(hc, R_CHIP_ID); 1126 if ((val >> 4) != 0x8 && (val >> 4) != 0xc && (val >> 4) != 0xe && 1127 (val >> 1) != 0x31) { 1128 printk(KERN_INFO "HFC_multi: unknown CHIP_ID:%x\n", (u_int)val); 1129 err = -EIO; 1130 goto out; 1131 } 1132 rev = HFC_inb(hc, R_CHIP_RV); 1133 printk(KERN_INFO 1134 "HFC_multi: detected HFC with chip ID=0x%lx revision=%ld%s\n", 1135 val, rev, (rev == 0 && (hc->ctype != HFC_TYPE_XHFC)) ? 1136 " (old FIFO handling)" : ""); 1137 if (hc->ctype != HFC_TYPE_XHFC && rev == 0) { 1138 test_and_set_bit(HFC_CHIP_REVISION0, &hc->chip); 1139 printk(KERN_WARNING 1140 "HFC_multi: NOTE: Your chip is revision 0, " 1141 "ask Cologne Chip for update. Newer chips " 1142 "have a better FIFO handling. Old chips " 1143 "still work but may have slightly lower " 1144 "HDLC transmit performance.\n"); 1145 } 1146 if (rev > 1) { 1147 printk(KERN_WARNING "HFC_multi: WARNING: This driver doesn't " 1148 "consider chip revision = %ld. The chip / " 1149 "bridge may not work.\n", rev); 1150 } 1151 1152 /* set s-ram size */ 1153 hc->Flen = 0x10; 1154 hc->Zmin = 0x80; 1155 hc->Zlen = 384; 1156 hc->DTMFbase = 0x1000; 1157 if (test_bit(HFC_CHIP_EXRAM_128, &hc->chip)) { 1158 if (debug & DEBUG_HFCMULTI_INIT) 1159 printk(KERN_DEBUG "%s: changing to 128K extenal RAM\n", 1160 __func__); 1161 hc->hw.r_ctrl |= V_EXT_RAM; 1162 hc->hw.r_ram_sz = 1; 1163 hc->Flen = 0x20; 1164 hc->Zmin = 0xc0; 1165 hc->Zlen = 1856; 1166 hc->DTMFbase = 0x2000; 1167 } 1168 if (test_bit(HFC_CHIP_EXRAM_512, &hc->chip)) { 1169 if (debug & DEBUG_HFCMULTI_INIT) 1170 printk(KERN_DEBUG "%s: changing to 512K extenal RAM\n", 1171 __func__); 1172 hc->hw.r_ctrl |= V_EXT_RAM; 1173 hc->hw.r_ram_sz = 2; 1174 hc->Flen = 0x20; 1175 hc->Zmin = 0xc0; 1176 hc->Zlen = 8000; 1177 hc->DTMFbase = 0x2000; 1178 } 1179 if (hc->ctype == HFC_TYPE_XHFC) { 1180 hc->Flen = 0x8; 1181 hc->Zmin = 0x0; 1182 hc->Zlen = 64; 1183 hc->DTMFbase = 0x0; 1184 } 1185 hc->max_trans = poll << 1; 1186 if (hc->max_trans > hc->Zlen) 1187 hc->max_trans = hc->Zlen; 1188 1189 /* Speech Design PLX bridge */ 1190 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) { 1191 if (debug & DEBUG_HFCMULTI_PLXSD) 1192 printk(KERN_DEBUG "%s: initializing PLXSD card %d\n", 1193 __func__, hc->id + 1); 1194 spin_lock_irqsave(&plx_lock, plx_flags); 1195 plx_acc_32 = hc->plx_membase + PLX_GPIOC; 1196 writel(PLX_GPIOC_INIT, plx_acc_32); 1197 pv = readl(plx_acc_32); 1198 /* The first and the last cards are terminating the PCM bus */ 1199 pv |= PLX_TERM_ON; /* hc is currently the last */ 1200 /* Disconnect the PCM */ 1201 pv |= PLX_SLAVE_EN_N; 1202 pv &= ~PLX_MASTER_EN; 1203 pv &= ~PLX_SYNC_O_EN; 1204 /* Put the DSP in Reset */ 1205 pv &= ~PLX_DSP_RES_N; 1206 writel(pv, plx_acc_32); 1207 spin_unlock_irqrestore(&plx_lock, plx_flags); 1208 if (debug & DEBUG_HFCMULTI_INIT) 1209 printk(KERN_DEBUG "%s: slave/term: PLX_GPIO=%x\n", 1210 __func__, pv); 1211 /* 1212 * If we are the 3rd PLXSD card or higher, we must turn 1213 * termination of last PLXSD card off. 1214 */ 1215 spin_lock_irqsave(&HFClock, hfc_flags); 1216 plx_count = 0; 1217 plx_last_hc = NULL; 1218 list_for_each_entry_safe(pos, next, &HFClist, list) { 1219 if (test_bit(HFC_CHIP_PLXSD, &pos->chip)) { 1220 plx_count++; 1221 if (pos != hc) 1222 plx_last_hc = pos; 1223 } 1224 } 1225 if (plx_count >= 3) { 1226 if (debug & DEBUG_HFCMULTI_PLXSD) 1227 printk(KERN_DEBUG "%s: card %d is between, so " 1228 "we disable termination\n", 1229 __func__, plx_last_hc->id + 1); 1230 spin_lock_irqsave(&plx_lock, plx_flags); 1231 plx_acc_32 = plx_last_hc->plx_membase + PLX_GPIOC; 1232 pv = readl(plx_acc_32); 1233 pv &= ~PLX_TERM_ON; 1234 writel(pv, plx_acc_32); 1235 spin_unlock_irqrestore(&plx_lock, plx_flags); 1236 if (debug & DEBUG_HFCMULTI_INIT) 1237 printk(KERN_DEBUG 1238 "%s: term off: PLX_GPIO=%x\n", 1239 __func__, pv); 1240 } 1241 spin_unlock_irqrestore(&HFClock, hfc_flags); 1242 hc->hw.r_pcm_md0 = V_F0_LEN; /* shift clock for DSP */ 1243 } 1244 1245 if (test_bit(HFC_CHIP_EMBSD, &hc->chip)) 1246 hc->hw.r_pcm_md0 = V_F0_LEN; /* shift clock for DSP */ 1247 1248 /* we only want the real Z2 read-pointer for revision > 0 */ 1249 if (!test_bit(HFC_CHIP_REVISION0, &hc->chip)) 1250 hc->hw.r_ram_sz |= V_FZ_MD; 1251 1252 /* select pcm mode */ 1253 if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip)) { 1254 if (debug & DEBUG_HFCMULTI_INIT) 1255 printk(KERN_DEBUG "%s: setting PCM into slave mode\n", 1256 __func__); 1257 } else 1258 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip) && !plxsd_master) { 1259 if (debug & DEBUG_HFCMULTI_INIT) 1260 printk(KERN_DEBUG "%s: setting PCM into master mode\n", 1261 __func__); 1262 hc->hw.r_pcm_md0 |= V_PCM_MD; 1263 } else { 1264 if (debug & DEBUG_HFCMULTI_INIT) 1265 printk(KERN_DEBUG "%s: performing PCM auto detect\n", 1266 __func__); 1267 } 1268 1269 /* soft reset */ 1270 HFC_outb(hc, R_CTRL, hc->hw.r_ctrl); 1271 if (hc->ctype == HFC_TYPE_XHFC) 1272 HFC_outb(hc, 0x0C /* R_FIFO_THRES */, 1273 0x11 /* 16 Bytes TX/RX */); 1274 else 1275 HFC_outb(hc, R_RAM_SZ, hc->hw.r_ram_sz); 1276 HFC_outb(hc, R_FIFO_MD, 0); 1277 if (hc->ctype == HFC_TYPE_XHFC) 1278 hc->hw.r_cirm = V_SRES | V_HFCRES | V_PCMRES | V_STRES; 1279 else 1280 hc->hw.r_cirm = V_SRES | V_HFCRES | V_PCMRES | V_STRES 1281 | V_RLD_EPR; 1282 HFC_outb(hc, R_CIRM, hc->hw.r_cirm); 1283 udelay(100); 1284 hc->hw.r_cirm = 0; 1285 HFC_outb(hc, R_CIRM, hc->hw.r_cirm); 1286 udelay(100); 1287 if (hc->ctype != HFC_TYPE_XHFC) 1288 HFC_outb(hc, R_RAM_SZ, hc->hw.r_ram_sz); 1289 1290 /* Speech Design PLX bridge pcm and sync mode */ 1291 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) { 1292 spin_lock_irqsave(&plx_lock, plx_flags); 1293 plx_acc_32 = hc->plx_membase + PLX_GPIOC; 1294 pv = readl(plx_acc_32); 1295 /* Connect PCM */ 1296 if (hc->hw.r_pcm_md0 & V_PCM_MD) { 1297 pv |= PLX_MASTER_EN | PLX_SLAVE_EN_N; 1298 pv |= PLX_SYNC_O_EN; 1299 if (debug & DEBUG_HFCMULTI_INIT) 1300 printk(KERN_DEBUG "%s: master: PLX_GPIO=%x\n", 1301 __func__, pv); 1302 } else { 1303 pv &= ~(PLX_MASTER_EN | PLX_SLAVE_EN_N); 1304 pv &= ~PLX_SYNC_O_EN; 1305 if (debug & DEBUG_HFCMULTI_INIT) 1306 printk(KERN_DEBUG "%s: slave: PLX_GPIO=%x\n", 1307 __func__, pv); 1308 } 1309 writel(pv, plx_acc_32); 1310 spin_unlock_irqrestore(&plx_lock, plx_flags); 1311 } 1312 1313 /* PCM setup */ 1314 HFC_outb(hc, R_PCM_MD0, hc->hw.r_pcm_md0 | 0x90); 1315 if (hc->slots == 32) 1316 HFC_outb(hc, R_PCM_MD1, 0x00); 1317 if (hc->slots == 64) 1318 HFC_outb(hc, R_PCM_MD1, 0x10); 1319 if (hc->slots == 128) 1320 HFC_outb(hc, R_PCM_MD1, 0x20); 1321 HFC_outb(hc, R_PCM_MD0, hc->hw.r_pcm_md0 | 0xa0); 1322 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) 1323 HFC_outb(hc, R_PCM_MD2, V_SYNC_SRC); /* sync via SYNC_I / O */ 1324 else if (test_bit(HFC_CHIP_EMBSD, &hc->chip)) 1325 HFC_outb(hc, R_PCM_MD2, 0x10); /* V_C2O_EN */ 1326 else 1327 HFC_outb(hc, R_PCM_MD2, 0x00); /* sync from interface */ 1328 HFC_outb(hc, R_PCM_MD0, hc->hw.r_pcm_md0 | 0x00); 1329 for (i = 0; i < 256; i++) { 1330 HFC_outb_nodebug(hc, R_SLOT, i); 1331 HFC_outb_nodebug(hc, A_SL_CFG, 0); 1332 if (hc->ctype != HFC_TYPE_XHFC) 1333 HFC_outb_nodebug(hc, A_CONF, 0); 1334 hc->slot_owner[i] = -1; 1335 } 1336 1337 /* set clock speed */ 1338 if (test_bit(HFC_CHIP_CLOCK2, &hc->chip)) { 1339 if (debug & DEBUG_HFCMULTI_INIT) 1340 printk(KERN_DEBUG 1341 "%s: setting double clock\n", __func__); 1342 HFC_outb(hc, R_BRG_PCM_CFG, V_PCM_CLK); 1343 } 1344 1345 if (test_bit(HFC_CHIP_EMBSD, &hc->chip)) 1346 HFC_outb(hc, 0x02 /* R_CLK_CFG */, 0x40 /* V_CLKO_OFF */); 1347 1348 /* B410P GPIO */ 1349 if (test_bit(HFC_CHIP_B410P, &hc->chip)) { 1350 printk(KERN_NOTICE "Setting GPIOs\n"); 1351 HFC_outb(hc, R_GPIO_SEL, 0x30); 1352 HFC_outb(hc, R_GPIO_EN1, 0x3); 1353 udelay(1000); 1354 printk(KERN_NOTICE "calling vpm_init\n"); 1355 vpm_init(hc); 1356 } 1357 1358 /* check if R_F0_CNT counts (8 kHz frame count) */ 1359 val = HFC_inb(hc, R_F0_CNTL); 1360 val += HFC_inb(hc, R_F0_CNTH) << 8; 1361 if (debug & DEBUG_HFCMULTI_INIT) 1362 printk(KERN_DEBUG 1363 "HFC_multi F0_CNT %ld after reset\n", val); 1364 spin_unlock_irqrestore(&hc->lock, flags); 1365 set_current_state(TASK_UNINTERRUPTIBLE); 1366 schedule_timeout((HZ/100)?:1); /* Timeout minimum 10ms */ 1367 spin_lock_irqsave(&hc->lock, flags); 1368 val2 = HFC_inb(hc, R_F0_CNTL); 1369 val2 += HFC_inb(hc, R_F0_CNTH) << 8; 1370 if (debug & DEBUG_HFCMULTI_INIT) 1371 printk(KERN_DEBUG 1372 "HFC_multi F0_CNT %ld after 10 ms (1st try)\n", 1373 val2); 1374 if (val2 >= val+8) { /* 1 ms */ 1375 /* it counts, so we keep the pcm mode */ 1376 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip)) 1377 printk(KERN_INFO "controller is PCM bus MASTER\n"); 1378 else 1379 if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip)) 1380 printk(KERN_INFO "controller is PCM bus SLAVE\n"); 1381 else { 1382 test_and_set_bit(HFC_CHIP_PCM_SLAVE, &hc->chip); 1383 printk(KERN_INFO "controller is PCM bus SLAVE " 1384 "(auto detected)\n"); 1385 } 1386 } else { 1387 /* does not count */ 1388 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip)) { 1389 controller_fail: 1390 printk(KERN_ERR "HFC_multi ERROR, getting no 125us " 1391 "pulse. Seems that controller fails.\n"); 1392 err = -EIO; 1393 goto out; 1394 } 1395 if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip)) { 1396 printk(KERN_INFO "controller is PCM bus SLAVE " 1397 "(ignoring missing PCM clock)\n"); 1398 } else { 1399 /* only one pcm master */ 1400 if (test_bit(HFC_CHIP_PLXSD, &hc->chip) 1401 && plxsd_master) { 1402 printk(KERN_ERR "HFC_multi ERROR, no clock " 1403 "on another Speech Design card found. " 1404 "Please be sure to connect PCM cable.\n"); 1405 err = -EIO; 1406 goto out; 1407 } 1408 /* retry with master clock */ 1409 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) { 1410 spin_lock_irqsave(&plx_lock, plx_flags); 1411 plx_acc_32 = hc->plx_membase + PLX_GPIOC; 1412 pv = readl(plx_acc_32); 1413 pv |= PLX_MASTER_EN | PLX_SLAVE_EN_N; 1414 pv |= PLX_SYNC_O_EN; 1415 writel(pv, plx_acc_32); 1416 spin_unlock_irqrestore(&plx_lock, plx_flags); 1417 if (debug & DEBUG_HFCMULTI_INIT) 1418 printk(KERN_DEBUG "%s: master: " 1419 "PLX_GPIO=%x\n", __func__, pv); 1420 } 1421 hc->hw.r_pcm_md0 |= V_PCM_MD; 1422 HFC_outb(hc, R_PCM_MD0, hc->hw.r_pcm_md0 | 0x00); 1423 spin_unlock_irqrestore(&hc->lock, flags); 1424 set_current_state(TASK_UNINTERRUPTIBLE); 1425 schedule_timeout((HZ/100)?:1); /* Timeout min. 10ms */ 1426 spin_lock_irqsave(&hc->lock, flags); 1427 val2 = HFC_inb(hc, R_F0_CNTL); 1428 val2 += HFC_inb(hc, R_F0_CNTH) << 8; 1429 if (debug & DEBUG_HFCMULTI_INIT) 1430 printk(KERN_DEBUG "HFC_multi F0_CNT %ld after " 1431 "10 ms (2nd try)\n", val2); 1432 if (val2 >= val+8) { /* 1 ms */ 1433 test_and_set_bit(HFC_CHIP_PCM_MASTER, 1434 &hc->chip); 1435 printk(KERN_INFO "controller is PCM bus MASTER " 1436 "(auto detected)\n"); 1437 } else 1438 goto controller_fail; 1439 } 1440 } 1441 1442 /* Release the DSP Reset */ 1443 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) { 1444 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip)) 1445 plxsd_master = 1; 1446 spin_lock_irqsave(&plx_lock, plx_flags); 1447 plx_acc_32 = hc->plx_membase + PLX_GPIOC; 1448 pv = readl(plx_acc_32); 1449 pv |= PLX_DSP_RES_N; 1450 writel(pv, plx_acc_32); 1451 spin_unlock_irqrestore(&plx_lock, plx_flags); 1452 if (debug & DEBUG_HFCMULTI_INIT) 1453 printk(KERN_DEBUG "%s: reset off: PLX_GPIO=%x\n", 1454 __func__, pv); 1455 } 1456 1457 /* pcm id */ 1458 if (hc->pcm) 1459 printk(KERN_INFO "controller has given PCM BUS ID %d\n", 1460 hc->pcm); 1461 else { 1462 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip) 1463 || test_bit(HFC_CHIP_PLXSD, &hc->chip)) { 1464 PCM_cnt++; /* SD has proprietary bridging */ 1465 } 1466 hc->pcm = PCM_cnt; 1467 printk(KERN_INFO "controller has PCM BUS ID %d " 1468 "(auto selected)\n", hc->pcm); 1469 } 1470 1471 /* set up timer */ 1472 HFC_outb(hc, R_TI_WD, poll_timer); 1473 hc->hw.r_irqmsk_misc |= V_TI_IRQMSK; 1474 1475 /* set E1 state machine IRQ */ 1476 if (hc->ctype == HFC_TYPE_E1) 1477 hc->hw.r_irqmsk_misc |= V_STA_IRQMSK; 1478 1479 /* set DTMF detection */ 1480 if (test_bit(HFC_CHIP_DTMF, &hc->chip)) { 1481 if (debug & DEBUG_HFCMULTI_INIT) 1482 printk(KERN_DEBUG "%s: enabling DTMF detection " 1483 "for all B-channel\n", __func__); 1484 hc->hw.r_dtmf = V_DTMF_EN | V_DTMF_STOP; 1485 if (test_bit(HFC_CHIP_ULAW, &hc->chip)) 1486 hc->hw.r_dtmf |= V_ULAW_SEL; 1487 HFC_outb(hc, R_DTMF_N, 102 - 1); 1488 hc->hw.r_irqmsk_misc |= V_DTMF_IRQMSK; 1489 } 1490 1491 /* conference engine */ 1492 if (test_bit(HFC_CHIP_ULAW, &hc->chip)) 1493 r_conf_en = V_CONF_EN | V_ULAW; 1494 else 1495 r_conf_en = V_CONF_EN; 1496 if (hc->ctype != HFC_TYPE_XHFC) 1497 HFC_outb(hc, R_CONF_EN, r_conf_en); 1498 1499 /* setting leds */ 1500 switch (hc->leds) { 1501 case 1: /* HFC-E1 OEM */ 1502 if (test_bit(HFC_CHIP_WATCHDOG, &hc->chip)) 1503 HFC_outb(hc, R_GPIO_SEL, 0x32); 1504 else 1505 HFC_outb(hc, R_GPIO_SEL, 0x30); 1506 1507 HFC_outb(hc, R_GPIO_EN1, 0x0f); 1508 HFC_outb(hc, R_GPIO_OUT1, 0x00); 1509 1510 HFC_outb(hc, R_GPIO_EN0, V_GPIO_EN2 | V_GPIO_EN3); 1511 break; 1512 1513 case 2: /* HFC-4S OEM */ 1514 case 3: 1515 HFC_outb(hc, R_GPIO_SEL, 0xf0); 1516 HFC_outb(hc, R_GPIO_EN1, 0xff); 1517 HFC_outb(hc, R_GPIO_OUT1, 0x00); 1518 break; 1519 } 1520 1521 if (test_bit(HFC_CHIP_EMBSD, &hc->chip)) { 1522 hc->hw.r_st_sync = 0x10; /* V_AUTO_SYNCI */ 1523 HFC_outb(hc, R_ST_SYNC, hc->hw.r_st_sync); 1524 } 1525 1526 /* set master clock */ 1527 if (hc->masterclk >= 0) { 1528 if (debug & DEBUG_HFCMULTI_INIT) 1529 printk(KERN_DEBUG "%s: setting ST master clock " 1530 "to port %d (0..%d)\n", 1531 __func__, hc->masterclk, hc->ports-1); 1532 hc->hw.r_st_sync |= (hc->masterclk | V_AUTO_SYNC); 1533 HFC_outb(hc, R_ST_SYNC, hc->hw.r_st_sync); 1534 } 1535 1536 1537 1538 /* setting misc irq */ 1539 HFC_outb(hc, R_IRQMSK_MISC, hc->hw.r_irqmsk_misc); 1540 if (debug & DEBUG_HFCMULTI_INIT) 1541 printk(KERN_DEBUG "r_irqmsk_misc.2: 0x%x\n", 1542 hc->hw.r_irqmsk_misc); 1543 1544 /* RAM access test */ 1545 HFC_outb(hc, R_RAM_ADDR0, 0); 1546 HFC_outb(hc, R_RAM_ADDR1, 0); 1547 HFC_outb(hc, R_RAM_ADDR2, 0); 1548 for (i = 0; i < 256; i++) { 1549 HFC_outb_nodebug(hc, R_RAM_ADDR0, i); 1550 HFC_outb_nodebug(hc, R_RAM_DATA, ((i*3)&0xff)); 1551 } 1552 for (i = 0; i < 256; i++) { 1553 HFC_outb_nodebug(hc, R_RAM_ADDR0, i); 1554 HFC_inb_nodebug(hc, R_RAM_DATA); 1555 rval = HFC_inb_nodebug(hc, R_INT_DATA); 1556 if (rval != ((i * 3) & 0xff)) { 1557 printk(KERN_DEBUG 1558 "addr:%x val:%x should:%x\n", i, rval, 1559 (i * 3) & 0xff); 1560 err++; 1561 } 1562 } 1563 if (err) { 1564 printk(KERN_DEBUG "aborting - %d RAM access errors\n", err); 1565 err = -EIO; 1566 goto out; 1567 } 1568 1569 if (debug & DEBUG_HFCMULTI_INIT) 1570 printk(KERN_DEBUG "%s: done\n", __func__); 1571 out: 1572 spin_unlock_irqrestore(&hc->lock, flags); 1573 return err; 1574 } 1575 1576 1577 /* 1578 * control the watchdog 1579 */ 1580 static void 1581 hfcmulti_watchdog(struct hfc_multi *hc) 1582 { 1583 hc->wdcount++; 1584 1585 if (hc->wdcount > 10) { 1586 hc->wdcount = 0; 1587 hc->wdbyte = hc->wdbyte == V_GPIO_OUT2 ? 1588 V_GPIO_OUT3 : V_GPIO_OUT2; 1589 1590 /* printk("Sending Watchdog Kill %x\n",hc->wdbyte); */ 1591 HFC_outb(hc, R_GPIO_EN0, V_GPIO_EN2 | V_GPIO_EN3); 1592 HFC_outb(hc, R_GPIO_OUT0, hc->wdbyte); 1593 } 1594 } 1595 1596 1597 1598 /* 1599 * output leds 1600 */ 1601 static void 1602 hfcmulti_leds(struct hfc_multi *hc) 1603 { 1604 unsigned long lled; 1605 unsigned long leddw; 1606 int i, state, active, leds; 1607 struct dchannel *dch; 1608 int led[4]; 1609 1610 hc->ledcount += poll; 1611 if (hc->ledcount > 4096) { 1612 hc->ledcount -= 4096; 1613 hc->ledstate = 0xAFFEAFFE; 1614 } 1615 1616 switch (hc->leds) { 1617 case 1: /* HFC-E1 OEM */ 1618 /* 2 red blinking: NT mode deactivate 1619 * 2 red steady: TE mode deactivate 1620 * left green: L1 active 1621 * left red: frame sync, but no L1 1622 * right green: L2 active 1623 */ 1624 if (hc->chan[hc->dslot].sync != 2) { /* no frame sync */ 1625 if (hc->chan[hc->dslot].dch->dev.D.protocol 1626 != ISDN_P_NT_E1) { 1627 led[0] = 1; 1628 led[1] = 1; 1629 } else if (hc->ledcount>>11) { 1630 led[0] = 1; 1631 led[1] = 1; 1632 } else { 1633 led[0] = 0; 1634 led[1] = 0; 1635 } 1636 led[2] = 0; 1637 led[3] = 0; 1638 } else { /* with frame sync */ 1639 /* TODO make it work */ 1640 led[0] = 0; 1641 led[1] = 0; 1642 led[2] = 0; 1643 led[3] = 1; 1644 } 1645 leds = (led[0] | (led[1]<<2) | (led[2]<<1) | (led[3]<<3))^0xF; 1646 /* leds are inverted */ 1647 if (leds != (int)hc->ledstate) { 1648 HFC_outb_nodebug(hc, R_GPIO_OUT1, leds); 1649 hc->ledstate = leds; 1650 } 1651 break; 1652 1653 case 2: /* HFC-4S OEM */ 1654 /* red blinking = PH_DEACTIVATE NT Mode 1655 * red steady = PH_DEACTIVATE TE Mode 1656 * green steady = PH_ACTIVATE 1657 */ 1658 for (i = 0; i < 4; i++) { 1659 state = 0; 1660 active = -1; 1661 dch = hc->chan[(i << 2) | 2].dch; 1662 if (dch) { 1663 state = dch->state; 1664 if (dch->dev.D.protocol == ISDN_P_NT_S0) 1665 active = 3; 1666 else 1667 active = 7; 1668 } 1669 if (state) { 1670 if (state == active) { 1671 led[i] = 1; /* led green */ 1672 } else 1673 if (dch->dev.D.protocol == ISDN_P_TE_S0) 1674 /* TE mode: led red */ 1675 led[i] = 2; 1676 else 1677 if (hc->ledcount>>11) 1678 /* led red */ 1679 led[i] = 2; 1680 else 1681 /* led off */ 1682 led[i] = 0; 1683 } else 1684 led[i] = 0; /* led off */ 1685 } 1686 if (test_bit(HFC_CHIP_B410P, &hc->chip)) { 1687 leds = 0; 1688 for (i = 0; i < 4; i++) { 1689 if (led[i] == 1) { 1690 /*green*/ 1691 leds |= (0x2 << (i * 2)); 1692 } else if (led[i] == 2) { 1693 /*red*/ 1694 leds |= (0x1 << (i * 2)); 1695 } 1696 } 1697 if (leds != (int)hc->ledstate) { 1698 vpm_out(hc, 0, 0x1a8 + 3, leds); 1699 hc->ledstate = leds; 1700 } 1701 } else { 1702 leds = ((led[3] > 0) << 0) | ((led[1] > 0) << 1) | 1703 ((led[0] > 0) << 2) | ((led[2] > 0) << 3) | 1704 ((led[3] & 1) << 4) | ((led[1] & 1) << 5) | 1705 ((led[0] & 1) << 6) | ((led[2] & 1) << 7); 1706 if (leds != (int)hc->ledstate) { 1707 HFC_outb_nodebug(hc, R_GPIO_EN1, leds & 0x0F); 1708 HFC_outb_nodebug(hc, R_GPIO_OUT1, leds >> 4); 1709 hc->ledstate = leds; 1710 } 1711 } 1712 break; 1713 1714 case 3: /* HFC 1S/2S Beronet */ 1715 /* red blinking = PH_DEACTIVATE NT Mode 1716 * red steady = PH_DEACTIVATE TE Mode 1717 * green steady = PH_ACTIVATE 1718 */ 1719 for (i = 0; i < 2; i++) { 1720 state = 0; 1721 active = -1; 1722 dch = hc->chan[(i << 2) | 2].dch; 1723 if (dch) { 1724 state = dch->state; 1725 if (dch->dev.D.protocol == ISDN_P_NT_S0) 1726 active = 3; 1727 else 1728 active = 7; 1729 } 1730 if (state) { 1731 if (state == active) { 1732 led[i] = 1; /* led green */ 1733 } else 1734 if (dch->dev.D.protocol == ISDN_P_TE_S0) 1735 /* TE mode: led red */ 1736 led[i] = 2; 1737 else 1738 if (hc->ledcount >> 11) 1739 /* led red */ 1740 led[i] = 2; 1741 else 1742 /* led off */ 1743 led[i] = 0; 1744 } else 1745 led[i] = 0; /* led off */ 1746 } 1747 1748 1749 leds = (led[0] > 0) | ((led[1] > 0)<<1) | ((led[0]&1)<<2) 1750 | ((led[1]&1)<<3); 1751 if (leds != (int)hc->ledstate) { 1752 HFC_outb_nodebug(hc, R_GPIO_EN1, 1753 ((led[0] > 0) << 2) | ((led[1] > 0) << 3)); 1754 HFC_outb_nodebug(hc, R_GPIO_OUT1, 1755 ((led[0] & 1) << 2) | ((led[1] & 1) << 3)); 1756 hc->ledstate = leds; 1757 } 1758 break; 1759 case 8: /* HFC 8S+ Beronet */ 1760 lled = 0; 1761 1762 for (i = 0; i < 8; i++) { 1763 state = 0; 1764 active = -1; 1765 dch = hc->chan[(i << 2) | 2].dch; 1766 if (dch) { 1767 state = dch->state; 1768 if (dch->dev.D.protocol == ISDN_P_NT_S0) 1769 active = 3; 1770 else 1771 active = 7; 1772 } 1773 if (state) { 1774 if (state == active) { 1775 lled |= 0 << i; 1776 } else 1777 if (hc->ledcount >> 11) 1778 lled |= 0 << i; 1779 else 1780 lled |= 1 << i; 1781 } else 1782 lled |= 1 << i; 1783 } 1784 leddw = lled << 24 | lled << 16 | lled << 8 | lled; 1785 if (leddw != hc->ledstate) { 1786 /* HFC_outb(hc, R_BRG_PCM_CFG, 1); 1787 HFC_outb(c, R_BRG_PCM_CFG, (0x0 << 6) | 0x3); */ 1788 /* was _io before */ 1789 HFC_outb_nodebug(hc, R_BRG_PCM_CFG, 1 | V_PCM_CLK); 1790 outw(0x4000, hc->pci_iobase + 4); 1791 outl(leddw, hc->pci_iobase); 1792 HFC_outb_nodebug(hc, R_BRG_PCM_CFG, V_PCM_CLK); 1793 hc->ledstate = leddw; 1794 } 1795 break; 1796 } 1797 } 1798 /* 1799 * read dtmf coefficients 1800 */ 1801 1802 static void 1803 hfcmulti_dtmf(struct hfc_multi *hc) 1804 { 1805 s32 *coeff; 1806 u_int mantissa; 1807 int co, ch; 1808 struct bchannel *bch = NULL; 1809 u8 exponent; 1810 int dtmf = 0; 1811 int addr; 1812 u16 w_float; 1813 struct sk_buff *skb; 1814 struct mISDNhead *hh; 1815 1816 if (debug & DEBUG_HFCMULTI_DTMF) 1817 printk(KERN_DEBUG "%s: dtmf detection irq\n", __func__); 1818 for (ch = 0; ch <= 31; ch++) { 1819 /* only process enabled B-channels */ 1820 bch = hc->chan[ch].bch; 1821 if (!bch) 1822 continue; 1823 if (!hc->created[hc->chan[ch].port]) 1824 continue; 1825 if (!test_bit(FLG_TRANSPARENT, &bch->Flags)) 1826 continue; 1827 if (debug & DEBUG_HFCMULTI_DTMF) 1828 printk(KERN_DEBUG "%s: dtmf channel %d:", 1829 __func__, ch); 1830 coeff = &(hc->chan[ch].coeff[hc->chan[ch].coeff_count * 16]); 1831 dtmf = 1; 1832 for (co = 0; co < 8; co++) { 1833 /* read W(n-1) coefficient */ 1834 addr = hc->DTMFbase + ((co<<7) | (ch<<2)); 1835 HFC_outb_nodebug(hc, R_RAM_ADDR0, addr); 1836 HFC_outb_nodebug(hc, R_RAM_ADDR1, addr>>8); 1837 HFC_outb_nodebug(hc, R_RAM_ADDR2, (addr>>16) 1838 | V_ADDR_INC); 1839 w_float = HFC_inb_nodebug(hc, R_RAM_DATA); 1840 w_float |= (HFC_inb_nodebug(hc, R_RAM_DATA) << 8); 1841 if (debug & DEBUG_HFCMULTI_DTMF) 1842 printk(" %04x", w_float); 1843 1844 /* decode float (see chip doc) */ 1845 mantissa = w_float & 0x0fff; 1846 if (w_float & 0x8000) 1847 mantissa |= 0xfffff000; 1848 exponent = (w_float>>12) & 0x7; 1849 if (exponent) { 1850 mantissa ^= 0x1000; 1851 mantissa <<= (exponent-1); 1852 } 1853 1854 /* store coefficient */ 1855 coeff[co<<1] = mantissa; 1856 1857 /* read W(n) coefficient */ 1858 w_float = HFC_inb_nodebug(hc, R_RAM_DATA); 1859 w_float |= (HFC_inb_nodebug(hc, R_RAM_DATA) << 8); 1860 if (debug & DEBUG_HFCMULTI_DTMF) 1861 printk(" %04x", w_float); 1862 1863 /* decode float (see chip doc) */ 1864 mantissa = w_float & 0x0fff; 1865 if (w_float & 0x8000) 1866 mantissa |= 0xfffff000; 1867 exponent = (w_float>>12) & 0x7; 1868 if (exponent) { 1869 mantissa ^= 0x1000; 1870 mantissa <<= (exponent-1); 1871 } 1872 1873 /* store coefficient */ 1874 coeff[(co<<1)|1] = mantissa; 1875 } 1876 if (debug & DEBUG_HFCMULTI_DTMF) 1877 printk(" DTMF ready %08x %08x %08x %08x " 1878 "%08x %08x %08x %08x\n", 1879 coeff[0], coeff[1], coeff[2], coeff[3], 1880 coeff[4], coeff[5], coeff[6], coeff[7]); 1881 hc->chan[ch].coeff_count++; 1882 if (hc->chan[ch].coeff_count == 8) { 1883 hc->chan[ch].coeff_count = 0; 1884 skb = mI_alloc_skb(512, GFP_ATOMIC); 1885 if (!skb) { 1886 printk(KERN_DEBUG "%s: No memory for skb\n", 1887 __func__); 1888 continue; 1889 } 1890 hh = mISDN_HEAD_P(skb); 1891 hh->prim = PH_CONTROL_IND; 1892 hh->id = DTMF_HFC_COEF; 1893 memcpy(skb_put(skb, 512), hc->chan[ch].coeff, 512); 1894 recv_Bchannel_skb(bch, skb); 1895 } 1896 } 1897 1898 /* restart DTMF processing */ 1899 hc->dtmf = dtmf; 1900 if (dtmf) 1901 HFC_outb_nodebug(hc, R_DTMF, hc->hw.r_dtmf | V_RST_DTMF); 1902 } 1903 1904 1905 /* 1906 * fill fifo as much as possible 1907 */ 1908 1909 static void 1910 hfcmulti_tx(struct hfc_multi *hc, int ch) 1911 { 1912 int i, ii, temp, len = 0; 1913 int Zspace, z1, z2; /* must be int for calculation */ 1914 int Fspace, f1, f2; 1915 u_char *d; 1916 int *txpending, slot_tx; 1917 struct bchannel *bch; 1918 struct dchannel *dch; 1919 struct sk_buff **sp = NULL; 1920 int *idxp; 1921 1922 bch = hc->chan[ch].bch; 1923 dch = hc->chan[ch].dch; 1924 if ((!dch) && (!bch)) 1925 return; 1926 1927 txpending = &hc->chan[ch].txpending; 1928 slot_tx = hc->chan[ch].slot_tx; 1929 if (dch) { 1930 if (!test_bit(FLG_ACTIVE, &dch->Flags)) 1931 return; 1932 sp = &dch->tx_skb; 1933 idxp = &dch->tx_idx; 1934 } else { 1935 if (!test_bit(FLG_ACTIVE, &bch->Flags)) 1936 return; 1937 sp = &bch->tx_skb; 1938 idxp = &bch->tx_idx; 1939 } 1940 if (*sp) 1941 len = (*sp)->len; 1942 1943 if ((!len) && *txpending != 1) 1944 return; /* no data */ 1945 1946 if (test_bit(HFC_CHIP_B410P, &hc->chip) && 1947 (hc->chan[ch].protocol == ISDN_P_B_RAW) && 1948 (hc->chan[ch].slot_rx < 0) && 1949 (hc->chan[ch].slot_tx < 0)) 1950 HFC_outb_nodebug(hc, R_FIFO, 0x20 | (ch << 1)); 1951 else 1952 HFC_outb_nodebug(hc, R_FIFO, ch << 1); 1953 HFC_wait_nodebug(hc); 1954 1955 if (*txpending == 2) { 1956 /* reset fifo */ 1957 HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_RES_F); 1958 HFC_wait_nodebug(hc); 1959 HFC_outb(hc, A_SUBCH_CFG, 0); 1960 *txpending = 1; 1961 } 1962 next_frame: 1963 if (dch || test_bit(FLG_HDLC, &bch->Flags)) { 1964 f1 = HFC_inb_nodebug(hc, A_F1); 1965 f2 = HFC_inb_nodebug(hc, A_F2); 1966 while (f2 != (temp = HFC_inb_nodebug(hc, A_F2))) { 1967 if (debug & DEBUG_HFCMULTI_FIFO) 1968 printk(KERN_DEBUG 1969 "%s(card %d): reread f2 because %d!=%d\n", 1970 __func__, hc->id + 1, temp, f2); 1971 f2 = temp; /* repeat until F2 is equal */ 1972 } 1973 Fspace = f2 - f1 - 1; 1974 if (Fspace < 0) 1975 Fspace += hc->Flen; 1976 /* 1977 * Old FIFO handling doesn't give us the current Z2 read 1978 * pointer, so we cannot send the next frame before the fifo 1979 * is empty. It makes no difference except for a slightly 1980 * lower performance. 1981 */ 1982 if (test_bit(HFC_CHIP_REVISION0, &hc->chip)) { 1983 if (f1 != f2) 1984 Fspace = 0; 1985 else 1986 Fspace = 1; 1987 } 1988 /* one frame only for ST D-channels, to allow resending */ 1989 if (hc->ctype != HFC_TYPE_E1 && dch) { 1990 if (f1 != f2) 1991 Fspace = 0; 1992 } 1993 /* F-counter full condition */ 1994 if (Fspace == 0) 1995 return; 1996 } 1997 z1 = HFC_inw_nodebug(hc, A_Z1) - hc->Zmin; 1998 z2 = HFC_inw_nodebug(hc, A_Z2) - hc->Zmin; 1999 while (z2 != (temp = (HFC_inw_nodebug(hc, A_Z2) - hc->Zmin))) { 2000 if (debug & DEBUG_HFCMULTI_FIFO) 2001 printk(KERN_DEBUG "%s(card %d): reread z2 because " 2002 "%d!=%d\n", __func__, hc->id + 1, temp, z2); 2003 z2 = temp; /* repeat unti Z2 is equal */ 2004 } 2005 hc->chan[ch].Zfill = z1 - z2; 2006 if (hc->chan[ch].Zfill < 0) 2007 hc->chan[ch].Zfill += hc->Zlen; 2008 Zspace = z2 - z1; 2009 if (Zspace <= 0) 2010 Zspace += hc->Zlen; 2011 Zspace -= 4; /* keep not too full, so pointers will not overrun */ 2012 /* fill transparent data only to maxinum transparent load (minus 4) */ 2013 if (bch && test_bit(FLG_TRANSPARENT, &bch->Flags)) 2014 Zspace = Zspace - hc->Zlen + hc->max_trans; 2015 if (Zspace <= 0) /* no space of 4 bytes */ 2016 return; 2017 2018 /* if no data */ 2019 if (!len) { 2020 if (z1 == z2) { /* empty */ 2021 /* if done with FIFO audio data during PCM connection */ 2022 if (bch && (!test_bit(FLG_HDLC, &bch->Flags)) && 2023 *txpending && slot_tx >= 0) { 2024 if (debug & DEBUG_HFCMULTI_MODE) 2025 printk(KERN_DEBUG 2026 "%s: reconnecting PCM due to no " 2027 "more FIFO data: channel %d " 2028 "slot_tx %d\n", 2029 __func__, ch, slot_tx); 2030 /* connect slot */ 2031 if (hc->ctype == HFC_TYPE_XHFC) 2032 HFC_outb(hc, A_CON_HDLC, 0xc0 2033 | 0x07 << 2 | V_HDLC_TRP | V_IFF); 2034 /* Enable FIFO, no interrupt */ 2035 else 2036 HFC_outb(hc, A_CON_HDLC, 0xc0 | 0x00 | 2037 V_HDLC_TRP | V_IFF); 2038 HFC_outb_nodebug(hc, R_FIFO, ch<<1 | 1); 2039 HFC_wait_nodebug(hc); 2040 if (hc->ctype == HFC_TYPE_XHFC) 2041 HFC_outb(hc, A_CON_HDLC, 0xc0 2042 | 0x07 << 2 | V_HDLC_TRP | V_IFF); 2043 /* Enable FIFO, no interrupt */ 2044 else 2045 HFC_outb(hc, A_CON_HDLC, 0xc0 | 0x00 | 2046 V_HDLC_TRP | V_IFF); 2047 HFC_outb_nodebug(hc, R_FIFO, ch<<1); 2048 HFC_wait_nodebug(hc); 2049 } 2050 *txpending = 0; 2051 } 2052 return; /* no data */ 2053 } 2054 2055 /* "fill fifo if empty" feature */ 2056 if (bch && test_bit(FLG_FILLEMPTY, &bch->Flags) 2057 && !test_bit(FLG_HDLC, &bch->Flags) && z2 == z1) { 2058 if (debug & DEBUG_HFCMULTI_FILL) 2059 printk(KERN_DEBUG "%s: buffer empty, so we have " 2060 "underrun\n", __func__); 2061 /* fill buffer, to prevent future underrun */ 2062 hc->write_fifo(hc, hc->silence_data, poll >> 1); 2063 Zspace -= (poll >> 1); 2064 } 2065 2066 /* if audio data and connected slot */ 2067 if (bch && (!test_bit(FLG_HDLC, &bch->Flags)) && (!*txpending) 2068 && slot_tx >= 0) { 2069 if (debug & DEBUG_HFCMULTI_MODE) 2070 printk(KERN_DEBUG "%s: disconnecting PCM due to " 2071 "FIFO data: channel %d slot_tx %d\n", 2072 __func__, ch, slot_tx); 2073 /* disconnect slot */ 2074 if (hc->ctype == HFC_TYPE_XHFC) 2075 HFC_outb(hc, A_CON_HDLC, 0x80 2076 | 0x07 << 2 | V_HDLC_TRP | V_IFF); 2077 /* Enable FIFO, no interrupt */ 2078 else 2079 HFC_outb(hc, A_CON_HDLC, 0x80 | 0x00 | 2080 V_HDLC_TRP | V_IFF); 2081 HFC_outb_nodebug(hc, R_FIFO, ch<<1 | 1); 2082 HFC_wait_nodebug(hc); 2083 if (hc->ctype == HFC_TYPE_XHFC) 2084 HFC_outb(hc, A_CON_HDLC, 0x80 2085 | 0x07 << 2 | V_HDLC_TRP | V_IFF); 2086 /* Enable FIFO, no interrupt */ 2087 else 2088 HFC_outb(hc, A_CON_HDLC, 0x80 | 0x00 | 2089 V_HDLC_TRP | V_IFF); 2090 HFC_outb_nodebug(hc, R_FIFO, ch<<1); 2091 HFC_wait_nodebug(hc); 2092 } 2093 *txpending = 1; 2094 2095 /* show activity */ 2096 hc->activity[hc->chan[ch].port] = 1; 2097 2098 /* fill fifo to what we have left */ 2099 ii = len; 2100 if (dch || test_bit(FLG_HDLC, &bch->Flags)) 2101 temp = 1; 2102 else 2103 temp = 0; 2104 i = *idxp; 2105 d = (*sp)->data + i; 2106 if (ii - i > Zspace) 2107 ii = Zspace + i; 2108 if (debug & DEBUG_HFCMULTI_FIFO) 2109 printk(KERN_DEBUG "%s(card %d): fifo(%d) has %d bytes space " 2110 "left (z1=%04x, z2=%04x) sending %d of %d bytes %s\n", 2111 __func__, hc->id + 1, ch, Zspace, z1, z2, ii-i, len-i, 2112 temp ? "HDLC" : "TRANS"); 2113 2114 /* Have to prep the audio data */ 2115 hc->write_fifo(hc, d, ii - i); 2116 hc->chan[ch].Zfill += ii - i; 2117 *idxp = ii; 2118 2119 /* if not all data has been written */ 2120 if (ii != len) { 2121 /* NOTE: fifo is started by the calling function */ 2122 return; 2123 } 2124 2125 /* if all data has been written, terminate frame */ 2126 if (dch || test_bit(FLG_HDLC, &bch->Flags)) { 2127 /* increment f-counter */ 2128 HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_INC_F); 2129 HFC_wait_nodebug(hc); 2130 } 2131 2132 /* send confirm, since get_net_bframe will not do it with trans */ 2133 if (bch && test_bit(FLG_TRANSPARENT, &bch->Flags)) 2134 confirm_Bsend(bch); 2135 2136 /* check for next frame */ 2137 dev_kfree_skb(*sp); 2138 if (bch && get_next_bframe(bch)) { /* hdlc is confirmed here */ 2139 len = (*sp)->len; 2140 goto next_frame; 2141 } 2142 if (dch && get_next_dframe(dch)) { 2143 len = (*sp)->len; 2144 goto next_frame; 2145 } 2146 2147 /* 2148 * now we have no more data, so in case of transparent, 2149 * we set the last byte in fifo to 'silence' in case we will get 2150 * no more data at all. this prevents sending an undefined value. 2151 */ 2152 if (bch && test_bit(FLG_TRANSPARENT, &bch->Flags)) 2153 HFC_outb_nodebug(hc, A_FIFO_DATA0_NOINC, hc->silence); 2154 } 2155 2156 2157 /* NOTE: only called if E1 card is in active state */ 2158 static void 2159 hfcmulti_rx(struct hfc_multi *hc, int ch) 2160 { 2161 int temp; 2162 int Zsize, z1, z2 = 0; /* = 0, to make GCC happy */ 2163 int f1 = 0, f2 = 0; /* = 0, to make GCC happy */ 2164 int again = 0; 2165 struct bchannel *bch; 2166 struct dchannel *dch; 2167 struct sk_buff *skb, **sp = NULL; 2168 int maxlen; 2169 2170 bch = hc->chan[ch].bch; 2171 dch = hc->chan[ch].dch; 2172 if ((!dch) && (!bch)) 2173 return; 2174 if (dch) { 2175 if (!test_bit(FLG_ACTIVE, &dch->Flags)) 2176 return; 2177 sp = &dch->rx_skb; 2178 maxlen = dch->maxlen; 2179 } else { 2180 if (!test_bit(FLG_ACTIVE, &bch->Flags)) 2181 return; 2182 sp = &bch->rx_skb; 2183 maxlen = bch->maxlen; 2184 } 2185 next_frame: 2186 /* on first AND before getting next valid frame, R_FIFO must be written 2187 to. */ 2188 if (test_bit(HFC_CHIP_B410P, &hc->chip) && 2189 (hc->chan[ch].protocol == ISDN_P_B_RAW) && 2190 (hc->chan[ch].slot_rx < 0) && 2191 (hc->chan[ch].slot_tx < 0)) 2192 HFC_outb_nodebug(hc, R_FIFO, 0x20 | (ch<<1) | 1); 2193 else 2194 HFC_outb_nodebug(hc, R_FIFO, (ch<<1)|1); 2195 HFC_wait_nodebug(hc); 2196 2197 /* ignore if rx is off BUT change fifo (above) to start pending TX */ 2198 if (hc->chan[ch].rx_off) 2199 return; 2200 2201 if (dch || test_bit(FLG_HDLC, &bch->Flags)) { 2202 f1 = HFC_inb_nodebug(hc, A_F1); 2203 while (f1 != (temp = HFC_inb_nodebug(hc, A_F1))) { 2204 if (debug & DEBUG_HFCMULTI_FIFO) 2205 printk(KERN_DEBUG 2206 "%s(card %d): reread f1 because %d!=%d\n", 2207 __func__, hc->id + 1, temp, f1); 2208 f1 = temp; /* repeat until F1 is equal */ 2209 } 2210 f2 = HFC_inb_nodebug(hc, A_F2); 2211 } 2212 z1 = HFC_inw_nodebug(hc, A_Z1) - hc->Zmin; 2213 while (z1 != (temp = (HFC_inw_nodebug(hc, A_Z1) - hc->Zmin))) { 2214 if (debug & DEBUG_HFCMULTI_FIFO) 2215 printk(KERN_DEBUG "%s(card %d): reread z2 because " 2216 "%d!=%d\n", __func__, hc->id + 1, temp, z2); 2217 z1 = temp; /* repeat until Z1 is equal */ 2218 } 2219 z2 = HFC_inw_nodebug(hc, A_Z2) - hc->Zmin; 2220 Zsize = z1 - z2; 2221 if ((dch || test_bit(FLG_HDLC, &bch->Flags)) && f1 != f2) 2222 /* complete hdlc frame */ 2223 Zsize++; 2224 if (Zsize < 0) 2225 Zsize += hc->Zlen; 2226 /* if buffer is empty */ 2227 if (Zsize <= 0) 2228 return; 2229 2230 if (*sp == NULL) { 2231 *sp = mI_alloc_skb(maxlen + 3, GFP_ATOMIC); 2232 if (*sp == NULL) { 2233 printk(KERN_DEBUG "%s: No mem for rx_skb\n", 2234 __func__); 2235 return; 2236 } 2237 } 2238 /* show activity */ 2239 hc->activity[hc->chan[ch].port] = 1; 2240 2241 /* empty fifo with what we have */ 2242 if (dch || test_bit(FLG_HDLC, &bch->Flags)) { 2243 if (debug & DEBUG_HFCMULTI_FIFO) 2244 printk(KERN_DEBUG "%s(card %d): fifo(%d) reading %d " 2245 "bytes (z1=%04x, z2=%04x) HDLC %s (f1=%d, f2=%d) " 2246 "got=%d (again %d)\n", __func__, hc->id + 1, ch, 2247 Zsize, z1, z2, (f1 == f2) ? "fragment" : "COMPLETE", 2248 f1, f2, Zsize + (*sp)->len, again); 2249 /* HDLC */ 2250 if ((Zsize + (*sp)->len) > (maxlen + 3)) { 2251 if (debug & DEBUG_HFCMULTI_FIFO) 2252 printk(KERN_DEBUG 2253 "%s(card %d): hdlc-frame too large.\n", 2254 __func__, hc->id + 1); 2255 skb_trim(*sp, 0); 2256 HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_RES_F); 2257 HFC_wait_nodebug(hc); 2258 return; 2259 } 2260 2261 hc->read_fifo(hc, skb_put(*sp, Zsize), Zsize); 2262 2263 if (f1 != f2) { 2264 /* increment Z2,F2-counter */ 2265 HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_INC_F); 2266 HFC_wait_nodebug(hc); 2267 /* check size */ 2268 if ((*sp)->len < 4) { 2269 if (debug & DEBUG_HFCMULTI_FIFO) 2270 printk(KERN_DEBUG 2271 "%s(card %d): Frame below minimum " 2272 "size\n", __func__, hc->id + 1); 2273 skb_trim(*sp, 0); 2274 goto next_frame; 2275 } 2276 /* there is at least one complete frame, check crc */ 2277 if ((*sp)->data[(*sp)->len - 1]) { 2278 if (debug & DEBUG_HFCMULTI_CRC) 2279 printk(KERN_DEBUG 2280 "%s: CRC-error\n", __func__); 2281 skb_trim(*sp, 0); 2282 goto next_frame; 2283 } 2284 skb_trim(*sp, (*sp)->len - 3); 2285 if ((*sp)->len < MISDN_COPY_SIZE) { 2286 skb = *sp; 2287 *sp = mI_alloc_skb(skb->len, GFP_ATOMIC); 2288 if (*sp) { 2289 memcpy(skb_put(*sp, skb->len), 2290 skb->data, skb->len); 2291 skb_trim(skb, 0); 2292 } else { 2293 printk(KERN_DEBUG "%s: No mem\n", 2294 __func__); 2295 *sp = skb; 2296 skb = NULL; 2297 } 2298 } else { 2299 skb = NULL; 2300 } 2301 if (debug & DEBUG_HFCMULTI_FIFO) { 2302 printk(KERN_DEBUG "%s(card %d):", 2303 __func__, hc->id + 1); 2304 temp = 0; 2305 while (temp < (*sp)->len) 2306 printk(" %02x", (*sp)->data[temp++]); 2307 printk("\n"); 2308 } 2309 if (dch) 2310 recv_Dchannel(dch); 2311 else 2312 recv_Bchannel(bch, MISDN_ID_ANY); 2313 *sp = skb; 2314 again++; 2315 goto next_frame; 2316 } 2317 /* there is an incomplete frame */ 2318 } else { 2319 /* transparent */ 2320 if (Zsize > skb_tailroom(*sp)) 2321 Zsize = skb_tailroom(*sp); 2322 hc->read_fifo(hc, skb_put(*sp, Zsize), Zsize); 2323 if (((*sp)->len) < MISDN_COPY_SIZE) { 2324 skb = *sp; 2325 *sp = mI_alloc_skb(skb->len, GFP_ATOMIC); 2326 if (*sp) { 2327 memcpy(skb_put(*sp, skb->len), 2328 skb->data, skb->len); 2329 skb_trim(skb, 0); 2330 } else { 2331 printk(KERN_DEBUG "%s: No mem\n", __func__); 2332 *sp = skb; 2333 skb = NULL; 2334 } 2335 } else { 2336 skb = NULL; 2337 } 2338 if (debug & DEBUG_HFCMULTI_FIFO) 2339 printk(KERN_DEBUG 2340 "%s(card %d): fifo(%d) reading %d bytes " 2341 "(z1=%04x, z2=%04x) TRANS\n", 2342 __func__, hc->id + 1, ch, Zsize, z1, z2); 2343 /* only bch is transparent */ 2344 recv_Bchannel(bch, hc->chan[ch].Zfill); 2345 *sp = skb; 2346 } 2347 } 2348 2349 2350 /* 2351 * Interrupt handler 2352 */ 2353 static void 2354 signal_state_up(struct dchannel *dch, int info, char *msg) 2355 { 2356 struct sk_buff *skb; 2357 int id, data = info; 2358 2359 if (debug & DEBUG_HFCMULTI_STATE) 2360 printk(KERN_DEBUG "%s: %s\n", __func__, msg); 2361 2362 id = TEI_SAPI | (GROUP_TEI << 8); /* manager address */ 2363 2364 skb = _alloc_mISDN_skb(MPH_INFORMATION_IND, id, sizeof(data), &data, 2365 GFP_ATOMIC); 2366 if (!skb) 2367 return; 2368 recv_Dchannel_skb(dch, skb); 2369 } 2370 2371 static inline void 2372 handle_timer_irq(struct hfc_multi *hc) 2373 { 2374 int ch, temp; 2375 struct dchannel *dch; 2376 u_long flags; 2377 2378 /* process queued resync jobs */ 2379 if (hc->e1_resync) { 2380 /* lock, so e1_resync gets not changed */ 2381 spin_lock_irqsave(&HFClock, flags); 2382 if (hc->e1_resync & 1) { 2383 if (debug & DEBUG_HFCMULTI_PLXSD) 2384 printk(KERN_DEBUG "Enable SYNC_I\n"); 2385 HFC_outb(hc, R_SYNC_CTRL, V_EXT_CLK_SYNC); 2386 /* disable JATT, if RX_SYNC is set */ 2387 if (test_bit(HFC_CHIP_RX_SYNC, &hc->chip)) 2388 HFC_outb(hc, R_SYNC_OUT, V_SYNC_E1_RX); 2389 } 2390 if (hc->e1_resync & 2) { 2391 if (debug & DEBUG_HFCMULTI_PLXSD) 2392 printk(KERN_DEBUG "Enable jatt PLL\n"); 2393 HFC_outb(hc, R_SYNC_CTRL, V_SYNC_OFFS); 2394 } 2395 if (hc->e1_resync & 4) { 2396 if (debug & DEBUG_HFCMULTI_PLXSD) 2397 printk(KERN_DEBUG 2398 "Enable QUARTZ for HFC-E1\n"); 2399 /* set jatt to quartz */ 2400 HFC_outb(hc, R_SYNC_CTRL, V_EXT_CLK_SYNC 2401 | V_JATT_OFF); 2402 /* switch to JATT, in case it is not already */ 2403 HFC_outb(hc, R_SYNC_OUT, 0); 2404 } 2405 hc->e1_resync = 0; 2406 spin_unlock_irqrestore(&HFClock, flags); 2407 } 2408 2409 if (hc->ctype != HFC_TYPE_E1 || hc->e1_state == 1) 2410 for (ch = 0; ch <= 31; ch++) { 2411 if (hc->created[hc->chan[ch].port]) { 2412 hfcmulti_tx(hc, ch); 2413 /* fifo is started when switching to rx-fifo */ 2414 hfcmulti_rx(hc, ch); 2415 if (hc->chan[ch].dch && 2416 hc->chan[ch].nt_timer > -1) { 2417 dch = hc->chan[ch].dch; 2418 if (!(--hc->chan[ch].nt_timer)) { 2419 schedule_event(dch, 2420 FLG_PHCHANGE); 2421 if (debug & 2422 DEBUG_HFCMULTI_STATE) 2423 printk(KERN_DEBUG 2424 "%s: nt_timer at " 2425 "state %x\n", 2426 __func__, 2427 dch->state); 2428 } 2429 } 2430 } 2431 } 2432 if (hc->ctype == HFC_TYPE_E1 && hc->created[0]) { 2433 dch = hc->chan[hc->dslot].dch; 2434 if (test_bit(HFC_CFG_REPORT_LOS, &hc->chan[hc->dslot].cfg)) { 2435 /* LOS */ 2436 temp = HFC_inb_nodebug(hc, R_SYNC_STA) & V_SIG_LOS; 2437 if (!temp && hc->chan[hc->dslot].los) 2438 signal_state_up(dch, L1_SIGNAL_LOS_ON, 2439 "LOS detected"); 2440 if (temp && !hc->chan[hc->dslot].los) 2441 signal_state_up(dch, L1_SIGNAL_LOS_OFF, 2442 "LOS gone"); 2443 hc->chan[hc->dslot].los = temp; 2444 } 2445 if (test_bit(HFC_CFG_REPORT_AIS, &hc->chan[hc->dslot].cfg)) { 2446 /* AIS */ 2447 temp = HFC_inb_nodebug(hc, R_SYNC_STA) & V_AIS; 2448 if (!temp && hc->chan[hc->dslot].ais) 2449 signal_state_up(dch, L1_SIGNAL_AIS_ON, 2450 "AIS detected"); 2451 if (temp && !hc->chan[hc->dslot].ais) 2452 signal_state_up(dch, L1_SIGNAL_AIS_OFF, 2453 "AIS gone"); 2454 hc->chan[hc->dslot].ais = temp; 2455 } 2456 if (test_bit(HFC_CFG_REPORT_SLIP, &hc->chan[hc->dslot].cfg)) { 2457 /* SLIP */ 2458 temp = HFC_inb_nodebug(hc, R_SLIP) & V_FOSLIP_RX; 2459 if (!temp && hc->chan[hc->dslot].slip_rx) 2460 signal_state_up(dch, L1_SIGNAL_SLIP_RX, 2461 " bit SLIP detected RX"); 2462 hc->chan[hc->dslot].slip_rx = temp; 2463 temp = HFC_inb_nodebug(hc, R_SLIP) & V_FOSLIP_TX; 2464 if (!temp && hc->chan[hc->dslot].slip_tx) 2465 signal_state_up(dch, L1_SIGNAL_SLIP_TX, 2466 " bit SLIP detected TX"); 2467 hc->chan[hc->dslot].slip_tx = temp; 2468 } 2469 if (test_bit(HFC_CFG_REPORT_RDI, &hc->chan[hc->dslot].cfg)) { 2470 /* RDI */ 2471 temp = HFC_inb_nodebug(hc, R_RX_SL0_0) & V_A; 2472 if (!temp && hc->chan[hc->dslot].rdi) 2473 signal_state_up(dch, L1_SIGNAL_RDI_ON, 2474 "RDI detected"); 2475 if (temp && !hc->chan[hc->dslot].rdi) 2476 signal_state_up(dch, L1_SIGNAL_RDI_OFF, 2477 "RDI gone"); 2478 hc->chan[hc->dslot].rdi = temp; 2479 } 2480 temp = HFC_inb_nodebug(hc, R_JATT_DIR); 2481 switch (hc->chan[hc->dslot].sync) { 2482 case 0: 2483 if ((temp & 0x60) == 0x60) { 2484 if (debug & DEBUG_HFCMULTI_SYNC) 2485 printk(KERN_DEBUG 2486 "%s: (id=%d) E1 now " 2487 "in clock sync\n", 2488 __func__, hc->id); 2489 HFC_outb(hc, R_RX_OFF, 2490 hc->chan[hc->dslot].jitter | V_RX_INIT); 2491 HFC_outb(hc, R_TX_OFF, 2492 hc->chan[hc->dslot].jitter | V_RX_INIT); 2493 hc->chan[hc->dslot].sync = 1; 2494 goto check_framesync; 2495 } 2496 break; 2497 case 1: 2498 if ((temp & 0x60) != 0x60) { 2499 if (debug & DEBUG_HFCMULTI_SYNC) 2500 printk(KERN_DEBUG 2501 "%s: (id=%d) E1 " 2502 "lost clock sync\n", 2503 __func__, hc->id); 2504 hc->chan[hc->dslot].sync = 0; 2505 break; 2506 } 2507 check_framesync: 2508 temp = HFC_inb_nodebug(hc, R_SYNC_STA); 2509 if (temp == 0x27) { 2510 if (debug & DEBUG_HFCMULTI_SYNC) 2511 printk(KERN_DEBUG 2512 "%s: (id=%d) E1 " 2513 "now in frame sync\n", 2514 __func__, hc->id); 2515 hc->chan[hc->dslot].sync = 2; 2516 } 2517 break; 2518 case 2: 2519 if ((temp & 0x60) != 0x60) { 2520 if (debug & DEBUG_HFCMULTI_SYNC) 2521 printk(KERN_DEBUG 2522 "%s: (id=%d) E1 lost " 2523 "clock & frame sync\n", 2524 __func__, hc->id); 2525 hc->chan[hc->dslot].sync = 0; 2526 break; 2527 } 2528 temp = HFC_inb_nodebug(hc, R_SYNC_STA); 2529 if (temp != 0x27) { 2530 if (debug & DEBUG_HFCMULTI_SYNC) 2531 printk(KERN_DEBUG 2532 "%s: (id=%d) E1 " 2533 "lost frame sync\n", 2534 __func__, hc->id); 2535 hc->chan[hc->dslot].sync = 1; 2536 } 2537 break; 2538 } 2539 } 2540 2541 if (test_bit(HFC_CHIP_WATCHDOG, &hc->chip)) 2542 hfcmulti_watchdog(hc); 2543 2544 if (hc->leds) 2545 hfcmulti_leds(hc); 2546 } 2547 2548 static void 2549 ph_state_irq(struct hfc_multi *hc, u_char r_irq_statech) 2550 { 2551 struct dchannel *dch; 2552 int ch; 2553 int active; 2554 u_char st_status, temp; 2555 2556 /* state machine */ 2557 for (ch = 0; ch <= 31; ch++) { 2558 if (hc->chan[ch].dch) { 2559 dch = hc->chan[ch].dch; 2560 if (r_irq_statech & 1) { 2561 HFC_outb_nodebug(hc, R_ST_SEL, 2562 hc->chan[ch].port); 2563 /* undocumented: delay after R_ST_SEL */ 2564 udelay(1); 2565 /* undocumented: status changes during read */ 2566 st_status = HFC_inb_nodebug(hc, A_ST_RD_STATE); 2567 while (st_status != (temp = 2568 HFC_inb_nodebug(hc, A_ST_RD_STATE))) { 2569 if (debug & DEBUG_HFCMULTI_STATE) 2570 printk(KERN_DEBUG "%s: reread " 2571 "STATE because %d!=%d\n", 2572 __func__, temp, 2573 st_status); 2574 st_status = temp; /* repeat */ 2575 } 2576 2577 /* Speech Design TE-sync indication */ 2578 if (test_bit(HFC_CHIP_PLXSD, &hc->chip) && 2579 dch->dev.D.protocol == ISDN_P_TE_S0) { 2580 if (st_status & V_FR_SYNC_ST) 2581 hc->syncronized |= 2582 (1 << hc->chan[ch].port); 2583 else 2584 hc->syncronized &= 2585 ~(1 << hc->chan[ch].port); 2586 } 2587 dch->state = st_status & 0x0f; 2588 if (dch->dev.D.protocol == ISDN_P_NT_S0) 2589 active = 3; 2590 else 2591 active = 7; 2592 if (dch->state == active) { 2593 HFC_outb_nodebug(hc, R_FIFO, 2594 (ch << 1) | 1); 2595 HFC_wait_nodebug(hc); 2596 HFC_outb_nodebug(hc, 2597 R_INC_RES_FIFO, V_RES_F); 2598 HFC_wait_nodebug(hc); 2599 dch->tx_idx = 0; 2600 } 2601 schedule_event(dch, FLG_PHCHANGE); 2602 if (debug & DEBUG_HFCMULTI_STATE) 2603 printk(KERN_DEBUG 2604 "%s: S/T newstate %x port %d\n", 2605 __func__, dch->state, 2606 hc->chan[ch].port); 2607 } 2608 r_irq_statech >>= 1; 2609 } 2610 } 2611 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) 2612 plxsd_checksync(hc, 0); 2613 } 2614 2615 static void 2616 fifo_irq(struct hfc_multi *hc, int block) 2617 { 2618 int ch, j; 2619 struct dchannel *dch; 2620 struct bchannel *bch; 2621 u_char r_irq_fifo_bl; 2622 2623 r_irq_fifo_bl = HFC_inb_nodebug(hc, R_IRQ_FIFO_BL0 + block); 2624 j = 0; 2625 while (j < 8) { 2626 ch = (block << 2) + (j >> 1); 2627 dch = hc->chan[ch].dch; 2628 bch = hc->chan[ch].bch; 2629 if (((!dch) && (!bch)) || (!hc->created[hc->chan[ch].port])) { 2630 j += 2; 2631 continue; 2632 } 2633 if (dch && (r_irq_fifo_bl & (1 << j)) && 2634 test_bit(FLG_ACTIVE, &dch->Flags)) { 2635 hfcmulti_tx(hc, ch); 2636 /* start fifo */ 2637 HFC_outb_nodebug(hc, R_FIFO, 0); 2638 HFC_wait_nodebug(hc); 2639 } 2640 if (bch && (r_irq_fifo_bl & (1 << j)) && 2641 test_bit(FLG_ACTIVE, &bch->Flags)) { 2642 hfcmulti_tx(hc, ch); 2643 /* start fifo */ 2644 HFC_outb_nodebug(hc, R_FIFO, 0); 2645 HFC_wait_nodebug(hc); 2646 } 2647 j++; 2648 if (dch && (r_irq_fifo_bl & (1 << j)) && 2649 test_bit(FLG_ACTIVE, &dch->Flags)) { 2650 hfcmulti_rx(hc, ch); 2651 } 2652 if (bch && (r_irq_fifo_bl & (1 << j)) && 2653 test_bit(FLG_ACTIVE, &bch->Flags)) { 2654 hfcmulti_rx(hc, ch); 2655 } 2656 j++; 2657 } 2658 } 2659 2660 #ifdef IRQ_DEBUG 2661 int irqsem; 2662 #endif 2663 static irqreturn_t 2664 hfcmulti_interrupt(int intno, void *dev_id) 2665 { 2666 #ifdef IRQCOUNT_DEBUG 2667 static int iq1 = 0, iq2 = 0, iq3 = 0, iq4 = 0, 2668 iq5 = 0, iq6 = 0, iqcnt = 0; 2669 #endif 2670 struct hfc_multi *hc = dev_id; 2671 struct dchannel *dch; 2672 u_char r_irq_statech, status, r_irq_misc, r_irq_oview; 2673 int i; 2674 void __iomem *plx_acc; 2675 u_short wval; 2676 u_char e1_syncsta, temp; 2677 u_long flags; 2678 2679 if (!hc) { 2680 printk(KERN_ERR "HFC-multi: Spurious interrupt!\n"); 2681 return IRQ_NONE; 2682 } 2683 2684 spin_lock(&hc->lock); 2685 2686 #ifdef IRQ_DEBUG 2687 if (irqsem) 2688 printk(KERN_ERR "irq for card %d during irq from " 2689 "card %d, this is no bug.\n", hc->id + 1, irqsem); 2690 irqsem = hc->id + 1; 2691 #endif 2692 #ifdef CONFIG_MISDN_HFCMULTI_8xx 2693 if (hc->immap->im_cpm.cp_pbdat & hc->pb_irqmsk) 2694 goto irq_notforus; 2695 #endif 2696 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) { 2697 spin_lock_irqsave(&plx_lock, flags); 2698 plx_acc = hc->plx_membase + PLX_INTCSR; 2699 wval = readw(plx_acc); 2700 spin_unlock_irqrestore(&plx_lock, flags); 2701 if (!(wval & PLX_INTCSR_LINTI1_STATUS)) 2702 goto irq_notforus; 2703 } 2704 2705 status = HFC_inb_nodebug(hc, R_STATUS); 2706 r_irq_statech = HFC_inb_nodebug(hc, R_IRQ_STATECH); 2707 #ifdef IRQCOUNT_DEBUG 2708 if (r_irq_statech) 2709 iq1++; 2710 if (status & V_DTMF_STA) 2711 iq2++; 2712 if (status & V_LOST_STA) 2713 iq3++; 2714 if (status & V_EXT_IRQSTA) 2715 iq4++; 2716 if (status & V_MISC_IRQSTA) 2717 iq5++; 2718 if (status & V_FR_IRQSTA) 2719 iq6++; 2720 if (iqcnt++ > 5000) { 2721 printk(KERN_ERR "iq1:%x iq2:%x iq3:%x iq4:%x iq5:%x iq6:%x\n", 2722 iq1, iq2, iq3, iq4, iq5, iq6); 2723 iqcnt = 0; 2724 } 2725 #endif 2726 2727 if (!r_irq_statech && 2728 !(status & (V_DTMF_STA | V_LOST_STA | V_EXT_IRQSTA | 2729 V_MISC_IRQSTA | V_FR_IRQSTA))) { 2730 /* irq is not for us */ 2731 goto irq_notforus; 2732 } 2733 hc->irqcnt++; 2734 if (r_irq_statech) { 2735 if (hc->ctype != HFC_TYPE_E1) 2736 ph_state_irq(hc, r_irq_statech); 2737 } 2738 if (status & V_EXT_IRQSTA) 2739 ; /* external IRQ */ 2740 if (status & V_LOST_STA) { 2741 /* LOST IRQ */ 2742 HFC_outb(hc, R_INC_RES_FIFO, V_RES_LOST); /* clear irq! */ 2743 } 2744 if (status & V_MISC_IRQSTA) { 2745 /* misc IRQ */ 2746 r_irq_misc = HFC_inb_nodebug(hc, R_IRQ_MISC); 2747 r_irq_misc &= hc->hw.r_irqmsk_misc; /* ignore disabled irqs */ 2748 if (r_irq_misc & V_STA_IRQ) { 2749 if (hc->ctype == HFC_TYPE_E1) { 2750 /* state machine */ 2751 dch = hc->chan[hc->dslot].dch; 2752 e1_syncsta = HFC_inb_nodebug(hc, R_SYNC_STA); 2753 if (test_bit(HFC_CHIP_PLXSD, &hc->chip) 2754 && hc->e1_getclock) { 2755 if (e1_syncsta & V_FR_SYNC_E1) 2756 hc->syncronized = 1; 2757 else 2758 hc->syncronized = 0; 2759 } 2760 /* undocumented: status changes during read */ 2761 dch->state = HFC_inb_nodebug(hc, R_E1_RD_STA); 2762 while (dch->state != (temp = 2763 HFC_inb_nodebug(hc, R_E1_RD_STA))) { 2764 if (debug & DEBUG_HFCMULTI_STATE) 2765 printk(KERN_DEBUG "%s: reread " 2766 "STATE because %d!=%d\n", 2767 __func__, temp, 2768 dch->state); 2769 dch->state = temp; /* repeat */ 2770 } 2771 dch->state = HFC_inb_nodebug(hc, R_E1_RD_STA) 2772 & 0x7; 2773 schedule_event(dch, FLG_PHCHANGE); 2774 if (debug & DEBUG_HFCMULTI_STATE) 2775 printk(KERN_DEBUG 2776 "%s: E1 (id=%d) newstate %x\n", 2777 __func__, hc->id, dch->state); 2778 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) 2779 plxsd_checksync(hc, 0); 2780 } 2781 } 2782 if (r_irq_misc & V_TI_IRQ) { 2783 if (hc->iclock_on) 2784 mISDN_clock_update(hc->iclock, poll, NULL); 2785 handle_timer_irq(hc); 2786 } 2787 2788 if (r_irq_misc & V_DTMF_IRQ) 2789 hfcmulti_dtmf(hc); 2790 2791 if (r_irq_misc & V_IRQ_PROC) { 2792 static int irq_proc_cnt; 2793 if (!irq_proc_cnt++) 2794 printk(KERN_DEBUG "%s: got V_IRQ_PROC -" 2795 " this should not happen\n", __func__); 2796 } 2797 2798 } 2799 if (status & V_FR_IRQSTA) { 2800 /* FIFO IRQ */ 2801 r_irq_oview = HFC_inb_nodebug(hc, R_IRQ_OVIEW); 2802 for (i = 0; i < 8; i++) { 2803 if (r_irq_oview & (1 << i)) 2804 fifo_irq(hc, i); 2805 } 2806 } 2807 2808 #ifdef IRQ_DEBUG 2809 irqsem = 0; 2810 #endif 2811 spin_unlock(&hc->lock); 2812 return IRQ_HANDLED; 2813 2814 irq_notforus: 2815 #ifdef IRQ_DEBUG 2816 irqsem = 0; 2817 #endif 2818 spin_unlock(&hc->lock); 2819 return IRQ_NONE; 2820 } 2821 2822 2823 /* 2824 * timer callback for D-chan busy resolution. Currently no function 2825 */ 2826 2827 static void 2828 hfcmulti_dbusy_timer(struct hfc_multi *hc) 2829 { 2830 } 2831 2832 2833 /* 2834 * activate/deactivate hardware for selected channels and mode 2835 * 2836 * configure B-channel with the given protocol 2837 * ch eqals to the HFC-channel (0-31) 2838 * ch is the number of channel (0-4,4-7,8-11,12-15,16-19,20-23,24-27,28-31 2839 * for S/T, 1-31 for E1) 2840 * the hdlc interrupts will be set/unset 2841 */ 2842 static int 2843 mode_hfcmulti(struct hfc_multi *hc, int ch, int protocol, int slot_tx, 2844 int bank_tx, int slot_rx, int bank_rx) 2845 { 2846 int flow_tx = 0, flow_rx = 0, routing = 0; 2847 int oslot_tx, oslot_rx; 2848 int conf; 2849 2850 if (ch < 0 || ch > 31) 2851 return -EINVAL; 2852 oslot_tx = hc->chan[ch].slot_tx; 2853 oslot_rx = hc->chan[ch].slot_rx; 2854 conf = hc->chan[ch].conf; 2855 2856 if (debug & DEBUG_HFCMULTI_MODE) 2857 printk(KERN_DEBUG 2858 "%s: card %d channel %d protocol %x slot old=%d new=%d " 2859 "bank new=%d (TX) slot old=%d new=%d bank new=%d (RX)\n", 2860 __func__, hc->id, ch, protocol, oslot_tx, slot_tx, 2861 bank_tx, oslot_rx, slot_rx, bank_rx); 2862 2863 if (oslot_tx >= 0 && slot_tx != oslot_tx) { 2864 /* remove from slot */ 2865 if (debug & DEBUG_HFCMULTI_MODE) 2866 printk(KERN_DEBUG "%s: remove from slot %d (TX)\n", 2867 __func__, oslot_tx); 2868 if (hc->slot_owner[oslot_tx<<1] == ch) { 2869 HFC_outb(hc, R_SLOT, oslot_tx << 1); 2870 HFC_outb(hc, A_SL_CFG, 0); 2871 if (hc->ctype != HFC_TYPE_XHFC) 2872 HFC_outb(hc, A_CONF, 0); 2873 hc->slot_owner[oslot_tx<<1] = -1; 2874 } else { 2875 if (debug & DEBUG_HFCMULTI_MODE) 2876 printk(KERN_DEBUG 2877 "%s: we are not owner of this tx slot " 2878 "anymore, channel %d is.\n", 2879 __func__, hc->slot_owner[oslot_tx<<1]); 2880 } 2881 } 2882 2883 if (oslot_rx >= 0 && slot_rx != oslot_rx) { 2884 /* remove from slot */ 2885 if (debug & DEBUG_HFCMULTI_MODE) 2886 printk(KERN_DEBUG 2887 "%s: remove from slot %d (RX)\n", 2888 __func__, oslot_rx); 2889 if (hc->slot_owner[(oslot_rx << 1) | 1] == ch) { 2890 HFC_outb(hc, R_SLOT, (oslot_rx << 1) | V_SL_DIR); 2891 HFC_outb(hc, A_SL_CFG, 0); 2892 hc->slot_owner[(oslot_rx << 1) | 1] = -1; 2893 } else { 2894 if (debug & DEBUG_HFCMULTI_MODE) 2895 printk(KERN_DEBUG 2896 "%s: we are not owner of this rx slot " 2897 "anymore, channel %d is.\n", 2898 __func__, 2899 hc->slot_owner[(oslot_rx << 1) | 1]); 2900 } 2901 } 2902 2903 if (slot_tx < 0) { 2904 flow_tx = 0x80; /* FIFO->ST */ 2905 /* disable pcm slot */ 2906 hc->chan[ch].slot_tx = -1; 2907 hc->chan[ch].bank_tx = 0; 2908 } else { 2909 /* set pcm slot */ 2910 if (hc->chan[ch].txpending) 2911 flow_tx = 0x80; /* FIFO->ST */ 2912 else 2913 flow_tx = 0xc0; /* PCM->ST */ 2914 /* put on slot */ 2915 routing = bank_tx ? 0xc0 : 0x80; 2916 if (conf >= 0 || bank_tx > 1) 2917 routing = 0x40; /* loop */ 2918 if (debug & DEBUG_HFCMULTI_MODE) 2919 printk(KERN_DEBUG "%s: put channel %d to slot %d bank" 2920 " %d flow %02x routing %02x conf %d (TX)\n", 2921 __func__, ch, slot_tx, bank_tx, 2922 flow_tx, routing, conf); 2923 HFC_outb(hc, R_SLOT, slot_tx << 1); 2924 HFC_outb(hc, A_SL_CFG, (ch<<1) | routing); 2925 if (hc->ctype != HFC_TYPE_XHFC) 2926 HFC_outb(hc, A_CONF, 2927 (conf < 0) ? 0 : (conf | V_CONF_SL)); 2928 hc->slot_owner[slot_tx << 1] = ch; 2929 hc->chan[ch].slot_tx = slot_tx; 2930 hc->chan[ch].bank_tx = bank_tx; 2931 } 2932 if (slot_rx < 0) { 2933 /* disable pcm slot */ 2934 flow_rx = 0x80; /* ST->FIFO */ 2935 hc->chan[ch].slot_rx = -1; 2936 hc->chan[ch].bank_rx = 0; 2937 } else { 2938 /* set pcm slot */ 2939 if (hc->chan[ch].txpending) 2940 flow_rx = 0x80; /* ST->FIFO */ 2941 else 2942 flow_rx = 0xc0; /* ST->(FIFO,PCM) */ 2943 /* put on slot */ 2944 routing = bank_rx ? 0x80 : 0xc0; /* reversed */ 2945 if (conf >= 0 || bank_rx > 1) 2946 routing = 0x40; /* loop */ 2947 if (debug & DEBUG_HFCMULTI_MODE) 2948 printk(KERN_DEBUG "%s: put channel %d to slot %d bank" 2949 " %d flow %02x routing %02x conf %d (RX)\n", 2950 __func__, ch, slot_rx, bank_rx, 2951 flow_rx, routing, conf); 2952 HFC_outb(hc, R_SLOT, (slot_rx<<1) | V_SL_DIR); 2953 HFC_outb(hc, A_SL_CFG, (ch<<1) | V_CH_DIR | routing); 2954 hc->slot_owner[(slot_rx<<1)|1] = ch; 2955 hc->chan[ch].slot_rx = slot_rx; 2956 hc->chan[ch].bank_rx = bank_rx; 2957 } 2958 2959 switch (protocol) { 2960 case (ISDN_P_NONE): 2961 /* disable TX fifo */ 2962 HFC_outb(hc, R_FIFO, ch << 1); 2963 HFC_wait(hc); 2964 HFC_outb(hc, A_CON_HDLC, flow_tx | 0x00 | V_IFF); 2965 HFC_outb(hc, A_SUBCH_CFG, 0); 2966 HFC_outb(hc, A_IRQ_MSK, 0); 2967 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F); 2968 HFC_wait(hc); 2969 /* disable RX fifo */ 2970 HFC_outb(hc, R_FIFO, (ch<<1)|1); 2971 HFC_wait(hc); 2972 HFC_outb(hc, A_CON_HDLC, flow_rx | 0x00); 2973 HFC_outb(hc, A_SUBCH_CFG, 0); 2974 HFC_outb(hc, A_IRQ_MSK, 0); 2975 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F); 2976 HFC_wait(hc); 2977 if (hc->chan[ch].bch && hc->ctype != HFC_TYPE_E1) { 2978 hc->hw.a_st_ctrl0[hc->chan[ch].port] &= 2979 ((ch & 0x3) == 0) ? ~V_B1_EN : ~V_B2_EN; 2980 HFC_outb(hc, R_ST_SEL, hc->chan[ch].port); 2981 /* undocumented: delay after R_ST_SEL */ 2982 udelay(1); 2983 HFC_outb(hc, A_ST_CTRL0, 2984 hc->hw.a_st_ctrl0[hc->chan[ch].port]); 2985 } 2986 if (hc->chan[ch].bch) { 2987 test_and_clear_bit(FLG_HDLC, &hc->chan[ch].bch->Flags); 2988 test_and_clear_bit(FLG_TRANSPARENT, 2989 &hc->chan[ch].bch->Flags); 2990 } 2991 break; 2992 case (ISDN_P_B_RAW): /* B-channel */ 2993 2994 if (test_bit(HFC_CHIP_B410P, &hc->chip) && 2995 (hc->chan[ch].slot_rx < 0) && 2996 (hc->chan[ch].slot_tx < 0)) { 2997 2998 printk(KERN_DEBUG 2999 "Setting B-channel %d to echo cancelable " 3000 "state on PCM slot %d\n", ch, 3001 ((ch / 4) * 8) + ((ch % 4) * 4) + 1); 3002 printk(KERN_DEBUG 3003 "Enabling pass through for channel\n"); 3004 vpm_out(hc, ch, ((ch / 4) * 8) + 3005 ((ch % 4) * 4) + 1, 0x01); 3006 /* rx path */ 3007 /* S/T -> PCM */ 3008 HFC_outb(hc, R_FIFO, (ch << 1)); 3009 HFC_wait(hc); 3010 HFC_outb(hc, A_CON_HDLC, 0xc0 | V_HDLC_TRP | V_IFF); 3011 HFC_outb(hc, R_SLOT, (((ch / 4) * 8) + 3012 ((ch % 4) * 4) + 1) << 1); 3013 HFC_outb(hc, A_SL_CFG, 0x80 | (ch << 1)); 3014 3015 /* PCM -> FIFO */ 3016 HFC_outb(hc, R_FIFO, 0x20 | (ch << 1) | 1); 3017 HFC_wait(hc); 3018 HFC_outb(hc, A_CON_HDLC, 0x20 | V_HDLC_TRP | V_IFF); 3019 HFC_outb(hc, A_SUBCH_CFG, 0); 3020 HFC_outb(hc, A_IRQ_MSK, 0); 3021 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F); 3022 HFC_wait(hc); 3023 HFC_outb(hc, R_SLOT, ((((ch / 4) * 8) + 3024 ((ch % 4) * 4) + 1) << 1) | 1); 3025 HFC_outb(hc, A_SL_CFG, 0x80 | 0x20 | (ch << 1) | 1); 3026 3027 /* tx path */ 3028 /* PCM -> S/T */ 3029 HFC_outb(hc, R_FIFO, (ch << 1) | 1); 3030 HFC_wait(hc); 3031 HFC_outb(hc, A_CON_HDLC, 0xc0 | V_HDLC_TRP | V_IFF); 3032 HFC_outb(hc, R_SLOT, ((((ch / 4) * 8) + 3033 ((ch % 4) * 4)) << 1) | 1); 3034 HFC_outb(hc, A_SL_CFG, 0x80 | 0x40 | (ch << 1) | 1); 3035 3036 /* FIFO -> PCM */ 3037 HFC_outb(hc, R_FIFO, 0x20 | (ch << 1)); 3038 HFC_wait(hc); 3039 HFC_outb(hc, A_CON_HDLC, 0x20 | V_HDLC_TRP | V_IFF); 3040 HFC_outb(hc, A_SUBCH_CFG, 0); 3041 HFC_outb(hc, A_IRQ_MSK, 0); 3042 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F); 3043 HFC_wait(hc); 3044 /* tx silence */ 3045 HFC_outb_nodebug(hc, A_FIFO_DATA0_NOINC, hc->silence); 3046 HFC_outb(hc, R_SLOT, (((ch / 4) * 8) + 3047 ((ch % 4) * 4)) << 1); 3048 HFC_outb(hc, A_SL_CFG, 0x80 | 0x20 | (ch << 1)); 3049 } else { 3050 /* enable TX fifo */ 3051 HFC_outb(hc, R_FIFO, ch << 1); 3052 HFC_wait(hc); 3053 if (hc->ctype == HFC_TYPE_XHFC) 3054 HFC_outb(hc, A_CON_HDLC, flow_tx | 0x07 << 2 | 3055 V_HDLC_TRP | V_IFF); 3056 /* Enable FIFO, no interrupt */ 3057 else 3058 HFC_outb(hc, A_CON_HDLC, flow_tx | 0x00 | 3059 V_HDLC_TRP | V_IFF); 3060 HFC_outb(hc, A_SUBCH_CFG, 0); 3061 HFC_outb(hc, A_IRQ_MSK, 0); 3062 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F); 3063 HFC_wait(hc); 3064 /* tx silence */ 3065 HFC_outb_nodebug(hc, A_FIFO_DATA0_NOINC, hc->silence); 3066 /* enable RX fifo */ 3067 HFC_outb(hc, R_FIFO, (ch<<1)|1); 3068 HFC_wait(hc); 3069 if (hc->ctype == HFC_TYPE_XHFC) 3070 HFC_outb(hc, A_CON_HDLC, flow_rx | 0x07 << 2 | 3071 V_HDLC_TRP); 3072 /* Enable FIFO, no interrupt*/ 3073 else 3074 HFC_outb(hc, A_CON_HDLC, flow_rx | 0x00 | 3075 V_HDLC_TRP); 3076 HFC_outb(hc, A_SUBCH_CFG, 0); 3077 HFC_outb(hc, A_IRQ_MSK, 0); 3078 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F); 3079 HFC_wait(hc); 3080 } 3081 if (hc->ctype != HFC_TYPE_E1) { 3082 hc->hw.a_st_ctrl0[hc->chan[ch].port] |= 3083 ((ch & 0x3) == 0) ? V_B1_EN : V_B2_EN; 3084 HFC_outb(hc, R_ST_SEL, hc->chan[ch].port); 3085 /* undocumented: delay after R_ST_SEL */ 3086 udelay(1); 3087 HFC_outb(hc, A_ST_CTRL0, 3088 hc->hw.a_st_ctrl0[hc->chan[ch].port]); 3089 } 3090 if (hc->chan[ch].bch) 3091 test_and_set_bit(FLG_TRANSPARENT, 3092 &hc->chan[ch].bch->Flags); 3093 break; 3094 case (ISDN_P_B_HDLC): /* B-channel */ 3095 case (ISDN_P_TE_S0): /* D-channel */ 3096 case (ISDN_P_NT_S0): 3097 case (ISDN_P_TE_E1): 3098 case (ISDN_P_NT_E1): 3099 /* enable TX fifo */ 3100 HFC_outb(hc, R_FIFO, ch<<1); 3101 HFC_wait(hc); 3102 if (hc->ctype == HFC_TYPE_E1 || hc->chan[ch].bch) { 3103 /* E1 or B-channel */ 3104 HFC_outb(hc, A_CON_HDLC, flow_tx | 0x04); 3105 HFC_outb(hc, A_SUBCH_CFG, 0); 3106 } else { 3107 /* D-Channel without HDLC fill flags */ 3108 HFC_outb(hc, A_CON_HDLC, flow_tx | 0x04 | V_IFF); 3109 HFC_outb(hc, A_SUBCH_CFG, 2); 3110 } 3111 HFC_outb(hc, A_IRQ_MSK, V_IRQ); 3112 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F); 3113 HFC_wait(hc); 3114 /* enable RX fifo */ 3115 HFC_outb(hc, R_FIFO, (ch<<1)|1); 3116 HFC_wait(hc); 3117 HFC_outb(hc, A_CON_HDLC, flow_rx | 0x04); 3118 if (hc->ctype == HFC_TYPE_E1 || hc->chan[ch].bch) 3119 HFC_outb(hc, A_SUBCH_CFG, 0); /* full 8 bits */ 3120 else 3121 HFC_outb(hc, A_SUBCH_CFG, 2); /* 2 bits dchannel */ 3122 HFC_outb(hc, A_IRQ_MSK, V_IRQ); 3123 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F); 3124 HFC_wait(hc); 3125 if (hc->chan[ch].bch) { 3126 test_and_set_bit(FLG_HDLC, &hc->chan[ch].bch->Flags); 3127 if (hc->ctype != HFC_TYPE_E1) { 3128 hc->hw.a_st_ctrl0[hc->chan[ch].port] |= 3129 ((ch&0x3) == 0) ? V_B1_EN : V_B2_EN; 3130 HFC_outb(hc, R_ST_SEL, hc->chan[ch].port); 3131 /* undocumented: delay after R_ST_SEL */ 3132 udelay(1); 3133 HFC_outb(hc, A_ST_CTRL0, 3134 hc->hw.a_st_ctrl0[hc->chan[ch].port]); 3135 } 3136 } 3137 break; 3138 default: 3139 printk(KERN_DEBUG "%s: protocol not known %x\n", 3140 __func__, protocol); 3141 hc->chan[ch].protocol = ISDN_P_NONE; 3142 return -ENOPROTOOPT; 3143 } 3144 hc->chan[ch].protocol = protocol; 3145 return 0; 3146 } 3147 3148 3149 /* 3150 * connect/disconnect PCM 3151 */ 3152 3153 static void 3154 hfcmulti_pcm(struct hfc_multi *hc, int ch, int slot_tx, int bank_tx, 3155 int slot_rx, int bank_rx) 3156 { 3157 if (slot_tx < 0 || slot_rx < 0 || bank_tx < 0 || bank_rx < 0) { 3158 /* disable PCM */ 3159 mode_hfcmulti(hc, ch, hc->chan[ch].protocol, -1, 0, -1, 0); 3160 return; 3161 } 3162 3163 /* enable pcm */ 3164 mode_hfcmulti(hc, ch, hc->chan[ch].protocol, slot_tx, bank_tx, 3165 slot_rx, bank_rx); 3166 } 3167 3168 /* 3169 * set/disable conference 3170 */ 3171 3172 static void 3173 hfcmulti_conf(struct hfc_multi *hc, int ch, int num) 3174 { 3175 if (num >= 0 && num <= 7) 3176 hc->chan[ch].conf = num; 3177 else 3178 hc->chan[ch].conf = -1; 3179 mode_hfcmulti(hc, ch, hc->chan[ch].protocol, hc->chan[ch].slot_tx, 3180 hc->chan[ch].bank_tx, hc->chan[ch].slot_rx, 3181 hc->chan[ch].bank_rx); 3182 } 3183 3184 3185 /* 3186 * set/disable sample loop 3187 */ 3188 3189 /* NOTE: this function is experimental and therefore disabled */ 3190 3191 /* 3192 * Layer 1 callback function 3193 */ 3194 static int 3195 hfcm_l1callback(struct dchannel *dch, u_int cmd) 3196 { 3197 struct hfc_multi *hc = dch->hw; 3198 u_long flags; 3199 3200 switch (cmd) { 3201 case INFO3_P8: 3202 case INFO3_P10: 3203 break; 3204 case HW_RESET_REQ: 3205 /* start activation */ 3206 spin_lock_irqsave(&hc->lock, flags); 3207 if (hc->ctype == HFC_TYPE_E1) { 3208 if (debug & DEBUG_HFCMULTI_MSG) 3209 printk(KERN_DEBUG 3210 "%s: HW_RESET_REQ no BRI\n", 3211 __func__); 3212 } else { 3213 HFC_outb(hc, R_ST_SEL, hc->chan[dch->slot].port); 3214 /* undocumented: delay after R_ST_SEL */ 3215 udelay(1); 3216 HFC_outb(hc, A_ST_WR_STATE, V_ST_LD_STA | 3); /* F3 */ 3217 udelay(6); /* wait at least 5,21us */ 3218 HFC_outb(hc, A_ST_WR_STATE, 3); 3219 HFC_outb(hc, A_ST_WR_STATE, 3 | (V_ST_ACT*3)); 3220 /* activate */ 3221 } 3222 spin_unlock_irqrestore(&hc->lock, flags); 3223 l1_event(dch->l1, HW_POWERUP_IND); 3224 break; 3225 case HW_DEACT_REQ: 3226 /* start deactivation */ 3227 spin_lock_irqsave(&hc->lock, flags); 3228 if (hc->ctype == HFC_TYPE_E1) { 3229 if (debug & DEBUG_HFCMULTI_MSG) 3230 printk(KERN_DEBUG 3231 "%s: HW_DEACT_REQ no BRI\n", 3232 __func__); 3233 } else { 3234 HFC_outb(hc, R_ST_SEL, hc->chan[dch->slot].port); 3235 /* undocumented: delay after R_ST_SEL */ 3236 udelay(1); 3237 HFC_outb(hc, A_ST_WR_STATE, V_ST_ACT*2); 3238 /* deactivate */ 3239 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) { 3240 hc->syncronized &= 3241 ~(1 << hc->chan[dch->slot].port); 3242 plxsd_checksync(hc, 0); 3243 } 3244 } 3245 skb_queue_purge(&dch->squeue); 3246 if (dch->tx_skb) { 3247 dev_kfree_skb(dch->tx_skb); 3248 dch->tx_skb = NULL; 3249 } 3250 dch->tx_idx = 0; 3251 if (dch->rx_skb) { 3252 dev_kfree_skb(dch->rx_skb); 3253 dch->rx_skb = NULL; 3254 } 3255 test_and_clear_bit(FLG_TX_BUSY, &dch->Flags); 3256 if (test_and_clear_bit(FLG_BUSY_TIMER, &dch->Flags)) 3257 del_timer(&dch->timer); 3258 spin_unlock_irqrestore(&hc->lock, flags); 3259 break; 3260 case HW_POWERUP_REQ: 3261 spin_lock_irqsave(&hc->lock, flags); 3262 if (hc->ctype == HFC_TYPE_E1) { 3263 if (debug & DEBUG_HFCMULTI_MSG) 3264 printk(KERN_DEBUG 3265 "%s: HW_POWERUP_REQ no BRI\n", 3266 __func__); 3267 } else { 3268 HFC_outb(hc, R_ST_SEL, hc->chan[dch->slot].port); 3269 /* undocumented: delay after R_ST_SEL */ 3270 udelay(1); 3271 HFC_outb(hc, A_ST_WR_STATE, 3 | 0x10); /* activate */ 3272 udelay(6); /* wait at least 5,21us */ 3273 HFC_outb(hc, A_ST_WR_STATE, 3); /* activate */ 3274 } 3275 spin_unlock_irqrestore(&hc->lock, flags); 3276 break; 3277 case PH_ACTIVATE_IND: 3278 test_and_set_bit(FLG_ACTIVE, &dch->Flags); 3279 _queue_data(&dch->dev.D, cmd, MISDN_ID_ANY, 0, NULL, 3280 GFP_ATOMIC); 3281 break; 3282 case PH_DEACTIVATE_IND: 3283 test_and_clear_bit(FLG_ACTIVE, &dch->Flags); 3284 _queue_data(&dch->dev.D, cmd, MISDN_ID_ANY, 0, NULL, 3285 GFP_ATOMIC); 3286 break; 3287 default: 3288 if (dch->debug & DEBUG_HW) 3289 printk(KERN_DEBUG "%s: unknown command %x\n", 3290 __func__, cmd); 3291 return -1; 3292 } 3293 return 0; 3294 } 3295 3296 /* 3297 * Layer2 -> Layer 1 Transfer 3298 */ 3299 3300 static int 3301 handle_dmsg(struct mISDNchannel *ch, struct sk_buff *skb) 3302 { 3303 struct mISDNdevice *dev = container_of(ch, struct mISDNdevice, D); 3304 struct dchannel *dch = container_of(dev, struct dchannel, dev); 3305 struct hfc_multi *hc = dch->hw; 3306 struct mISDNhead *hh = mISDN_HEAD_P(skb); 3307 int ret = -EINVAL; 3308 unsigned int id; 3309 u_long flags; 3310 3311 switch (hh->prim) { 3312 case PH_DATA_REQ: 3313 if (skb->len < 1) 3314 break; 3315 spin_lock_irqsave(&hc->lock, flags); 3316 ret = dchannel_senddata(dch, skb); 3317 if (ret > 0) { /* direct TX */ 3318 id = hh->id; /* skb can be freed */ 3319 hfcmulti_tx(hc, dch->slot); 3320 ret = 0; 3321 /* start fifo */ 3322 HFC_outb(hc, R_FIFO, 0); 3323 HFC_wait(hc); 3324 spin_unlock_irqrestore(&hc->lock, flags); 3325 queue_ch_frame(ch, PH_DATA_CNF, id, NULL); 3326 } else 3327 spin_unlock_irqrestore(&hc->lock, flags); 3328 return ret; 3329 case PH_ACTIVATE_REQ: 3330 if (dch->dev.D.protocol != ISDN_P_TE_S0) { 3331 spin_lock_irqsave(&hc->lock, flags); 3332 ret = 0; 3333 if (debug & DEBUG_HFCMULTI_MSG) 3334 printk(KERN_DEBUG 3335 "%s: PH_ACTIVATE port %d (0..%d)\n", 3336 __func__, hc->chan[dch->slot].port, 3337 hc->ports-1); 3338 /* start activation */ 3339 if (hc->ctype == HFC_TYPE_E1) { 3340 ph_state_change(dch); 3341 if (debug & DEBUG_HFCMULTI_STATE) 3342 printk(KERN_DEBUG 3343 "%s: E1 report state %x \n", 3344 __func__, dch->state); 3345 } else { 3346 HFC_outb(hc, R_ST_SEL, 3347 hc->chan[dch->slot].port); 3348 /* undocumented: delay after R_ST_SEL */ 3349 udelay(1); 3350 HFC_outb(hc, A_ST_WR_STATE, V_ST_LD_STA | 1); 3351 /* G1 */ 3352 udelay(6); /* wait at least 5,21us */ 3353 HFC_outb(hc, A_ST_WR_STATE, 1); 3354 HFC_outb(hc, A_ST_WR_STATE, 1 | 3355 (V_ST_ACT*3)); /* activate */ 3356 dch->state = 1; 3357 } 3358 spin_unlock_irqrestore(&hc->lock, flags); 3359 } else 3360 ret = l1_event(dch->l1, hh->prim); 3361 break; 3362 case PH_DEACTIVATE_REQ: 3363 test_and_clear_bit(FLG_L2_ACTIVATED, &dch->Flags); 3364 if (dch->dev.D.protocol != ISDN_P_TE_S0) { 3365 spin_lock_irqsave(&hc->lock, flags); 3366 if (debug & DEBUG_HFCMULTI_MSG) 3367 printk(KERN_DEBUG 3368 "%s: PH_DEACTIVATE port %d (0..%d)\n", 3369 __func__, hc->chan[dch->slot].port, 3370 hc->ports-1); 3371 /* start deactivation */ 3372 if (hc->ctype == HFC_TYPE_E1) { 3373 if (debug & DEBUG_HFCMULTI_MSG) 3374 printk(KERN_DEBUG 3375 "%s: PH_DEACTIVATE no BRI\n", 3376 __func__); 3377 } else { 3378 HFC_outb(hc, R_ST_SEL, 3379 hc->chan[dch->slot].port); 3380 /* undocumented: delay after R_ST_SEL */ 3381 udelay(1); 3382 HFC_outb(hc, A_ST_WR_STATE, V_ST_ACT * 2); 3383 /* deactivate */ 3384 dch->state = 1; 3385 } 3386 skb_queue_purge(&dch->squeue); 3387 if (dch->tx_skb) { 3388 dev_kfree_skb(dch->tx_skb); 3389 dch->tx_skb = NULL; 3390 } 3391 dch->tx_idx = 0; 3392 if (dch->rx_skb) { 3393 dev_kfree_skb(dch->rx_skb); 3394 dch->rx_skb = NULL; 3395 } 3396 test_and_clear_bit(FLG_TX_BUSY, &dch->Flags); 3397 if (test_and_clear_bit(FLG_BUSY_TIMER, &dch->Flags)) 3398 del_timer(&dch->timer); 3399 #ifdef FIXME 3400 if (test_and_clear_bit(FLG_L1_BUSY, &dch->Flags)) 3401 dchannel_sched_event(&hc->dch, D_CLEARBUSY); 3402 #endif 3403 ret = 0; 3404 spin_unlock_irqrestore(&hc->lock, flags); 3405 } else 3406 ret = l1_event(dch->l1, hh->prim); 3407 break; 3408 } 3409 if (!ret) 3410 dev_kfree_skb(skb); 3411 return ret; 3412 } 3413 3414 static void 3415 deactivate_bchannel(struct bchannel *bch) 3416 { 3417 struct hfc_multi *hc = bch->hw; 3418 u_long flags; 3419 3420 spin_lock_irqsave(&hc->lock, flags); 3421 mISDN_clear_bchannel(bch); 3422 hc->chan[bch->slot].coeff_count = 0; 3423 hc->chan[bch->slot].rx_off = 0; 3424 hc->chan[bch->slot].conf = -1; 3425 mode_hfcmulti(hc, bch->slot, ISDN_P_NONE, -1, 0, -1, 0); 3426 spin_unlock_irqrestore(&hc->lock, flags); 3427 } 3428 3429 static int 3430 handle_bmsg(struct mISDNchannel *ch, struct sk_buff *skb) 3431 { 3432 struct bchannel *bch = container_of(ch, struct bchannel, ch); 3433 struct hfc_multi *hc = bch->hw; 3434 int ret = -EINVAL; 3435 struct mISDNhead *hh = mISDN_HEAD_P(skb); 3436 unsigned int id; 3437 u_long flags; 3438 3439 switch (hh->prim) { 3440 case PH_DATA_REQ: 3441 if (!skb->len) 3442 break; 3443 spin_lock_irqsave(&hc->lock, flags); 3444 ret = bchannel_senddata(bch, skb); 3445 if (ret > 0) { /* direct TX */ 3446 id = hh->id; /* skb can be freed */ 3447 hfcmulti_tx(hc, bch->slot); 3448 ret = 0; 3449 /* start fifo */ 3450 HFC_outb_nodebug(hc, R_FIFO, 0); 3451 HFC_wait_nodebug(hc); 3452 if (!test_bit(FLG_TRANSPARENT, &bch->Flags)) { 3453 spin_unlock_irqrestore(&hc->lock, flags); 3454 queue_ch_frame(ch, PH_DATA_CNF, id, NULL); 3455 } else 3456 spin_unlock_irqrestore(&hc->lock, flags); 3457 } else 3458 spin_unlock_irqrestore(&hc->lock, flags); 3459 return ret; 3460 case PH_ACTIVATE_REQ: 3461 if (debug & DEBUG_HFCMULTI_MSG) 3462 printk(KERN_DEBUG "%s: PH_ACTIVATE ch %d (0..32)\n", 3463 __func__, bch->slot); 3464 spin_lock_irqsave(&hc->lock, flags); 3465 /* activate B-channel if not already activated */ 3466 if (!test_and_set_bit(FLG_ACTIVE, &bch->Flags)) { 3467 hc->chan[bch->slot].txpending = 0; 3468 ret = mode_hfcmulti(hc, bch->slot, 3469 ch->protocol, 3470 hc->chan[bch->slot].slot_tx, 3471 hc->chan[bch->slot].bank_tx, 3472 hc->chan[bch->slot].slot_rx, 3473 hc->chan[bch->slot].bank_rx); 3474 if (!ret) { 3475 if (ch->protocol == ISDN_P_B_RAW && !hc->dtmf 3476 && test_bit(HFC_CHIP_DTMF, &hc->chip)) { 3477 /* start decoder */ 3478 hc->dtmf = 1; 3479 if (debug & DEBUG_HFCMULTI_DTMF) 3480 printk(KERN_DEBUG 3481 "%s: start dtmf decoder\n", 3482 __func__); 3483 HFC_outb(hc, R_DTMF, hc->hw.r_dtmf | 3484 V_RST_DTMF); 3485 } 3486 } 3487 } else 3488 ret = 0; 3489 spin_unlock_irqrestore(&hc->lock, flags); 3490 if (!ret) 3491 _queue_data(ch, PH_ACTIVATE_IND, MISDN_ID_ANY, 0, NULL, 3492 GFP_KERNEL); 3493 break; 3494 case PH_CONTROL_REQ: 3495 spin_lock_irqsave(&hc->lock, flags); 3496 switch (hh->id) { 3497 case HFC_SPL_LOOP_ON: /* set sample loop */ 3498 if (debug & DEBUG_HFCMULTI_MSG) 3499 printk(KERN_DEBUG 3500 "%s: HFC_SPL_LOOP_ON (len = %d)\n", 3501 __func__, skb->len); 3502 ret = 0; 3503 break; 3504 case HFC_SPL_LOOP_OFF: /* set silence */ 3505 if (debug & DEBUG_HFCMULTI_MSG) 3506 printk(KERN_DEBUG "%s: HFC_SPL_LOOP_OFF\n", 3507 __func__); 3508 ret = 0; 3509 break; 3510 default: 3511 printk(KERN_ERR 3512 "%s: unknown PH_CONTROL_REQ info %x\n", 3513 __func__, hh->id); 3514 ret = -EINVAL; 3515 } 3516 spin_unlock_irqrestore(&hc->lock, flags); 3517 break; 3518 case PH_DEACTIVATE_REQ: 3519 deactivate_bchannel(bch); /* locked there */ 3520 _queue_data(ch, PH_DEACTIVATE_IND, MISDN_ID_ANY, 0, NULL, 3521 GFP_KERNEL); 3522 ret = 0; 3523 break; 3524 } 3525 if (!ret) 3526 dev_kfree_skb(skb); 3527 return ret; 3528 } 3529 3530 /* 3531 * bchannel control function 3532 */ 3533 static int 3534 channel_bctrl(struct bchannel *bch, struct mISDN_ctrl_req *cq) 3535 { 3536 int ret = 0; 3537 struct dsp_features *features = 3538 (struct dsp_features *)(*((u_long *)&cq->p1)); 3539 struct hfc_multi *hc = bch->hw; 3540 int slot_tx; 3541 int bank_tx; 3542 int slot_rx; 3543 int bank_rx; 3544 int num; 3545 3546 switch (cq->op) { 3547 case MISDN_CTRL_GETOP: 3548 cq->op = MISDN_CTRL_HFC_OP | MISDN_CTRL_HW_FEATURES_OP 3549 | MISDN_CTRL_RX_OFF | MISDN_CTRL_FILL_EMPTY; 3550 break; 3551 case MISDN_CTRL_RX_OFF: /* turn off / on rx stream */ 3552 hc->chan[bch->slot].rx_off = !!cq->p1; 3553 if (!hc->chan[bch->slot].rx_off) { 3554 /* reset fifo on rx on */ 3555 HFC_outb_nodebug(hc, R_FIFO, (bch->slot << 1) | 1); 3556 HFC_wait_nodebug(hc); 3557 HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_RES_F); 3558 HFC_wait_nodebug(hc); 3559 } 3560 if (debug & DEBUG_HFCMULTI_MSG) 3561 printk(KERN_DEBUG "%s: RX_OFF request (nr=%d off=%d)\n", 3562 __func__, bch->nr, hc->chan[bch->slot].rx_off); 3563 break; 3564 case MISDN_CTRL_FILL_EMPTY: /* fill fifo, if empty */ 3565 test_and_set_bit(FLG_FILLEMPTY, &bch->Flags); 3566 if (debug & DEBUG_HFCMULTI_MSG) 3567 printk(KERN_DEBUG "%s: FILL_EMPTY request (nr=%d " 3568 "off=%d)\n", __func__, bch->nr, !!cq->p1); 3569 break; 3570 case MISDN_CTRL_HW_FEATURES: /* fill features structure */ 3571 if (debug & DEBUG_HFCMULTI_MSG) 3572 printk(KERN_DEBUG "%s: HW_FEATURE request\n", 3573 __func__); 3574 /* create confirm */ 3575 features->hfc_id = hc->id; 3576 if (test_bit(HFC_CHIP_DTMF, &hc->chip)) 3577 features->hfc_dtmf = 1; 3578 if (test_bit(HFC_CHIP_CONF, &hc->chip)) 3579 features->hfc_conf = 1; 3580 features->hfc_loops = 0; 3581 if (test_bit(HFC_CHIP_B410P, &hc->chip)) { 3582 features->hfc_echocanhw = 1; 3583 } else { 3584 features->pcm_id = hc->pcm; 3585 features->pcm_slots = hc->slots; 3586 features->pcm_banks = 2; 3587 } 3588 break; 3589 case MISDN_CTRL_HFC_PCM_CONN: /* connect to pcm timeslot (0..N) */ 3590 slot_tx = cq->p1 & 0xff; 3591 bank_tx = cq->p1 >> 8; 3592 slot_rx = cq->p2 & 0xff; 3593 bank_rx = cq->p2 >> 8; 3594 if (debug & DEBUG_HFCMULTI_MSG) 3595 printk(KERN_DEBUG 3596 "%s: HFC_PCM_CONN slot %d bank %d (TX) " 3597 "slot %d bank %d (RX)\n", 3598 __func__, slot_tx, bank_tx, 3599 slot_rx, bank_rx); 3600 if (slot_tx < hc->slots && bank_tx <= 2 && 3601 slot_rx < hc->slots && bank_rx <= 2) 3602 hfcmulti_pcm(hc, bch->slot, 3603 slot_tx, bank_tx, slot_rx, bank_rx); 3604 else { 3605 printk(KERN_WARNING 3606 "%s: HFC_PCM_CONN slot %d bank %d (TX) " 3607 "slot %d bank %d (RX) out of range\n", 3608 __func__, slot_tx, bank_tx, 3609 slot_rx, bank_rx); 3610 ret = -EINVAL; 3611 } 3612 break; 3613 case MISDN_CTRL_HFC_PCM_DISC: /* release interface from pcm timeslot */ 3614 if (debug & DEBUG_HFCMULTI_MSG) 3615 printk(KERN_DEBUG "%s: HFC_PCM_DISC\n", 3616 __func__); 3617 hfcmulti_pcm(hc, bch->slot, -1, 0, -1, 0); 3618 break; 3619 case MISDN_CTRL_HFC_CONF_JOIN: /* join conference (0..7) */ 3620 num = cq->p1 & 0xff; 3621 if (debug & DEBUG_HFCMULTI_MSG) 3622 printk(KERN_DEBUG "%s: HFC_CONF_JOIN conf %d\n", 3623 __func__, num); 3624 if (num <= 7) 3625 hfcmulti_conf(hc, bch->slot, num); 3626 else { 3627 printk(KERN_WARNING 3628 "%s: HW_CONF_JOIN conf %d out of range\n", 3629 __func__, num); 3630 ret = -EINVAL; 3631 } 3632 break; 3633 case MISDN_CTRL_HFC_CONF_SPLIT: /* split conference */ 3634 if (debug & DEBUG_HFCMULTI_MSG) 3635 printk(KERN_DEBUG "%s: HFC_CONF_SPLIT\n", __func__); 3636 hfcmulti_conf(hc, bch->slot, -1); 3637 break; 3638 case MISDN_CTRL_HFC_ECHOCAN_ON: 3639 if (debug & DEBUG_HFCMULTI_MSG) 3640 printk(KERN_DEBUG "%s: HFC_ECHOCAN_ON\n", __func__); 3641 if (test_bit(HFC_CHIP_B410P, &hc->chip)) 3642 vpm_echocan_on(hc, bch->slot, cq->p1); 3643 else 3644 ret = -EINVAL; 3645 break; 3646 3647 case MISDN_CTRL_HFC_ECHOCAN_OFF: 3648 if (debug & DEBUG_HFCMULTI_MSG) 3649 printk(KERN_DEBUG "%s: HFC_ECHOCAN_OFF\n", 3650 __func__); 3651 if (test_bit(HFC_CHIP_B410P, &hc->chip)) 3652 vpm_echocan_off(hc, bch->slot); 3653 else 3654 ret = -EINVAL; 3655 break; 3656 default: 3657 printk(KERN_WARNING "%s: unknown Op %x\n", 3658 __func__, cq->op); 3659 ret = -EINVAL; 3660 break; 3661 } 3662 return ret; 3663 } 3664 3665 static int 3666 hfcm_bctrl(struct mISDNchannel *ch, u_int cmd, void *arg) 3667 { 3668 struct bchannel *bch = container_of(ch, struct bchannel, ch); 3669 struct hfc_multi *hc = bch->hw; 3670 int err = -EINVAL; 3671 u_long flags; 3672 3673 if (bch->debug & DEBUG_HW) 3674 printk(KERN_DEBUG "%s: cmd:%x %p\n", 3675 __func__, cmd, arg); 3676 switch (cmd) { 3677 case CLOSE_CHANNEL: 3678 test_and_clear_bit(FLG_OPEN, &bch->Flags); 3679 if (test_bit(FLG_ACTIVE, &bch->Flags)) 3680 deactivate_bchannel(bch); /* locked there */ 3681 ch->protocol = ISDN_P_NONE; 3682 ch->peer = NULL; 3683 module_put(THIS_MODULE); 3684 err = 0; 3685 break; 3686 case CONTROL_CHANNEL: 3687 spin_lock_irqsave(&hc->lock, flags); 3688 err = channel_bctrl(bch, arg); 3689 spin_unlock_irqrestore(&hc->lock, flags); 3690 break; 3691 default: 3692 printk(KERN_WARNING "%s: unknown prim(%x)\n", 3693 __func__, cmd); 3694 } 3695 return err; 3696 } 3697 3698 /* 3699 * handle D-channel events 3700 * 3701 * handle state change event 3702 */ 3703 static void 3704 ph_state_change(struct dchannel *dch) 3705 { 3706 struct hfc_multi *hc; 3707 int ch, i; 3708 3709 if (!dch) { 3710 printk(KERN_WARNING "%s: ERROR given dch is NULL\n", __func__); 3711 return; 3712 } 3713 hc = dch->hw; 3714 ch = dch->slot; 3715 3716 if (hc->ctype == HFC_TYPE_E1) { 3717 if (dch->dev.D.protocol == ISDN_P_TE_E1) { 3718 if (debug & DEBUG_HFCMULTI_STATE) 3719 printk(KERN_DEBUG 3720 "%s: E1 TE (id=%d) newstate %x\n", 3721 __func__, hc->id, dch->state); 3722 } else { 3723 if (debug & DEBUG_HFCMULTI_STATE) 3724 printk(KERN_DEBUG 3725 "%s: E1 NT (id=%d) newstate %x\n", 3726 __func__, hc->id, dch->state); 3727 } 3728 switch (dch->state) { 3729 case (1): 3730 if (hc->e1_state != 1) { 3731 for (i = 1; i <= 31; i++) { 3732 /* reset fifos on e1 activation */ 3733 HFC_outb_nodebug(hc, R_FIFO, 3734 (i << 1) | 1); 3735 HFC_wait_nodebug(hc); 3736 HFC_outb_nodebug(hc, R_INC_RES_FIFO, 3737 V_RES_F); 3738 HFC_wait_nodebug(hc); 3739 } 3740 } 3741 test_and_set_bit(FLG_ACTIVE, &dch->Flags); 3742 _queue_data(&dch->dev.D, PH_ACTIVATE_IND, 3743 MISDN_ID_ANY, 0, NULL, GFP_ATOMIC); 3744 break; 3745 3746 default: 3747 if (hc->e1_state != 1) 3748 return; 3749 test_and_clear_bit(FLG_ACTIVE, &dch->Flags); 3750 _queue_data(&dch->dev.D, PH_DEACTIVATE_IND, 3751 MISDN_ID_ANY, 0, NULL, GFP_ATOMIC); 3752 } 3753 hc->e1_state = dch->state; 3754 } else { 3755 if (dch->dev.D.protocol == ISDN_P_TE_S0) { 3756 if (debug & DEBUG_HFCMULTI_STATE) 3757 printk(KERN_DEBUG 3758 "%s: S/T TE newstate %x\n", 3759 __func__, dch->state); 3760 switch (dch->state) { 3761 case (0): 3762 l1_event(dch->l1, HW_RESET_IND); 3763 break; 3764 case (3): 3765 l1_event(dch->l1, HW_DEACT_IND); 3766 break; 3767 case (5): 3768 case (8): 3769 l1_event(dch->l1, ANYSIGNAL); 3770 break; 3771 case (6): 3772 l1_event(dch->l1, INFO2); 3773 break; 3774 case (7): 3775 l1_event(dch->l1, INFO4_P8); 3776 break; 3777 } 3778 } else { 3779 if (debug & DEBUG_HFCMULTI_STATE) 3780 printk(KERN_DEBUG "%s: S/T NT newstate %x\n", 3781 __func__, dch->state); 3782 switch (dch->state) { 3783 case (2): 3784 if (hc->chan[ch].nt_timer == 0) { 3785 hc->chan[ch].nt_timer = -1; 3786 HFC_outb(hc, R_ST_SEL, 3787 hc->chan[ch].port); 3788 /* undocumented: delay after R_ST_SEL */ 3789 udelay(1); 3790 HFC_outb(hc, A_ST_WR_STATE, 4 | 3791 V_ST_LD_STA); /* G4 */ 3792 udelay(6); /* wait at least 5,21us */ 3793 HFC_outb(hc, A_ST_WR_STATE, 4); 3794 dch->state = 4; 3795 } else { 3796 /* one extra count for the next event */ 3797 hc->chan[ch].nt_timer = 3798 nt_t1_count[poll_timer] + 1; 3799 HFC_outb(hc, R_ST_SEL, 3800 hc->chan[ch].port); 3801 /* undocumented: delay after R_ST_SEL */ 3802 udelay(1); 3803 /* allow G2 -> G3 transition */ 3804 HFC_outb(hc, A_ST_WR_STATE, 2 | 3805 V_SET_G2_G3); 3806 } 3807 break; 3808 case (1): 3809 hc->chan[ch].nt_timer = -1; 3810 test_and_clear_bit(FLG_ACTIVE, &dch->Flags); 3811 _queue_data(&dch->dev.D, PH_DEACTIVATE_IND, 3812 MISDN_ID_ANY, 0, NULL, GFP_ATOMIC); 3813 break; 3814 case (4): 3815 hc->chan[ch].nt_timer = -1; 3816 break; 3817 case (3): 3818 hc->chan[ch].nt_timer = -1; 3819 test_and_set_bit(FLG_ACTIVE, &dch->Flags); 3820 _queue_data(&dch->dev.D, PH_ACTIVATE_IND, 3821 MISDN_ID_ANY, 0, NULL, GFP_ATOMIC); 3822 break; 3823 } 3824 } 3825 } 3826 } 3827 3828 /* 3829 * called for card mode init message 3830 */ 3831 3832 static void 3833 hfcmulti_initmode(struct dchannel *dch) 3834 { 3835 struct hfc_multi *hc = dch->hw; 3836 u_char a_st_wr_state, r_e1_wr_sta; 3837 int i, pt; 3838 3839 if (debug & DEBUG_HFCMULTI_INIT) 3840 printk(KERN_DEBUG "%s: entered\n", __func__); 3841 3842 if (hc->ctype == HFC_TYPE_E1) { 3843 hc->chan[hc->dslot].slot_tx = -1; 3844 hc->chan[hc->dslot].slot_rx = -1; 3845 hc->chan[hc->dslot].conf = -1; 3846 if (hc->dslot) { 3847 mode_hfcmulti(hc, hc->dslot, dch->dev.D.protocol, 3848 -1, 0, -1, 0); 3849 dch->timer.function = (void *) hfcmulti_dbusy_timer; 3850 dch->timer.data = (long) dch; 3851 init_timer(&dch->timer); 3852 } 3853 for (i = 1; i <= 31; i++) { 3854 if (i == hc->dslot) 3855 continue; 3856 hc->chan[i].slot_tx = -1; 3857 hc->chan[i].slot_rx = -1; 3858 hc->chan[i].conf = -1; 3859 mode_hfcmulti(hc, i, ISDN_P_NONE, -1, 0, -1, 0); 3860 } 3861 /* E1 */ 3862 if (test_bit(HFC_CFG_REPORT_LOS, &hc->chan[hc->dslot].cfg)) { 3863 HFC_outb(hc, R_LOS0, 255); /* 2 ms */ 3864 HFC_outb(hc, R_LOS1, 255); /* 512 ms */ 3865 } 3866 if (test_bit(HFC_CFG_OPTICAL, &hc->chan[hc->dslot].cfg)) { 3867 HFC_outb(hc, R_RX0, 0); 3868 hc->hw.r_tx0 = 0 | V_OUT_EN; 3869 } else { 3870 HFC_outb(hc, R_RX0, 1); 3871 hc->hw.r_tx0 = 1 | V_OUT_EN; 3872 } 3873 hc->hw.r_tx1 = V_ATX | V_NTRI; 3874 HFC_outb(hc, R_TX0, hc->hw.r_tx0); 3875 HFC_outb(hc, R_TX1, hc->hw.r_tx1); 3876 HFC_outb(hc, R_TX_FR0, 0x00); 3877 HFC_outb(hc, R_TX_FR1, 0xf8); 3878 3879 if (test_bit(HFC_CFG_CRC4, &hc->chan[hc->dslot].cfg)) 3880 HFC_outb(hc, R_TX_FR2, V_TX_MF | V_TX_E | V_NEG_E); 3881 3882 HFC_outb(hc, R_RX_FR0, V_AUTO_RESYNC | V_AUTO_RECO | 0); 3883 3884 if (test_bit(HFC_CFG_CRC4, &hc->chan[hc->dslot].cfg)) 3885 HFC_outb(hc, R_RX_FR1, V_RX_MF | V_RX_MF_SYNC); 3886 3887 if (dch->dev.D.protocol == ISDN_P_NT_E1) { 3888 if (debug & DEBUG_HFCMULTI_INIT) 3889 printk(KERN_DEBUG "%s: E1 port is NT-mode\n", 3890 __func__); 3891 r_e1_wr_sta = 0; /* G0 */ 3892 hc->e1_getclock = 0; 3893 } else { 3894 if (debug & DEBUG_HFCMULTI_INIT) 3895 printk(KERN_DEBUG "%s: E1 port is TE-mode\n", 3896 __func__); 3897 r_e1_wr_sta = 0; /* F0 */ 3898 hc->e1_getclock = 1; 3899 } 3900 if (test_bit(HFC_CHIP_RX_SYNC, &hc->chip)) 3901 HFC_outb(hc, R_SYNC_OUT, V_SYNC_E1_RX); 3902 else 3903 HFC_outb(hc, R_SYNC_OUT, 0); 3904 if (test_bit(HFC_CHIP_E1CLOCK_GET, &hc->chip)) 3905 hc->e1_getclock = 1; 3906 if (test_bit(HFC_CHIP_E1CLOCK_PUT, &hc->chip)) 3907 hc->e1_getclock = 0; 3908 if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip)) { 3909 /* SLAVE (clock master) */ 3910 if (debug & DEBUG_HFCMULTI_INIT) 3911 printk(KERN_DEBUG 3912 "%s: E1 port is clock master " 3913 "(clock from PCM)\n", __func__); 3914 HFC_outb(hc, R_SYNC_CTRL, V_EXT_CLK_SYNC | V_PCM_SYNC); 3915 } else { 3916 if (hc->e1_getclock) { 3917 /* MASTER (clock slave) */ 3918 if (debug & DEBUG_HFCMULTI_INIT) 3919 printk(KERN_DEBUG 3920 "%s: E1 port is clock slave " 3921 "(clock to PCM)\n", __func__); 3922 HFC_outb(hc, R_SYNC_CTRL, V_SYNC_OFFS); 3923 } else { 3924 /* MASTER (clock master) */ 3925 if (debug & DEBUG_HFCMULTI_INIT) 3926 printk(KERN_DEBUG "%s: E1 port is " 3927 "clock master " 3928 "(clock from QUARTZ)\n", 3929 __func__); 3930 HFC_outb(hc, R_SYNC_CTRL, V_EXT_CLK_SYNC | 3931 V_PCM_SYNC | V_JATT_OFF); 3932 HFC_outb(hc, R_SYNC_OUT, 0); 3933 } 3934 } 3935 HFC_outb(hc, R_JATT_ATT, 0x9c); /* undoc register */ 3936 HFC_outb(hc, R_PWM_MD, V_PWM0_MD); 3937 HFC_outb(hc, R_PWM0, 0x50); 3938 HFC_outb(hc, R_PWM1, 0xff); 3939 /* state machine setup */ 3940 HFC_outb(hc, R_E1_WR_STA, r_e1_wr_sta | V_E1_LD_STA); 3941 udelay(6); /* wait at least 5,21us */ 3942 HFC_outb(hc, R_E1_WR_STA, r_e1_wr_sta); 3943 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) { 3944 hc->syncronized = 0; 3945 plxsd_checksync(hc, 0); 3946 } 3947 } else { 3948 i = dch->slot; 3949 hc->chan[i].slot_tx = -1; 3950 hc->chan[i].slot_rx = -1; 3951 hc->chan[i].conf = -1; 3952 mode_hfcmulti(hc, i, dch->dev.D.protocol, -1, 0, -1, 0); 3953 dch->timer.function = (void *)hfcmulti_dbusy_timer; 3954 dch->timer.data = (long) dch; 3955 init_timer(&dch->timer); 3956 hc->chan[i - 2].slot_tx = -1; 3957 hc->chan[i - 2].slot_rx = -1; 3958 hc->chan[i - 2].conf = -1; 3959 mode_hfcmulti(hc, i - 2, ISDN_P_NONE, -1, 0, -1, 0); 3960 hc->chan[i - 1].slot_tx = -1; 3961 hc->chan[i - 1].slot_rx = -1; 3962 hc->chan[i - 1].conf = -1; 3963 mode_hfcmulti(hc, i - 1, ISDN_P_NONE, -1, 0, -1, 0); 3964 /* ST */ 3965 pt = hc->chan[i].port; 3966 /* select interface */ 3967 HFC_outb(hc, R_ST_SEL, pt); 3968 /* undocumented: delay after R_ST_SEL */ 3969 udelay(1); 3970 if (dch->dev.D.protocol == ISDN_P_NT_S0) { 3971 if (debug & DEBUG_HFCMULTI_INIT) 3972 printk(KERN_DEBUG 3973 "%s: ST port %d is NT-mode\n", 3974 __func__, pt); 3975 /* clock delay */ 3976 HFC_outb(hc, A_ST_CLK_DLY, clockdelay_nt); 3977 a_st_wr_state = 1; /* G1 */ 3978 hc->hw.a_st_ctrl0[pt] = V_ST_MD; 3979 } else { 3980 if (debug & DEBUG_HFCMULTI_INIT) 3981 printk(KERN_DEBUG 3982 "%s: ST port %d is TE-mode\n", 3983 __func__, pt); 3984 /* clock delay */ 3985 HFC_outb(hc, A_ST_CLK_DLY, clockdelay_te); 3986 a_st_wr_state = 2; /* F2 */ 3987 hc->hw.a_st_ctrl0[pt] = 0; 3988 } 3989 if (!test_bit(HFC_CFG_NONCAP_TX, &hc->chan[i].cfg)) 3990 hc->hw.a_st_ctrl0[pt] |= V_TX_LI; 3991 if (hc->ctype == HFC_TYPE_XHFC) { 3992 hc->hw.a_st_ctrl0[pt] |= 0x40 /* V_ST_PU_CTRL */; 3993 HFC_outb(hc, 0x35 /* A_ST_CTRL3 */, 3994 0x7c << 1 /* V_ST_PULSE */); 3995 } 3996 /* line setup */ 3997 HFC_outb(hc, A_ST_CTRL0, hc->hw.a_st_ctrl0[pt]); 3998 /* disable E-channel */ 3999 if ((dch->dev.D.protocol == ISDN_P_NT_S0) || 4000 test_bit(HFC_CFG_DIS_ECHANNEL, &hc->chan[i].cfg)) 4001 HFC_outb(hc, A_ST_CTRL1, V_E_IGNO); 4002 else 4003 HFC_outb(hc, A_ST_CTRL1, 0); 4004 /* enable B-channel receive */ 4005 HFC_outb(hc, A_ST_CTRL2, V_B1_RX_EN | V_B2_RX_EN); 4006 /* state machine setup */ 4007 HFC_outb(hc, A_ST_WR_STATE, a_st_wr_state | V_ST_LD_STA); 4008 udelay(6); /* wait at least 5,21us */ 4009 HFC_outb(hc, A_ST_WR_STATE, a_st_wr_state); 4010 hc->hw.r_sci_msk |= 1 << pt; 4011 /* state machine interrupts */ 4012 HFC_outb(hc, R_SCI_MSK, hc->hw.r_sci_msk); 4013 /* unset sync on port */ 4014 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) { 4015 hc->syncronized &= 4016 ~(1 << hc->chan[dch->slot].port); 4017 plxsd_checksync(hc, 0); 4018 } 4019 } 4020 if (debug & DEBUG_HFCMULTI_INIT) 4021 printk("%s: done\n", __func__); 4022 } 4023 4024 4025 static int 4026 open_dchannel(struct hfc_multi *hc, struct dchannel *dch, 4027 struct channel_req *rq) 4028 { 4029 int err = 0; 4030 u_long flags; 4031 4032 if (debug & DEBUG_HW_OPEN) 4033 printk(KERN_DEBUG "%s: dev(%d) open from %p\n", __func__, 4034 dch->dev.id, __builtin_return_address(0)); 4035 if (rq->protocol == ISDN_P_NONE) 4036 return -EINVAL; 4037 if ((dch->dev.D.protocol != ISDN_P_NONE) && 4038 (dch->dev.D.protocol != rq->protocol)) { 4039 if (debug & DEBUG_HFCMULTI_MODE) 4040 printk(KERN_DEBUG "%s: change protocol %x to %x\n", 4041 __func__, dch->dev.D.protocol, rq->protocol); 4042 } 4043 if ((dch->dev.D.protocol == ISDN_P_TE_S0) && 4044 (rq->protocol != ISDN_P_TE_S0)) 4045 l1_event(dch->l1, CLOSE_CHANNEL); 4046 if (dch->dev.D.protocol != rq->protocol) { 4047 if (rq->protocol == ISDN_P_TE_S0) { 4048 err = create_l1(dch, hfcm_l1callback); 4049 if (err) 4050 return err; 4051 } 4052 dch->dev.D.protocol = rq->protocol; 4053 spin_lock_irqsave(&hc->lock, flags); 4054 hfcmulti_initmode(dch); 4055 spin_unlock_irqrestore(&hc->lock, flags); 4056 } 4057 4058 if (((rq->protocol == ISDN_P_NT_S0) && (dch->state == 3)) || 4059 ((rq->protocol == ISDN_P_TE_S0) && (dch->state == 7)) || 4060 ((rq->protocol == ISDN_P_NT_E1) && (dch->state == 1)) || 4061 ((rq->protocol == ISDN_P_TE_E1) && (dch->state == 1))) { 4062 _queue_data(&dch->dev.D, PH_ACTIVATE_IND, MISDN_ID_ANY, 4063 0, NULL, GFP_KERNEL); 4064 } 4065 rq->ch = &dch->dev.D; 4066 if (!try_module_get(THIS_MODULE)) 4067 printk(KERN_WARNING "%s:cannot get module\n", __func__); 4068 return 0; 4069 } 4070 4071 static int 4072 open_bchannel(struct hfc_multi *hc, struct dchannel *dch, 4073 struct channel_req *rq) 4074 { 4075 struct bchannel *bch; 4076 int ch; 4077 4078 if (!test_channelmap(rq->adr.channel, dch->dev.channelmap)) 4079 return -EINVAL; 4080 if (rq->protocol == ISDN_P_NONE) 4081 return -EINVAL; 4082 if (hc->ctype == HFC_TYPE_E1) 4083 ch = rq->adr.channel; 4084 else 4085 ch = (rq->adr.channel - 1) + (dch->slot - 2); 4086 bch = hc->chan[ch].bch; 4087 if (!bch) { 4088 printk(KERN_ERR "%s:internal error ch %d has no bch\n", 4089 __func__, ch); 4090 return -EINVAL; 4091 } 4092 if (test_and_set_bit(FLG_OPEN, &bch->Flags)) 4093 return -EBUSY; /* b-channel can be only open once */ 4094 test_and_clear_bit(FLG_FILLEMPTY, &bch->Flags); 4095 bch->ch.protocol = rq->protocol; 4096 hc->chan[ch].rx_off = 0; 4097 rq->ch = &bch->ch; 4098 if (!try_module_get(THIS_MODULE)) 4099 printk(KERN_WARNING "%s:cannot get module\n", __func__); 4100 return 0; 4101 } 4102 4103 /* 4104 * device control function 4105 */ 4106 static int 4107 channel_dctrl(struct dchannel *dch, struct mISDN_ctrl_req *cq) 4108 { 4109 struct hfc_multi *hc = dch->hw; 4110 int ret = 0; 4111 int wd_mode, wd_cnt; 4112 4113 switch (cq->op) { 4114 case MISDN_CTRL_GETOP: 4115 cq->op = MISDN_CTRL_HFC_OP; 4116 break; 4117 case MISDN_CTRL_HFC_WD_INIT: /* init the watchdog */ 4118 wd_cnt = cq->p1 & 0xf; 4119 wd_mode = !!(cq->p1 >> 4); 4120 if (debug & DEBUG_HFCMULTI_MSG) 4121 printk(KERN_DEBUG "%s: MISDN_CTRL_HFC_WD_INIT mode %s" 4122 ", counter 0x%x\n", __func__, 4123 wd_mode ? "AUTO" : "MANUAL", wd_cnt); 4124 /* set the watchdog timer */ 4125 HFC_outb(hc, R_TI_WD, poll_timer | (wd_cnt << 4)); 4126 hc->hw.r_bert_wd_md = (wd_mode ? V_AUTO_WD_RES : 0); 4127 if (hc->ctype == HFC_TYPE_XHFC) 4128 hc->hw.r_bert_wd_md |= 0x40 /* V_WD_EN */; 4129 /* init the watchdog register and reset the counter */ 4130 HFC_outb(hc, R_BERT_WD_MD, hc->hw.r_bert_wd_md | V_WD_RES); 4131 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) { 4132 /* enable the watchdog output for Speech-Design */ 4133 HFC_outb(hc, R_GPIO_SEL, V_GPIO_SEL7); 4134 HFC_outb(hc, R_GPIO_EN1, V_GPIO_EN15); 4135 HFC_outb(hc, R_GPIO_OUT1, 0); 4136 HFC_outb(hc, R_GPIO_OUT1, V_GPIO_OUT15); 4137 } 4138 break; 4139 case MISDN_CTRL_HFC_WD_RESET: /* reset the watchdog counter */ 4140 if (debug & DEBUG_HFCMULTI_MSG) 4141 printk(KERN_DEBUG "%s: MISDN_CTRL_HFC_WD_RESET\n", 4142 __func__); 4143 HFC_outb(hc, R_BERT_WD_MD, hc->hw.r_bert_wd_md | V_WD_RES); 4144 break; 4145 default: 4146 printk(KERN_WARNING "%s: unknown Op %x\n", 4147 __func__, cq->op); 4148 ret = -EINVAL; 4149 break; 4150 } 4151 return ret; 4152 } 4153 4154 static int 4155 hfcm_dctrl(struct mISDNchannel *ch, u_int cmd, void *arg) 4156 { 4157 struct mISDNdevice *dev = container_of(ch, struct mISDNdevice, D); 4158 struct dchannel *dch = container_of(dev, struct dchannel, dev); 4159 struct hfc_multi *hc = dch->hw; 4160 struct channel_req *rq; 4161 int err = 0; 4162 u_long flags; 4163 4164 if (dch->debug & DEBUG_HW) 4165 printk(KERN_DEBUG "%s: cmd:%x %p\n", 4166 __func__, cmd, arg); 4167 switch (cmd) { 4168 case OPEN_CHANNEL: 4169 rq = arg; 4170 switch (rq->protocol) { 4171 case ISDN_P_TE_S0: 4172 case ISDN_P_NT_S0: 4173 if (hc->ctype == HFC_TYPE_E1) { 4174 err = -EINVAL; 4175 break; 4176 } 4177 err = open_dchannel(hc, dch, rq); /* locked there */ 4178 break; 4179 case ISDN_P_TE_E1: 4180 case ISDN_P_NT_E1: 4181 if (hc->ctype != HFC_TYPE_E1) { 4182 err = -EINVAL; 4183 break; 4184 } 4185 err = open_dchannel(hc, dch, rq); /* locked there */ 4186 break; 4187 default: 4188 spin_lock_irqsave(&hc->lock, flags); 4189 err = open_bchannel(hc, dch, rq); 4190 spin_unlock_irqrestore(&hc->lock, flags); 4191 } 4192 break; 4193 case CLOSE_CHANNEL: 4194 if (debug & DEBUG_HW_OPEN) 4195 printk(KERN_DEBUG "%s: dev(%d) close from %p\n", 4196 __func__, dch->dev.id, 4197 __builtin_return_address(0)); 4198 module_put(THIS_MODULE); 4199 break; 4200 case CONTROL_CHANNEL: 4201 spin_lock_irqsave(&hc->lock, flags); 4202 err = channel_dctrl(dch, arg); 4203 spin_unlock_irqrestore(&hc->lock, flags); 4204 break; 4205 default: 4206 if (dch->debug & DEBUG_HW) 4207 printk(KERN_DEBUG "%s: unknown command %x\n", 4208 __func__, cmd); 4209 err = -EINVAL; 4210 } 4211 return err; 4212 } 4213 4214 static int 4215 clockctl(void *priv, int enable) 4216 { 4217 struct hfc_multi *hc = priv; 4218 4219 hc->iclock_on = enable; 4220 return 0; 4221 } 4222 4223 /* 4224 * initialize the card 4225 */ 4226 4227 /* 4228 * start timer irq, wait some time and check if we have interrupts. 4229 * if not, reset chip and try again. 4230 */ 4231 static int 4232 init_card(struct hfc_multi *hc) 4233 { 4234 int err = -EIO; 4235 u_long flags; 4236 void __iomem *plx_acc; 4237 u_long plx_flags; 4238 4239 if (debug & DEBUG_HFCMULTI_INIT) 4240 printk(KERN_DEBUG "%s: entered\n", __func__); 4241 4242 spin_lock_irqsave(&hc->lock, flags); 4243 /* set interrupts but leave global interrupt disabled */ 4244 hc->hw.r_irq_ctrl = V_FIFO_IRQ; 4245 disable_hwirq(hc); 4246 spin_unlock_irqrestore(&hc->lock, flags); 4247 4248 if (request_irq(hc->irq, hfcmulti_interrupt, IRQF_SHARED, 4249 "HFC-multi", hc)) { 4250 printk(KERN_WARNING "mISDN: Could not get interrupt %d.\n", 4251 hc->irq); 4252 hc->irq = 0; 4253 return -EIO; 4254 } 4255 4256 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) { 4257 spin_lock_irqsave(&plx_lock, plx_flags); 4258 plx_acc = hc->plx_membase + PLX_INTCSR; 4259 writew((PLX_INTCSR_PCIINT_ENABLE | PLX_INTCSR_LINTI1_ENABLE), 4260 plx_acc); /* enable PCI & LINT1 irq */ 4261 spin_unlock_irqrestore(&plx_lock, plx_flags); 4262 } 4263 4264 if (debug & DEBUG_HFCMULTI_INIT) 4265 printk(KERN_DEBUG "%s: IRQ %d count %d\n", 4266 __func__, hc->irq, hc->irqcnt); 4267 err = init_chip(hc); 4268 if (err) 4269 goto error; 4270 /* 4271 * Finally enable IRQ output 4272 * this is only allowed, if an IRQ routine is already 4273 * established for this HFC, so don't do that earlier 4274 */ 4275 spin_lock_irqsave(&hc->lock, flags); 4276 enable_hwirq(hc); 4277 spin_unlock_irqrestore(&hc->lock, flags); 4278 /* printk(KERN_DEBUG "no master irq set!!!\n"); */ 4279 set_current_state(TASK_UNINTERRUPTIBLE); 4280 schedule_timeout((100*HZ)/1000); /* Timeout 100ms */ 4281 /* turn IRQ off until chip is completely initialized */ 4282 spin_lock_irqsave(&hc->lock, flags); 4283 disable_hwirq(hc); 4284 spin_unlock_irqrestore(&hc->lock, flags); 4285 if (debug & DEBUG_HFCMULTI_INIT) 4286 printk(KERN_DEBUG "%s: IRQ %d count %d\n", 4287 __func__, hc->irq, hc->irqcnt); 4288 if (hc->irqcnt) { 4289 if (debug & DEBUG_HFCMULTI_INIT) 4290 printk(KERN_DEBUG "%s: done\n", __func__); 4291 4292 return 0; 4293 } 4294 if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip)) { 4295 printk(KERN_INFO "ignoring missing interrupts\n"); 4296 return 0; 4297 } 4298 4299 printk(KERN_ERR "HFC PCI: IRQ(%d) getting no interrupts during init.\n", 4300 hc->irq); 4301 4302 err = -EIO; 4303 4304 error: 4305 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) { 4306 spin_lock_irqsave(&plx_lock, plx_flags); 4307 plx_acc = hc->plx_membase + PLX_INTCSR; 4308 writew(0x00, plx_acc); /*disable IRQs*/ 4309 spin_unlock_irqrestore(&plx_lock, plx_flags); 4310 } 4311 4312 if (debug & DEBUG_HFCMULTI_INIT) 4313 printk(KERN_DEBUG "%s: free irq %d\n", __func__, hc->irq); 4314 if (hc->irq) { 4315 free_irq(hc->irq, hc); 4316 hc->irq = 0; 4317 } 4318 4319 if (debug & DEBUG_HFCMULTI_INIT) 4320 printk(KERN_DEBUG "%s: done (err=%d)\n", __func__, err); 4321 return err; 4322 } 4323 4324 /* 4325 * find pci device and set it up 4326 */ 4327 4328 static int 4329 setup_pci(struct hfc_multi *hc, struct pci_dev *pdev, 4330 const struct pci_device_id *ent) 4331 { 4332 struct hm_map *m = (struct hm_map *)ent->driver_data; 4333 4334 printk(KERN_INFO 4335 "HFC-multi: card manufacturer: '%s' card name: '%s' clock: %s\n", 4336 m->vendor_name, m->card_name, m->clock2 ? "double" : "normal"); 4337 4338 hc->pci_dev = pdev; 4339 if (m->clock2) 4340 test_and_set_bit(HFC_CHIP_CLOCK2, &hc->chip); 4341 4342 if (ent->device == 0xB410) { 4343 test_and_set_bit(HFC_CHIP_B410P, &hc->chip); 4344 test_and_set_bit(HFC_CHIP_PCM_MASTER, &hc->chip); 4345 test_and_clear_bit(HFC_CHIP_PCM_SLAVE, &hc->chip); 4346 hc->slots = 32; 4347 } 4348 4349 if (hc->pci_dev->irq <= 0) { 4350 printk(KERN_WARNING "HFC-multi: No IRQ for PCI card found.\n"); 4351 return -EIO; 4352 } 4353 if (pci_enable_device(hc->pci_dev)) { 4354 printk(KERN_WARNING "HFC-multi: Error enabling PCI card.\n"); 4355 return -EIO; 4356 } 4357 hc->leds = m->leds; 4358 hc->ledstate = 0xAFFEAFFE; 4359 hc->opticalsupport = m->opticalsupport; 4360 4361 hc->pci_iobase = 0; 4362 hc->pci_membase = NULL; 4363 hc->plx_membase = NULL; 4364 4365 /* set memory access methods */ 4366 if (m->io_mode) /* use mode from card config */ 4367 hc->io_mode = m->io_mode; 4368 switch (hc->io_mode) { 4369 case HFC_IO_MODE_PLXSD: 4370 test_and_set_bit(HFC_CHIP_PLXSD, &hc->chip); 4371 hc->slots = 128; /* required */ 4372 hc->HFC_outb = HFC_outb_pcimem; 4373 hc->HFC_inb = HFC_inb_pcimem; 4374 hc->HFC_inw = HFC_inw_pcimem; 4375 hc->HFC_wait = HFC_wait_pcimem; 4376 hc->read_fifo = read_fifo_pcimem; 4377 hc->write_fifo = write_fifo_pcimem; 4378 hc->plx_origmembase = hc->pci_dev->resource[0].start; 4379 /* MEMBASE 1 is PLX PCI Bridge */ 4380 4381 if (!hc->plx_origmembase) { 4382 printk(KERN_WARNING 4383 "HFC-multi: No IO-Memory for PCI PLX bridge found\n"); 4384 pci_disable_device(hc->pci_dev); 4385 return -EIO; 4386 } 4387 4388 hc->plx_membase = ioremap(hc->plx_origmembase, 0x80); 4389 if (!hc->plx_membase) { 4390 printk(KERN_WARNING 4391 "HFC-multi: failed to remap plx address space. " 4392 "(internal error)\n"); 4393 pci_disable_device(hc->pci_dev); 4394 return -EIO; 4395 } 4396 printk(KERN_INFO 4397 "HFC-multi: plx_membase:%#lx plx_origmembase:%#lx\n", 4398 (u_long)hc->plx_membase, hc->plx_origmembase); 4399 4400 hc->pci_origmembase = hc->pci_dev->resource[2].start; 4401 /* MEMBASE 1 is PLX PCI Bridge */ 4402 if (!hc->pci_origmembase) { 4403 printk(KERN_WARNING 4404 "HFC-multi: No IO-Memory for PCI card found\n"); 4405 pci_disable_device(hc->pci_dev); 4406 return -EIO; 4407 } 4408 4409 hc->pci_membase = ioremap(hc->pci_origmembase, 0x400); 4410 if (!hc->pci_membase) { 4411 printk(KERN_WARNING "HFC-multi: failed to remap io " 4412 "address space. (internal error)\n"); 4413 pci_disable_device(hc->pci_dev); 4414 return -EIO; 4415 } 4416 4417 printk(KERN_INFO 4418 "card %d: defined at MEMBASE %#lx (%#lx) IRQ %d HZ %d " 4419 "leds-type %d\n", 4420 hc->id, (u_long)hc->pci_membase, hc->pci_origmembase, 4421 hc->pci_dev->irq, HZ, hc->leds); 4422 pci_write_config_word(hc->pci_dev, PCI_COMMAND, PCI_ENA_MEMIO); 4423 break; 4424 case HFC_IO_MODE_PCIMEM: 4425 hc->HFC_outb = HFC_outb_pcimem; 4426 hc->HFC_inb = HFC_inb_pcimem; 4427 hc->HFC_inw = HFC_inw_pcimem; 4428 hc->HFC_wait = HFC_wait_pcimem; 4429 hc->read_fifo = read_fifo_pcimem; 4430 hc->write_fifo = write_fifo_pcimem; 4431 hc->pci_origmembase = hc->pci_dev->resource[1].start; 4432 if (!hc->pci_origmembase) { 4433 printk(KERN_WARNING 4434 "HFC-multi: No IO-Memory for PCI card found\n"); 4435 pci_disable_device(hc->pci_dev); 4436 return -EIO; 4437 } 4438 4439 hc->pci_membase = ioremap(hc->pci_origmembase, 256); 4440 if (!hc->pci_membase) { 4441 printk(KERN_WARNING 4442 "HFC-multi: failed to remap io address space. " 4443 "(internal error)\n"); 4444 pci_disable_device(hc->pci_dev); 4445 return -EIO; 4446 } 4447 printk(KERN_INFO "card %d: defined at MEMBASE %#lx (%#lx) IRQ " 4448 "%d HZ %d leds-type %d\n", hc->id, (u_long)hc->pci_membase, 4449 hc->pci_origmembase, hc->pci_dev->irq, HZ, hc->leds); 4450 pci_write_config_word(hc->pci_dev, PCI_COMMAND, PCI_ENA_MEMIO); 4451 break; 4452 case HFC_IO_MODE_REGIO: 4453 hc->HFC_outb = HFC_outb_regio; 4454 hc->HFC_inb = HFC_inb_regio; 4455 hc->HFC_inw = HFC_inw_regio; 4456 hc->HFC_wait = HFC_wait_regio; 4457 hc->read_fifo = read_fifo_regio; 4458 hc->write_fifo = write_fifo_regio; 4459 hc->pci_iobase = (u_int) hc->pci_dev->resource[0].start; 4460 if (!hc->pci_iobase) { 4461 printk(KERN_WARNING 4462 "HFC-multi: No IO for PCI card found\n"); 4463 pci_disable_device(hc->pci_dev); 4464 return -EIO; 4465 } 4466 4467 if (!request_region(hc->pci_iobase, 8, "hfcmulti")) { 4468 printk(KERN_WARNING "HFC-multi: failed to request " 4469 "address space at 0x%08lx (internal error)\n", 4470 hc->pci_iobase); 4471 pci_disable_device(hc->pci_dev); 4472 return -EIO; 4473 } 4474 4475 printk(KERN_INFO 4476 "%s %s: defined at IOBASE %#x IRQ %d HZ %d leds-type %d\n", 4477 m->vendor_name, m->card_name, (u_int) hc->pci_iobase, 4478 hc->pci_dev->irq, HZ, hc->leds); 4479 pci_write_config_word(hc->pci_dev, PCI_COMMAND, PCI_ENA_REGIO); 4480 break; 4481 default: 4482 printk(KERN_WARNING "HFC-multi: Invalid IO mode.\n"); 4483 pci_disable_device(hc->pci_dev); 4484 return -EIO; 4485 } 4486 4487 pci_set_drvdata(hc->pci_dev, hc); 4488 4489 /* At this point the needed PCI config is done */ 4490 /* fifos are still not enabled */ 4491 return 0; 4492 } 4493 4494 4495 /* 4496 * remove port 4497 */ 4498 4499 static void 4500 release_port(struct hfc_multi *hc, struct dchannel *dch) 4501 { 4502 int pt, ci, i = 0; 4503 u_long flags; 4504 struct bchannel *pb; 4505 4506 ci = dch->slot; 4507 pt = hc->chan[ci].port; 4508 4509 if (debug & DEBUG_HFCMULTI_INIT) 4510 printk(KERN_DEBUG "%s: entered for port %d\n", 4511 __func__, pt + 1); 4512 4513 if (pt >= hc->ports) { 4514 printk(KERN_WARNING "%s: ERROR port out of range (%d).\n", 4515 __func__, pt + 1); 4516 return; 4517 } 4518 4519 if (debug & DEBUG_HFCMULTI_INIT) 4520 printk(KERN_DEBUG "%s: releasing port=%d\n", 4521 __func__, pt + 1); 4522 4523 if (dch->dev.D.protocol == ISDN_P_TE_S0) 4524 l1_event(dch->l1, CLOSE_CHANNEL); 4525 4526 hc->chan[ci].dch = NULL; 4527 4528 if (hc->created[pt]) { 4529 hc->created[pt] = 0; 4530 mISDN_unregister_device(&dch->dev); 4531 } 4532 4533 spin_lock_irqsave(&hc->lock, flags); 4534 4535 if (dch->timer.function) { 4536 del_timer(&dch->timer); 4537 dch->timer.function = NULL; 4538 } 4539 4540 if (hc->ctype == HFC_TYPE_E1) { /* E1 */ 4541 /* remove sync */ 4542 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) { 4543 hc->syncronized = 0; 4544 plxsd_checksync(hc, 1); 4545 } 4546 /* free channels */ 4547 for (i = 0; i <= 31; i++) { 4548 if (hc->chan[i].bch) { 4549 if (debug & DEBUG_HFCMULTI_INIT) 4550 printk(KERN_DEBUG 4551 "%s: free port %d channel %d\n", 4552 __func__, hc->chan[i].port+1, i); 4553 pb = hc->chan[i].bch; 4554 hc->chan[i].bch = NULL; 4555 spin_unlock_irqrestore(&hc->lock, flags); 4556 mISDN_freebchannel(pb); 4557 kfree(pb); 4558 kfree(hc->chan[i].coeff); 4559 spin_lock_irqsave(&hc->lock, flags); 4560 } 4561 } 4562 } else { 4563 /* remove sync */ 4564 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) { 4565 hc->syncronized &= 4566 ~(1 << hc->chan[ci].port); 4567 plxsd_checksync(hc, 1); 4568 } 4569 /* free channels */ 4570 if (hc->chan[ci - 2].bch) { 4571 if (debug & DEBUG_HFCMULTI_INIT) 4572 printk(KERN_DEBUG 4573 "%s: free port %d channel %d\n", 4574 __func__, hc->chan[ci - 2].port+1, 4575 ci - 2); 4576 pb = hc->chan[ci - 2].bch; 4577 hc->chan[ci - 2].bch = NULL; 4578 spin_unlock_irqrestore(&hc->lock, flags); 4579 mISDN_freebchannel(pb); 4580 kfree(pb); 4581 kfree(hc->chan[ci - 2].coeff); 4582 spin_lock_irqsave(&hc->lock, flags); 4583 } 4584 if (hc->chan[ci - 1].bch) { 4585 if (debug & DEBUG_HFCMULTI_INIT) 4586 printk(KERN_DEBUG 4587 "%s: free port %d channel %d\n", 4588 __func__, hc->chan[ci - 1].port+1, 4589 ci - 1); 4590 pb = hc->chan[ci - 1].bch; 4591 hc->chan[ci - 1].bch = NULL; 4592 spin_unlock_irqrestore(&hc->lock, flags); 4593 mISDN_freebchannel(pb); 4594 kfree(pb); 4595 kfree(hc->chan[ci - 1].coeff); 4596 spin_lock_irqsave(&hc->lock, flags); 4597 } 4598 } 4599 4600 spin_unlock_irqrestore(&hc->lock, flags); 4601 4602 if (debug & DEBUG_HFCMULTI_INIT) 4603 printk(KERN_DEBUG "%s: free port %d channel D\n", __func__, pt); 4604 mISDN_freedchannel(dch); 4605 kfree(dch); 4606 4607 if (debug & DEBUG_HFCMULTI_INIT) 4608 printk(KERN_DEBUG "%s: done!\n", __func__); 4609 } 4610 4611 static void 4612 release_card(struct hfc_multi *hc) 4613 { 4614 u_long flags; 4615 int ch; 4616 4617 if (debug & DEBUG_HFCMULTI_INIT) 4618 printk(KERN_DEBUG "%s: release card (%d) entered\n", 4619 __func__, hc->id); 4620 4621 /* unregister clock source */ 4622 if (hc->iclock) 4623 mISDN_unregister_clock(hc->iclock); 4624 4625 /* disable irq */ 4626 spin_lock_irqsave(&hc->lock, flags); 4627 disable_hwirq(hc); 4628 spin_unlock_irqrestore(&hc->lock, flags); 4629 udelay(1000); 4630 4631 /* dimm leds */ 4632 if (hc->leds) 4633 hfcmulti_leds(hc); 4634 4635 /* disable D-channels & B-channels */ 4636 if (debug & DEBUG_HFCMULTI_INIT) 4637 printk(KERN_DEBUG "%s: disable all channels (d and b)\n", 4638 __func__); 4639 for (ch = 0; ch <= 31; ch++) { 4640 if (hc->chan[ch].dch) 4641 release_port(hc, hc->chan[ch].dch); 4642 } 4643 4644 /* release hardware & irq */ 4645 if (hc->irq) { 4646 if (debug & DEBUG_HFCMULTI_INIT) 4647 printk(KERN_DEBUG "%s: free irq %d\n", 4648 __func__, hc->irq); 4649 free_irq(hc->irq, hc); 4650 hc->irq = 0; 4651 4652 } 4653 release_io_hfcmulti(hc); 4654 4655 if (debug & DEBUG_HFCMULTI_INIT) 4656 printk(KERN_DEBUG "%s: remove instance from list\n", 4657 __func__); 4658 list_del(&hc->list); 4659 4660 if (debug & DEBUG_HFCMULTI_INIT) 4661 printk(KERN_DEBUG "%s: delete instance\n", __func__); 4662 if (hc == syncmaster) 4663 syncmaster = NULL; 4664 kfree(hc); 4665 if (debug & DEBUG_HFCMULTI_INIT) 4666 printk(KERN_DEBUG "%s: card successfully removed\n", 4667 __func__); 4668 } 4669 4670 static int 4671 init_e1_port(struct hfc_multi *hc, struct hm_map *m) 4672 { 4673 struct dchannel *dch; 4674 struct bchannel *bch; 4675 int ch, ret = 0; 4676 char name[MISDN_MAX_IDLEN]; 4677 4678 dch = kzalloc(sizeof(struct dchannel), GFP_KERNEL); 4679 if (!dch) 4680 return -ENOMEM; 4681 dch->debug = debug; 4682 mISDN_initdchannel(dch, MAX_DFRAME_LEN_L1, ph_state_change); 4683 dch->hw = hc; 4684 dch->dev.Dprotocols = (1 << ISDN_P_TE_E1) | (1 << ISDN_P_NT_E1); 4685 dch->dev.Bprotocols = (1 << (ISDN_P_B_RAW & ISDN_P_B_MASK)) | 4686 (1 << (ISDN_P_B_HDLC & ISDN_P_B_MASK)); 4687 dch->dev.D.send = handle_dmsg; 4688 dch->dev.D.ctrl = hfcm_dctrl; 4689 dch->dev.nrbchan = (hc->dslot) ? 30 : 31; 4690 dch->slot = hc->dslot; 4691 hc->chan[hc->dslot].dch = dch; 4692 hc->chan[hc->dslot].port = 0; 4693 hc->chan[hc->dslot].nt_timer = -1; 4694 for (ch = 1; ch <= 31; ch++) { 4695 if (ch == hc->dslot) /* skip dchannel */ 4696 continue; 4697 bch = kzalloc(sizeof(struct bchannel), GFP_KERNEL); 4698 if (!bch) { 4699 printk(KERN_ERR "%s: no memory for bchannel\n", 4700 __func__); 4701 ret = -ENOMEM; 4702 goto free_chan; 4703 } 4704 hc->chan[ch].coeff = kzalloc(512, GFP_KERNEL); 4705 if (!hc->chan[ch].coeff) { 4706 printk(KERN_ERR "%s: no memory for coeffs\n", 4707 __func__); 4708 ret = -ENOMEM; 4709 kfree(bch); 4710 goto free_chan; 4711 } 4712 bch->nr = ch; 4713 bch->slot = ch; 4714 bch->debug = debug; 4715 mISDN_initbchannel(bch, MAX_DATA_MEM); 4716 bch->hw = hc; 4717 bch->ch.send = handle_bmsg; 4718 bch->ch.ctrl = hfcm_bctrl; 4719 bch->ch.nr = ch; 4720 list_add(&bch->ch.list, &dch->dev.bchannels); 4721 hc->chan[ch].bch = bch; 4722 hc->chan[ch].port = 0; 4723 set_channelmap(bch->nr, dch->dev.channelmap); 4724 } 4725 /* set optical line type */ 4726 if (port[Port_cnt] & 0x001) { 4727 if (!m->opticalsupport) { 4728 printk(KERN_INFO 4729 "This board has no optical " 4730 "support\n"); 4731 } else { 4732 if (debug & DEBUG_HFCMULTI_INIT) 4733 printk(KERN_DEBUG 4734 "%s: PORT set optical " 4735 "interfacs: card(%d) " 4736 "port(%d)\n", 4737 __func__, 4738 HFC_cnt + 1, 1); 4739 test_and_set_bit(HFC_CFG_OPTICAL, 4740 &hc->chan[hc->dslot].cfg); 4741 } 4742 } 4743 /* set LOS report */ 4744 if (port[Port_cnt] & 0x004) { 4745 if (debug & DEBUG_HFCMULTI_INIT) 4746 printk(KERN_DEBUG "%s: PORT set " 4747 "LOS report: card(%d) port(%d)\n", 4748 __func__, HFC_cnt + 1, 1); 4749 test_and_set_bit(HFC_CFG_REPORT_LOS, 4750 &hc->chan[hc->dslot].cfg); 4751 } 4752 /* set AIS report */ 4753 if (port[Port_cnt] & 0x008) { 4754 if (debug & DEBUG_HFCMULTI_INIT) 4755 printk(KERN_DEBUG "%s: PORT set " 4756 "AIS report: card(%d) port(%d)\n", 4757 __func__, HFC_cnt + 1, 1); 4758 test_and_set_bit(HFC_CFG_REPORT_AIS, 4759 &hc->chan[hc->dslot].cfg); 4760 } 4761 /* set SLIP report */ 4762 if (port[Port_cnt] & 0x010) { 4763 if (debug & DEBUG_HFCMULTI_INIT) 4764 printk(KERN_DEBUG 4765 "%s: PORT set SLIP report: " 4766 "card(%d) port(%d)\n", 4767 __func__, HFC_cnt + 1, 1); 4768 test_and_set_bit(HFC_CFG_REPORT_SLIP, 4769 &hc->chan[hc->dslot].cfg); 4770 } 4771 /* set RDI report */ 4772 if (port[Port_cnt] & 0x020) { 4773 if (debug & DEBUG_HFCMULTI_INIT) 4774 printk(KERN_DEBUG 4775 "%s: PORT set RDI report: " 4776 "card(%d) port(%d)\n", 4777 __func__, HFC_cnt + 1, 1); 4778 test_and_set_bit(HFC_CFG_REPORT_RDI, 4779 &hc->chan[hc->dslot].cfg); 4780 } 4781 /* set CRC-4 Mode */ 4782 if (!(port[Port_cnt] & 0x100)) { 4783 if (debug & DEBUG_HFCMULTI_INIT) 4784 printk(KERN_DEBUG "%s: PORT turn on CRC4 report:" 4785 " card(%d) port(%d)\n", 4786 __func__, HFC_cnt + 1, 1); 4787 test_and_set_bit(HFC_CFG_CRC4, 4788 &hc->chan[hc->dslot].cfg); 4789 } else { 4790 if (debug & DEBUG_HFCMULTI_INIT) 4791 printk(KERN_DEBUG "%s: PORT turn off CRC4" 4792 " report: card(%d) port(%d)\n", 4793 __func__, HFC_cnt + 1, 1); 4794 } 4795 /* set forced clock */ 4796 if (port[Port_cnt] & 0x0200) { 4797 if (debug & DEBUG_HFCMULTI_INIT) 4798 printk(KERN_DEBUG "%s: PORT force getting clock from " 4799 "E1: card(%d) port(%d)\n", 4800 __func__, HFC_cnt + 1, 1); 4801 test_and_set_bit(HFC_CHIP_E1CLOCK_GET, &hc->chip); 4802 } else 4803 if (port[Port_cnt] & 0x0400) { 4804 if (debug & DEBUG_HFCMULTI_INIT) 4805 printk(KERN_DEBUG "%s: PORT force putting clock to " 4806 "E1: card(%d) port(%d)\n", 4807 __func__, HFC_cnt + 1, 1); 4808 test_and_set_bit(HFC_CHIP_E1CLOCK_PUT, &hc->chip); 4809 } 4810 /* set JATT PLL */ 4811 if (port[Port_cnt] & 0x0800) { 4812 if (debug & DEBUG_HFCMULTI_INIT) 4813 printk(KERN_DEBUG "%s: PORT disable JATT PLL on " 4814 "E1: card(%d) port(%d)\n", 4815 __func__, HFC_cnt + 1, 1); 4816 test_and_set_bit(HFC_CHIP_RX_SYNC, &hc->chip); 4817 } 4818 /* set elastic jitter buffer */ 4819 if (port[Port_cnt] & 0x3000) { 4820 hc->chan[hc->dslot].jitter = (port[Port_cnt]>>12) & 0x3; 4821 if (debug & DEBUG_HFCMULTI_INIT) 4822 printk(KERN_DEBUG 4823 "%s: PORT set elastic " 4824 "buffer to %d: card(%d) port(%d)\n", 4825 __func__, hc->chan[hc->dslot].jitter, 4826 HFC_cnt + 1, 1); 4827 } else 4828 hc->chan[hc->dslot].jitter = 2; /* default */ 4829 snprintf(name, MISDN_MAX_IDLEN - 1, "hfc-e1.%d", HFC_cnt + 1); 4830 ret = mISDN_register_device(&dch->dev, &hc->pci_dev->dev, name); 4831 if (ret) 4832 goto free_chan; 4833 hc->created[0] = 1; 4834 return ret; 4835 free_chan: 4836 release_port(hc, dch); 4837 return ret; 4838 } 4839 4840 static int 4841 init_multi_port(struct hfc_multi *hc, int pt) 4842 { 4843 struct dchannel *dch; 4844 struct bchannel *bch; 4845 int ch, i, ret = 0; 4846 char name[MISDN_MAX_IDLEN]; 4847 4848 dch = kzalloc(sizeof(struct dchannel), GFP_KERNEL); 4849 if (!dch) 4850 return -ENOMEM; 4851 dch->debug = debug; 4852 mISDN_initdchannel(dch, MAX_DFRAME_LEN_L1, ph_state_change); 4853 dch->hw = hc; 4854 dch->dev.Dprotocols = (1 << ISDN_P_TE_S0) | (1 << ISDN_P_NT_S0); 4855 dch->dev.Bprotocols = (1 << (ISDN_P_B_RAW & ISDN_P_B_MASK)) | 4856 (1 << (ISDN_P_B_HDLC & ISDN_P_B_MASK)); 4857 dch->dev.D.send = handle_dmsg; 4858 dch->dev.D.ctrl = hfcm_dctrl; 4859 dch->dev.nrbchan = 2; 4860 i = pt << 2; 4861 dch->slot = i + 2; 4862 hc->chan[i + 2].dch = dch; 4863 hc->chan[i + 2].port = pt; 4864 hc->chan[i + 2].nt_timer = -1; 4865 for (ch = 0; ch < dch->dev.nrbchan; ch++) { 4866 bch = kzalloc(sizeof(struct bchannel), GFP_KERNEL); 4867 if (!bch) { 4868 printk(KERN_ERR "%s: no memory for bchannel\n", 4869 __func__); 4870 ret = -ENOMEM; 4871 goto free_chan; 4872 } 4873 hc->chan[i + ch].coeff = kzalloc(512, GFP_KERNEL); 4874 if (!hc->chan[i + ch].coeff) { 4875 printk(KERN_ERR "%s: no memory for coeffs\n", 4876 __func__); 4877 ret = -ENOMEM; 4878 kfree(bch); 4879 goto free_chan; 4880 } 4881 bch->nr = ch + 1; 4882 bch->slot = i + ch; 4883 bch->debug = debug; 4884 mISDN_initbchannel(bch, MAX_DATA_MEM); 4885 bch->hw = hc; 4886 bch->ch.send = handle_bmsg; 4887 bch->ch.ctrl = hfcm_bctrl; 4888 bch->ch.nr = ch + 1; 4889 list_add(&bch->ch.list, &dch->dev.bchannels); 4890 hc->chan[i + ch].bch = bch; 4891 hc->chan[i + ch].port = pt; 4892 set_channelmap(bch->nr, dch->dev.channelmap); 4893 } 4894 /* set master clock */ 4895 if (port[Port_cnt] & 0x001) { 4896 if (debug & DEBUG_HFCMULTI_INIT) 4897 printk(KERN_DEBUG 4898 "%s: PROTOCOL set master clock: " 4899 "card(%d) port(%d)\n", 4900 __func__, HFC_cnt + 1, pt + 1); 4901 if (dch->dev.D.protocol != ISDN_P_TE_S0) { 4902 printk(KERN_ERR "Error: Master clock " 4903 "for port(%d) of card(%d) is only" 4904 " possible with TE-mode\n", 4905 pt + 1, HFC_cnt + 1); 4906 ret = -EINVAL; 4907 goto free_chan; 4908 } 4909 if (hc->masterclk >= 0) { 4910 printk(KERN_ERR "Error: Master clock " 4911 "for port(%d) of card(%d) already " 4912 "defined for port(%d)\n", 4913 pt + 1, HFC_cnt + 1, hc->masterclk+1); 4914 ret = -EINVAL; 4915 goto free_chan; 4916 } 4917 hc->masterclk = pt; 4918 } 4919 /* set transmitter line to non capacitive */ 4920 if (port[Port_cnt] & 0x002) { 4921 if (debug & DEBUG_HFCMULTI_INIT) 4922 printk(KERN_DEBUG 4923 "%s: PROTOCOL set non capacitive " 4924 "transmitter: card(%d) port(%d)\n", 4925 __func__, HFC_cnt + 1, pt + 1); 4926 test_and_set_bit(HFC_CFG_NONCAP_TX, 4927 &hc->chan[i + 2].cfg); 4928 } 4929 /* disable E-channel */ 4930 if (port[Port_cnt] & 0x004) { 4931 if (debug & DEBUG_HFCMULTI_INIT) 4932 printk(KERN_DEBUG 4933 "%s: PROTOCOL disable E-channel: " 4934 "card(%d) port(%d)\n", 4935 __func__, HFC_cnt + 1, pt + 1); 4936 test_and_set_bit(HFC_CFG_DIS_ECHANNEL, 4937 &hc->chan[i + 2].cfg); 4938 } 4939 if (hc->ctype == HFC_TYPE_XHFC) { 4940 snprintf(name, MISDN_MAX_IDLEN - 1, "xhfc.%d-%d", 4941 HFC_cnt + 1, pt + 1); 4942 ret = mISDN_register_device(&dch->dev, NULL, name); 4943 } else { 4944 snprintf(name, MISDN_MAX_IDLEN - 1, "hfc-%ds.%d-%d", 4945 hc->ctype, HFC_cnt + 1, pt + 1); 4946 ret = mISDN_register_device(&dch->dev, &hc->pci_dev->dev, name); 4947 } 4948 if (ret) 4949 goto free_chan; 4950 hc->created[pt] = 1; 4951 return ret; 4952 free_chan: 4953 release_port(hc, dch); 4954 return ret; 4955 } 4956 4957 static int 4958 hfcmulti_init(struct hm_map *m, struct pci_dev *pdev, 4959 const struct pci_device_id *ent) 4960 { 4961 int ret_err = 0; 4962 int pt; 4963 struct hfc_multi *hc; 4964 u_long flags; 4965 u_char dips = 0, pmj = 0; /* dip settings, port mode Jumpers */ 4966 int i; 4967 4968 if (HFC_cnt >= MAX_CARDS) { 4969 printk(KERN_ERR "too many cards (max=%d).\n", 4970 MAX_CARDS); 4971 return -EINVAL; 4972 } 4973 if ((type[HFC_cnt] & 0xff) && (type[HFC_cnt] & 0xff) != m->type) { 4974 printk(KERN_WARNING "HFC-MULTI: Card '%s:%s' type %d found but " 4975 "type[%d] %d was supplied as module parameter\n", 4976 m->vendor_name, m->card_name, m->type, HFC_cnt, 4977 type[HFC_cnt] & 0xff); 4978 printk(KERN_WARNING "HFC-MULTI: Load module without parameters " 4979 "first, to see cards and their types."); 4980 return -EINVAL; 4981 } 4982 if (debug & DEBUG_HFCMULTI_INIT) 4983 printk(KERN_DEBUG "%s: Registering %s:%s chip type %d (0x%x)\n", 4984 __func__, m->vendor_name, m->card_name, m->type, 4985 type[HFC_cnt]); 4986 4987 /* allocate card+fifo structure */ 4988 hc = kzalloc(sizeof(struct hfc_multi), GFP_KERNEL); 4989 if (!hc) { 4990 printk(KERN_ERR "No kmem for HFC-Multi card\n"); 4991 return -ENOMEM; 4992 } 4993 spin_lock_init(&hc->lock); 4994 hc->mtyp = m; 4995 hc->ctype = m->type; 4996 hc->ports = m->ports; 4997 hc->id = HFC_cnt; 4998 hc->pcm = pcm[HFC_cnt]; 4999 hc->io_mode = iomode[HFC_cnt]; 5000 if (dslot[HFC_cnt] < 0 && hc->ctype == HFC_TYPE_E1) { 5001 hc->dslot = 0; 5002 printk(KERN_INFO "HFC-E1 card has disabled D-channel, but " 5003 "31 B-channels\n"); 5004 } 5005 if (dslot[HFC_cnt] > 0 && dslot[HFC_cnt] < 32 5006 && hc->ctype == HFC_TYPE_E1) { 5007 hc->dslot = dslot[HFC_cnt]; 5008 printk(KERN_INFO "HFC-E1 card has alternating D-channel on " 5009 "time slot %d\n", dslot[HFC_cnt]); 5010 } else 5011 hc->dslot = 16; 5012 5013 /* set chip specific features */ 5014 hc->masterclk = -1; 5015 if (type[HFC_cnt] & 0x100) { 5016 test_and_set_bit(HFC_CHIP_ULAW, &hc->chip); 5017 hc->silence = 0xff; /* ulaw silence */ 5018 } else 5019 hc->silence = 0x2a; /* alaw silence */ 5020 if ((poll >> 1) > sizeof(hc->silence_data)) { 5021 printk(KERN_ERR "HFCMULTI error: silence_data too small, " 5022 "please fix\n"); 5023 return -EINVAL; 5024 } 5025 for (i = 0; i < (poll >> 1); i++) 5026 hc->silence_data[i] = hc->silence; 5027 5028 if (hc->ctype != HFC_TYPE_XHFC) { 5029 if (!(type[HFC_cnt] & 0x200)) 5030 test_and_set_bit(HFC_CHIP_DTMF, &hc->chip); 5031 test_and_set_bit(HFC_CHIP_CONF, &hc->chip); 5032 } 5033 5034 if (type[HFC_cnt] & 0x800) 5035 test_and_set_bit(HFC_CHIP_PCM_SLAVE, &hc->chip); 5036 if (type[HFC_cnt] & 0x1000) { 5037 test_and_set_bit(HFC_CHIP_PCM_MASTER, &hc->chip); 5038 test_and_clear_bit(HFC_CHIP_PCM_SLAVE, &hc->chip); 5039 } 5040 if (type[HFC_cnt] & 0x4000) 5041 test_and_set_bit(HFC_CHIP_EXRAM_128, &hc->chip); 5042 if (type[HFC_cnt] & 0x8000) 5043 test_and_set_bit(HFC_CHIP_EXRAM_512, &hc->chip); 5044 hc->slots = 32; 5045 if (type[HFC_cnt] & 0x10000) 5046 hc->slots = 64; 5047 if (type[HFC_cnt] & 0x20000) 5048 hc->slots = 128; 5049 if (type[HFC_cnt] & 0x80000) { 5050 test_and_set_bit(HFC_CHIP_WATCHDOG, &hc->chip); 5051 hc->wdcount = 0; 5052 hc->wdbyte = V_GPIO_OUT2; 5053 printk(KERN_NOTICE "Watchdog enabled\n"); 5054 } 5055 5056 if (pdev && ent) 5057 /* setup pci, hc->slots may change due to PLXSD */ 5058 ret_err = setup_pci(hc, pdev, ent); 5059 else 5060 #ifdef CONFIG_MISDN_HFCMULTI_8xx 5061 ret_err = setup_embedded(hc, m); 5062 #else 5063 { 5064 printk(KERN_WARNING "Embedded IO Mode not selected\n"); 5065 ret_err = -EIO; 5066 } 5067 #endif 5068 if (ret_err) { 5069 if (hc == syncmaster) 5070 syncmaster = NULL; 5071 kfree(hc); 5072 return ret_err; 5073 } 5074 5075 hc->HFC_outb_nodebug = hc->HFC_outb; 5076 hc->HFC_inb_nodebug = hc->HFC_inb; 5077 hc->HFC_inw_nodebug = hc->HFC_inw; 5078 hc->HFC_wait_nodebug = hc->HFC_wait; 5079 #ifdef HFC_REGISTER_DEBUG 5080 hc->HFC_outb = HFC_outb_debug; 5081 hc->HFC_inb = HFC_inb_debug; 5082 hc->HFC_inw = HFC_inw_debug; 5083 hc->HFC_wait = HFC_wait_debug; 5084 #endif 5085 /* create channels */ 5086 for (pt = 0; pt < hc->ports; pt++) { 5087 if (Port_cnt >= MAX_PORTS) { 5088 printk(KERN_ERR "too many ports (max=%d).\n", 5089 MAX_PORTS); 5090 ret_err = -EINVAL; 5091 goto free_card; 5092 } 5093 if (hc->ctype == HFC_TYPE_E1) 5094 ret_err = init_e1_port(hc, m); 5095 else 5096 ret_err = init_multi_port(hc, pt); 5097 if (debug & DEBUG_HFCMULTI_INIT) 5098 printk(KERN_DEBUG 5099 "%s: Registering D-channel, card(%d) port(%d)" 5100 "result %d\n", 5101 __func__, HFC_cnt + 1, pt, ret_err); 5102 5103 if (ret_err) { 5104 while (pt) { /* release already registered ports */ 5105 pt--; 5106 release_port(hc, hc->chan[(pt << 2) + 2].dch); 5107 } 5108 goto free_card; 5109 } 5110 Port_cnt++; 5111 } 5112 5113 /* disp switches */ 5114 switch (m->dip_type) { 5115 case DIP_4S: 5116 /* 5117 * Get DIP setting for beroNet 1S/2S/4S cards 5118 * DIP Setting: (collect GPIO 13/14/15 (R_GPIO_IN1) + 5119 * GPI 19/23 (R_GPI_IN2)) 5120 */ 5121 dips = ((~HFC_inb(hc, R_GPIO_IN1) & 0xE0) >> 5) | 5122 ((~HFC_inb(hc, R_GPI_IN2) & 0x80) >> 3) | 5123 (~HFC_inb(hc, R_GPI_IN2) & 0x08); 5124 5125 /* Port mode (TE/NT) jumpers */ 5126 pmj = ((HFC_inb(hc, R_GPI_IN3) >> 4) & 0xf); 5127 5128 if (test_bit(HFC_CHIP_B410P, &hc->chip)) 5129 pmj = ~pmj & 0xf; 5130 5131 printk(KERN_INFO "%s: %s DIPs(0x%x) jumpers(0x%x)\n", 5132 m->vendor_name, m->card_name, dips, pmj); 5133 break; 5134 case DIP_8S: 5135 /* 5136 * Get DIP Setting for beroNet 8S0+ cards 5137 * Enable PCI auxbridge function 5138 */ 5139 HFC_outb(hc, R_BRG_PCM_CFG, 1 | V_PCM_CLK); 5140 /* prepare access to auxport */ 5141 outw(0x4000, hc->pci_iobase + 4); 5142 /* 5143 * some dummy reads are required to 5144 * read valid DIP switch data 5145 */ 5146 dips = inb(hc->pci_iobase); 5147 dips = inb(hc->pci_iobase); 5148 dips = inb(hc->pci_iobase); 5149 dips = ~inb(hc->pci_iobase) & 0x3F; 5150 outw(0x0, hc->pci_iobase + 4); 5151 /* disable PCI auxbridge function */ 5152 HFC_outb(hc, R_BRG_PCM_CFG, V_PCM_CLK); 5153 printk(KERN_INFO "%s: %s DIPs(0x%x)\n", 5154 m->vendor_name, m->card_name, dips); 5155 break; 5156 case DIP_E1: 5157 /* 5158 * get DIP Setting for beroNet E1 cards 5159 * DIP Setting: collect GPI 4/5/6/7 (R_GPI_IN0) 5160 */ 5161 dips = (~HFC_inb(hc, R_GPI_IN0) & 0xF0)>>4; 5162 printk(KERN_INFO "%s: %s DIPs(0x%x)\n", 5163 m->vendor_name, m->card_name, dips); 5164 break; 5165 } 5166 5167 /* add to list */ 5168 spin_lock_irqsave(&HFClock, flags); 5169 list_add_tail(&hc->list, &HFClist); 5170 spin_unlock_irqrestore(&HFClock, flags); 5171 5172 /* use as clock source */ 5173 if (clock == HFC_cnt + 1) 5174 hc->iclock = mISDN_register_clock("HFCMulti", 0, clockctl, hc); 5175 5176 /* initialize hardware */ 5177 hc->irq = (m->irq) ? : hc->pci_dev->irq; 5178 ret_err = init_card(hc); 5179 if (ret_err) { 5180 printk(KERN_ERR "init card returns %d\n", ret_err); 5181 release_card(hc); 5182 return ret_err; 5183 } 5184 5185 /* start IRQ and return */ 5186 spin_lock_irqsave(&hc->lock, flags); 5187 enable_hwirq(hc); 5188 spin_unlock_irqrestore(&hc->lock, flags); 5189 return 0; 5190 5191 free_card: 5192 release_io_hfcmulti(hc); 5193 if (hc == syncmaster) 5194 syncmaster = NULL; 5195 kfree(hc); 5196 return ret_err; 5197 } 5198 5199 static void __devexit hfc_remove_pci(struct pci_dev *pdev) 5200 { 5201 struct hfc_multi *card = pci_get_drvdata(pdev); 5202 u_long flags; 5203 5204 if (debug) 5205 printk(KERN_INFO "removing hfc_multi card vendor:%x " 5206 "device:%x subvendor:%x subdevice:%x\n", 5207 pdev->vendor, pdev->device, 5208 pdev->subsystem_vendor, pdev->subsystem_device); 5209 5210 if (card) { 5211 spin_lock_irqsave(&HFClock, flags); 5212 release_card(card); 5213 spin_unlock_irqrestore(&HFClock, flags); 5214 } else { 5215 if (debug) 5216 printk(KERN_DEBUG "%s: drvdata already removed\n", 5217 __func__); 5218 } 5219 } 5220 5221 #define VENDOR_CCD "Cologne Chip AG" 5222 #define VENDOR_BN "beroNet GmbH" 5223 #define VENDOR_DIG "Digium Inc." 5224 #define VENDOR_JH "Junghanns.NET GmbH" 5225 #define VENDOR_PRIM "PrimuX" 5226 5227 static const struct hm_map hfcm_map[] = { 5228 /*0*/ {VENDOR_BN, "HFC-1S Card (mini PCI)", 4, 1, 1, 3, 0, DIP_4S, 0, 0}, 5229 /*1*/ {VENDOR_BN, "HFC-2S Card", 4, 2, 1, 3, 0, DIP_4S, 0, 0}, 5230 /*2*/ {VENDOR_BN, "HFC-2S Card (mini PCI)", 4, 2, 1, 3, 0, DIP_4S, 0, 0}, 5231 /*3*/ {VENDOR_BN, "HFC-4S Card", 4, 4, 1, 2, 0, DIP_4S, 0, 0}, 5232 /*4*/ {VENDOR_BN, "HFC-4S Card (mini PCI)", 4, 4, 1, 2, 0, 0, 0, 0}, 5233 /*5*/ {VENDOR_CCD, "HFC-4S Eval (old)", 4, 4, 0, 0, 0, 0, 0, 0}, 5234 /*6*/ {VENDOR_CCD, "HFC-4S IOB4ST", 4, 4, 1, 2, 0, DIP_4S, 0, 0}, 5235 /*7*/ {VENDOR_CCD, "HFC-4S", 4, 4, 1, 2, 0, 0, 0, 0}, 5236 /*8*/ {VENDOR_DIG, "HFC-4S Card", 4, 4, 0, 2, 0, 0, HFC_IO_MODE_REGIO, 0}, 5237 /*9*/ {VENDOR_CCD, "HFC-4S Swyx 4xS0 SX2 QuadBri", 4, 4, 1, 2, 0, 0, 0, 0}, 5238 /*10*/ {VENDOR_JH, "HFC-4S (junghanns 2.0)", 4, 4, 1, 2, 0, 0, 0, 0}, 5239 /*11*/ {VENDOR_PRIM, "HFC-2S Primux Card", 4, 2, 0, 0, 0, 0, 0, 0}, 5240 5241 /*12*/ {VENDOR_BN, "HFC-8S Card", 8, 8, 1, 0, 0, 0, 0, 0}, 5242 /*13*/ {VENDOR_BN, "HFC-8S Card (+)", 8, 8, 1, 8, 0, DIP_8S, 5243 HFC_IO_MODE_REGIO, 0}, 5244 /*14*/ {VENDOR_CCD, "HFC-8S Eval (old)", 8, 8, 0, 0, 0, 0, 0, 0}, 5245 /*15*/ {VENDOR_CCD, "HFC-8S IOB4ST Recording", 8, 8, 1, 0, 0, 0, 0, 0}, 5246 5247 /*16*/ {VENDOR_CCD, "HFC-8S IOB8ST", 8, 8, 1, 0, 0, 0, 0, 0}, 5248 /*17*/ {VENDOR_CCD, "HFC-8S", 8, 8, 1, 0, 0, 0, 0, 0}, 5249 /*18*/ {VENDOR_CCD, "HFC-8S", 8, 8, 1, 0, 0, 0, 0, 0}, 5250 5251 /*19*/ {VENDOR_BN, "HFC-E1 Card", 1, 1, 0, 1, 0, DIP_E1, 0, 0}, 5252 /*20*/ {VENDOR_BN, "HFC-E1 Card (mini PCI)", 1, 1, 0, 1, 0, 0, 0, 0}, 5253 /*21*/ {VENDOR_BN, "HFC-E1+ Card (Dual)", 1, 1, 0, 1, 0, DIP_E1, 0, 0}, 5254 /*22*/ {VENDOR_BN, "HFC-E1 Card (Dual)", 1, 1, 0, 1, 0, DIP_E1, 0, 0}, 5255 5256 /*23*/ {VENDOR_CCD, "HFC-E1 Eval (old)", 1, 1, 0, 0, 0, 0, 0, 0}, 5257 /*24*/ {VENDOR_CCD, "HFC-E1 IOB1E1", 1, 1, 0, 1, 0, 0, 0, 0}, 5258 /*25*/ {VENDOR_CCD, "HFC-E1", 1, 1, 0, 1, 0, 0, 0, 0}, 5259 5260 /*26*/ {VENDOR_CCD, "HFC-4S Speech Design", 4, 4, 0, 0, 0, 0, 5261 HFC_IO_MODE_PLXSD, 0}, 5262 /*27*/ {VENDOR_CCD, "HFC-E1 Speech Design", 1, 1, 0, 0, 0, 0, 5263 HFC_IO_MODE_PLXSD, 0}, 5264 /*28*/ {VENDOR_CCD, "HFC-4S OpenVox", 4, 4, 1, 0, 0, 0, 0, 0}, 5265 /*29*/ {VENDOR_CCD, "HFC-2S OpenVox", 4, 2, 1, 0, 0, 0, 0, 0}, 5266 /*30*/ {VENDOR_CCD, "HFC-8S OpenVox", 8, 8, 1, 0, 0, 0, 0, 0}, 5267 /*31*/ {VENDOR_CCD, "XHFC-4S Speech Design", 5, 4, 0, 0, 0, 0, 5268 HFC_IO_MODE_EMBSD, XHFC_IRQ}, 5269 /*32*/ {VENDOR_JH, "HFC-8S (junghanns)", 8, 8, 1, 0, 0, 0, 0, 0}, 5270 /*33*/ {VENDOR_BN, "HFC-2S Beronet Card PCIe", 4, 2, 1, 3, 0, DIP_4S, 0, 0}, 5271 /*34*/ {VENDOR_BN, "HFC-4S Beronet Card PCIe", 4, 4, 1, 2, 0, DIP_4S, 0, 0}, 5272 }; 5273 5274 #undef H 5275 #define H(x) ((unsigned long)&hfcm_map[x]) 5276 static struct pci_device_id hfmultipci_ids[] __devinitdata = { 5277 5278 /* Cards with HFC-4S Chip */ 5279 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD, 5280 PCI_SUBDEVICE_ID_CCD_BN1SM, 0, 0, H(0)}, /* BN1S mini PCI */ 5281 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD, 5282 PCI_SUBDEVICE_ID_CCD_BN2S, 0, 0, H(1)}, /* BN2S */ 5283 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD, 5284 PCI_SUBDEVICE_ID_CCD_BN2SM, 0, 0, H(2)}, /* BN2S mini PCI */ 5285 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD, 5286 PCI_SUBDEVICE_ID_CCD_BN4S, 0, 0, H(3)}, /* BN4S */ 5287 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD, 5288 PCI_SUBDEVICE_ID_CCD_BN4SM, 0, 0, H(4)}, /* BN4S mini PCI */ 5289 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD, 5290 PCI_DEVICE_ID_CCD_HFC4S, 0, 0, H(5)}, /* Old Eval */ 5291 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD, 5292 PCI_SUBDEVICE_ID_CCD_IOB4ST, 0, 0, H(6)}, /* IOB4ST */ 5293 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD, 5294 PCI_SUBDEVICE_ID_CCD_HFC4S, 0, 0, H(7)}, /* 4S */ 5295 { PCI_VENDOR_ID_DIGIUM, PCI_DEVICE_ID_DIGIUM_HFC4S, 5296 PCI_VENDOR_ID_DIGIUM, PCI_DEVICE_ID_DIGIUM_HFC4S, 0, 0, H(8)}, 5297 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD, 5298 PCI_SUBDEVICE_ID_CCD_SWYX4S, 0, 0, H(9)}, /* 4S Swyx */ 5299 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD, 5300 PCI_SUBDEVICE_ID_CCD_JH4S20, 0, 0, H(10)}, 5301 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD, 5302 PCI_SUBDEVICE_ID_CCD_PMX2S, 0, 0, H(11)}, /* Primux */ 5303 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD, 5304 PCI_SUBDEVICE_ID_CCD_OV4S, 0, 0, H(28)}, /* OpenVox 4 */ 5305 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD, 5306 PCI_SUBDEVICE_ID_CCD_OV2S, 0, 0, H(29)}, /* OpenVox 2 */ 5307 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD, 5308 0xb761, 0, 0, H(33)}, /* BN2S PCIe */ 5309 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD, 5310 0xb762, 0, 0, H(34)}, /* BN4S PCIe */ 5311 5312 /* Cards with HFC-8S Chip */ 5313 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD, 5314 PCI_SUBDEVICE_ID_CCD_BN8S, 0, 0, H(12)}, /* BN8S */ 5315 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD, 5316 PCI_SUBDEVICE_ID_CCD_BN8SP, 0, 0, H(13)}, /* BN8S+ */ 5317 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD, 5318 PCI_DEVICE_ID_CCD_HFC8S, 0, 0, H(14)}, /* old Eval */ 5319 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD, 5320 PCI_SUBDEVICE_ID_CCD_IOB8STR, 0, 0, H(15)}, /* IOB8ST Recording */ 5321 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD, 5322 PCI_SUBDEVICE_ID_CCD_IOB8ST, 0, 0, H(16)}, /* IOB8ST */ 5323 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD, 5324 PCI_SUBDEVICE_ID_CCD_IOB8ST_1, 0, 0, H(17)}, /* IOB8ST */ 5325 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD, 5326 PCI_SUBDEVICE_ID_CCD_HFC8S, 0, 0, H(18)}, /* 8S */ 5327 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD, 5328 PCI_SUBDEVICE_ID_CCD_OV8S, 0, 0, H(30)}, /* OpenVox 8 */ 5329 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD, 5330 PCI_SUBDEVICE_ID_CCD_JH8S, 0, 0, H(32)}, /* Junganns 8S */ 5331 5332 5333 /* Cards with HFC-E1 Chip */ 5334 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD, 5335 PCI_SUBDEVICE_ID_CCD_BNE1, 0, 0, H(19)}, /* BNE1 */ 5336 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD, 5337 PCI_SUBDEVICE_ID_CCD_BNE1M, 0, 0, H(20)}, /* BNE1 mini PCI */ 5338 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD, 5339 PCI_SUBDEVICE_ID_CCD_BNE1DP, 0, 0, H(21)}, /* BNE1 + (Dual) */ 5340 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD, 5341 PCI_SUBDEVICE_ID_CCD_BNE1D, 0, 0, H(22)}, /* BNE1 (Dual) */ 5342 5343 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD, 5344 PCI_DEVICE_ID_CCD_HFCE1, 0, 0, H(23)}, /* Old Eval */ 5345 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD, 5346 PCI_SUBDEVICE_ID_CCD_IOB1E1, 0, 0, H(24)}, /* IOB1E1 */ 5347 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD, 5348 PCI_SUBDEVICE_ID_CCD_HFCE1, 0, 0, H(25)}, /* E1 */ 5349 5350 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, PCI_VENDOR_ID_CCD, 5351 PCI_SUBDEVICE_ID_CCD_SPD4S, 0, 0, H(26)}, /* PLX PCI Bridge */ 5352 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, PCI_VENDOR_ID_CCD, 5353 PCI_SUBDEVICE_ID_CCD_SPDE1, 0, 0, H(27)}, /* PLX PCI Bridge */ 5354 5355 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD, 5356 PCI_SUBDEVICE_ID_CCD_JHSE1, 0, 0, H(25)}, /* Junghanns E1 */ 5357 5358 { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_HFC4S), 0 }, 5359 { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_HFC8S), 0 }, 5360 { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_HFCE1), 0 }, 5361 {0, } 5362 }; 5363 #undef H 5364 5365 MODULE_DEVICE_TABLE(pci, hfmultipci_ids); 5366 5367 static int 5368 hfcmulti_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 5369 { 5370 struct hm_map *m = (struct hm_map *)ent->driver_data; 5371 int ret; 5372 5373 if (m == NULL && ent->vendor == PCI_VENDOR_ID_CCD && ( 5374 ent->device == PCI_DEVICE_ID_CCD_HFC4S || 5375 ent->device == PCI_DEVICE_ID_CCD_HFC8S || 5376 ent->device == PCI_DEVICE_ID_CCD_HFCE1)) { 5377 printk(KERN_ERR 5378 "Unknown HFC multiport controller (vendor:%04x device:%04x " 5379 "subvendor:%04x subdevice:%04x)\n", pdev->vendor, 5380 pdev->device, pdev->subsystem_vendor, 5381 pdev->subsystem_device); 5382 printk(KERN_ERR 5383 "Please contact the driver maintainer for support.\n"); 5384 return -ENODEV; 5385 } 5386 ret = hfcmulti_init(m, pdev, ent); 5387 if (ret) 5388 return ret; 5389 HFC_cnt++; 5390 printk(KERN_INFO "%d devices registered\n", HFC_cnt); 5391 return 0; 5392 } 5393 5394 static struct pci_driver hfcmultipci_driver = { 5395 .name = "hfc_multi", 5396 .probe = hfcmulti_probe, 5397 .remove = __devexit_p(hfc_remove_pci), 5398 .id_table = hfmultipci_ids, 5399 }; 5400 5401 static void __exit 5402 HFCmulti_cleanup(void) 5403 { 5404 struct hfc_multi *card, *next; 5405 5406 /* get rid of all devices of this driver */ 5407 list_for_each_entry_safe(card, next, &HFClist, list) 5408 release_card(card); 5409 pci_unregister_driver(&hfcmultipci_driver); 5410 } 5411 5412 static int __init 5413 HFCmulti_init(void) 5414 { 5415 int err; 5416 int i, xhfc = 0; 5417 struct hm_map m; 5418 5419 printk(KERN_INFO "mISDN: HFC-multi driver %s\n", HFC_MULTI_VERSION); 5420 5421 #ifdef IRQ_DEBUG 5422 printk(KERN_DEBUG "%s: IRQ_DEBUG IS ENABLED!\n", __func__); 5423 #endif 5424 5425 spin_lock_init(&HFClock); 5426 spin_lock_init(&plx_lock); 5427 5428 if (debug & DEBUG_HFCMULTI_INIT) 5429 printk(KERN_DEBUG "%s: init entered\n", __func__); 5430 5431 switch (poll) { 5432 case 0: 5433 poll_timer = 6; 5434 poll = 128; 5435 break; 5436 case 8: 5437 poll_timer = 2; 5438 break; 5439 case 16: 5440 poll_timer = 3; 5441 break; 5442 case 32: 5443 poll_timer = 4; 5444 break; 5445 case 64: 5446 poll_timer = 5; 5447 break; 5448 case 128: 5449 poll_timer = 6; 5450 break; 5451 case 256: 5452 poll_timer = 7; 5453 break; 5454 default: 5455 printk(KERN_ERR 5456 "%s: Wrong poll value (%d).\n", __func__, poll); 5457 err = -EINVAL; 5458 return err; 5459 5460 } 5461 5462 if (!clock) 5463 clock = 1; 5464 5465 /* Register the embedded devices. 5466 * This should be done before the PCI cards registration */ 5467 switch (hwid) { 5468 case HWID_MINIP4: 5469 xhfc = 1; 5470 m = hfcm_map[31]; 5471 break; 5472 case HWID_MINIP8: 5473 xhfc = 2; 5474 m = hfcm_map[31]; 5475 break; 5476 case HWID_MINIP16: 5477 xhfc = 4; 5478 m = hfcm_map[31]; 5479 break; 5480 default: 5481 xhfc = 0; 5482 } 5483 5484 for (i = 0; i < xhfc; ++i) { 5485 err = hfcmulti_init(&m, NULL, NULL); 5486 if (err) { 5487 printk(KERN_ERR "error registering embedded driver: " 5488 "%x\n", err); 5489 return err; 5490 } 5491 HFC_cnt++; 5492 printk(KERN_INFO "%d devices registered\n", HFC_cnt); 5493 } 5494 5495 /* Register the PCI cards */ 5496 err = pci_register_driver(&hfcmultipci_driver); 5497 if (err < 0) { 5498 printk(KERN_ERR "error registering pci driver: %x\n", err); 5499 return err; 5500 } 5501 5502 return 0; 5503 } 5504 5505 5506 module_init(HFCmulti_init); 5507 module_exit(HFCmulti_cleanup); 5508