1 /* 2 * hfcmulti.c low level driver for hfc-4s/hfc-8s/hfc-e1 based cards 3 * 4 * Author Andreas Eversberg (jolly@eversberg.eu) 5 * ported to mqueue mechanism: 6 * Peter Sprenger (sprengermoving-bytes.de) 7 * 8 * inspired by existing hfc-pci driver: 9 * Copyright 1999 by Werner Cornelius (werner@isdn-development.de) 10 * Copyright 2008 by Karsten Keil (kkeil@suse.de) 11 * Copyright 2008 by Andreas Eversberg (jolly@eversberg.eu) 12 * 13 * This program is free software; you can redistribute it and/or modify 14 * it under the terms of the GNU General Public License as published by 15 * the Free Software Foundation; either version 2, or (at your option) 16 * any later version. 17 * 18 * This program is distributed in the hope that it will be useful, 19 * but WITHOUT ANY WARRANTY; without even the implied warranty of 20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 * GNU General Public License for more details. 22 * 23 * You should have received a copy of the GNU General Public License 24 * along with this program; if not, write to the Free Software 25 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 26 * 27 * 28 * Thanks to Cologne Chip AG for this great controller! 29 */ 30 31 /* 32 * module parameters: 33 * type: 34 * By default (0), the card is automatically detected. 35 * Or use the following combinations: 36 * Bit 0-7 = 0x00001 = HFC-E1 (1 port) 37 * or Bit 0-7 = 0x00004 = HFC-4S (4 ports) 38 * or Bit 0-7 = 0x00008 = HFC-8S (8 ports) 39 * Bit 8 = 0x00100 = uLaw (instead of aLaw) 40 * Bit 9 = 0x00200 = Disable DTMF detect on all B-channels via hardware 41 * Bit 10 = spare 42 * Bit 11 = 0x00800 = Force PCM bus into slave mode. (otherwhise auto) 43 * or Bit 12 = 0x01000 = Force PCM bus into master mode. (otherwhise auto) 44 * Bit 13 = spare 45 * Bit 14 = 0x04000 = Use external ram (128K) 46 * Bit 15 = 0x08000 = Use external ram (512K) 47 * Bit 16 = 0x10000 = Use 64 timeslots instead of 32 48 * or Bit 17 = 0x20000 = Use 128 timeslots instead of anything else 49 * Bit 18 = spare 50 * Bit 19 = 0x80000 = Send the Watchdog a Signal (Dual E1 with Watchdog) 51 * (all other bits are reserved and shall be 0) 52 * example: 0x20204 one HFC-4S with dtmf detection and 128 timeslots on PCM 53 * bus (PCM master) 54 * 55 * port: (optional or required for all ports on all installed cards) 56 * HFC-4S/HFC-8S only bits: 57 * Bit 0 = 0x001 = Use master clock for this S/T interface 58 * (ony once per chip). 59 * Bit 1 = 0x002 = transmitter line setup (non capacitive mode) 60 * Don't use this unless you know what you are doing! 61 * Bit 2 = 0x004 = Disable E-channel. (No E-channel processing) 62 * example: 0x0001,0x0000,0x0000,0x0000 one HFC-4S with master clock 63 * received from port 1 64 * 65 * HFC-E1 only bits: 66 * Bit 0 = 0x0001 = interface: 0=copper, 1=optical 67 * Bit 1 = 0x0002 = reserved (later for 32 B-channels transparent mode) 68 * Bit 2 = 0x0004 = Report LOS 69 * Bit 3 = 0x0008 = Report AIS 70 * Bit 4 = 0x0010 = Report SLIP 71 * Bit 5 = 0x0020 = Report RDI 72 * Bit 8 = 0x0100 = Turn off CRC-4 Multiframe Mode, use double frame 73 * mode instead. 74 * Bit 9 = 0x0200 = Force get clock from interface, even in NT mode. 75 * or Bit 10 = 0x0400 = Force put clock to interface, even in TE mode. 76 * Bit 11 = 0x0800 = Use direct RX clock for PCM sync rather than PLL. 77 * (E1 only) 78 * Bit 12-13 = 0xX000 = elastic jitter buffer (1-3), Set both bits to 0 79 * for default. 80 * (all other bits are reserved and shall be 0) 81 * 82 * debug: 83 * NOTE: only one debug value must be given for all cards 84 * enable debugging (see hfc_multi.h for debug options) 85 * 86 * poll: 87 * NOTE: only one poll value must be given for all cards 88 * Give the number of samples for each fifo process. 89 * By default 128 is used. Decrease to reduce delay, increase to 90 * reduce cpu load. If unsure, don't mess with it! 91 * Valid is 8, 16, 32, 64, 128, 256. 92 * 93 * pcm: 94 * NOTE: only one pcm value must be given for every card. 95 * The PCM bus id tells the mISDNdsp module about the connected PCM bus. 96 * By default (0), the PCM bus id is 100 for the card that is PCM master. 97 * If multiple cards are PCM master (because they are not interconnected), 98 * each card with PCM master will have increasing PCM id. 99 * All PCM busses with the same ID are expected to be connected and have 100 * common time slots slots. 101 * Only one chip of the PCM bus must be master, the others slave. 102 * -1 means no support of PCM bus not even. 103 * Omit this value, if all cards are interconnected or none is connected. 104 * If unsure, don't give this parameter. 105 * 106 * dmask and bmask: 107 * NOTE: One dmask value must be given for every HFC-E1 card. 108 * If omitted, the E1 card has D-channel on time slot 16, which is default. 109 * dmask is a 32 bit mask. The bit must be set for an alternate time slot. 110 * If multiple bits are set, multiple virtual card fragments are created. 111 * For each bit set, a bmask value must be given. Each bit on the bmask 112 * value stands for a B-channel. The bmask may not overlap with dmask or 113 * with other bmask values for that card. 114 * Example: dmask=0x00020002 bmask=0x0000fffc,0xfffc0000 115 * This will create one fragment with D-channel on slot 1 with 116 * B-channels on slots 2..15, and a second fragment with D-channel 117 * on slot 17 with B-channels on slot 18..31. Slot 16 is unused. 118 * If bit 0 is set (dmask=0x00000001) the D-channel is on slot 0 and will 119 * not function. 120 * Example: dmask=0x00000001 bmask=0xfffffffe 121 * This will create a port with all 31 usable timeslots as 122 * B-channels. 123 * If no bits are set on bmask, no B-channel is created for that fragment. 124 * Example: dmask=0xfffffffe bmask=0,0,0,0.... (31 0-values for bmask) 125 * This will create 31 ports with one D-channel only. 126 * If you don't know how to use it, you don't need it! 127 * 128 * iomode: 129 * NOTE: only one mode value must be given for every card. 130 * -> See hfc_multi.h for HFC_IO_MODE_* values 131 * By default, the IO mode is pci memory IO (MEMIO). 132 * Some cards require specific IO mode, so it cannot be changed. 133 * It may be useful to set IO mode to register io (REGIO) to solve 134 * PCI bridge problems. 135 * If unsure, don't give this parameter. 136 * 137 * clockdelay_nt: 138 * NOTE: only one clockdelay_nt value must be given once for all cards. 139 * Give the value of the clock control register (A_ST_CLK_DLY) 140 * of the S/T interfaces in NT mode. 141 * This register is needed for the TBR3 certification, so don't change it. 142 * 143 * clockdelay_te: 144 * NOTE: only one clockdelay_te value must be given once 145 * Give the value of the clock control register (A_ST_CLK_DLY) 146 * of the S/T interfaces in TE mode. 147 * This register is needed for the TBR3 certification, so don't change it. 148 * 149 * clock: 150 * NOTE: only one clock value must be given once 151 * Selects interface with clock source for mISDN and applications. 152 * Set to card number starting with 1. Set to -1 to disable. 153 * By default, the first card is used as clock source. 154 * 155 * hwid: 156 * NOTE: only one hwid value must be given once 157 * Enable special embedded devices with XHFC controllers. 158 */ 159 160 /* 161 * debug register access (never use this, it will flood your system log) 162 * #define HFC_REGISTER_DEBUG 163 */ 164 165 #define HFC_MULTI_VERSION "2.03" 166 167 #include <linux/interrupt.h> 168 #include <linux/module.h> 169 #include <linux/slab.h> 170 #include <linux/pci.h> 171 #include <linux/delay.h> 172 #include <linux/mISDNhw.h> 173 #include <linux/mISDNdsp.h> 174 175 /* 176 #define IRQCOUNT_DEBUG 177 #define IRQ_DEBUG 178 */ 179 180 #include "hfc_multi.h" 181 #ifdef ECHOPREP 182 #include "gaintab.h" 183 #endif 184 185 #define MAX_CARDS 8 186 #define MAX_PORTS (8 * MAX_CARDS) 187 #define MAX_FRAGS (32 * MAX_CARDS) 188 189 static LIST_HEAD(HFClist); 190 static spinlock_t HFClock; /* global hfc list lock */ 191 192 static void ph_state_change(struct dchannel *); 193 194 static struct hfc_multi *syncmaster; 195 static int plxsd_master; /* if we have a master card (yet) */ 196 static spinlock_t plx_lock; /* may not acquire other lock inside */ 197 198 #define TYP_E1 1 199 #define TYP_4S 4 200 #define TYP_8S 8 201 202 static int poll_timer = 6; /* default = 128 samples = 16ms */ 203 /* number of POLL_TIMER interrupts for G2 timeout (ca 1s) */ 204 static int nt_t1_count[] = { 3840, 1920, 960, 480, 240, 120, 60, 30 }; 205 #define CLKDEL_TE 0x0f /* CLKDEL in TE mode */ 206 #define CLKDEL_NT 0x6c /* CLKDEL in NT mode 207 (0x60 MUST be included!) */ 208 209 #define DIP_4S 0x1 /* DIP Switches for Beronet 1S/2S/4S cards */ 210 #define DIP_8S 0x2 /* DIP Switches for Beronet 8S+ cards */ 211 #define DIP_E1 0x3 /* DIP Switches for Beronet E1 cards */ 212 213 /* 214 * module stuff 215 */ 216 217 static uint type[MAX_CARDS]; 218 static int pcm[MAX_CARDS]; 219 static uint dmask[MAX_CARDS]; 220 static uint bmask[MAX_FRAGS]; 221 static uint iomode[MAX_CARDS]; 222 static uint port[MAX_PORTS]; 223 static uint debug; 224 static uint poll; 225 static int clock; 226 static uint timer; 227 static uint clockdelay_te = CLKDEL_TE; 228 static uint clockdelay_nt = CLKDEL_NT; 229 #define HWID_NONE 0 230 #define HWID_MINIP4 1 231 #define HWID_MINIP8 2 232 #define HWID_MINIP16 3 233 static uint hwid = HWID_NONE; 234 235 static int HFC_cnt, E1_cnt, bmask_cnt, Port_cnt, PCM_cnt = 99; 236 237 MODULE_AUTHOR("Andreas Eversberg"); 238 MODULE_LICENSE("GPL"); 239 MODULE_VERSION(HFC_MULTI_VERSION); 240 module_param(debug, uint, S_IRUGO | S_IWUSR); 241 module_param(poll, uint, S_IRUGO | S_IWUSR); 242 module_param(clock, int, S_IRUGO | S_IWUSR); 243 module_param(timer, uint, S_IRUGO | S_IWUSR); 244 module_param(clockdelay_te, uint, S_IRUGO | S_IWUSR); 245 module_param(clockdelay_nt, uint, S_IRUGO | S_IWUSR); 246 module_param_array(type, uint, NULL, S_IRUGO | S_IWUSR); 247 module_param_array(pcm, int, NULL, S_IRUGO | S_IWUSR); 248 module_param_array(dmask, uint, NULL, S_IRUGO | S_IWUSR); 249 module_param_array(bmask, uint, NULL, S_IRUGO | S_IWUSR); 250 module_param_array(iomode, uint, NULL, S_IRUGO | S_IWUSR); 251 module_param_array(port, uint, NULL, S_IRUGO | S_IWUSR); 252 module_param(hwid, uint, S_IRUGO | S_IWUSR); /* The hardware ID */ 253 254 #ifdef HFC_REGISTER_DEBUG 255 #define HFC_outb(hc, reg, val) \ 256 (hc->HFC_outb(hc, reg, val, __func__, __LINE__)) 257 #define HFC_outb_nodebug(hc, reg, val) \ 258 (hc->HFC_outb_nodebug(hc, reg, val, __func__, __LINE__)) 259 #define HFC_inb(hc, reg) \ 260 (hc->HFC_inb(hc, reg, __func__, __LINE__)) 261 #define HFC_inb_nodebug(hc, reg) \ 262 (hc->HFC_inb_nodebug(hc, reg, __func__, __LINE__)) 263 #define HFC_inw(hc, reg) \ 264 (hc->HFC_inw(hc, reg, __func__, __LINE__)) 265 #define HFC_inw_nodebug(hc, reg) \ 266 (hc->HFC_inw_nodebug(hc, reg, __func__, __LINE__)) 267 #define HFC_wait(hc) \ 268 (hc->HFC_wait(hc, __func__, __LINE__)) 269 #define HFC_wait_nodebug(hc) \ 270 (hc->HFC_wait_nodebug(hc, __func__, __LINE__)) 271 #else 272 #define HFC_outb(hc, reg, val) (hc->HFC_outb(hc, reg, val)) 273 #define HFC_outb_nodebug(hc, reg, val) (hc->HFC_outb_nodebug(hc, reg, val)) 274 #define HFC_inb(hc, reg) (hc->HFC_inb(hc, reg)) 275 #define HFC_inb_nodebug(hc, reg) (hc->HFC_inb_nodebug(hc, reg)) 276 #define HFC_inw(hc, reg) (hc->HFC_inw(hc, reg)) 277 #define HFC_inw_nodebug(hc, reg) (hc->HFC_inw_nodebug(hc, reg)) 278 #define HFC_wait(hc) (hc->HFC_wait(hc)) 279 #define HFC_wait_nodebug(hc) (hc->HFC_wait_nodebug(hc)) 280 #endif 281 282 #ifdef CONFIG_MISDN_HFCMULTI_8xx 283 #include "hfc_multi_8xx.h" 284 #endif 285 286 /* HFC_IO_MODE_PCIMEM */ 287 static void 288 #ifdef HFC_REGISTER_DEBUG 289 HFC_outb_pcimem(struct hfc_multi *hc, u_char reg, u_char val, 290 const char *function, int line) 291 #else 292 HFC_outb_pcimem(struct hfc_multi *hc, u_char reg, u_char val) 293 #endif 294 { 295 writeb(val, hc->pci_membase + reg); 296 } 297 static u_char 298 #ifdef HFC_REGISTER_DEBUG 299 HFC_inb_pcimem(struct hfc_multi *hc, u_char reg, const char *function, int line) 300 #else 301 HFC_inb_pcimem(struct hfc_multi *hc, u_char reg) 302 #endif 303 { 304 return readb(hc->pci_membase + reg); 305 } 306 static u_short 307 #ifdef HFC_REGISTER_DEBUG 308 HFC_inw_pcimem(struct hfc_multi *hc, u_char reg, const char *function, int line) 309 #else 310 HFC_inw_pcimem(struct hfc_multi *hc, u_char reg) 311 #endif 312 { 313 return readw(hc->pci_membase + reg); 314 } 315 static void 316 #ifdef HFC_REGISTER_DEBUG 317 HFC_wait_pcimem(struct hfc_multi *hc, const char *function, int line) 318 #else 319 HFC_wait_pcimem(struct hfc_multi *hc) 320 #endif 321 { 322 while (readb(hc->pci_membase + R_STATUS) & V_BUSY) 323 cpu_relax(); 324 } 325 326 /* HFC_IO_MODE_REGIO */ 327 static void 328 #ifdef HFC_REGISTER_DEBUG 329 HFC_outb_regio(struct hfc_multi *hc, u_char reg, u_char val, 330 const char *function, int line) 331 #else 332 HFC_outb_regio(struct hfc_multi *hc, u_char reg, u_char val) 333 #endif 334 { 335 outb(reg, hc->pci_iobase + 4); 336 outb(val, hc->pci_iobase); 337 } 338 static u_char 339 #ifdef HFC_REGISTER_DEBUG 340 HFC_inb_regio(struct hfc_multi *hc, u_char reg, const char *function, int line) 341 #else 342 HFC_inb_regio(struct hfc_multi *hc, u_char reg) 343 #endif 344 { 345 outb(reg, hc->pci_iobase + 4); 346 return inb(hc->pci_iobase); 347 } 348 static u_short 349 #ifdef HFC_REGISTER_DEBUG 350 HFC_inw_regio(struct hfc_multi *hc, u_char reg, const char *function, int line) 351 #else 352 HFC_inw_regio(struct hfc_multi *hc, u_char reg) 353 #endif 354 { 355 outb(reg, hc->pci_iobase + 4); 356 return inw(hc->pci_iobase); 357 } 358 static void 359 #ifdef HFC_REGISTER_DEBUG 360 HFC_wait_regio(struct hfc_multi *hc, const char *function, int line) 361 #else 362 HFC_wait_regio(struct hfc_multi *hc) 363 #endif 364 { 365 outb(R_STATUS, hc->pci_iobase + 4); 366 while (inb(hc->pci_iobase) & V_BUSY) 367 cpu_relax(); 368 } 369 370 #ifdef HFC_REGISTER_DEBUG 371 static void 372 HFC_outb_debug(struct hfc_multi *hc, u_char reg, u_char val, 373 const char *function, int line) 374 { 375 char regname[256] = "", bits[9] = "xxxxxxxx"; 376 int i; 377 378 i = -1; 379 while (hfc_register_names[++i].name) { 380 if (hfc_register_names[i].reg == reg) 381 strcat(regname, hfc_register_names[i].name); 382 } 383 if (regname[0] == '\0') 384 strcpy(regname, "register"); 385 386 bits[7] = '0' + (!!(val & 1)); 387 bits[6] = '0' + (!!(val & 2)); 388 bits[5] = '0' + (!!(val & 4)); 389 bits[4] = '0' + (!!(val & 8)); 390 bits[3] = '0' + (!!(val & 16)); 391 bits[2] = '0' + (!!(val & 32)); 392 bits[1] = '0' + (!!(val & 64)); 393 bits[0] = '0' + (!!(val & 128)); 394 printk(KERN_DEBUG 395 "HFC_outb(chip %d, %02x=%s, 0x%02x=%s); in %s() line %d\n", 396 hc->id, reg, regname, val, bits, function, line); 397 HFC_outb_nodebug(hc, reg, val); 398 } 399 static u_char 400 HFC_inb_debug(struct hfc_multi *hc, u_char reg, const char *function, int line) 401 { 402 char regname[256] = "", bits[9] = "xxxxxxxx"; 403 u_char val = HFC_inb_nodebug(hc, reg); 404 int i; 405 406 i = 0; 407 while (hfc_register_names[i++].name) 408 ; 409 while (hfc_register_names[++i].name) { 410 if (hfc_register_names[i].reg == reg) 411 strcat(regname, hfc_register_names[i].name); 412 } 413 if (regname[0] == '\0') 414 strcpy(regname, "register"); 415 416 bits[7] = '0' + (!!(val & 1)); 417 bits[6] = '0' + (!!(val & 2)); 418 bits[5] = '0' + (!!(val & 4)); 419 bits[4] = '0' + (!!(val & 8)); 420 bits[3] = '0' + (!!(val & 16)); 421 bits[2] = '0' + (!!(val & 32)); 422 bits[1] = '0' + (!!(val & 64)); 423 bits[0] = '0' + (!!(val & 128)); 424 printk(KERN_DEBUG 425 "HFC_inb(chip %d, %02x=%s) = 0x%02x=%s; in %s() line %d\n", 426 hc->id, reg, regname, val, bits, function, line); 427 return val; 428 } 429 static u_short 430 HFC_inw_debug(struct hfc_multi *hc, u_char reg, const char *function, int line) 431 { 432 char regname[256] = ""; 433 u_short val = HFC_inw_nodebug(hc, reg); 434 int i; 435 436 i = 0; 437 while (hfc_register_names[i++].name) 438 ; 439 while (hfc_register_names[++i].name) { 440 if (hfc_register_names[i].reg == reg) 441 strcat(regname, hfc_register_names[i].name); 442 } 443 if (regname[0] == '\0') 444 strcpy(regname, "register"); 445 446 printk(KERN_DEBUG 447 "HFC_inw(chip %d, %02x=%s) = 0x%04x; in %s() line %d\n", 448 hc->id, reg, regname, val, function, line); 449 return val; 450 } 451 static void 452 HFC_wait_debug(struct hfc_multi *hc, const char *function, int line) 453 { 454 printk(KERN_DEBUG "HFC_wait(chip %d); in %s() line %d\n", 455 hc->id, function, line); 456 HFC_wait_nodebug(hc); 457 } 458 #endif 459 460 /* write fifo data (REGIO) */ 461 static void 462 write_fifo_regio(struct hfc_multi *hc, u_char *data, int len) 463 { 464 outb(A_FIFO_DATA0, (hc->pci_iobase) + 4); 465 while (len >> 2) { 466 outl(cpu_to_le32(*(u32 *)data), hc->pci_iobase); 467 data += 4; 468 len -= 4; 469 } 470 while (len >> 1) { 471 outw(cpu_to_le16(*(u16 *)data), hc->pci_iobase); 472 data += 2; 473 len -= 2; 474 } 475 while (len) { 476 outb(*data, hc->pci_iobase); 477 data++; 478 len--; 479 } 480 } 481 /* write fifo data (PCIMEM) */ 482 static void 483 write_fifo_pcimem(struct hfc_multi *hc, u_char *data, int len) 484 { 485 while (len >> 2) { 486 writel(cpu_to_le32(*(u32 *)data), 487 hc->pci_membase + A_FIFO_DATA0); 488 data += 4; 489 len -= 4; 490 } 491 while (len >> 1) { 492 writew(cpu_to_le16(*(u16 *)data), 493 hc->pci_membase + A_FIFO_DATA0); 494 data += 2; 495 len -= 2; 496 } 497 while (len) { 498 writeb(*data, hc->pci_membase + A_FIFO_DATA0); 499 data++; 500 len--; 501 } 502 } 503 504 /* read fifo data (REGIO) */ 505 static void 506 read_fifo_regio(struct hfc_multi *hc, u_char *data, int len) 507 { 508 outb(A_FIFO_DATA0, (hc->pci_iobase) + 4); 509 while (len >> 2) { 510 *(u32 *)data = le32_to_cpu(inl(hc->pci_iobase)); 511 data += 4; 512 len -= 4; 513 } 514 while (len >> 1) { 515 *(u16 *)data = le16_to_cpu(inw(hc->pci_iobase)); 516 data += 2; 517 len -= 2; 518 } 519 while (len) { 520 *data = inb(hc->pci_iobase); 521 data++; 522 len--; 523 } 524 } 525 526 /* read fifo data (PCIMEM) */ 527 static void 528 read_fifo_pcimem(struct hfc_multi *hc, u_char *data, int len) 529 { 530 while (len >> 2) { 531 *(u32 *)data = 532 le32_to_cpu(readl(hc->pci_membase + A_FIFO_DATA0)); 533 data += 4; 534 len -= 4; 535 } 536 while (len >> 1) { 537 *(u16 *)data = 538 le16_to_cpu(readw(hc->pci_membase + A_FIFO_DATA0)); 539 data += 2; 540 len -= 2; 541 } 542 while (len) { 543 *data = readb(hc->pci_membase + A_FIFO_DATA0); 544 data++; 545 len--; 546 } 547 } 548 549 static void 550 enable_hwirq(struct hfc_multi *hc) 551 { 552 hc->hw.r_irq_ctrl |= V_GLOB_IRQ_EN; 553 HFC_outb(hc, R_IRQ_CTRL, hc->hw.r_irq_ctrl); 554 } 555 556 static void 557 disable_hwirq(struct hfc_multi *hc) 558 { 559 hc->hw.r_irq_ctrl &= ~((u_char)V_GLOB_IRQ_EN); 560 HFC_outb(hc, R_IRQ_CTRL, hc->hw.r_irq_ctrl); 561 } 562 563 #define NUM_EC 2 564 #define MAX_TDM_CHAN 32 565 566 567 inline void 568 enablepcibridge(struct hfc_multi *c) 569 { 570 HFC_outb(c, R_BRG_PCM_CFG, (0x0 << 6) | 0x3); /* was _io before */ 571 } 572 573 inline void 574 disablepcibridge(struct hfc_multi *c) 575 { 576 HFC_outb(c, R_BRG_PCM_CFG, (0x0 << 6) | 0x2); /* was _io before */ 577 } 578 579 inline unsigned char 580 readpcibridge(struct hfc_multi *hc, unsigned char address) 581 { 582 unsigned short cipv; 583 unsigned char data; 584 585 if (!hc->pci_iobase) 586 return 0; 587 588 /* slow down a PCI read access by 1 PCI clock cycle */ 589 HFC_outb(hc, R_CTRL, 0x4); /*was _io before*/ 590 591 if (address == 0) 592 cipv = 0x4000; 593 else 594 cipv = 0x5800; 595 596 /* select local bridge port address by writing to CIP port */ 597 /* data = HFC_inb(c, cipv); * was _io before */ 598 outw(cipv, hc->pci_iobase + 4); 599 data = inb(hc->pci_iobase); 600 601 /* restore R_CTRL for normal PCI read cycle speed */ 602 HFC_outb(hc, R_CTRL, 0x0); /* was _io before */ 603 604 return data; 605 } 606 607 inline void 608 writepcibridge(struct hfc_multi *hc, unsigned char address, unsigned char data) 609 { 610 unsigned short cipv; 611 unsigned int datav; 612 613 if (!hc->pci_iobase) 614 return; 615 616 if (address == 0) 617 cipv = 0x4000; 618 else 619 cipv = 0x5800; 620 621 /* select local bridge port address by writing to CIP port */ 622 outw(cipv, hc->pci_iobase + 4); 623 /* define a 32 bit dword with 4 identical bytes for write sequence */ 624 datav = data | ((__u32) data << 8) | ((__u32) data << 16) | 625 ((__u32) data << 24); 626 627 /* 628 * write this 32 bit dword to the bridge data port 629 * this will initiate a write sequence of up to 4 writes to the same 630 * address on the local bus interface the number of write accesses 631 * is undefined but >=1 and depends on the next PCI transaction 632 * during write sequence on the local bus 633 */ 634 outl(datav, hc->pci_iobase); 635 } 636 637 inline void 638 cpld_set_reg(struct hfc_multi *hc, unsigned char reg) 639 { 640 /* Do data pin read low byte */ 641 HFC_outb(hc, R_GPIO_OUT1, reg); 642 } 643 644 inline void 645 cpld_write_reg(struct hfc_multi *hc, unsigned char reg, unsigned char val) 646 { 647 cpld_set_reg(hc, reg); 648 649 enablepcibridge(hc); 650 writepcibridge(hc, 1, val); 651 disablepcibridge(hc); 652 653 return; 654 } 655 656 inline unsigned char 657 cpld_read_reg(struct hfc_multi *hc, unsigned char reg) 658 { 659 unsigned char bytein; 660 661 cpld_set_reg(hc, reg); 662 663 /* Do data pin read low byte */ 664 HFC_outb(hc, R_GPIO_OUT1, reg); 665 666 enablepcibridge(hc); 667 bytein = readpcibridge(hc, 1); 668 disablepcibridge(hc); 669 670 return bytein; 671 } 672 673 inline void 674 vpm_write_address(struct hfc_multi *hc, unsigned short addr) 675 { 676 cpld_write_reg(hc, 0, 0xff & addr); 677 cpld_write_reg(hc, 1, 0x01 & (addr >> 8)); 678 } 679 680 inline unsigned short 681 vpm_read_address(struct hfc_multi *c) 682 { 683 unsigned short addr; 684 unsigned short highbit; 685 686 addr = cpld_read_reg(c, 0); 687 highbit = cpld_read_reg(c, 1); 688 689 addr = addr | (highbit << 8); 690 691 return addr & 0x1ff; 692 } 693 694 inline unsigned char 695 vpm_in(struct hfc_multi *c, int which, unsigned short addr) 696 { 697 unsigned char res; 698 699 vpm_write_address(c, addr); 700 701 if (!which) 702 cpld_set_reg(c, 2); 703 else 704 cpld_set_reg(c, 3); 705 706 enablepcibridge(c); 707 res = readpcibridge(c, 1); 708 disablepcibridge(c); 709 710 cpld_set_reg(c, 0); 711 712 return res; 713 } 714 715 inline void 716 vpm_out(struct hfc_multi *c, int which, unsigned short addr, 717 unsigned char data) 718 { 719 vpm_write_address(c, addr); 720 721 enablepcibridge(c); 722 723 if (!which) 724 cpld_set_reg(c, 2); 725 else 726 cpld_set_reg(c, 3); 727 728 writepcibridge(c, 1, data); 729 730 cpld_set_reg(c, 0); 731 732 disablepcibridge(c); 733 734 { 735 unsigned char regin; 736 regin = vpm_in(c, which, addr); 737 if (regin != data) 738 printk(KERN_DEBUG "Wrote 0x%x to register 0x%x but got back " 739 "0x%x\n", data, addr, regin); 740 } 741 742 } 743 744 745 static void 746 vpm_init(struct hfc_multi *wc) 747 { 748 unsigned char reg; 749 unsigned int mask; 750 unsigned int i, x, y; 751 unsigned int ver; 752 753 for (x = 0; x < NUM_EC; x++) { 754 /* Setup GPIO's */ 755 if (!x) { 756 ver = vpm_in(wc, x, 0x1a0); 757 printk(KERN_DEBUG "VPM: Chip %d: ver %02x\n", x, ver); 758 } 759 760 for (y = 0; y < 4; y++) { 761 vpm_out(wc, x, 0x1a8 + y, 0x00); /* GPIO out */ 762 vpm_out(wc, x, 0x1ac + y, 0x00); /* GPIO dir */ 763 vpm_out(wc, x, 0x1b0 + y, 0x00); /* GPIO sel */ 764 } 765 766 /* Setup TDM path - sets fsync and tdm_clk as inputs */ 767 reg = vpm_in(wc, x, 0x1a3); /* misc_con */ 768 vpm_out(wc, x, 0x1a3, reg & ~2); 769 770 /* Setup Echo length (256 taps) */ 771 vpm_out(wc, x, 0x022, 1); 772 vpm_out(wc, x, 0x023, 0xff); 773 774 /* Setup timeslots */ 775 vpm_out(wc, x, 0x02f, 0x00); 776 mask = 0x02020202 << (x * 4); 777 778 /* Setup the tdm channel masks for all chips */ 779 for (i = 0; i < 4; i++) 780 vpm_out(wc, x, 0x33 - i, (mask >> (i << 3)) & 0xff); 781 782 /* Setup convergence rate */ 783 printk(KERN_DEBUG "VPM: A-law mode\n"); 784 reg = 0x00 | 0x10 | 0x01; 785 vpm_out(wc, x, 0x20, reg); 786 printk(KERN_DEBUG "VPM reg 0x20 is %x\n", reg); 787 /*vpm_out(wc, x, 0x20, (0x00 | 0x08 | 0x20 | 0x10)); */ 788 789 vpm_out(wc, x, 0x24, 0x02); 790 reg = vpm_in(wc, x, 0x24); 791 printk(KERN_DEBUG "NLP Thresh is set to %d (0x%x)\n", reg, reg); 792 793 /* Initialize echo cans */ 794 for (i = 0; i < MAX_TDM_CHAN; i++) { 795 if (mask & (0x00000001 << i)) 796 vpm_out(wc, x, i, 0x00); 797 } 798 799 /* 800 * ARM arch at least disallows a udelay of 801 * more than 2ms... it gives a fake "__bad_udelay" 802 * reference at link-time. 803 * long delays in kernel code are pretty sucky anyway 804 * for now work around it using 5 x 2ms instead of 1 x 10ms 805 */ 806 807 udelay(2000); 808 udelay(2000); 809 udelay(2000); 810 udelay(2000); 811 udelay(2000); 812 813 /* Put in bypass mode */ 814 for (i = 0; i < MAX_TDM_CHAN; i++) { 815 if (mask & (0x00000001 << i)) 816 vpm_out(wc, x, i, 0x01); 817 } 818 819 /* Enable bypass */ 820 for (i = 0; i < MAX_TDM_CHAN; i++) { 821 if (mask & (0x00000001 << i)) 822 vpm_out(wc, x, 0x78 + i, 0x01); 823 } 824 825 } 826 } 827 828 #ifdef UNUSED 829 static void 830 vpm_check(struct hfc_multi *hctmp) 831 { 832 unsigned char gpi2; 833 834 gpi2 = HFC_inb(hctmp, R_GPI_IN2); 835 836 if ((gpi2 & 0x3) != 0x3) 837 printk(KERN_DEBUG "Got interrupt 0x%x from VPM!\n", gpi2); 838 } 839 #endif /* UNUSED */ 840 841 842 /* 843 * Interface to enable/disable the HW Echocan 844 * 845 * these functions are called within a spin_lock_irqsave on 846 * the channel instance lock, so we are not disturbed by irqs 847 * 848 * we can later easily change the interface to make other 849 * things configurable, for now we configure the taps 850 * 851 */ 852 853 static void 854 vpm_echocan_on(struct hfc_multi *hc, int ch, int taps) 855 { 856 unsigned int timeslot; 857 unsigned int unit; 858 struct bchannel *bch = hc->chan[ch].bch; 859 #ifdef TXADJ 860 int txadj = -4; 861 struct sk_buff *skb; 862 #endif 863 if (hc->chan[ch].protocol != ISDN_P_B_RAW) 864 return; 865 866 if (!bch) 867 return; 868 869 #ifdef TXADJ 870 skb = _alloc_mISDN_skb(PH_CONTROL_IND, HFC_VOL_CHANGE_TX, 871 sizeof(int), &txadj, GFP_ATOMIC); 872 if (skb) 873 recv_Bchannel_skb(bch, skb); 874 #endif 875 876 timeslot = ((ch / 4) * 8) + ((ch % 4) * 4) + 1; 877 unit = ch % 4; 878 879 printk(KERN_NOTICE "vpm_echocan_on called taps [%d] on timeslot %d\n", 880 taps, timeslot); 881 882 vpm_out(hc, unit, timeslot, 0x7e); 883 } 884 885 static void 886 vpm_echocan_off(struct hfc_multi *hc, int ch) 887 { 888 unsigned int timeslot; 889 unsigned int unit; 890 struct bchannel *bch = hc->chan[ch].bch; 891 #ifdef TXADJ 892 int txadj = 0; 893 struct sk_buff *skb; 894 #endif 895 896 if (hc->chan[ch].protocol != ISDN_P_B_RAW) 897 return; 898 899 if (!bch) 900 return; 901 902 #ifdef TXADJ 903 skb = _alloc_mISDN_skb(PH_CONTROL_IND, HFC_VOL_CHANGE_TX, 904 sizeof(int), &txadj, GFP_ATOMIC); 905 if (skb) 906 recv_Bchannel_skb(bch, skb); 907 #endif 908 909 timeslot = ((ch / 4) * 8) + ((ch % 4) * 4) + 1; 910 unit = ch % 4; 911 912 printk(KERN_NOTICE "vpm_echocan_off called on timeslot %d\n", 913 timeslot); 914 /* FILLME */ 915 vpm_out(hc, unit, timeslot, 0x01); 916 } 917 918 919 /* 920 * Speech Design resync feature 921 * NOTE: This is called sometimes outside interrupt handler. 922 * We must lock irqsave, so no other interrupt (other card) will occur! 923 * Also multiple interrupts may nest, so must lock each access (lists, card)! 924 */ 925 static inline void 926 hfcmulti_resync(struct hfc_multi *locked, struct hfc_multi *newmaster, int rm) 927 { 928 struct hfc_multi *hc, *next, *pcmmaster = NULL; 929 void __iomem *plx_acc_32; 930 u_int pv; 931 u_long flags; 932 933 spin_lock_irqsave(&HFClock, flags); 934 spin_lock(&plx_lock); /* must be locked inside other locks */ 935 936 if (debug & DEBUG_HFCMULTI_PLXSD) 937 printk(KERN_DEBUG "%s: RESYNC(syncmaster=0x%p)\n", 938 __func__, syncmaster); 939 940 /* select new master */ 941 if (newmaster) { 942 if (debug & DEBUG_HFCMULTI_PLXSD) 943 printk(KERN_DEBUG "using provided controller\n"); 944 } else { 945 list_for_each_entry_safe(hc, next, &HFClist, list) { 946 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) { 947 if (hc->syncronized) { 948 newmaster = hc; 949 break; 950 } 951 } 952 } 953 } 954 955 /* Disable sync of all cards */ 956 list_for_each_entry_safe(hc, next, &HFClist, list) { 957 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) { 958 plx_acc_32 = hc->plx_membase + PLX_GPIOC; 959 pv = readl(plx_acc_32); 960 pv &= ~PLX_SYNC_O_EN; 961 writel(pv, plx_acc_32); 962 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip)) { 963 pcmmaster = hc; 964 if (hc->ctype == HFC_TYPE_E1) { 965 if (debug & DEBUG_HFCMULTI_PLXSD) 966 printk(KERN_DEBUG 967 "Schedule SYNC_I\n"); 968 hc->e1_resync |= 1; /* get SYNC_I */ 969 } 970 } 971 } 972 } 973 974 if (newmaster) { 975 hc = newmaster; 976 if (debug & DEBUG_HFCMULTI_PLXSD) 977 printk(KERN_DEBUG "id=%d (0x%p) = syncronized with " 978 "interface.\n", hc->id, hc); 979 /* Enable new sync master */ 980 plx_acc_32 = hc->plx_membase + PLX_GPIOC; 981 pv = readl(plx_acc_32); 982 pv |= PLX_SYNC_O_EN; 983 writel(pv, plx_acc_32); 984 /* switch to jatt PLL, if not disabled by RX_SYNC */ 985 if (hc->ctype == HFC_TYPE_E1 986 && !test_bit(HFC_CHIP_RX_SYNC, &hc->chip)) { 987 if (debug & DEBUG_HFCMULTI_PLXSD) 988 printk(KERN_DEBUG "Schedule jatt PLL\n"); 989 hc->e1_resync |= 2; /* switch to jatt */ 990 } 991 } else { 992 if (pcmmaster) { 993 hc = pcmmaster; 994 if (debug & DEBUG_HFCMULTI_PLXSD) 995 printk(KERN_DEBUG 996 "id=%d (0x%p) = PCM master syncronized " 997 "with QUARTZ\n", hc->id, hc); 998 if (hc->ctype == HFC_TYPE_E1) { 999 /* Use the crystal clock for the PCM 1000 master card */ 1001 if (debug & DEBUG_HFCMULTI_PLXSD) 1002 printk(KERN_DEBUG 1003 "Schedule QUARTZ for HFC-E1\n"); 1004 hc->e1_resync |= 4; /* switch quartz */ 1005 } else { 1006 if (debug & DEBUG_HFCMULTI_PLXSD) 1007 printk(KERN_DEBUG 1008 "QUARTZ is automatically " 1009 "enabled by HFC-%dS\n", hc->ctype); 1010 } 1011 plx_acc_32 = hc->plx_membase + PLX_GPIOC; 1012 pv = readl(plx_acc_32); 1013 pv |= PLX_SYNC_O_EN; 1014 writel(pv, plx_acc_32); 1015 } else 1016 if (!rm) 1017 printk(KERN_ERR "%s no pcm master, this MUST " 1018 "not happen!\n", __func__); 1019 } 1020 syncmaster = newmaster; 1021 1022 spin_unlock(&plx_lock); 1023 spin_unlock_irqrestore(&HFClock, flags); 1024 } 1025 1026 /* This must be called AND hc must be locked irqsave!!! */ 1027 inline void 1028 plxsd_checksync(struct hfc_multi *hc, int rm) 1029 { 1030 if (hc->syncronized) { 1031 if (syncmaster == NULL) { 1032 if (debug & DEBUG_HFCMULTI_PLXSD) 1033 printk(KERN_DEBUG "%s: GOT sync on card %d" 1034 " (id=%d)\n", __func__, hc->id + 1, 1035 hc->id); 1036 hfcmulti_resync(hc, hc, rm); 1037 } 1038 } else { 1039 if (syncmaster == hc) { 1040 if (debug & DEBUG_HFCMULTI_PLXSD) 1041 printk(KERN_DEBUG "%s: LOST sync on card %d" 1042 " (id=%d)\n", __func__, hc->id + 1, 1043 hc->id); 1044 hfcmulti_resync(hc, NULL, rm); 1045 } 1046 } 1047 } 1048 1049 1050 /* 1051 * free hardware resources used by driver 1052 */ 1053 static void 1054 release_io_hfcmulti(struct hfc_multi *hc) 1055 { 1056 void __iomem *plx_acc_32; 1057 u_int pv; 1058 u_long plx_flags; 1059 1060 if (debug & DEBUG_HFCMULTI_INIT) 1061 printk(KERN_DEBUG "%s: entered\n", __func__); 1062 1063 /* soft reset also masks all interrupts */ 1064 hc->hw.r_cirm |= V_SRES; 1065 HFC_outb(hc, R_CIRM, hc->hw.r_cirm); 1066 udelay(1000); 1067 hc->hw.r_cirm &= ~V_SRES; 1068 HFC_outb(hc, R_CIRM, hc->hw.r_cirm); 1069 udelay(1000); /* instead of 'wait' that may cause locking */ 1070 1071 /* release Speech Design card, if PLX was initialized */ 1072 if (test_bit(HFC_CHIP_PLXSD, &hc->chip) && hc->plx_membase) { 1073 if (debug & DEBUG_HFCMULTI_PLXSD) 1074 printk(KERN_DEBUG "%s: release PLXSD card %d\n", 1075 __func__, hc->id + 1); 1076 spin_lock_irqsave(&plx_lock, plx_flags); 1077 plx_acc_32 = hc->plx_membase + PLX_GPIOC; 1078 writel(PLX_GPIOC_INIT, plx_acc_32); 1079 pv = readl(plx_acc_32); 1080 /* Termination off */ 1081 pv &= ~PLX_TERM_ON; 1082 /* Disconnect the PCM */ 1083 pv |= PLX_SLAVE_EN_N; 1084 pv &= ~PLX_MASTER_EN; 1085 pv &= ~PLX_SYNC_O_EN; 1086 /* Put the DSP in Reset */ 1087 pv &= ~PLX_DSP_RES_N; 1088 writel(pv, plx_acc_32); 1089 if (debug & DEBUG_HFCMULTI_INIT) 1090 printk(KERN_DEBUG "%s: PCM off: PLX_GPIO=%x\n", 1091 __func__, pv); 1092 spin_unlock_irqrestore(&plx_lock, plx_flags); 1093 } 1094 1095 /* disable memory mapped ports / io ports */ 1096 test_and_clear_bit(HFC_CHIP_PLXSD, &hc->chip); /* prevent resync */ 1097 if (hc->pci_dev) 1098 pci_write_config_word(hc->pci_dev, PCI_COMMAND, 0); 1099 if (hc->pci_membase) 1100 iounmap(hc->pci_membase); 1101 if (hc->plx_membase) 1102 iounmap(hc->plx_membase); 1103 if (hc->pci_iobase) 1104 release_region(hc->pci_iobase, 8); 1105 if (hc->xhfc_membase) 1106 iounmap((void *)hc->xhfc_membase); 1107 1108 if (hc->pci_dev) { 1109 pci_disable_device(hc->pci_dev); 1110 pci_set_drvdata(hc->pci_dev, NULL); 1111 } 1112 if (debug & DEBUG_HFCMULTI_INIT) 1113 printk(KERN_DEBUG "%s: done\n", __func__); 1114 } 1115 1116 /* 1117 * function called to reset the HFC chip. A complete software reset of chip 1118 * and fifos is done. All configuration of the chip is done. 1119 */ 1120 1121 static int 1122 init_chip(struct hfc_multi *hc) 1123 { 1124 u_long flags, val, val2 = 0, rev; 1125 int i, err = 0; 1126 u_char r_conf_en, rval; 1127 void __iomem *plx_acc_32; 1128 u_int pv; 1129 u_long plx_flags, hfc_flags; 1130 int plx_count; 1131 struct hfc_multi *pos, *next, *plx_last_hc; 1132 1133 spin_lock_irqsave(&hc->lock, flags); 1134 /* reset all registers */ 1135 memset(&hc->hw, 0, sizeof(struct hfcm_hw)); 1136 1137 /* revision check */ 1138 if (debug & DEBUG_HFCMULTI_INIT) 1139 printk(KERN_DEBUG "%s: entered\n", __func__); 1140 val = HFC_inb(hc, R_CHIP_ID); 1141 if ((val >> 4) != 0x8 && (val >> 4) != 0xc && (val >> 4) != 0xe && 1142 (val >> 1) != 0x31) { 1143 printk(KERN_INFO "HFC_multi: unknown CHIP_ID:%x\n", (u_int)val); 1144 err = -EIO; 1145 goto out; 1146 } 1147 rev = HFC_inb(hc, R_CHIP_RV); 1148 printk(KERN_INFO 1149 "HFC_multi: detected HFC with chip ID=0x%lx revision=%ld%s\n", 1150 val, rev, (rev == 0 && (hc->ctype != HFC_TYPE_XHFC)) ? 1151 " (old FIFO handling)" : ""); 1152 if (hc->ctype != HFC_TYPE_XHFC && rev == 0) { 1153 test_and_set_bit(HFC_CHIP_REVISION0, &hc->chip); 1154 printk(KERN_WARNING 1155 "HFC_multi: NOTE: Your chip is revision 0, " 1156 "ask Cologne Chip for update. Newer chips " 1157 "have a better FIFO handling. Old chips " 1158 "still work but may have slightly lower " 1159 "HDLC transmit performance.\n"); 1160 } 1161 if (rev > 1) { 1162 printk(KERN_WARNING "HFC_multi: WARNING: This driver doesn't " 1163 "consider chip revision = %ld. The chip / " 1164 "bridge may not work.\n", rev); 1165 } 1166 1167 /* set s-ram size */ 1168 hc->Flen = 0x10; 1169 hc->Zmin = 0x80; 1170 hc->Zlen = 384; 1171 hc->DTMFbase = 0x1000; 1172 if (test_bit(HFC_CHIP_EXRAM_128, &hc->chip)) { 1173 if (debug & DEBUG_HFCMULTI_INIT) 1174 printk(KERN_DEBUG "%s: changing to 128K extenal RAM\n", 1175 __func__); 1176 hc->hw.r_ctrl |= V_EXT_RAM; 1177 hc->hw.r_ram_sz = 1; 1178 hc->Flen = 0x20; 1179 hc->Zmin = 0xc0; 1180 hc->Zlen = 1856; 1181 hc->DTMFbase = 0x2000; 1182 } 1183 if (test_bit(HFC_CHIP_EXRAM_512, &hc->chip)) { 1184 if (debug & DEBUG_HFCMULTI_INIT) 1185 printk(KERN_DEBUG "%s: changing to 512K extenal RAM\n", 1186 __func__); 1187 hc->hw.r_ctrl |= V_EXT_RAM; 1188 hc->hw.r_ram_sz = 2; 1189 hc->Flen = 0x20; 1190 hc->Zmin = 0xc0; 1191 hc->Zlen = 8000; 1192 hc->DTMFbase = 0x2000; 1193 } 1194 if (hc->ctype == HFC_TYPE_XHFC) { 1195 hc->Flen = 0x8; 1196 hc->Zmin = 0x0; 1197 hc->Zlen = 64; 1198 hc->DTMFbase = 0x0; 1199 } 1200 hc->max_trans = poll << 1; 1201 if (hc->max_trans > hc->Zlen) 1202 hc->max_trans = hc->Zlen; 1203 1204 /* Speech Design PLX bridge */ 1205 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) { 1206 if (debug & DEBUG_HFCMULTI_PLXSD) 1207 printk(KERN_DEBUG "%s: initializing PLXSD card %d\n", 1208 __func__, hc->id + 1); 1209 spin_lock_irqsave(&plx_lock, plx_flags); 1210 plx_acc_32 = hc->plx_membase + PLX_GPIOC; 1211 writel(PLX_GPIOC_INIT, plx_acc_32); 1212 pv = readl(plx_acc_32); 1213 /* The first and the last cards are terminating the PCM bus */ 1214 pv |= PLX_TERM_ON; /* hc is currently the last */ 1215 /* Disconnect the PCM */ 1216 pv |= PLX_SLAVE_EN_N; 1217 pv &= ~PLX_MASTER_EN; 1218 pv &= ~PLX_SYNC_O_EN; 1219 /* Put the DSP in Reset */ 1220 pv &= ~PLX_DSP_RES_N; 1221 writel(pv, plx_acc_32); 1222 spin_unlock_irqrestore(&plx_lock, plx_flags); 1223 if (debug & DEBUG_HFCMULTI_INIT) 1224 printk(KERN_DEBUG "%s: slave/term: PLX_GPIO=%x\n", 1225 __func__, pv); 1226 /* 1227 * If we are the 3rd PLXSD card or higher, we must turn 1228 * termination of last PLXSD card off. 1229 */ 1230 spin_lock_irqsave(&HFClock, hfc_flags); 1231 plx_count = 0; 1232 plx_last_hc = NULL; 1233 list_for_each_entry_safe(pos, next, &HFClist, list) { 1234 if (test_bit(HFC_CHIP_PLXSD, &pos->chip)) { 1235 plx_count++; 1236 if (pos != hc) 1237 plx_last_hc = pos; 1238 } 1239 } 1240 if (plx_count >= 3) { 1241 if (debug & DEBUG_HFCMULTI_PLXSD) 1242 printk(KERN_DEBUG "%s: card %d is between, so " 1243 "we disable termination\n", 1244 __func__, plx_last_hc->id + 1); 1245 spin_lock_irqsave(&plx_lock, plx_flags); 1246 plx_acc_32 = plx_last_hc->plx_membase + PLX_GPIOC; 1247 pv = readl(plx_acc_32); 1248 pv &= ~PLX_TERM_ON; 1249 writel(pv, plx_acc_32); 1250 spin_unlock_irqrestore(&plx_lock, plx_flags); 1251 if (debug & DEBUG_HFCMULTI_INIT) 1252 printk(KERN_DEBUG 1253 "%s: term off: PLX_GPIO=%x\n", 1254 __func__, pv); 1255 } 1256 spin_unlock_irqrestore(&HFClock, hfc_flags); 1257 hc->hw.r_pcm_md0 = V_F0_LEN; /* shift clock for DSP */ 1258 } 1259 1260 if (test_bit(HFC_CHIP_EMBSD, &hc->chip)) 1261 hc->hw.r_pcm_md0 = V_F0_LEN; /* shift clock for DSP */ 1262 1263 /* we only want the real Z2 read-pointer for revision > 0 */ 1264 if (!test_bit(HFC_CHIP_REVISION0, &hc->chip)) 1265 hc->hw.r_ram_sz |= V_FZ_MD; 1266 1267 /* select pcm mode */ 1268 if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip)) { 1269 if (debug & DEBUG_HFCMULTI_INIT) 1270 printk(KERN_DEBUG "%s: setting PCM into slave mode\n", 1271 __func__); 1272 } else 1273 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip) && !plxsd_master) { 1274 if (debug & DEBUG_HFCMULTI_INIT) 1275 printk(KERN_DEBUG "%s: setting PCM into master mode\n", 1276 __func__); 1277 hc->hw.r_pcm_md0 |= V_PCM_MD; 1278 } else { 1279 if (debug & DEBUG_HFCMULTI_INIT) 1280 printk(KERN_DEBUG "%s: performing PCM auto detect\n", 1281 __func__); 1282 } 1283 1284 /* soft reset */ 1285 HFC_outb(hc, R_CTRL, hc->hw.r_ctrl); 1286 if (hc->ctype == HFC_TYPE_XHFC) 1287 HFC_outb(hc, 0x0C /* R_FIFO_THRES */, 1288 0x11 /* 16 Bytes TX/RX */); 1289 else 1290 HFC_outb(hc, R_RAM_SZ, hc->hw.r_ram_sz); 1291 HFC_outb(hc, R_FIFO_MD, 0); 1292 if (hc->ctype == HFC_TYPE_XHFC) 1293 hc->hw.r_cirm = V_SRES | V_HFCRES | V_PCMRES | V_STRES; 1294 else 1295 hc->hw.r_cirm = V_SRES | V_HFCRES | V_PCMRES | V_STRES 1296 | V_RLD_EPR; 1297 HFC_outb(hc, R_CIRM, hc->hw.r_cirm); 1298 udelay(100); 1299 hc->hw.r_cirm = 0; 1300 HFC_outb(hc, R_CIRM, hc->hw.r_cirm); 1301 udelay(100); 1302 if (hc->ctype != HFC_TYPE_XHFC) 1303 HFC_outb(hc, R_RAM_SZ, hc->hw.r_ram_sz); 1304 1305 /* Speech Design PLX bridge pcm and sync mode */ 1306 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) { 1307 spin_lock_irqsave(&plx_lock, plx_flags); 1308 plx_acc_32 = hc->plx_membase + PLX_GPIOC; 1309 pv = readl(plx_acc_32); 1310 /* Connect PCM */ 1311 if (hc->hw.r_pcm_md0 & V_PCM_MD) { 1312 pv |= PLX_MASTER_EN | PLX_SLAVE_EN_N; 1313 pv |= PLX_SYNC_O_EN; 1314 if (debug & DEBUG_HFCMULTI_INIT) 1315 printk(KERN_DEBUG "%s: master: PLX_GPIO=%x\n", 1316 __func__, pv); 1317 } else { 1318 pv &= ~(PLX_MASTER_EN | PLX_SLAVE_EN_N); 1319 pv &= ~PLX_SYNC_O_EN; 1320 if (debug & DEBUG_HFCMULTI_INIT) 1321 printk(KERN_DEBUG "%s: slave: PLX_GPIO=%x\n", 1322 __func__, pv); 1323 } 1324 writel(pv, plx_acc_32); 1325 spin_unlock_irqrestore(&plx_lock, plx_flags); 1326 } 1327 1328 /* PCM setup */ 1329 HFC_outb(hc, R_PCM_MD0, hc->hw.r_pcm_md0 | 0x90); 1330 if (hc->slots == 32) 1331 HFC_outb(hc, R_PCM_MD1, 0x00); 1332 if (hc->slots == 64) 1333 HFC_outb(hc, R_PCM_MD1, 0x10); 1334 if (hc->slots == 128) 1335 HFC_outb(hc, R_PCM_MD1, 0x20); 1336 HFC_outb(hc, R_PCM_MD0, hc->hw.r_pcm_md0 | 0xa0); 1337 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) 1338 HFC_outb(hc, R_PCM_MD2, V_SYNC_SRC); /* sync via SYNC_I / O */ 1339 else if (test_bit(HFC_CHIP_EMBSD, &hc->chip)) 1340 HFC_outb(hc, R_PCM_MD2, 0x10); /* V_C2O_EN */ 1341 else 1342 HFC_outb(hc, R_PCM_MD2, 0x00); /* sync from interface */ 1343 HFC_outb(hc, R_PCM_MD0, hc->hw.r_pcm_md0 | 0x00); 1344 for (i = 0; i < 256; i++) { 1345 HFC_outb_nodebug(hc, R_SLOT, i); 1346 HFC_outb_nodebug(hc, A_SL_CFG, 0); 1347 if (hc->ctype != HFC_TYPE_XHFC) 1348 HFC_outb_nodebug(hc, A_CONF, 0); 1349 hc->slot_owner[i] = -1; 1350 } 1351 1352 /* set clock speed */ 1353 if (test_bit(HFC_CHIP_CLOCK2, &hc->chip)) { 1354 if (debug & DEBUG_HFCMULTI_INIT) 1355 printk(KERN_DEBUG 1356 "%s: setting double clock\n", __func__); 1357 HFC_outb(hc, R_BRG_PCM_CFG, V_PCM_CLK); 1358 } 1359 1360 if (test_bit(HFC_CHIP_EMBSD, &hc->chip)) 1361 HFC_outb(hc, 0x02 /* R_CLK_CFG */, 0x40 /* V_CLKO_OFF */); 1362 1363 /* B410P GPIO */ 1364 if (test_bit(HFC_CHIP_B410P, &hc->chip)) { 1365 printk(KERN_NOTICE "Setting GPIOs\n"); 1366 HFC_outb(hc, R_GPIO_SEL, 0x30); 1367 HFC_outb(hc, R_GPIO_EN1, 0x3); 1368 udelay(1000); 1369 printk(KERN_NOTICE "calling vpm_init\n"); 1370 vpm_init(hc); 1371 } 1372 1373 /* check if R_F0_CNT counts (8 kHz frame count) */ 1374 val = HFC_inb(hc, R_F0_CNTL); 1375 val += HFC_inb(hc, R_F0_CNTH) << 8; 1376 if (debug & DEBUG_HFCMULTI_INIT) 1377 printk(KERN_DEBUG 1378 "HFC_multi F0_CNT %ld after reset\n", val); 1379 spin_unlock_irqrestore(&hc->lock, flags); 1380 set_current_state(TASK_UNINTERRUPTIBLE); 1381 schedule_timeout((HZ / 100) ? : 1); /* Timeout minimum 10ms */ 1382 spin_lock_irqsave(&hc->lock, flags); 1383 val2 = HFC_inb(hc, R_F0_CNTL); 1384 val2 += HFC_inb(hc, R_F0_CNTH) << 8; 1385 if (debug & DEBUG_HFCMULTI_INIT) 1386 printk(KERN_DEBUG 1387 "HFC_multi F0_CNT %ld after 10 ms (1st try)\n", 1388 val2); 1389 if (val2 >= val + 8) { /* 1 ms */ 1390 /* it counts, so we keep the pcm mode */ 1391 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip)) 1392 printk(KERN_INFO "controller is PCM bus MASTER\n"); 1393 else 1394 if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip)) 1395 printk(KERN_INFO "controller is PCM bus SLAVE\n"); 1396 else { 1397 test_and_set_bit(HFC_CHIP_PCM_SLAVE, &hc->chip); 1398 printk(KERN_INFO "controller is PCM bus SLAVE " 1399 "(auto detected)\n"); 1400 } 1401 } else { 1402 /* does not count */ 1403 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip)) { 1404 controller_fail: 1405 printk(KERN_ERR "HFC_multi ERROR, getting no 125us " 1406 "pulse. Seems that controller fails.\n"); 1407 err = -EIO; 1408 goto out; 1409 } 1410 if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip)) { 1411 printk(KERN_INFO "controller is PCM bus SLAVE " 1412 "(ignoring missing PCM clock)\n"); 1413 } else { 1414 /* only one pcm master */ 1415 if (test_bit(HFC_CHIP_PLXSD, &hc->chip) 1416 && plxsd_master) { 1417 printk(KERN_ERR "HFC_multi ERROR, no clock " 1418 "on another Speech Design card found. " 1419 "Please be sure to connect PCM cable.\n"); 1420 err = -EIO; 1421 goto out; 1422 } 1423 /* retry with master clock */ 1424 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) { 1425 spin_lock_irqsave(&plx_lock, plx_flags); 1426 plx_acc_32 = hc->plx_membase + PLX_GPIOC; 1427 pv = readl(plx_acc_32); 1428 pv |= PLX_MASTER_EN | PLX_SLAVE_EN_N; 1429 pv |= PLX_SYNC_O_EN; 1430 writel(pv, plx_acc_32); 1431 spin_unlock_irqrestore(&plx_lock, plx_flags); 1432 if (debug & DEBUG_HFCMULTI_INIT) 1433 printk(KERN_DEBUG "%s: master: " 1434 "PLX_GPIO=%x\n", __func__, pv); 1435 } 1436 hc->hw.r_pcm_md0 |= V_PCM_MD; 1437 HFC_outb(hc, R_PCM_MD0, hc->hw.r_pcm_md0 | 0x00); 1438 spin_unlock_irqrestore(&hc->lock, flags); 1439 set_current_state(TASK_UNINTERRUPTIBLE); 1440 schedule_timeout((HZ / 100) ?: 1); /* Timeout min. 10ms */ 1441 spin_lock_irqsave(&hc->lock, flags); 1442 val2 = HFC_inb(hc, R_F0_CNTL); 1443 val2 += HFC_inb(hc, R_F0_CNTH) << 8; 1444 if (debug & DEBUG_HFCMULTI_INIT) 1445 printk(KERN_DEBUG "HFC_multi F0_CNT %ld after " 1446 "10 ms (2nd try)\n", val2); 1447 if (val2 >= val + 8) { /* 1 ms */ 1448 test_and_set_bit(HFC_CHIP_PCM_MASTER, 1449 &hc->chip); 1450 printk(KERN_INFO "controller is PCM bus MASTER " 1451 "(auto detected)\n"); 1452 } else 1453 goto controller_fail; 1454 } 1455 } 1456 1457 /* Release the DSP Reset */ 1458 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) { 1459 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip)) 1460 plxsd_master = 1; 1461 spin_lock_irqsave(&plx_lock, plx_flags); 1462 plx_acc_32 = hc->plx_membase + PLX_GPIOC; 1463 pv = readl(plx_acc_32); 1464 pv |= PLX_DSP_RES_N; 1465 writel(pv, plx_acc_32); 1466 spin_unlock_irqrestore(&plx_lock, plx_flags); 1467 if (debug & DEBUG_HFCMULTI_INIT) 1468 printk(KERN_DEBUG "%s: reset off: PLX_GPIO=%x\n", 1469 __func__, pv); 1470 } 1471 1472 /* pcm id */ 1473 if (hc->pcm) 1474 printk(KERN_INFO "controller has given PCM BUS ID %d\n", 1475 hc->pcm); 1476 else { 1477 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip) 1478 || test_bit(HFC_CHIP_PLXSD, &hc->chip)) { 1479 PCM_cnt++; /* SD has proprietary bridging */ 1480 } 1481 hc->pcm = PCM_cnt; 1482 printk(KERN_INFO "controller has PCM BUS ID %d " 1483 "(auto selected)\n", hc->pcm); 1484 } 1485 1486 /* set up timer */ 1487 HFC_outb(hc, R_TI_WD, poll_timer); 1488 hc->hw.r_irqmsk_misc |= V_TI_IRQMSK; 1489 1490 /* set E1 state machine IRQ */ 1491 if (hc->ctype == HFC_TYPE_E1) 1492 hc->hw.r_irqmsk_misc |= V_STA_IRQMSK; 1493 1494 /* set DTMF detection */ 1495 if (test_bit(HFC_CHIP_DTMF, &hc->chip)) { 1496 if (debug & DEBUG_HFCMULTI_INIT) 1497 printk(KERN_DEBUG "%s: enabling DTMF detection " 1498 "for all B-channel\n", __func__); 1499 hc->hw.r_dtmf = V_DTMF_EN | V_DTMF_STOP; 1500 if (test_bit(HFC_CHIP_ULAW, &hc->chip)) 1501 hc->hw.r_dtmf |= V_ULAW_SEL; 1502 HFC_outb(hc, R_DTMF_N, 102 - 1); 1503 hc->hw.r_irqmsk_misc |= V_DTMF_IRQMSK; 1504 } 1505 1506 /* conference engine */ 1507 if (test_bit(HFC_CHIP_ULAW, &hc->chip)) 1508 r_conf_en = V_CONF_EN | V_ULAW; 1509 else 1510 r_conf_en = V_CONF_EN; 1511 if (hc->ctype != HFC_TYPE_XHFC) 1512 HFC_outb(hc, R_CONF_EN, r_conf_en); 1513 1514 /* setting leds */ 1515 switch (hc->leds) { 1516 case 1: /* HFC-E1 OEM */ 1517 if (test_bit(HFC_CHIP_WATCHDOG, &hc->chip)) 1518 HFC_outb(hc, R_GPIO_SEL, 0x32); 1519 else 1520 HFC_outb(hc, R_GPIO_SEL, 0x30); 1521 1522 HFC_outb(hc, R_GPIO_EN1, 0x0f); 1523 HFC_outb(hc, R_GPIO_OUT1, 0x00); 1524 1525 HFC_outb(hc, R_GPIO_EN0, V_GPIO_EN2 | V_GPIO_EN3); 1526 break; 1527 1528 case 2: /* HFC-4S OEM */ 1529 case 3: 1530 HFC_outb(hc, R_GPIO_SEL, 0xf0); 1531 HFC_outb(hc, R_GPIO_EN1, 0xff); 1532 HFC_outb(hc, R_GPIO_OUT1, 0x00); 1533 break; 1534 } 1535 1536 if (test_bit(HFC_CHIP_EMBSD, &hc->chip)) { 1537 hc->hw.r_st_sync = 0x10; /* V_AUTO_SYNCI */ 1538 HFC_outb(hc, R_ST_SYNC, hc->hw.r_st_sync); 1539 } 1540 1541 /* set master clock */ 1542 if (hc->masterclk >= 0) { 1543 if (debug & DEBUG_HFCMULTI_INIT) 1544 printk(KERN_DEBUG "%s: setting ST master clock " 1545 "to port %d (0..%d)\n", 1546 __func__, hc->masterclk, hc->ports - 1); 1547 hc->hw.r_st_sync |= (hc->masterclk | V_AUTO_SYNC); 1548 HFC_outb(hc, R_ST_SYNC, hc->hw.r_st_sync); 1549 } 1550 1551 1552 1553 /* setting misc irq */ 1554 HFC_outb(hc, R_IRQMSK_MISC, hc->hw.r_irqmsk_misc); 1555 if (debug & DEBUG_HFCMULTI_INIT) 1556 printk(KERN_DEBUG "r_irqmsk_misc.2: 0x%x\n", 1557 hc->hw.r_irqmsk_misc); 1558 1559 /* RAM access test */ 1560 HFC_outb(hc, R_RAM_ADDR0, 0); 1561 HFC_outb(hc, R_RAM_ADDR1, 0); 1562 HFC_outb(hc, R_RAM_ADDR2, 0); 1563 for (i = 0; i < 256; i++) { 1564 HFC_outb_nodebug(hc, R_RAM_ADDR0, i); 1565 HFC_outb_nodebug(hc, R_RAM_DATA, ((i * 3) & 0xff)); 1566 } 1567 for (i = 0; i < 256; i++) { 1568 HFC_outb_nodebug(hc, R_RAM_ADDR0, i); 1569 HFC_inb_nodebug(hc, R_RAM_DATA); 1570 rval = HFC_inb_nodebug(hc, R_INT_DATA); 1571 if (rval != ((i * 3) & 0xff)) { 1572 printk(KERN_DEBUG 1573 "addr:%x val:%x should:%x\n", i, rval, 1574 (i * 3) & 0xff); 1575 err++; 1576 } 1577 } 1578 if (err) { 1579 printk(KERN_DEBUG "aborting - %d RAM access errors\n", err); 1580 err = -EIO; 1581 goto out; 1582 } 1583 1584 if (debug & DEBUG_HFCMULTI_INIT) 1585 printk(KERN_DEBUG "%s: done\n", __func__); 1586 out: 1587 spin_unlock_irqrestore(&hc->lock, flags); 1588 return err; 1589 } 1590 1591 1592 /* 1593 * control the watchdog 1594 */ 1595 static void 1596 hfcmulti_watchdog(struct hfc_multi *hc) 1597 { 1598 hc->wdcount++; 1599 1600 if (hc->wdcount > 10) { 1601 hc->wdcount = 0; 1602 hc->wdbyte = hc->wdbyte == V_GPIO_OUT2 ? 1603 V_GPIO_OUT3 : V_GPIO_OUT2; 1604 1605 /* printk("Sending Watchdog Kill %x\n",hc->wdbyte); */ 1606 HFC_outb(hc, R_GPIO_EN0, V_GPIO_EN2 | V_GPIO_EN3); 1607 HFC_outb(hc, R_GPIO_OUT0, hc->wdbyte); 1608 } 1609 } 1610 1611 1612 1613 /* 1614 * output leds 1615 */ 1616 static void 1617 hfcmulti_leds(struct hfc_multi *hc) 1618 { 1619 unsigned long lled; 1620 unsigned long leddw; 1621 int i, state, active, leds; 1622 struct dchannel *dch; 1623 int led[4]; 1624 1625 switch (hc->leds) { 1626 case 1: /* HFC-E1 OEM */ 1627 /* 2 red steady: LOS 1628 * 1 red steady: L1 not active 1629 * 2 green steady: L1 active 1630 * 1st green flashing: activity on TX 1631 * 2nd green flashing: activity on RX 1632 */ 1633 led[0] = 0; 1634 led[1] = 0; 1635 led[2] = 0; 1636 led[3] = 0; 1637 dch = hc->chan[hc->dnum[0]].dch; 1638 if (dch) { 1639 if (hc->chan[hc->dnum[0]].los) 1640 led[1] = 1; 1641 if (hc->e1_state != 1) { 1642 led[0] = 1; 1643 hc->flash[2] = 0; 1644 hc->flash[3] = 0; 1645 } else { 1646 led[2] = 1; 1647 led[3] = 1; 1648 if (!hc->flash[2] && hc->activity_tx) 1649 hc->flash[2] = poll; 1650 if (!hc->flash[3] && hc->activity_rx) 1651 hc->flash[3] = poll; 1652 if (hc->flash[2] && hc->flash[2] < 1024) 1653 led[2] = 0; 1654 if (hc->flash[3] && hc->flash[3] < 1024) 1655 led[3] = 0; 1656 if (hc->flash[2] >= 2048) 1657 hc->flash[2] = 0; 1658 if (hc->flash[3] >= 2048) 1659 hc->flash[3] = 0; 1660 if (hc->flash[2]) 1661 hc->flash[2] += poll; 1662 if (hc->flash[3]) 1663 hc->flash[3] += poll; 1664 } 1665 } 1666 leds = (led[0] | (led[1]<<2) | (led[2]<<1) | (led[3]<<3))^0xF; 1667 /* leds are inverted */ 1668 if (leds != (int)hc->ledstate) { 1669 HFC_outb_nodebug(hc, R_GPIO_OUT1, leds); 1670 hc->ledstate = leds; 1671 } 1672 break; 1673 1674 case 2: /* HFC-4S OEM */ 1675 /* red steady: PH_DEACTIVATE 1676 * green steady: PH_ACTIVATE 1677 * green flashing: activity on TX 1678 */ 1679 for (i = 0; i < 4; i++) { 1680 state = 0; 1681 active = -1; 1682 dch = hc->chan[(i << 2) | 2].dch; 1683 if (dch) { 1684 state = dch->state; 1685 if (dch->dev.D.protocol == ISDN_P_NT_S0) 1686 active = 3; 1687 else 1688 active = 7; 1689 } 1690 if (state) { 1691 if (state == active) { 1692 led[i] = 1; /* led green */ 1693 hc->activity_tx |= hc->activity_rx; 1694 if (!hc->flash[i] && 1695 (hc->activity_tx & (1 << i))) 1696 hc->flash[i] = poll; 1697 if (hc->flash[i] && hc->flash[i] < 1024) 1698 led[i] = 0; /* led off */ 1699 if (hc->flash[i] >= 2048) 1700 hc->flash[i] = 0; 1701 if (hc->flash[i]) 1702 hc->flash[i] += poll; 1703 } else { 1704 led[i] = 2; /* led red */ 1705 hc->flash[i] = 0; 1706 } 1707 } else 1708 led[i] = 0; /* led off */ 1709 } 1710 if (test_bit(HFC_CHIP_B410P, &hc->chip)) { 1711 leds = 0; 1712 for (i = 0; i < 4; i++) { 1713 if (led[i] == 1) { 1714 /*green*/ 1715 leds |= (0x2 << (i * 2)); 1716 } else if (led[i] == 2) { 1717 /*red*/ 1718 leds |= (0x1 << (i * 2)); 1719 } 1720 } 1721 if (leds != (int)hc->ledstate) { 1722 vpm_out(hc, 0, 0x1a8 + 3, leds); 1723 hc->ledstate = leds; 1724 } 1725 } else { 1726 leds = ((led[3] > 0) << 0) | ((led[1] > 0) << 1) | 1727 ((led[0] > 0) << 2) | ((led[2] > 0) << 3) | 1728 ((led[3] & 1) << 4) | ((led[1] & 1) << 5) | 1729 ((led[0] & 1) << 6) | ((led[2] & 1) << 7); 1730 if (leds != (int)hc->ledstate) { 1731 HFC_outb_nodebug(hc, R_GPIO_EN1, leds & 0x0F); 1732 HFC_outb_nodebug(hc, R_GPIO_OUT1, leds >> 4); 1733 hc->ledstate = leds; 1734 } 1735 } 1736 break; 1737 1738 case 3: /* HFC 1S/2S Beronet */ 1739 /* red steady: PH_DEACTIVATE 1740 * green steady: PH_ACTIVATE 1741 * green flashing: activity on TX 1742 */ 1743 for (i = 0; i < 2; i++) { 1744 state = 0; 1745 active = -1; 1746 dch = hc->chan[(i << 2) | 2].dch; 1747 if (dch) { 1748 state = dch->state; 1749 if (dch->dev.D.protocol == ISDN_P_NT_S0) 1750 active = 3; 1751 else 1752 active = 7; 1753 } 1754 if (state) { 1755 if (state == active) { 1756 led[i] = 1; /* led green */ 1757 hc->activity_tx |= hc->activity_rx; 1758 if (!hc->flash[i] && 1759 (hc->activity_tx & (1 << i))) 1760 hc->flash[i] = poll; 1761 if (hc->flash[i] < 1024) 1762 led[i] = 0; /* led off */ 1763 if (hc->flash[i] >= 2048) 1764 hc->flash[i] = 0; 1765 if (hc->flash[i]) 1766 hc->flash[i] += poll; 1767 } else { 1768 led[i] = 2; /* led red */ 1769 hc->flash[i] = 0; 1770 } 1771 } else 1772 led[i] = 0; /* led off */ 1773 } 1774 leds = (led[0] > 0) | ((led[1] > 0) << 1) | ((led[0]&1) << 2) 1775 | ((led[1]&1) << 3); 1776 if (leds != (int)hc->ledstate) { 1777 HFC_outb_nodebug(hc, R_GPIO_EN1, 1778 ((led[0] > 0) << 2) | ((led[1] > 0) << 3)); 1779 HFC_outb_nodebug(hc, R_GPIO_OUT1, 1780 ((led[0] & 1) << 2) | ((led[1] & 1) << 3)); 1781 hc->ledstate = leds; 1782 } 1783 break; 1784 case 8: /* HFC 8S+ Beronet */ 1785 /* off: PH_DEACTIVATE 1786 * steady: PH_ACTIVATE 1787 * flashing: activity on TX 1788 */ 1789 lled = 0xff; /* leds off */ 1790 for (i = 0; i < 8; i++) { 1791 state = 0; 1792 active = -1; 1793 dch = hc->chan[(i << 2) | 2].dch; 1794 if (dch) { 1795 state = dch->state; 1796 if (dch->dev.D.protocol == ISDN_P_NT_S0) 1797 active = 3; 1798 else 1799 active = 7; 1800 } 1801 if (state) { 1802 if (state == active) { 1803 lled &= ~(1 << i); /* led on */ 1804 hc->activity_tx |= hc->activity_rx; 1805 if (!hc->flash[i] && 1806 (hc->activity_tx & (1 << i))) 1807 hc->flash[i] = poll; 1808 if (hc->flash[i] < 1024) 1809 lled |= 1 << i; /* led off */ 1810 if (hc->flash[i] >= 2048) 1811 hc->flash[i] = 0; 1812 if (hc->flash[i]) 1813 hc->flash[i] += poll; 1814 } else 1815 hc->flash[i] = 0; 1816 } 1817 } 1818 leddw = lled << 24 | lled << 16 | lled << 8 | lled; 1819 if (leddw != hc->ledstate) { 1820 /* HFC_outb(hc, R_BRG_PCM_CFG, 1); 1821 HFC_outb(c, R_BRG_PCM_CFG, (0x0 << 6) | 0x3); */ 1822 /* was _io before */ 1823 HFC_outb_nodebug(hc, R_BRG_PCM_CFG, 1 | V_PCM_CLK); 1824 outw(0x4000, hc->pci_iobase + 4); 1825 outl(leddw, hc->pci_iobase); 1826 HFC_outb_nodebug(hc, R_BRG_PCM_CFG, V_PCM_CLK); 1827 hc->ledstate = leddw; 1828 } 1829 break; 1830 } 1831 hc->activity_tx = 0; 1832 hc->activity_rx = 0; 1833 } 1834 /* 1835 * read dtmf coefficients 1836 */ 1837 1838 static void 1839 hfcmulti_dtmf(struct hfc_multi *hc) 1840 { 1841 s32 *coeff; 1842 u_int mantissa; 1843 int co, ch; 1844 struct bchannel *bch = NULL; 1845 u8 exponent; 1846 int dtmf = 0; 1847 int addr; 1848 u16 w_float; 1849 struct sk_buff *skb; 1850 struct mISDNhead *hh; 1851 1852 if (debug & DEBUG_HFCMULTI_DTMF) 1853 printk(KERN_DEBUG "%s: dtmf detection irq\n", __func__); 1854 for (ch = 0; ch <= 31; ch++) { 1855 /* only process enabled B-channels */ 1856 bch = hc->chan[ch].bch; 1857 if (!bch) 1858 continue; 1859 if (!hc->created[hc->chan[ch].port]) 1860 continue; 1861 if (!test_bit(FLG_TRANSPARENT, &bch->Flags)) 1862 continue; 1863 if (debug & DEBUG_HFCMULTI_DTMF) 1864 printk(KERN_DEBUG "%s: dtmf channel %d:", 1865 __func__, ch); 1866 coeff = &(hc->chan[ch].coeff[hc->chan[ch].coeff_count * 16]); 1867 dtmf = 1; 1868 for (co = 0; co < 8; co++) { 1869 /* read W(n-1) coefficient */ 1870 addr = hc->DTMFbase + ((co << 7) | (ch << 2)); 1871 HFC_outb_nodebug(hc, R_RAM_ADDR0, addr); 1872 HFC_outb_nodebug(hc, R_RAM_ADDR1, addr >> 8); 1873 HFC_outb_nodebug(hc, R_RAM_ADDR2, (addr >> 16) 1874 | V_ADDR_INC); 1875 w_float = HFC_inb_nodebug(hc, R_RAM_DATA); 1876 w_float |= (HFC_inb_nodebug(hc, R_RAM_DATA) << 8); 1877 if (debug & DEBUG_HFCMULTI_DTMF) 1878 printk(" %04x", w_float); 1879 1880 /* decode float (see chip doc) */ 1881 mantissa = w_float & 0x0fff; 1882 if (w_float & 0x8000) 1883 mantissa |= 0xfffff000; 1884 exponent = (w_float >> 12) & 0x7; 1885 if (exponent) { 1886 mantissa ^= 0x1000; 1887 mantissa <<= (exponent - 1); 1888 } 1889 1890 /* store coefficient */ 1891 coeff[co << 1] = mantissa; 1892 1893 /* read W(n) coefficient */ 1894 w_float = HFC_inb_nodebug(hc, R_RAM_DATA); 1895 w_float |= (HFC_inb_nodebug(hc, R_RAM_DATA) << 8); 1896 if (debug & DEBUG_HFCMULTI_DTMF) 1897 printk(" %04x", w_float); 1898 1899 /* decode float (see chip doc) */ 1900 mantissa = w_float & 0x0fff; 1901 if (w_float & 0x8000) 1902 mantissa |= 0xfffff000; 1903 exponent = (w_float >> 12) & 0x7; 1904 if (exponent) { 1905 mantissa ^= 0x1000; 1906 mantissa <<= (exponent - 1); 1907 } 1908 1909 /* store coefficient */ 1910 coeff[(co << 1) | 1] = mantissa; 1911 } 1912 if (debug & DEBUG_HFCMULTI_DTMF) 1913 printk(" DTMF ready %08x %08x %08x %08x " 1914 "%08x %08x %08x %08x\n", 1915 coeff[0], coeff[1], coeff[2], coeff[3], 1916 coeff[4], coeff[5], coeff[6], coeff[7]); 1917 hc->chan[ch].coeff_count++; 1918 if (hc->chan[ch].coeff_count == 8) { 1919 hc->chan[ch].coeff_count = 0; 1920 skb = mI_alloc_skb(512, GFP_ATOMIC); 1921 if (!skb) { 1922 printk(KERN_DEBUG "%s: No memory for skb\n", 1923 __func__); 1924 continue; 1925 } 1926 hh = mISDN_HEAD_P(skb); 1927 hh->prim = PH_CONTROL_IND; 1928 hh->id = DTMF_HFC_COEF; 1929 memcpy(skb_put(skb, 512), hc->chan[ch].coeff, 512); 1930 recv_Bchannel_skb(bch, skb); 1931 } 1932 } 1933 1934 /* restart DTMF processing */ 1935 hc->dtmf = dtmf; 1936 if (dtmf) 1937 HFC_outb_nodebug(hc, R_DTMF, hc->hw.r_dtmf | V_RST_DTMF); 1938 } 1939 1940 1941 /* 1942 * fill fifo as much as possible 1943 */ 1944 1945 static void 1946 hfcmulti_tx(struct hfc_multi *hc, int ch) 1947 { 1948 int i, ii, temp, len = 0; 1949 int Zspace, z1, z2; /* must be int for calculation */ 1950 int Fspace, f1, f2; 1951 u_char *d; 1952 int *txpending, slot_tx; 1953 struct bchannel *bch; 1954 struct dchannel *dch; 1955 struct sk_buff **sp = NULL; 1956 int *idxp; 1957 1958 bch = hc->chan[ch].bch; 1959 dch = hc->chan[ch].dch; 1960 if ((!dch) && (!bch)) 1961 return; 1962 1963 txpending = &hc->chan[ch].txpending; 1964 slot_tx = hc->chan[ch].slot_tx; 1965 if (dch) { 1966 if (!test_bit(FLG_ACTIVE, &dch->Flags)) 1967 return; 1968 sp = &dch->tx_skb; 1969 idxp = &dch->tx_idx; 1970 } else { 1971 if (!test_bit(FLG_ACTIVE, &bch->Flags)) 1972 return; 1973 sp = &bch->tx_skb; 1974 idxp = &bch->tx_idx; 1975 } 1976 if (*sp) 1977 len = (*sp)->len; 1978 1979 if ((!len) && *txpending != 1) 1980 return; /* no data */ 1981 1982 if (test_bit(HFC_CHIP_B410P, &hc->chip) && 1983 (hc->chan[ch].protocol == ISDN_P_B_RAW) && 1984 (hc->chan[ch].slot_rx < 0) && 1985 (hc->chan[ch].slot_tx < 0)) 1986 HFC_outb_nodebug(hc, R_FIFO, 0x20 | (ch << 1)); 1987 else 1988 HFC_outb_nodebug(hc, R_FIFO, ch << 1); 1989 HFC_wait_nodebug(hc); 1990 1991 if (*txpending == 2) { 1992 /* reset fifo */ 1993 HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_RES_F); 1994 HFC_wait_nodebug(hc); 1995 HFC_outb(hc, A_SUBCH_CFG, 0); 1996 *txpending = 1; 1997 } 1998 next_frame: 1999 if (dch || test_bit(FLG_HDLC, &bch->Flags)) { 2000 f1 = HFC_inb_nodebug(hc, A_F1); 2001 f2 = HFC_inb_nodebug(hc, A_F2); 2002 while (f2 != (temp = HFC_inb_nodebug(hc, A_F2))) { 2003 if (debug & DEBUG_HFCMULTI_FIFO) 2004 printk(KERN_DEBUG 2005 "%s(card %d): reread f2 because %d!=%d\n", 2006 __func__, hc->id + 1, temp, f2); 2007 f2 = temp; /* repeat until F2 is equal */ 2008 } 2009 Fspace = f2 - f1 - 1; 2010 if (Fspace < 0) 2011 Fspace += hc->Flen; 2012 /* 2013 * Old FIFO handling doesn't give us the current Z2 read 2014 * pointer, so we cannot send the next frame before the fifo 2015 * is empty. It makes no difference except for a slightly 2016 * lower performance. 2017 */ 2018 if (test_bit(HFC_CHIP_REVISION0, &hc->chip)) { 2019 if (f1 != f2) 2020 Fspace = 0; 2021 else 2022 Fspace = 1; 2023 } 2024 /* one frame only for ST D-channels, to allow resending */ 2025 if (hc->ctype != HFC_TYPE_E1 && dch) { 2026 if (f1 != f2) 2027 Fspace = 0; 2028 } 2029 /* F-counter full condition */ 2030 if (Fspace == 0) 2031 return; 2032 } 2033 z1 = HFC_inw_nodebug(hc, A_Z1) - hc->Zmin; 2034 z2 = HFC_inw_nodebug(hc, A_Z2) - hc->Zmin; 2035 while (z2 != (temp = (HFC_inw_nodebug(hc, A_Z2) - hc->Zmin))) { 2036 if (debug & DEBUG_HFCMULTI_FIFO) 2037 printk(KERN_DEBUG "%s(card %d): reread z2 because " 2038 "%d!=%d\n", __func__, hc->id + 1, temp, z2); 2039 z2 = temp; /* repeat unti Z2 is equal */ 2040 } 2041 hc->chan[ch].Zfill = z1 - z2; 2042 if (hc->chan[ch].Zfill < 0) 2043 hc->chan[ch].Zfill += hc->Zlen; 2044 Zspace = z2 - z1; 2045 if (Zspace <= 0) 2046 Zspace += hc->Zlen; 2047 Zspace -= 4; /* keep not too full, so pointers will not overrun */ 2048 /* fill transparent data only to maxinum transparent load (minus 4) */ 2049 if (bch && test_bit(FLG_TRANSPARENT, &bch->Flags)) 2050 Zspace = Zspace - hc->Zlen + hc->max_trans; 2051 if (Zspace <= 0) /* no space of 4 bytes */ 2052 return; 2053 2054 /* if no data */ 2055 if (!len) { 2056 if (z1 == z2) { /* empty */ 2057 /* if done with FIFO audio data during PCM connection */ 2058 if (bch && (!test_bit(FLG_HDLC, &bch->Flags)) && 2059 *txpending && slot_tx >= 0) { 2060 if (debug & DEBUG_HFCMULTI_MODE) 2061 printk(KERN_DEBUG 2062 "%s: reconnecting PCM due to no " 2063 "more FIFO data: channel %d " 2064 "slot_tx %d\n", 2065 __func__, ch, slot_tx); 2066 /* connect slot */ 2067 if (hc->ctype == HFC_TYPE_XHFC) 2068 HFC_outb(hc, A_CON_HDLC, 0xc0 2069 | 0x07 << 2 | V_HDLC_TRP | V_IFF); 2070 /* Enable FIFO, no interrupt */ 2071 else 2072 HFC_outb(hc, A_CON_HDLC, 0xc0 | 0x00 | 2073 V_HDLC_TRP | V_IFF); 2074 HFC_outb_nodebug(hc, R_FIFO, ch << 1 | 1); 2075 HFC_wait_nodebug(hc); 2076 if (hc->ctype == HFC_TYPE_XHFC) 2077 HFC_outb(hc, A_CON_HDLC, 0xc0 2078 | 0x07 << 2 | V_HDLC_TRP | V_IFF); 2079 /* Enable FIFO, no interrupt */ 2080 else 2081 HFC_outb(hc, A_CON_HDLC, 0xc0 | 0x00 | 2082 V_HDLC_TRP | V_IFF); 2083 HFC_outb_nodebug(hc, R_FIFO, ch << 1); 2084 HFC_wait_nodebug(hc); 2085 } 2086 *txpending = 0; 2087 } 2088 return; /* no data */ 2089 } 2090 2091 /* "fill fifo if empty" feature */ 2092 if (bch && test_bit(FLG_FILLEMPTY, &bch->Flags) 2093 && !test_bit(FLG_HDLC, &bch->Flags) && z2 == z1) { 2094 if (debug & DEBUG_HFCMULTI_FILL) 2095 printk(KERN_DEBUG "%s: buffer empty, so we have " 2096 "underrun\n", __func__); 2097 /* fill buffer, to prevent future underrun */ 2098 hc->write_fifo(hc, hc->silence_data, poll >> 1); 2099 Zspace -= (poll >> 1); 2100 } 2101 2102 /* if audio data and connected slot */ 2103 if (bch && (!test_bit(FLG_HDLC, &bch->Flags)) && (!*txpending) 2104 && slot_tx >= 0) { 2105 if (debug & DEBUG_HFCMULTI_MODE) 2106 printk(KERN_DEBUG "%s: disconnecting PCM due to " 2107 "FIFO data: channel %d slot_tx %d\n", 2108 __func__, ch, slot_tx); 2109 /* disconnect slot */ 2110 if (hc->ctype == HFC_TYPE_XHFC) 2111 HFC_outb(hc, A_CON_HDLC, 0x80 2112 | 0x07 << 2 | V_HDLC_TRP | V_IFF); 2113 /* Enable FIFO, no interrupt */ 2114 else 2115 HFC_outb(hc, A_CON_HDLC, 0x80 | 0x00 | 2116 V_HDLC_TRP | V_IFF); 2117 HFC_outb_nodebug(hc, R_FIFO, ch << 1 | 1); 2118 HFC_wait_nodebug(hc); 2119 if (hc->ctype == HFC_TYPE_XHFC) 2120 HFC_outb(hc, A_CON_HDLC, 0x80 2121 | 0x07 << 2 | V_HDLC_TRP | V_IFF); 2122 /* Enable FIFO, no interrupt */ 2123 else 2124 HFC_outb(hc, A_CON_HDLC, 0x80 | 0x00 | 2125 V_HDLC_TRP | V_IFF); 2126 HFC_outb_nodebug(hc, R_FIFO, ch << 1); 2127 HFC_wait_nodebug(hc); 2128 } 2129 *txpending = 1; 2130 2131 /* show activity */ 2132 if (dch) 2133 hc->activity_tx |= 1 << hc->chan[ch].port; 2134 2135 /* fill fifo to what we have left */ 2136 ii = len; 2137 if (dch || test_bit(FLG_HDLC, &bch->Flags)) 2138 temp = 1; 2139 else 2140 temp = 0; 2141 i = *idxp; 2142 d = (*sp)->data + i; 2143 if (ii - i > Zspace) 2144 ii = Zspace + i; 2145 if (debug & DEBUG_HFCMULTI_FIFO) 2146 printk(KERN_DEBUG "%s(card %d): fifo(%d) has %d bytes space " 2147 "left (z1=%04x, z2=%04x) sending %d of %d bytes %s\n", 2148 __func__, hc->id + 1, ch, Zspace, z1, z2, ii-i, len-i, 2149 temp ? "HDLC" : "TRANS"); 2150 2151 /* Have to prep the audio data */ 2152 hc->write_fifo(hc, d, ii - i); 2153 hc->chan[ch].Zfill += ii - i; 2154 *idxp = ii; 2155 2156 /* if not all data has been written */ 2157 if (ii != len) { 2158 /* NOTE: fifo is started by the calling function */ 2159 return; 2160 } 2161 2162 /* if all data has been written, terminate frame */ 2163 if (dch || test_bit(FLG_HDLC, &bch->Flags)) { 2164 /* increment f-counter */ 2165 HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_INC_F); 2166 HFC_wait_nodebug(hc); 2167 } 2168 2169 /* send confirm, since get_net_bframe will not do it with trans */ 2170 if (bch && test_bit(FLG_TRANSPARENT, &bch->Flags)) 2171 confirm_Bsend(bch); 2172 2173 /* check for next frame */ 2174 dev_kfree_skb(*sp); 2175 if (bch && get_next_bframe(bch)) { /* hdlc is confirmed here */ 2176 len = (*sp)->len; 2177 goto next_frame; 2178 } 2179 if (dch && get_next_dframe(dch)) { 2180 len = (*sp)->len; 2181 goto next_frame; 2182 } 2183 2184 /* 2185 * now we have no more data, so in case of transparent, 2186 * we set the last byte in fifo to 'silence' in case we will get 2187 * no more data at all. this prevents sending an undefined value. 2188 */ 2189 if (bch && test_bit(FLG_TRANSPARENT, &bch->Flags)) 2190 HFC_outb_nodebug(hc, A_FIFO_DATA0_NOINC, hc->silence); 2191 } 2192 2193 2194 /* NOTE: only called if E1 card is in active state */ 2195 static void 2196 hfcmulti_rx(struct hfc_multi *hc, int ch) 2197 { 2198 int temp; 2199 int Zsize, z1, z2 = 0; /* = 0, to make GCC happy */ 2200 int f1 = 0, f2 = 0; /* = 0, to make GCC happy */ 2201 int again = 0; 2202 struct bchannel *bch; 2203 struct dchannel *dch; 2204 struct sk_buff *skb, **sp = NULL; 2205 int maxlen; 2206 2207 bch = hc->chan[ch].bch; 2208 dch = hc->chan[ch].dch; 2209 if ((!dch) && (!bch)) 2210 return; 2211 if (dch) { 2212 if (!test_bit(FLG_ACTIVE, &dch->Flags)) 2213 return; 2214 sp = &dch->rx_skb; 2215 maxlen = dch->maxlen; 2216 } else { 2217 if (!test_bit(FLG_ACTIVE, &bch->Flags)) 2218 return; 2219 sp = &bch->rx_skb; 2220 maxlen = bch->maxlen; 2221 } 2222 next_frame: 2223 /* on first AND before getting next valid frame, R_FIFO must be written 2224 to. */ 2225 if (test_bit(HFC_CHIP_B410P, &hc->chip) && 2226 (hc->chan[ch].protocol == ISDN_P_B_RAW) && 2227 (hc->chan[ch].slot_rx < 0) && 2228 (hc->chan[ch].slot_tx < 0)) 2229 HFC_outb_nodebug(hc, R_FIFO, 0x20 | (ch << 1) | 1); 2230 else 2231 HFC_outb_nodebug(hc, R_FIFO, (ch << 1) | 1); 2232 HFC_wait_nodebug(hc); 2233 2234 /* ignore if rx is off BUT change fifo (above) to start pending TX */ 2235 if (hc->chan[ch].rx_off) 2236 return; 2237 2238 if (dch || test_bit(FLG_HDLC, &bch->Flags)) { 2239 f1 = HFC_inb_nodebug(hc, A_F1); 2240 while (f1 != (temp = HFC_inb_nodebug(hc, A_F1))) { 2241 if (debug & DEBUG_HFCMULTI_FIFO) 2242 printk(KERN_DEBUG 2243 "%s(card %d): reread f1 because %d!=%d\n", 2244 __func__, hc->id + 1, temp, f1); 2245 f1 = temp; /* repeat until F1 is equal */ 2246 } 2247 f2 = HFC_inb_nodebug(hc, A_F2); 2248 } 2249 z1 = HFC_inw_nodebug(hc, A_Z1) - hc->Zmin; 2250 while (z1 != (temp = (HFC_inw_nodebug(hc, A_Z1) - hc->Zmin))) { 2251 if (debug & DEBUG_HFCMULTI_FIFO) 2252 printk(KERN_DEBUG "%s(card %d): reread z2 because " 2253 "%d!=%d\n", __func__, hc->id + 1, temp, z2); 2254 z1 = temp; /* repeat until Z1 is equal */ 2255 } 2256 z2 = HFC_inw_nodebug(hc, A_Z2) - hc->Zmin; 2257 Zsize = z1 - z2; 2258 if ((dch || test_bit(FLG_HDLC, &bch->Flags)) && f1 != f2) 2259 /* complete hdlc frame */ 2260 Zsize++; 2261 if (Zsize < 0) 2262 Zsize += hc->Zlen; 2263 /* if buffer is empty */ 2264 if (Zsize <= 0) 2265 return; 2266 2267 if (*sp == NULL) { 2268 *sp = mI_alloc_skb(maxlen + 3, GFP_ATOMIC); 2269 if (*sp == NULL) { 2270 printk(KERN_DEBUG "%s: No mem for rx_skb\n", 2271 __func__); 2272 return; 2273 } 2274 } 2275 /* show activity */ 2276 if (dch) 2277 hc->activity_rx |= 1 << hc->chan[ch].port; 2278 2279 /* empty fifo with what we have */ 2280 if (dch || test_bit(FLG_HDLC, &bch->Flags)) { 2281 if (debug & DEBUG_HFCMULTI_FIFO) 2282 printk(KERN_DEBUG "%s(card %d): fifo(%d) reading %d " 2283 "bytes (z1=%04x, z2=%04x) HDLC %s (f1=%d, f2=%d) " 2284 "got=%d (again %d)\n", __func__, hc->id + 1, ch, 2285 Zsize, z1, z2, (f1 == f2) ? "fragment" : "COMPLETE", 2286 f1, f2, Zsize + (*sp)->len, again); 2287 /* HDLC */ 2288 if ((Zsize + (*sp)->len) > (maxlen + 3)) { 2289 if (debug & DEBUG_HFCMULTI_FIFO) 2290 printk(KERN_DEBUG 2291 "%s(card %d): hdlc-frame too large.\n", 2292 __func__, hc->id + 1); 2293 skb_trim(*sp, 0); 2294 HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_RES_F); 2295 HFC_wait_nodebug(hc); 2296 return; 2297 } 2298 2299 hc->read_fifo(hc, skb_put(*sp, Zsize), Zsize); 2300 2301 if (f1 != f2) { 2302 /* increment Z2,F2-counter */ 2303 HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_INC_F); 2304 HFC_wait_nodebug(hc); 2305 /* check size */ 2306 if ((*sp)->len < 4) { 2307 if (debug & DEBUG_HFCMULTI_FIFO) 2308 printk(KERN_DEBUG 2309 "%s(card %d): Frame below minimum " 2310 "size\n", __func__, hc->id + 1); 2311 skb_trim(*sp, 0); 2312 goto next_frame; 2313 } 2314 /* there is at least one complete frame, check crc */ 2315 if ((*sp)->data[(*sp)->len - 1]) { 2316 if (debug & DEBUG_HFCMULTI_CRC) 2317 printk(KERN_DEBUG 2318 "%s: CRC-error\n", __func__); 2319 skb_trim(*sp, 0); 2320 goto next_frame; 2321 } 2322 skb_trim(*sp, (*sp)->len - 3); 2323 if ((*sp)->len < MISDN_COPY_SIZE) { 2324 skb = *sp; 2325 *sp = mI_alloc_skb(skb->len, GFP_ATOMIC); 2326 if (*sp) { 2327 memcpy(skb_put(*sp, skb->len), 2328 skb->data, skb->len); 2329 skb_trim(skb, 0); 2330 } else { 2331 printk(KERN_DEBUG "%s: No mem\n", 2332 __func__); 2333 *sp = skb; 2334 skb = NULL; 2335 } 2336 } else { 2337 skb = NULL; 2338 } 2339 if (debug & DEBUG_HFCMULTI_FIFO) { 2340 printk(KERN_DEBUG "%s(card %d):", 2341 __func__, hc->id + 1); 2342 temp = 0; 2343 while (temp < (*sp)->len) 2344 printk(" %02x", (*sp)->data[temp++]); 2345 printk("\n"); 2346 } 2347 if (dch) 2348 recv_Dchannel(dch); 2349 else 2350 recv_Bchannel(bch, MISDN_ID_ANY); 2351 *sp = skb; 2352 again++; 2353 goto next_frame; 2354 } 2355 /* there is an incomplete frame */ 2356 } else { 2357 /* transparent */ 2358 if (Zsize > skb_tailroom(*sp)) 2359 Zsize = skb_tailroom(*sp); 2360 hc->read_fifo(hc, skb_put(*sp, Zsize), Zsize); 2361 if (((*sp)->len) < MISDN_COPY_SIZE) { 2362 skb = *sp; 2363 *sp = mI_alloc_skb(skb->len, GFP_ATOMIC); 2364 if (*sp) { 2365 memcpy(skb_put(*sp, skb->len), 2366 skb->data, skb->len); 2367 skb_trim(skb, 0); 2368 } else { 2369 printk(KERN_DEBUG "%s: No mem\n", __func__); 2370 *sp = skb; 2371 skb = NULL; 2372 } 2373 } else { 2374 skb = NULL; 2375 } 2376 if (debug & DEBUG_HFCMULTI_FIFO) 2377 printk(KERN_DEBUG 2378 "%s(card %d): fifo(%d) reading %d bytes " 2379 "(z1=%04x, z2=%04x) TRANS\n", 2380 __func__, hc->id + 1, ch, Zsize, z1, z2); 2381 /* only bch is transparent */ 2382 recv_Bchannel(bch, hc->chan[ch].Zfill); 2383 *sp = skb; 2384 } 2385 } 2386 2387 2388 /* 2389 * Interrupt handler 2390 */ 2391 static void 2392 signal_state_up(struct dchannel *dch, int info, char *msg) 2393 { 2394 struct sk_buff *skb; 2395 int id, data = info; 2396 2397 if (debug & DEBUG_HFCMULTI_STATE) 2398 printk(KERN_DEBUG "%s: %s\n", __func__, msg); 2399 2400 id = TEI_SAPI | (GROUP_TEI << 8); /* manager address */ 2401 2402 skb = _alloc_mISDN_skb(MPH_INFORMATION_IND, id, sizeof(data), &data, 2403 GFP_ATOMIC); 2404 if (!skb) 2405 return; 2406 recv_Dchannel_skb(dch, skb); 2407 } 2408 2409 static inline void 2410 handle_timer_irq(struct hfc_multi *hc) 2411 { 2412 int ch, temp; 2413 struct dchannel *dch; 2414 u_long flags; 2415 2416 /* process queued resync jobs */ 2417 if (hc->e1_resync) { 2418 /* lock, so e1_resync gets not changed */ 2419 spin_lock_irqsave(&HFClock, flags); 2420 if (hc->e1_resync & 1) { 2421 if (debug & DEBUG_HFCMULTI_PLXSD) 2422 printk(KERN_DEBUG "Enable SYNC_I\n"); 2423 HFC_outb(hc, R_SYNC_CTRL, V_EXT_CLK_SYNC); 2424 /* disable JATT, if RX_SYNC is set */ 2425 if (test_bit(HFC_CHIP_RX_SYNC, &hc->chip)) 2426 HFC_outb(hc, R_SYNC_OUT, V_SYNC_E1_RX); 2427 } 2428 if (hc->e1_resync & 2) { 2429 if (debug & DEBUG_HFCMULTI_PLXSD) 2430 printk(KERN_DEBUG "Enable jatt PLL\n"); 2431 HFC_outb(hc, R_SYNC_CTRL, V_SYNC_OFFS); 2432 } 2433 if (hc->e1_resync & 4) { 2434 if (debug & DEBUG_HFCMULTI_PLXSD) 2435 printk(KERN_DEBUG 2436 "Enable QUARTZ for HFC-E1\n"); 2437 /* set jatt to quartz */ 2438 HFC_outb(hc, R_SYNC_CTRL, V_EXT_CLK_SYNC 2439 | V_JATT_OFF); 2440 /* switch to JATT, in case it is not already */ 2441 HFC_outb(hc, R_SYNC_OUT, 0); 2442 } 2443 hc->e1_resync = 0; 2444 spin_unlock_irqrestore(&HFClock, flags); 2445 } 2446 2447 if (hc->ctype != HFC_TYPE_E1 || hc->e1_state == 1) 2448 for (ch = 0; ch <= 31; ch++) { 2449 if (hc->created[hc->chan[ch].port]) { 2450 hfcmulti_tx(hc, ch); 2451 /* fifo is started when switching to rx-fifo */ 2452 hfcmulti_rx(hc, ch); 2453 if (hc->chan[ch].dch && 2454 hc->chan[ch].nt_timer > -1) { 2455 dch = hc->chan[ch].dch; 2456 if (!(--hc->chan[ch].nt_timer)) { 2457 schedule_event(dch, 2458 FLG_PHCHANGE); 2459 if (debug & 2460 DEBUG_HFCMULTI_STATE) 2461 printk(KERN_DEBUG 2462 "%s: nt_timer at " 2463 "state %x\n", 2464 __func__, 2465 dch->state); 2466 } 2467 } 2468 } 2469 } 2470 if (hc->ctype == HFC_TYPE_E1 && hc->created[0]) { 2471 dch = hc->chan[hc->dnum[0]].dch; 2472 /* LOS */ 2473 temp = HFC_inb_nodebug(hc, R_SYNC_STA) & V_SIG_LOS; 2474 hc->chan[hc->dnum[0]].los = temp; 2475 if (test_bit(HFC_CFG_REPORT_LOS, &hc->chan[hc->dnum[0]].cfg)) { 2476 if (!temp && hc->chan[hc->dnum[0]].los) 2477 signal_state_up(dch, L1_SIGNAL_LOS_ON, 2478 "LOS detected"); 2479 if (temp && !hc->chan[hc->dnum[0]].los) 2480 signal_state_up(dch, L1_SIGNAL_LOS_OFF, 2481 "LOS gone"); 2482 } 2483 if (test_bit(HFC_CFG_REPORT_AIS, &hc->chan[hc->dnum[0]].cfg)) { 2484 /* AIS */ 2485 temp = HFC_inb_nodebug(hc, R_SYNC_STA) & V_AIS; 2486 if (!temp && hc->chan[hc->dnum[0]].ais) 2487 signal_state_up(dch, L1_SIGNAL_AIS_ON, 2488 "AIS detected"); 2489 if (temp && !hc->chan[hc->dnum[0]].ais) 2490 signal_state_up(dch, L1_SIGNAL_AIS_OFF, 2491 "AIS gone"); 2492 hc->chan[hc->dnum[0]].ais = temp; 2493 } 2494 if (test_bit(HFC_CFG_REPORT_SLIP, &hc->chan[hc->dnum[0]].cfg)) { 2495 /* SLIP */ 2496 temp = HFC_inb_nodebug(hc, R_SLIP) & V_FOSLIP_RX; 2497 if (!temp && hc->chan[hc->dnum[0]].slip_rx) 2498 signal_state_up(dch, L1_SIGNAL_SLIP_RX, 2499 " bit SLIP detected RX"); 2500 hc->chan[hc->dnum[0]].slip_rx = temp; 2501 temp = HFC_inb_nodebug(hc, R_SLIP) & V_FOSLIP_TX; 2502 if (!temp && hc->chan[hc->dnum[0]].slip_tx) 2503 signal_state_up(dch, L1_SIGNAL_SLIP_TX, 2504 " bit SLIP detected TX"); 2505 hc->chan[hc->dnum[0]].slip_tx = temp; 2506 } 2507 if (test_bit(HFC_CFG_REPORT_RDI, &hc->chan[hc->dnum[0]].cfg)) { 2508 /* RDI */ 2509 temp = HFC_inb_nodebug(hc, R_RX_SL0_0) & V_A; 2510 if (!temp && hc->chan[hc->dnum[0]].rdi) 2511 signal_state_up(dch, L1_SIGNAL_RDI_ON, 2512 "RDI detected"); 2513 if (temp && !hc->chan[hc->dnum[0]].rdi) 2514 signal_state_up(dch, L1_SIGNAL_RDI_OFF, 2515 "RDI gone"); 2516 hc->chan[hc->dnum[0]].rdi = temp; 2517 } 2518 temp = HFC_inb_nodebug(hc, R_JATT_DIR); 2519 switch (hc->chan[hc->dnum[0]].sync) { 2520 case 0: 2521 if ((temp & 0x60) == 0x60) { 2522 if (debug & DEBUG_HFCMULTI_SYNC) 2523 printk(KERN_DEBUG 2524 "%s: (id=%d) E1 now " 2525 "in clock sync\n", 2526 __func__, hc->id); 2527 HFC_outb(hc, R_RX_OFF, 2528 hc->chan[hc->dnum[0]].jitter | V_RX_INIT); 2529 HFC_outb(hc, R_TX_OFF, 2530 hc->chan[hc->dnum[0]].jitter | V_RX_INIT); 2531 hc->chan[hc->dnum[0]].sync = 1; 2532 goto check_framesync; 2533 } 2534 break; 2535 case 1: 2536 if ((temp & 0x60) != 0x60) { 2537 if (debug & DEBUG_HFCMULTI_SYNC) 2538 printk(KERN_DEBUG 2539 "%s: (id=%d) E1 " 2540 "lost clock sync\n", 2541 __func__, hc->id); 2542 hc->chan[hc->dnum[0]].sync = 0; 2543 break; 2544 } 2545 check_framesync: 2546 temp = HFC_inb_nodebug(hc, R_SYNC_STA); 2547 if (temp == 0x27) { 2548 if (debug & DEBUG_HFCMULTI_SYNC) 2549 printk(KERN_DEBUG 2550 "%s: (id=%d) E1 " 2551 "now in frame sync\n", 2552 __func__, hc->id); 2553 hc->chan[hc->dnum[0]].sync = 2; 2554 } 2555 break; 2556 case 2: 2557 if ((temp & 0x60) != 0x60) { 2558 if (debug & DEBUG_HFCMULTI_SYNC) 2559 printk(KERN_DEBUG 2560 "%s: (id=%d) E1 lost " 2561 "clock & frame sync\n", 2562 __func__, hc->id); 2563 hc->chan[hc->dnum[0]].sync = 0; 2564 break; 2565 } 2566 temp = HFC_inb_nodebug(hc, R_SYNC_STA); 2567 if (temp != 0x27) { 2568 if (debug & DEBUG_HFCMULTI_SYNC) 2569 printk(KERN_DEBUG 2570 "%s: (id=%d) E1 " 2571 "lost frame sync\n", 2572 __func__, hc->id); 2573 hc->chan[hc->dnum[0]].sync = 1; 2574 } 2575 break; 2576 } 2577 } 2578 2579 if (test_bit(HFC_CHIP_WATCHDOG, &hc->chip)) 2580 hfcmulti_watchdog(hc); 2581 2582 if (hc->leds) 2583 hfcmulti_leds(hc); 2584 } 2585 2586 static void 2587 ph_state_irq(struct hfc_multi *hc, u_char r_irq_statech) 2588 { 2589 struct dchannel *dch; 2590 int ch; 2591 int active; 2592 u_char st_status, temp; 2593 2594 /* state machine */ 2595 for (ch = 0; ch <= 31; ch++) { 2596 if (hc->chan[ch].dch) { 2597 dch = hc->chan[ch].dch; 2598 if (r_irq_statech & 1) { 2599 HFC_outb_nodebug(hc, R_ST_SEL, 2600 hc->chan[ch].port); 2601 /* undocumented: delay after R_ST_SEL */ 2602 udelay(1); 2603 /* undocumented: status changes during read */ 2604 st_status = HFC_inb_nodebug(hc, A_ST_RD_STATE); 2605 while (st_status != (temp = 2606 HFC_inb_nodebug(hc, A_ST_RD_STATE))) { 2607 if (debug & DEBUG_HFCMULTI_STATE) 2608 printk(KERN_DEBUG "%s: reread " 2609 "STATE because %d!=%d\n", 2610 __func__, temp, 2611 st_status); 2612 st_status = temp; /* repeat */ 2613 } 2614 2615 /* Speech Design TE-sync indication */ 2616 if (test_bit(HFC_CHIP_PLXSD, &hc->chip) && 2617 dch->dev.D.protocol == ISDN_P_TE_S0) { 2618 if (st_status & V_FR_SYNC_ST) 2619 hc->syncronized |= 2620 (1 << hc->chan[ch].port); 2621 else 2622 hc->syncronized &= 2623 ~(1 << hc->chan[ch].port); 2624 } 2625 dch->state = st_status & 0x0f; 2626 if (dch->dev.D.protocol == ISDN_P_NT_S0) 2627 active = 3; 2628 else 2629 active = 7; 2630 if (dch->state == active) { 2631 HFC_outb_nodebug(hc, R_FIFO, 2632 (ch << 1) | 1); 2633 HFC_wait_nodebug(hc); 2634 HFC_outb_nodebug(hc, 2635 R_INC_RES_FIFO, V_RES_F); 2636 HFC_wait_nodebug(hc); 2637 dch->tx_idx = 0; 2638 } 2639 schedule_event(dch, FLG_PHCHANGE); 2640 if (debug & DEBUG_HFCMULTI_STATE) 2641 printk(KERN_DEBUG 2642 "%s: S/T newstate %x port %d\n", 2643 __func__, dch->state, 2644 hc->chan[ch].port); 2645 } 2646 r_irq_statech >>= 1; 2647 } 2648 } 2649 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) 2650 plxsd_checksync(hc, 0); 2651 } 2652 2653 static void 2654 fifo_irq(struct hfc_multi *hc, int block) 2655 { 2656 int ch, j; 2657 struct dchannel *dch; 2658 struct bchannel *bch; 2659 u_char r_irq_fifo_bl; 2660 2661 r_irq_fifo_bl = HFC_inb_nodebug(hc, R_IRQ_FIFO_BL0 + block); 2662 j = 0; 2663 while (j < 8) { 2664 ch = (block << 2) + (j >> 1); 2665 dch = hc->chan[ch].dch; 2666 bch = hc->chan[ch].bch; 2667 if (((!dch) && (!bch)) || (!hc->created[hc->chan[ch].port])) { 2668 j += 2; 2669 continue; 2670 } 2671 if (dch && (r_irq_fifo_bl & (1 << j)) && 2672 test_bit(FLG_ACTIVE, &dch->Flags)) { 2673 hfcmulti_tx(hc, ch); 2674 /* start fifo */ 2675 HFC_outb_nodebug(hc, R_FIFO, 0); 2676 HFC_wait_nodebug(hc); 2677 } 2678 if (bch && (r_irq_fifo_bl & (1 << j)) && 2679 test_bit(FLG_ACTIVE, &bch->Flags)) { 2680 hfcmulti_tx(hc, ch); 2681 /* start fifo */ 2682 HFC_outb_nodebug(hc, R_FIFO, 0); 2683 HFC_wait_nodebug(hc); 2684 } 2685 j++; 2686 if (dch && (r_irq_fifo_bl & (1 << j)) && 2687 test_bit(FLG_ACTIVE, &dch->Flags)) { 2688 hfcmulti_rx(hc, ch); 2689 } 2690 if (bch && (r_irq_fifo_bl & (1 << j)) && 2691 test_bit(FLG_ACTIVE, &bch->Flags)) { 2692 hfcmulti_rx(hc, ch); 2693 } 2694 j++; 2695 } 2696 } 2697 2698 #ifdef IRQ_DEBUG 2699 int irqsem; 2700 #endif 2701 static irqreturn_t 2702 hfcmulti_interrupt(int intno, void *dev_id) 2703 { 2704 #ifdef IRQCOUNT_DEBUG 2705 static int iq1 = 0, iq2 = 0, iq3 = 0, iq4 = 0, 2706 iq5 = 0, iq6 = 0, iqcnt = 0; 2707 #endif 2708 struct hfc_multi *hc = dev_id; 2709 struct dchannel *dch; 2710 u_char r_irq_statech, status, r_irq_misc, r_irq_oview; 2711 int i; 2712 void __iomem *plx_acc; 2713 u_short wval; 2714 u_char e1_syncsta, temp, temp2; 2715 u_long flags; 2716 2717 if (!hc) { 2718 printk(KERN_ERR "HFC-multi: Spurious interrupt!\n"); 2719 return IRQ_NONE; 2720 } 2721 2722 spin_lock(&hc->lock); 2723 2724 #ifdef IRQ_DEBUG 2725 if (irqsem) 2726 printk(KERN_ERR "irq for card %d during irq from " 2727 "card %d, this is no bug.\n", hc->id + 1, irqsem); 2728 irqsem = hc->id + 1; 2729 #endif 2730 #ifdef CONFIG_MISDN_HFCMULTI_8xx 2731 if (hc->immap->im_cpm.cp_pbdat & hc->pb_irqmsk) 2732 goto irq_notforus; 2733 #endif 2734 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) { 2735 spin_lock_irqsave(&plx_lock, flags); 2736 plx_acc = hc->plx_membase + PLX_INTCSR; 2737 wval = readw(plx_acc); 2738 spin_unlock_irqrestore(&plx_lock, flags); 2739 if (!(wval & PLX_INTCSR_LINTI1_STATUS)) 2740 goto irq_notforus; 2741 } 2742 2743 status = HFC_inb_nodebug(hc, R_STATUS); 2744 r_irq_statech = HFC_inb_nodebug(hc, R_IRQ_STATECH); 2745 #ifdef IRQCOUNT_DEBUG 2746 if (r_irq_statech) 2747 iq1++; 2748 if (status & V_DTMF_STA) 2749 iq2++; 2750 if (status & V_LOST_STA) 2751 iq3++; 2752 if (status & V_EXT_IRQSTA) 2753 iq4++; 2754 if (status & V_MISC_IRQSTA) 2755 iq5++; 2756 if (status & V_FR_IRQSTA) 2757 iq6++; 2758 if (iqcnt++ > 5000) { 2759 printk(KERN_ERR "iq1:%x iq2:%x iq3:%x iq4:%x iq5:%x iq6:%x\n", 2760 iq1, iq2, iq3, iq4, iq5, iq6); 2761 iqcnt = 0; 2762 } 2763 #endif 2764 2765 if (!r_irq_statech && 2766 !(status & (V_DTMF_STA | V_LOST_STA | V_EXT_IRQSTA | 2767 V_MISC_IRQSTA | V_FR_IRQSTA))) { 2768 /* irq is not for us */ 2769 goto irq_notforus; 2770 } 2771 hc->irqcnt++; 2772 if (r_irq_statech) { 2773 if (hc->ctype != HFC_TYPE_E1) 2774 ph_state_irq(hc, r_irq_statech); 2775 } 2776 if (status & V_EXT_IRQSTA) 2777 ; /* external IRQ */ 2778 if (status & V_LOST_STA) { 2779 /* LOST IRQ */ 2780 HFC_outb(hc, R_INC_RES_FIFO, V_RES_LOST); /* clear irq! */ 2781 } 2782 if (status & V_MISC_IRQSTA) { 2783 /* misc IRQ */ 2784 r_irq_misc = HFC_inb_nodebug(hc, R_IRQ_MISC); 2785 r_irq_misc &= hc->hw.r_irqmsk_misc; /* ignore disabled irqs */ 2786 if (r_irq_misc & V_STA_IRQ) { 2787 if (hc->ctype == HFC_TYPE_E1) { 2788 /* state machine */ 2789 dch = hc->chan[hc->dnum[0]].dch; 2790 e1_syncsta = HFC_inb_nodebug(hc, R_SYNC_STA); 2791 if (test_bit(HFC_CHIP_PLXSD, &hc->chip) 2792 && hc->e1_getclock) { 2793 if (e1_syncsta & V_FR_SYNC_E1) 2794 hc->syncronized = 1; 2795 else 2796 hc->syncronized = 0; 2797 } 2798 /* undocumented: status changes during read */ 2799 temp = HFC_inb_nodebug(hc, R_E1_RD_STA); 2800 while (temp != (temp2 = 2801 HFC_inb_nodebug(hc, R_E1_RD_STA))) { 2802 if (debug & DEBUG_HFCMULTI_STATE) 2803 printk(KERN_DEBUG "%s: reread " 2804 "STATE because %d!=%d\n", 2805 __func__, temp, temp2); 2806 temp = temp2; /* repeat */ 2807 } 2808 /* broadcast state change to all fragments */ 2809 if (debug & DEBUG_HFCMULTI_STATE) 2810 printk(KERN_DEBUG 2811 "%s: E1 (id=%d) newstate %x\n", 2812 __func__, hc->id, temp & 0x7); 2813 for (i = 0; i < hc->ports; i++) { 2814 dch = hc->chan[hc->dnum[i]].dch; 2815 dch->state = temp & 0x7; 2816 schedule_event(dch, FLG_PHCHANGE); 2817 } 2818 2819 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) 2820 plxsd_checksync(hc, 0); 2821 } 2822 } 2823 if (r_irq_misc & V_TI_IRQ) { 2824 if (hc->iclock_on) 2825 mISDN_clock_update(hc->iclock, poll, NULL); 2826 handle_timer_irq(hc); 2827 } 2828 2829 if (r_irq_misc & V_DTMF_IRQ) 2830 hfcmulti_dtmf(hc); 2831 2832 if (r_irq_misc & V_IRQ_PROC) { 2833 static int irq_proc_cnt; 2834 if (!irq_proc_cnt++) 2835 printk(KERN_DEBUG "%s: got V_IRQ_PROC -" 2836 " this should not happen\n", __func__); 2837 } 2838 2839 } 2840 if (status & V_FR_IRQSTA) { 2841 /* FIFO IRQ */ 2842 r_irq_oview = HFC_inb_nodebug(hc, R_IRQ_OVIEW); 2843 for (i = 0; i < 8; i++) { 2844 if (r_irq_oview & (1 << i)) 2845 fifo_irq(hc, i); 2846 } 2847 } 2848 2849 #ifdef IRQ_DEBUG 2850 irqsem = 0; 2851 #endif 2852 spin_unlock(&hc->lock); 2853 return IRQ_HANDLED; 2854 2855 irq_notforus: 2856 #ifdef IRQ_DEBUG 2857 irqsem = 0; 2858 #endif 2859 spin_unlock(&hc->lock); 2860 return IRQ_NONE; 2861 } 2862 2863 2864 /* 2865 * timer callback for D-chan busy resolution. Currently no function 2866 */ 2867 2868 static void 2869 hfcmulti_dbusy_timer(struct hfc_multi *hc) 2870 { 2871 } 2872 2873 2874 /* 2875 * activate/deactivate hardware for selected channels and mode 2876 * 2877 * configure B-channel with the given protocol 2878 * ch eqals to the HFC-channel (0-31) 2879 * ch is the number of channel (0-4,4-7,8-11,12-15,16-19,20-23,24-27,28-31 2880 * for S/T, 1-31 for E1) 2881 * the hdlc interrupts will be set/unset 2882 */ 2883 static int 2884 mode_hfcmulti(struct hfc_multi *hc, int ch, int protocol, int slot_tx, 2885 int bank_tx, int slot_rx, int bank_rx) 2886 { 2887 int flow_tx = 0, flow_rx = 0, routing = 0; 2888 int oslot_tx, oslot_rx; 2889 int conf; 2890 2891 if (ch < 0 || ch > 31) 2892 return -EINVAL; 2893 oslot_tx = hc->chan[ch].slot_tx; 2894 oslot_rx = hc->chan[ch].slot_rx; 2895 conf = hc->chan[ch].conf; 2896 2897 if (debug & DEBUG_HFCMULTI_MODE) 2898 printk(KERN_DEBUG 2899 "%s: card %d channel %d protocol %x slot old=%d new=%d " 2900 "bank new=%d (TX) slot old=%d new=%d bank new=%d (RX)\n", 2901 __func__, hc->id, ch, protocol, oslot_tx, slot_tx, 2902 bank_tx, oslot_rx, slot_rx, bank_rx); 2903 2904 if (oslot_tx >= 0 && slot_tx != oslot_tx) { 2905 /* remove from slot */ 2906 if (debug & DEBUG_HFCMULTI_MODE) 2907 printk(KERN_DEBUG "%s: remove from slot %d (TX)\n", 2908 __func__, oslot_tx); 2909 if (hc->slot_owner[oslot_tx << 1] == ch) { 2910 HFC_outb(hc, R_SLOT, oslot_tx << 1); 2911 HFC_outb(hc, A_SL_CFG, 0); 2912 if (hc->ctype != HFC_TYPE_XHFC) 2913 HFC_outb(hc, A_CONF, 0); 2914 hc->slot_owner[oslot_tx << 1] = -1; 2915 } else { 2916 if (debug & DEBUG_HFCMULTI_MODE) 2917 printk(KERN_DEBUG 2918 "%s: we are not owner of this tx slot " 2919 "anymore, channel %d is.\n", 2920 __func__, hc->slot_owner[oslot_tx << 1]); 2921 } 2922 } 2923 2924 if (oslot_rx >= 0 && slot_rx != oslot_rx) { 2925 /* remove from slot */ 2926 if (debug & DEBUG_HFCMULTI_MODE) 2927 printk(KERN_DEBUG 2928 "%s: remove from slot %d (RX)\n", 2929 __func__, oslot_rx); 2930 if (hc->slot_owner[(oslot_rx << 1) | 1] == ch) { 2931 HFC_outb(hc, R_SLOT, (oslot_rx << 1) | V_SL_DIR); 2932 HFC_outb(hc, A_SL_CFG, 0); 2933 hc->slot_owner[(oslot_rx << 1) | 1] = -1; 2934 } else { 2935 if (debug & DEBUG_HFCMULTI_MODE) 2936 printk(KERN_DEBUG 2937 "%s: we are not owner of this rx slot " 2938 "anymore, channel %d is.\n", 2939 __func__, 2940 hc->slot_owner[(oslot_rx << 1) | 1]); 2941 } 2942 } 2943 2944 if (slot_tx < 0) { 2945 flow_tx = 0x80; /* FIFO->ST */ 2946 /* disable pcm slot */ 2947 hc->chan[ch].slot_tx = -1; 2948 hc->chan[ch].bank_tx = 0; 2949 } else { 2950 /* set pcm slot */ 2951 if (hc->chan[ch].txpending) 2952 flow_tx = 0x80; /* FIFO->ST */ 2953 else 2954 flow_tx = 0xc0; /* PCM->ST */ 2955 /* put on slot */ 2956 routing = bank_tx ? 0xc0 : 0x80; 2957 if (conf >= 0 || bank_tx > 1) 2958 routing = 0x40; /* loop */ 2959 if (debug & DEBUG_HFCMULTI_MODE) 2960 printk(KERN_DEBUG "%s: put channel %d to slot %d bank" 2961 " %d flow %02x routing %02x conf %d (TX)\n", 2962 __func__, ch, slot_tx, bank_tx, 2963 flow_tx, routing, conf); 2964 HFC_outb(hc, R_SLOT, slot_tx << 1); 2965 HFC_outb(hc, A_SL_CFG, (ch << 1) | routing); 2966 if (hc->ctype != HFC_TYPE_XHFC) 2967 HFC_outb(hc, A_CONF, 2968 (conf < 0) ? 0 : (conf | V_CONF_SL)); 2969 hc->slot_owner[slot_tx << 1] = ch; 2970 hc->chan[ch].slot_tx = slot_tx; 2971 hc->chan[ch].bank_tx = bank_tx; 2972 } 2973 if (slot_rx < 0) { 2974 /* disable pcm slot */ 2975 flow_rx = 0x80; /* ST->FIFO */ 2976 hc->chan[ch].slot_rx = -1; 2977 hc->chan[ch].bank_rx = 0; 2978 } else { 2979 /* set pcm slot */ 2980 if (hc->chan[ch].txpending) 2981 flow_rx = 0x80; /* ST->FIFO */ 2982 else 2983 flow_rx = 0xc0; /* ST->(FIFO,PCM) */ 2984 /* put on slot */ 2985 routing = bank_rx ? 0x80 : 0xc0; /* reversed */ 2986 if (conf >= 0 || bank_rx > 1) 2987 routing = 0x40; /* loop */ 2988 if (debug & DEBUG_HFCMULTI_MODE) 2989 printk(KERN_DEBUG "%s: put channel %d to slot %d bank" 2990 " %d flow %02x routing %02x conf %d (RX)\n", 2991 __func__, ch, slot_rx, bank_rx, 2992 flow_rx, routing, conf); 2993 HFC_outb(hc, R_SLOT, (slot_rx << 1) | V_SL_DIR); 2994 HFC_outb(hc, A_SL_CFG, (ch << 1) | V_CH_DIR | routing); 2995 hc->slot_owner[(slot_rx << 1) | 1] = ch; 2996 hc->chan[ch].slot_rx = slot_rx; 2997 hc->chan[ch].bank_rx = bank_rx; 2998 } 2999 3000 switch (protocol) { 3001 case (ISDN_P_NONE): 3002 /* disable TX fifo */ 3003 HFC_outb(hc, R_FIFO, ch << 1); 3004 HFC_wait(hc); 3005 HFC_outb(hc, A_CON_HDLC, flow_tx | 0x00 | V_IFF); 3006 HFC_outb(hc, A_SUBCH_CFG, 0); 3007 HFC_outb(hc, A_IRQ_MSK, 0); 3008 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F); 3009 HFC_wait(hc); 3010 /* disable RX fifo */ 3011 HFC_outb(hc, R_FIFO, (ch << 1) | 1); 3012 HFC_wait(hc); 3013 HFC_outb(hc, A_CON_HDLC, flow_rx | 0x00); 3014 HFC_outb(hc, A_SUBCH_CFG, 0); 3015 HFC_outb(hc, A_IRQ_MSK, 0); 3016 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F); 3017 HFC_wait(hc); 3018 if (hc->chan[ch].bch && hc->ctype != HFC_TYPE_E1) { 3019 hc->hw.a_st_ctrl0[hc->chan[ch].port] &= 3020 ((ch & 0x3) == 0) ? ~V_B1_EN : ~V_B2_EN; 3021 HFC_outb(hc, R_ST_SEL, hc->chan[ch].port); 3022 /* undocumented: delay after R_ST_SEL */ 3023 udelay(1); 3024 HFC_outb(hc, A_ST_CTRL0, 3025 hc->hw.a_st_ctrl0[hc->chan[ch].port]); 3026 } 3027 if (hc->chan[ch].bch) { 3028 test_and_clear_bit(FLG_HDLC, &hc->chan[ch].bch->Flags); 3029 test_and_clear_bit(FLG_TRANSPARENT, 3030 &hc->chan[ch].bch->Flags); 3031 } 3032 break; 3033 case (ISDN_P_B_RAW): /* B-channel */ 3034 3035 if (test_bit(HFC_CHIP_B410P, &hc->chip) && 3036 (hc->chan[ch].slot_rx < 0) && 3037 (hc->chan[ch].slot_tx < 0)) { 3038 3039 printk(KERN_DEBUG 3040 "Setting B-channel %d to echo cancelable " 3041 "state on PCM slot %d\n", ch, 3042 ((ch / 4) * 8) + ((ch % 4) * 4) + 1); 3043 printk(KERN_DEBUG 3044 "Enabling pass through for channel\n"); 3045 vpm_out(hc, ch, ((ch / 4) * 8) + 3046 ((ch % 4) * 4) + 1, 0x01); 3047 /* rx path */ 3048 /* S/T -> PCM */ 3049 HFC_outb(hc, R_FIFO, (ch << 1)); 3050 HFC_wait(hc); 3051 HFC_outb(hc, A_CON_HDLC, 0xc0 | V_HDLC_TRP | V_IFF); 3052 HFC_outb(hc, R_SLOT, (((ch / 4) * 8) + 3053 ((ch % 4) * 4) + 1) << 1); 3054 HFC_outb(hc, A_SL_CFG, 0x80 | (ch << 1)); 3055 3056 /* PCM -> FIFO */ 3057 HFC_outb(hc, R_FIFO, 0x20 | (ch << 1) | 1); 3058 HFC_wait(hc); 3059 HFC_outb(hc, A_CON_HDLC, 0x20 | V_HDLC_TRP | V_IFF); 3060 HFC_outb(hc, A_SUBCH_CFG, 0); 3061 HFC_outb(hc, A_IRQ_MSK, 0); 3062 if (hc->chan[ch].protocol != protocol) { 3063 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F); 3064 HFC_wait(hc); 3065 } 3066 HFC_outb(hc, R_SLOT, ((((ch / 4) * 8) + 3067 ((ch % 4) * 4) + 1) << 1) | 1); 3068 HFC_outb(hc, A_SL_CFG, 0x80 | 0x20 | (ch << 1) | 1); 3069 3070 /* tx path */ 3071 /* PCM -> S/T */ 3072 HFC_outb(hc, R_FIFO, (ch << 1) | 1); 3073 HFC_wait(hc); 3074 HFC_outb(hc, A_CON_HDLC, 0xc0 | V_HDLC_TRP | V_IFF); 3075 HFC_outb(hc, R_SLOT, ((((ch / 4) * 8) + 3076 ((ch % 4) * 4)) << 1) | 1); 3077 HFC_outb(hc, A_SL_CFG, 0x80 | 0x40 | (ch << 1) | 1); 3078 3079 /* FIFO -> PCM */ 3080 HFC_outb(hc, R_FIFO, 0x20 | (ch << 1)); 3081 HFC_wait(hc); 3082 HFC_outb(hc, A_CON_HDLC, 0x20 | V_HDLC_TRP | V_IFF); 3083 HFC_outb(hc, A_SUBCH_CFG, 0); 3084 HFC_outb(hc, A_IRQ_MSK, 0); 3085 if (hc->chan[ch].protocol != protocol) { 3086 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F); 3087 HFC_wait(hc); 3088 } 3089 /* tx silence */ 3090 HFC_outb_nodebug(hc, A_FIFO_DATA0_NOINC, hc->silence); 3091 HFC_outb(hc, R_SLOT, (((ch / 4) * 8) + 3092 ((ch % 4) * 4)) << 1); 3093 HFC_outb(hc, A_SL_CFG, 0x80 | 0x20 | (ch << 1)); 3094 } else { 3095 /* enable TX fifo */ 3096 HFC_outb(hc, R_FIFO, ch << 1); 3097 HFC_wait(hc); 3098 if (hc->ctype == HFC_TYPE_XHFC) 3099 HFC_outb(hc, A_CON_HDLC, flow_tx | 0x07 << 2 | 3100 V_HDLC_TRP | V_IFF); 3101 /* Enable FIFO, no interrupt */ 3102 else 3103 HFC_outb(hc, A_CON_HDLC, flow_tx | 0x00 | 3104 V_HDLC_TRP | V_IFF); 3105 HFC_outb(hc, A_SUBCH_CFG, 0); 3106 HFC_outb(hc, A_IRQ_MSK, 0); 3107 if (hc->chan[ch].protocol != protocol) { 3108 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F); 3109 HFC_wait(hc); 3110 } 3111 /* tx silence */ 3112 HFC_outb_nodebug(hc, A_FIFO_DATA0_NOINC, hc->silence); 3113 /* enable RX fifo */ 3114 HFC_outb(hc, R_FIFO, (ch << 1) | 1); 3115 HFC_wait(hc); 3116 if (hc->ctype == HFC_TYPE_XHFC) 3117 HFC_outb(hc, A_CON_HDLC, flow_rx | 0x07 << 2 | 3118 V_HDLC_TRP); 3119 /* Enable FIFO, no interrupt*/ 3120 else 3121 HFC_outb(hc, A_CON_HDLC, flow_rx | 0x00 | 3122 V_HDLC_TRP); 3123 HFC_outb(hc, A_SUBCH_CFG, 0); 3124 HFC_outb(hc, A_IRQ_MSK, 0); 3125 if (hc->chan[ch].protocol != protocol) { 3126 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F); 3127 HFC_wait(hc); 3128 } 3129 } 3130 if (hc->ctype != HFC_TYPE_E1) { 3131 hc->hw.a_st_ctrl0[hc->chan[ch].port] |= 3132 ((ch & 0x3) == 0) ? V_B1_EN : V_B2_EN; 3133 HFC_outb(hc, R_ST_SEL, hc->chan[ch].port); 3134 /* undocumented: delay after R_ST_SEL */ 3135 udelay(1); 3136 HFC_outb(hc, A_ST_CTRL0, 3137 hc->hw.a_st_ctrl0[hc->chan[ch].port]); 3138 } 3139 if (hc->chan[ch].bch) 3140 test_and_set_bit(FLG_TRANSPARENT, 3141 &hc->chan[ch].bch->Flags); 3142 break; 3143 case (ISDN_P_B_HDLC): /* B-channel */ 3144 case (ISDN_P_TE_S0): /* D-channel */ 3145 case (ISDN_P_NT_S0): 3146 case (ISDN_P_TE_E1): 3147 case (ISDN_P_NT_E1): 3148 /* enable TX fifo */ 3149 HFC_outb(hc, R_FIFO, ch << 1); 3150 HFC_wait(hc); 3151 if (hc->ctype == HFC_TYPE_E1 || hc->chan[ch].bch) { 3152 /* E1 or B-channel */ 3153 HFC_outb(hc, A_CON_HDLC, flow_tx | 0x04); 3154 HFC_outb(hc, A_SUBCH_CFG, 0); 3155 } else { 3156 /* D-Channel without HDLC fill flags */ 3157 HFC_outb(hc, A_CON_HDLC, flow_tx | 0x04 | V_IFF); 3158 HFC_outb(hc, A_SUBCH_CFG, 2); 3159 } 3160 HFC_outb(hc, A_IRQ_MSK, V_IRQ); 3161 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F); 3162 HFC_wait(hc); 3163 /* enable RX fifo */ 3164 HFC_outb(hc, R_FIFO, (ch << 1) | 1); 3165 HFC_wait(hc); 3166 HFC_outb(hc, A_CON_HDLC, flow_rx | 0x04); 3167 if (hc->ctype == HFC_TYPE_E1 || hc->chan[ch].bch) 3168 HFC_outb(hc, A_SUBCH_CFG, 0); /* full 8 bits */ 3169 else 3170 HFC_outb(hc, A_SUBCH_CFG, 2); /* 2 bits dchannel */ 3171 HFC_outb(hc, A_IRQ_MSK, V_IRQ); 3172 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F); 3173 HFC_wait(hc); 3174 if (hc->chan[ch].bch) { 3175 test_and_set_bit(FLG_HDLC, &hc->chan[ch].bch->Flags); 3176 if (hc->ctype != HFC_TYPE_E1) { 3177 hc->hw.a_st_ctrl0[hc->chan[ch].port] |= 3178 ((ch & 0x3) == 0) ? V_B1_EN : V_B2_EN; 3179 HFC_outb(hc, R_ST_SEL, hc->chan[ch].port); 3180 /* undocumented: delay after R_ST_SEL */ 3181 udelay(1); 3182 HFC_outb(hc, A_ST_CTRL0, 3183 hc->hw.a_st_ctrl0[hc->chan[ch].port]); 3184 } 3185 } 3186 break; 3187 default: 3188 printk(KERN_DEBUG "%s: protocol not known %x\n", 3189 __func__, protocol); 3190 hc->chan[ch].protocol = ISDN_P_NONE; 3191 return -ENOPROTOOPT; 3192 } 3193 hc->chan[ch].protocol = protocol; 3194 return 0; 3195 } 3196 3197 3198 /* 3199 * connect/disconnect PCM 3200 */ 3201 3202 static void 3203 hfcmulti_pcm(struct hfc_multi *hc, int ch, int slot_tx, int bank_tx, 3204 int slot_rx, int bank_rx) 3205 { 3206 if (slot_tx < 0 || slot_rx < 0 || bank_tx < 0 || bank_rx < 0) { 3207 /* disable PCM */ 3208 mode_hfcmulti(hc, ch, hc->chan[ch].protocol, -1, 0, -1, 0); 3209 return; 3210 } 3211 3212 /* enable pcm */ 3213 mode_hfcmulti(hc, ch, hc->chan[ch].protocol, slot_tx, bank_tx, 3214 slot_rx, bank_rx); 3215 } 3216 3217 /* 3218 * set/disable conference 3219 */ 3220 3221 static void 3222 hfcmulti_conf(struct hfc_multi *hc, int ch, int num) 3223 { 3224 if (num >= 0 && num <= 7) 3225 hc->chan[ch].conf = num; 3226 else 3227 hc->chan[ch].conf = -1; 3228 mode_hfcmulti(hc, ch, hc->chan[ch].protocol, hc->chan[ch].slot_tx, 3229 hc->chan[ch].bank_tx, hc->chan[ch].slot_rx, 3230 hc->chan[ch].bank_rx); 3231 } 3232 3233 3234 /* 3235 * set/disable sample loop 3236 */ 3237 3238 /* NOTE: this function is experimental and therefore disabled */ 3239 3240 /* 3241 * Layer 1 callback function 3242 */ 3243 static int 3244 hfcm_l1callback(struct dchannel *dch, u_int cmd) 3245 { 3246 struct hfc_multi *hc = dch->hw; 3247 u_long flags; 3248 3249 switch (cmd) { 3250 case INFO3_P8: 3251 case INFO3_P10: 3252 break; 3253 case HW_RESET_REQ: 3254 /* start activation */ 3255 spin_lock_irqsave(&hc->lock, flags); 3256 if (hc->ctype == HFC_TYPE_E1) { 3257 if (debug & DEBUG_HFCMULTI_MSG) 3258 printk(KERN_DEBUG 3259 "%s: HW_RESET_REQ no BRI\n", 3260 __func__); 3261 } else { 3262 HFC_outb(hc, R_ST_SEL, hc->chan[dch->slot].port); 3263 /* undocumented: delay after R_ST_SEL */ 3264 udelay(1); 3265 HFC_outb(hc, A_ST_WR_STATE, V_ST_LD_STA | 3); /* F3 */ 3266 udelay(6); /* wait at least 5,21us */ 3267 HFC_outb(hc, A_ST_WR_STATE, 3); 3268 HFC_outb(hc, A_ST_WR_STATE, 3 | (V_ST_ACT * 3)); 3269 /* activate */ 3270 } 3271 spin_unlock_irqrestore(&hc->lock, flags); 3272 l1_event(dch->l1, HW_POWERUP_IND); 3273 break; 3274 case HW_DEACT_REQ: 3275 /* start deactivation */ 3276 spin_lock_irqsave(&hc->lock, flags); 3277 if (hc->ctype == HFC_TYPE_E1) { 3278 if (debug & DEBUG_HFCMULTI_MSG) 3279 printk(KERN_DEBUG 3280 "%s: HW_DEACT_REQ no BRI\n", 3281 __func__); 3282 } else { 3283 HFC_outb(hc, R_ST_SEL, hc->chan[dch->slot].port); 3284 /* undocumented: delay after R_ST_SEL */ 3285 udelay(1); 3286 HFC_outb(hc, A_ST_WR_STATE, V_ST_ACT * 2); 3287 /* deactivate */ 3288 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) { 3289 hc->syncronized &= 3290 ~(1 << hc->chan[dch->slot].port); 3291 plxsd_checksync(hc, 0); 3292 } 3293 } 3294 skb_queue_purge(&dch->squeue); 3295 if (dch->tx_skb) { 3296 dev_kfree_skb(dch->tx_skb); 3297 dch->tx_skb = NULL; 3298 } 3299 dch->tx_idx = 0; 3300 if (dch->rx_skb) { 3301 dev_kfree_skb(dch->rx_skb); 3302 dch->rx_skb = NULL; 3303 } 3304 test_and_clear_bit(FLG_TX_BUSY, &dch->Flags); 3305 if (test_and_clear_bit(FLG_BUSY_TIMER, &dch->Flags)) 3306 del_timer(&dch->timer); 3307 spin_unlock_irqrestore(&hc->lock, flags); 3308 break; 3309 case HW_POWERUP_REQ: 3310 spin_lock_irqsave(&hc->lock, flags); 3311 if (hc->ctype == HFC_TYPE_E1) { 3312 if (debug & DEBUG_HFCMULTI_MSG) 3313 printk(KERN_DEBUG 3314 "%s: HW_POWERUP_REQ no BRI\n", 3315 __func__); 3316 } else { 3317 HFC_outb(hc, R_ST_SEL, hc->chan[dch->slot].port); 3318 /* undocumented: delay after R_ST_SEL */ 3319 udelay(1); 3320 HFC_outb(hc, A_ST_WR_STATE, 3 | 0x10); /* activate */ 3321 udelay(6); /* wait at least 5,21us */ 3322 HFC_outb(hc, A_ST_WR_STATE, 3); /* activate */ 3323 } 3324 spin_unlock_irqrestore(&hc->lock, flags); 3325 break; 3326 case PH_ACTIVATE_IND: 3327 test_and_set_bit(FLG_ACTIVE, &dch->Flags); 3328 _queue_data(&dch->dev.D, cmd, MISDN_ID_ANY, 0, NULL, 3329 GFP_ATOMIC); 3330 break; 3331 case PH_DEACTIVATE_IND: 3332 test_and_clear_bit(FLG_ACTIVE, &dch->Flags); 3333 _queue_data(&dch->dev.D, cmd, MISDN_ID_ANY, 0, NULL, 3334 GFP_ATOMIC); 3335 break; 3336 default: 3337 if (dch->debug & DEBUG_HW) 3338 printk(KERN_DEBUG "%s: unknown command %x\n", 3339 __func__, cmd); 3340 return -1; 3341 } 3342 return 0; 3343 } 3344 3345 /* 3346 * Layer2 -> Layer 1 Transfer 3347 */ 3348 3349 static int 3350 handle_dmsg(struct mISDNchannel *ch, struct sk_buff *skb) 3351 { 3352 struct mISDNdevice *dev = container_of(ch, struct mISDNdevice, D); 3353 struct dchannel *dch = container_of(dev, struct dchannel, dev); 3354 struct hfc_multi *hc = dch->hw; 3355 struct mISDNhead *hh = mISDN_HEAD_P(skb); 3356 int ret = -EINVAL; 3357 unsigned int id; 3358 u_long flags; 3359 3360 switch (hh->prim) { 3361 case PH_DATA_REQ: 3362 if (skb->len < 1) 3363 break; 3364 spin_lock_irqsave(&hc->lock, flags); 3365 ret = dchannel_senddata(dch, skb); 3366 if (ret > 0) { /* direct TX */ 3367 id = hh->id; /* skb can be freed */ 3368 hfcmulti_tx(hc, dch->slot); 3369 ret = 0; 3370 /* start fifo */ 3371 HFC_outb(hc, R_FIFO, 0); 3372 HFC_wait(hc); 3373 spin_unlock_irqrestore(&hc->lock, flags); 3374 queue_ch_frame(ch, PH_DATA_CNF, id, NULL); 3375 } else 3376 spin_unlock_irqrestore(&hc->lock, flags); 3377 return ret; 3378 case PH_ACTIVATE_REQ: 3379 if (dch->dev.D.protocol != ISDN_P_TE_S0) { 3380 spin_lock_irqsave(&hc->lock, flags); 3381 ret = 0; 3382 if (debug & DEBUG_HFCMULTI_MSG) 3383 printk(KERN_DEBUG 3384 "%s: PH_ACTIVATE port %d (0..%d)\n", 3385 __func__, hc->chan[dch->slot].port, 3386 hc->ports - 1); 3387 /* start activation */ 3388 if (hc->ctype == HFC_TYPE_E1) { 3389 ph_state_change(dch); 3390 if (debug & DEBUG_HFCMULTI_STATE) 3391 printk(KERN_DEBUG 3392 "%s: E1 report state %x \n", 3393 __func__, dch->state); 3394 } else { 3395 HFC_outb(hc, R_ST_SEL, 3396 hc->chan[dch->slot].port); 3397 /* undocumented: delay after R_ST_SEL */ 3398 udelay(1); 3399 HFC_outb(hc, A_ST_WR_STATE, V_ST_LD_STA | 1); 3400 /* G1 */ 3401 udelay(6); /* wait at least 5,21us */ 3402 HFC_outb(hc, A_ST_WR_STATE, 1); 3403 HFC_outb(hc, A_ST_WR_STATE, 1 | 3404 (V_ST_ACT * 3)); /* activate */ 3405 dch->state = 1; 3406 } 3407 spin_unlock_irqrestore(&hc->lock, flags); 3408 } else 3409 ret = l1_event(dch->l1, hh->prim); 3410 break; 3411 case PH_DEACTIVATE_REQ: 3412 test_and_clear_bit(FLG_L2_ACTIVATED, &dch->Flags); 3413 if (dch->dev.D.protocol != ISDN_P_TE_S0) { 3414 spin_lock_irqsave(&hc->lock, flags); 3415 if (debug & DEBUG_HFCMULTI_MSG) 3416 printk(KERN_DEBUG 3417 "%s: PH_DEACTIVATE port %d (0..%d)\n", 3418 __func__, hc->chan[dch->slot].port, 3419 hc->ports - 1); 3420 /* start deactivation */ 3421 if (hc->ctype == HFC_TYPE_E1) { 3422 if (debug & DEBUG_HFCMULTI_MSG) 3423 printk(KERN_DEBUG 3424 "%s: PH_DEACTIVATE no BRI\n", 3425 __func__); 3426 } else { 3427 HFC_outb(hc, R_ST_SEL, 3428 hc->chan[dch->slot].port); 3429 /* undocumented: delay after R_ST_SEL */ 3430 udelay(1); 3431 HFC_outb(hc, A_ST_WR_STATE, V_ST_ACT * 2); 3432 /* deactivate */ 3433 dch->state = 1; 3434 } 3435 skb_queue_purge(&dch->squeue); 3436 if (dch->tx_skb) { 3437 dev_kfree_skb(dch->tx_skb); 3438 dch->tx_skb = NULL; 3439 } 3440 dch->tx_idx = 0; 3441 if (dch->rx_skb) { 3442 dev_kfree_skb(dch->rx_skb); 3443 dch->rx_skb = NULL; 3444 } 3445 test_and_clear_bit(FLG_TX_BUSY, &dch->Flags); 3446 if (test_and_clear_bit(FLG_BUSY_TIMER, &dch->Flags)) 3447 del_timer(&dch->timer); 3448 #ifdef FIXME 3449 if (test_and_clear_bit(FLG_L1_BUSY, &dch->Flags)) 3450 dchannel_sched_event(&hc->dch, D_CLEARBUSY); 3451 #endif 3452 ret = 0; 3453 spin_unlock_irqrestore(&hc->lock, flags); 3454 } else 3455 ret = l1_event(dch->l1, hh->prim); 3456 break; 3457 } 3458 if (!ret) 3459 dev_kfree_skb(skb); 3460 return ret; 3461 } 3462 3463 static void 3464 deactivate_bchannel(struct bchannel *bch) 3465 { 3466 struct hfc_multi *hc = bch->hw; 3467 u_long flags; 3468 3469 spin_lock_irqsave(&hc->lock, flags); 3470 mISDN_clear_bchannel(bch); 3471 hc->chan[bch->slot].coeff_count = 0; 3472 hc->chan[bch->slot].rx_off = 0; 3473 hc->chan[bch->slot].conf = -1; 3474 mode_hfcmulti(hc, bch->slot, ISDN_P_NONE, -1, 0, -1, 0); 3475 spin_unlock_irqrestore(&hc->lock, flags); 3476 } 3477 3478 static int 3479 handle_bmsg(struct mISDNchannel *ch, struct sk_buff *skb) 3480 { 3481 struct bchannel *bch = container_of(ch, struct bchannel, ch); 3482 struct hfc_multi *hc = bch->hw; 3483 int ret = -EINVAL; 3484 struct mISDNhead *hh = mISDN_HEAD_P(skb); 3485 unsigned int id; 3486 u_long flags; 3487 3488 switch (hh->prim) { 3489 case PH_DATA_REQ: 3490 if (!skb->len) 3491 break; 3492 spin_lock_irqsave(&hc->lock, flags); 3493 ret = bchannel_senddata(bch, skb); 3494 if (ret > 0) { /* direct TX */ 3495 id = hh->id; /* skb can be freed */ 3496 hfcmulti_tx(hc, bch->slot); 3497 ret = 0; 3498 /* start fifo */ 3499 HFC_outb_nodebug(hc, R_FIFO, 0); 3500 HFC_wait_nodebug(hc); 3501 if (!test_bit(FLG_TRANSPARENT, &bch->Flags)) { 3502 spin_unlock_irqrestore(&hc->lock, flags); 3503 queue_ch_frame(ch, PH_DATA_CNF, id, NULL); 3504 } else 3505 spin_unlock_irqrestore(&hc->lock, flags); 3506 } else 3507 spin_unlock_irqrestore(&hc->lock, flags); 3508 return ret; 3509 case PH_ACTIVATE_REQ: 3510 if (debug & DEBUG_HFCMULTI_MSG) 3511 printk(KERN_DEBUG "%s: PH_ACTIVATE ch %d (0..32)\n", 3512 __func__, bch->slot); 3513 spin_lock_irqsave(&hc->lock, flags); 3514 /* activate B-channel if not already activated */ 3515 if (!test_and_set_bit(FLG_ACTIVE, &bch->Flags)) { 3516 hc->chan[bch->slot].txpending = 0; 3517 ret = mode_hfcmulti(hc, bch->slot, 3518 ch->protocol, 3519 hc->chan[bch->slot].slot_tx, 3520 hc->chan[bch->slot].bank_tx, 3521 hc->chan[bch->slot].slot_rx, 3522 hc->chan[bch->slot].bank_rx); 3523 if (!ret) { 3524 if (ch->protocol == ISDN_P_B_RAW && !hc->dtmf 3525 && test_bit(HFC_CHIP_DTMF, &hc->chip)) { 3526 /* start decoder */ 3527 hc->dtmf = 1; 3528 if (debug & DEBUG_HFCMULTI_DTMF) 3529 printk(KERN_DEBUG 3530 "%s: start dtmf decoder\n", 3531 __func__); 3532 HFC_outb(hc, R_DTMF, hc->hw.r_dtmf | 3533 V_RST_DTMF); 3534 } 3535 } 3536 } else 3537 ret = 0; 3538 spin_unlock_irqrestore(&hc->lock, flags); 3539 if (!ret) 3540 _queue_data(ch, PH_ACTIVATE_IND, MISDN_ID_ANY, 0, NULL, 3541 GFP_KERNEL); 3542 break; 3543 case PH_CONTROL_REQ: 3544 spin_lock_irqsave(&hc->lock, flags); 3545 switch (hh->id) { 3546 case HFC_SPL_LOOP_ON: /* set sample loop */ 3547 if (debug & DEBUG_HFCMULTI_MSG) 3548 printk(KERN_DEBUG 3549 "%s: HFC_SPL_LOOP_ON (len = %d)\n", 3550 __func__, skb->len); 3551 ret = 0; 3552 break; 3553 case HFC_SPL_LOOP_OFF: /* set silence */ 3554 if (debug & DEBUG_HFCMULTI_MSG) 3555 printk(KERN_DEBUG "%s: HFC_SPL_LOOP_OFF\n", 3556 __func__); 3557 ret = 0; 3558 break; 3559 default: 3560 printk(KERN_ERR 3561 "%s: unknown PH_CONTROL_REQ info %x\n", 3562 __func__, hh->id); 3563 ret = -EINVAL; 3564 } 3565 spin_unlock_irqrestore(&hc->lock, flags); 3566 break; 3567 case PH_DEACTIVATE_REQ: 3568 deactivate_bchannel(bch); /* locked there */ 3569 _queue_data(ch, PH_DEACTIVATE_IND, MISDN_ID_ANY, 0, NULL, 3570 GFP_KERNEL); 3571 ret = 0; 3572 break; 3573 } 3574 if (!ret) 3575 dev_kfree_skb(skb); 3576 return ret; 3577 } 3578 3579 /* 3580 * bchannel control function 3581 */ 3582 static int 3583 channel_bctrl(struct bchannel *bch, struct mISDN_ctrl_req *cq) 3584 { 3585 int ret = 0; 3586 struct dsp_features *features = 3587 (struct dsp_features *)(*((u_long *)&cq->p1)); 3588 struct hfc_multi *hc = bch->hw; 3589 int slot_tx; 3590 int bank_tx; 3591 int slot_rx; 3592 int bank_rx; 3593 int num; 3594 3595 switch (cq->op) { 3596 case MISDN_CTRL_GETOP: 3597 cq->op = MISDN_CTRL_HFC_OP | MISDN_CTRL_HW_FEATURES_OP 3598 | MISDN_CTRL_RX_OFF | MISDN_CTRL_FILL_EMPTY; 3599 break; 3600 case MISDN_CTRL_RX_OFF: /* turn off / on rx stream */ 3601 hc->chan[bch->slot].rx_off = !!cq->p1; 3602 if (!hc->chan[bch->slot].rx_off) { 3603 /* reset fifo on rx on */ 3604 HFC_outb_nodebug(hc, R_FIFO, (bch->slot << 1) | 1); 3605 HFC_wait_nodebug(hc); 3606 HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_RES_F); 3607 HFC_wait_nodebug(hc); 3608 } 3609 if (debug & DEBUG_HFCMULTI_MSG) 3610 printk(KERN_DEBUG "%s: RX_OFF request (nr=%d off=%d)\n", 3611 __func__, bch->nr, hc->chan[bch->slot].rx_off); 3612 break; 3613 case MISDN_CTRL_FILL_EMPTY: /* fill fifo, if empty */ 3614 test_and_set_bit(FLG_FILLEMPTY, &bch->Flags); 3615 if (debug & DEBUG_HFCMULTI_MSG) 3616 printk(KERN_DEBUG "%s: FILL_EMPTY request (nr=%d " 3617 "off=%d)\n", __func__, bch->nr, !!cq->p1); 3618 break; 3619 case MISDN_CTRL_HW_FEATURES: /* fill features structure */ 3620 if (debug & DEBUG_HFCMULTI_MSG) 3621 printk(KERN_DEBUG "%s: HW_FEATURE request\n", 3622 __func__); 3623 /* create confirm */ 3624 features->hfc_id = hc->id; 3625 if (test_bit(HFC_CHIP_DTMF, &hc->chip)) 3626 features->hfc_dtmf = 1; 3627 if (test_bit(HFC_CHIP_CONF, &hc->chip)) 3628 features->hfc_conf = 1; 3629 features->hfc_loops = 0; 3630 if (test_bit(HFC_CHIP_B410P, &hc->chip)) { 3631 features->hfc_echocanhw = 1; 3632 } else { 3633 features->pcm_id = hc->pcm; 3634 features->pcm_slots = hc->slots; 3635 features->pcm_banks = 2; 3636 } 3637 break; 3638 case MISDN_CTRL_HFC_PCM_CONN: /* connect to pcm timeslot (0..N) */ 3639 slot_tx = cq->p1 & 0xff; 3640 bank_tx = cq->p1 >> 8; 3641 slot_rx = cq->p2 & 0xff; 3642 bank_rx = cq->p2 >> 8; 3643 if (debug & DEBUG_HFCMULTI_MSG) 3644 printk(KERN_DEBUG 3645 "%s: HFC_PCM_CONN slot %d bank %d (TX) " 3646 "slot %d bank %d (RX)\n", 3647 __func__, slot_tx, bank_tx, 3648 slot_rx, bank_rx); 3649 if (slot_tx < hc->slots && bank_tx <= 2 && 3650 slot_rx < hc->slots && bank_rx <= 2) 3651 hfcmulti_pcm(hc, bch->slot, 3652 slot_tx, bank_tx, slot_rx, bank_rx); 3653 else { 3654 printk(KERN_WARNING 3655 "%s: HFC_PCM_CONN slot %d bank %d (TX) " 3656 "slot %d bank %d (RX) out of range\n", 3657 __func__, slot_tx, bank_tx, 3658 slot_rx, bank_rx); 3659 ret = -EINVAL; 3660 } 3661 break; 3662 case MISDN_CTRL_HFC_PCM_DISC: /* release interface from pcm timeslot */ 3663 if (debug & DEBUG_HFCMULTI_MSG) 3664 printk(KERN_DEBUG "%s: HFC_PCM_DISC\n", 3665 __func__); 3666 hfcmulti_pcm(hc, bch->slot, -1, 0, -1, 0); 3667 break; 3668 case MISDN_CTRL_HFC_CONF_JOIN: /* join conference (0..7) */ 3669 num = cq->p1 & 0xff; 3670 if (debug & DEBUG_HFCMULTI_MSG) 3671 printk(KERN_DEBUG "%s: HFC_CONF_JOIN conf %d\n", 3672 __func__, num); 3673 if (num <= 7) 3674 hfcmulti_conf(hc, bch->slot, num); 3675 else { 3676 printk(KERN_WARNING 3677 "%s: HW_CONF_JOIN conf %d out of range\n", 3678 __func__, num); 3679 ret = -EINVAL; 3680 } 3681 break; 3682 case MISDN_CTRL_HFC_CONF_SPLIT: /* split conference */ 3683 if (debug & DEBUG_HFCMULTI_MSG) 3684 printk(KERN_DEBUG "%s: HFC_CONF_SPLIT\n", __func__); 3685 hfcmulti_conf(hc, bch->slot, -1); 3686 break; 3687 case MISDN_CTRL_HFC_ECHOCAN_ON: 3688 if (debug & DEBUG_HFCMULTI_MSG) 3689 printk(KERN_DEBUG "%s: HFC_ECHOCAN_ON\n", __func__); 3690 if (test_bit(HFC_CHIP_B410P, &hc->chip)) 3691 vpm_echocan_on(hc, bch->slot, cq->p1); 3692 else 3693 ret = -EINVAL; 3694 break; 3695 3696 case MISDN_CTRL_HFC_ECHOCAN_OFF: 3697 if (debug & DEBUG_HFCMULTI_MSG) 3698 printk(KERN_DEBUG "%s: HFC_ECHOCAN_OFF\n", 3699 __func__); 3700 if (test_bit(HFC_CHIP_B410P, &hc->chip)) 3701 vpm_echocan_off(hc, bch->slot); 3702 else 3703 ret = -EINVAL; 3704 break; 3705 default: 3706 printk(KERN_WARNING "%s: unknown Op %x\n", 3707 __func__, cq->op); 3708 ret = -EINVAL; 3709 break; 3710 } 3711 return ret; 3712 } 3713 3714 static int 3715 hfcm_bctrl(struct mISDNchannel *ch, u_int cmd, void *arg) 3716 { 3717 struct bchannel *bch = container_of(ch, struct bchannel, ch); 3718 struct hfc_multi *hc = bch->hw; 3719 int err = -EINVAL; 3720 u_long flags; 3721 3722 if (bch->debug & DEBUG_HW) 3723 printk(KERN_DEBUG "%s: cmd:%x %p\n", 3724 __func__, cmd, arg); 3725 switch (cmd) { 3726 case CLOSE_CHANNEL: 3727 test_and_clear_bit(FLG_OPEN, &bch->Flags); 3728 if (test_bit(FLG_ACTIVE, &bch->Flags)) 3729 deactivate_bchannel(bch); /* locked there */ 3730 ch->protocol = ISDN_P_NONE; 3731 ch->peer = NULL; 3732 module_put(THIS_MODULE); 3733 err = 0; 3734 break; 3735 case CONTROL_CHANNEL: 3736 spin_lock_irqsave(&hc->lock, flags); 3737 err = channel_bctrl(bch, arg); 3738 spin_unlock_irqrestore(&hc->lock, flags); 3739 break; 3740 default: 3741 printk(KERN_WARNING "%s: unknown prim(%x)\n", 3742 __func__, cmd); 3743 } 3744 return err; 3745 } 3746 3747 /* 3748 * handle D-channel events 3749 * 3750 * handle state change event 3751 */ 3752 static void 3753 ph_state_change(struct dchannel *dch) 3754 { 3755 struct hfc_multi *hc; 3756 int ch, i; 3757 3758 if (!dch) { 3759 printk(KERN_WARNING "%s: ERROR given dch is NULL\n", __func__); 3760 return; 3761 } 3762 hc = dch->hw; 3763 ch = dch->slot; 3764 3765 if (hc->ctype == HFC_TYPE_E1) { 3766 if (dch->dev.D.protocol == ISDN_P_TE_E1) { 3767 if (debug & DEBUG_HFCMULTI_STATE) 3768 printk(KERN_DEBUG 3769 "%s: E1 TE (id=%d) newstate %x\n", 3770 __func__, hc->id, dch->state); 3771 } else { 3772 if (debug & DEBUG_HFCMULTI_STATE) 3773 printk(KERN_DEBUG 3774 "%s: E1 NT (id=%d) newstate %x\n", 3775 __func__, hc->id, dch->state); 3776 } 3777 switch (dch->state) { 3778 case (1): 3779 if (hc->e1_state != 1) { 3780 for (i = 1; i <= 31; i++) { 3781 /* reset fifos on e1 activation */ 3782 HFC_outb_nodebug(hc, R_FIFO, 3783 (i << 1) | 1); 3784 HFC_wait_nodebug(hc); 3785 HFC_outb_nodebug(hc, R_INC_RES_FIFO, 3786 V_RES_F); 3787 HFC_wait_nodebug(hc); 3788 } 3789 } 3790 test_and_set_bit(FLG_ACTIVE, &dch->Flags); 3791 _queue_data(&dch->dev.D, PH_ACTIVATE_IND, 3792 MISDN_ID_ANY, 0, NULL, GFP_ATOMIC); 3793 break; 3794 3795 default: 3796 if (hc->e1_state != 1) 3797 return; 3798 test_and_clear_bit(FLG_ACTIVE, &dch->Flags); 3799 _queue_data(&dch->dev.D, PH_DEACTIVATE_IND, 3800 MISDN_ID_ANY, 0, NULL, GFP_ATOMIC); 3801 } 3802 hc->e1_state = dch->state; 3803 } else { 3804 if (dch->dev.D.protocol == ISDN_P_TE_S0) { 3805 if (debug & DEBUG_HFCMULTI_STATE) 3806 printk(KERN_DEBUG 3807 "%s: S/T TE newstate %x\n", 3808 __func__, dch->state); 3809 switch (dch->state) { 3810 case (0): 3811 l1_event(dch->l1, HW_RESET_IND); 3812 break; 3813 case (3): 3814 l1_event(dch->l1, HW_DEACT_IND); 3815 break; 3816 case (5): 3817 case (8): 3818 l1_event(dch->l1, ANYSIGNAL); 3819 break; 3820 case (6): 3821 l1_event(dch->l1, INFO2); 3822 break; 3823 case (7): 3824 l1_event(dch->l1, INFO4_P8); 3825 break; 3826 } 3827 } else { 3828 if (debug & DEBUG_HFCMULTI_STATE) 3829 printk(KERN_DEBUG "%s: S/T NT newstate %x\n", 3830 __func__, dch->state); 3831 switch (dch->state) { 3832 case (2): 3833 if (hc->chan[ch].nt_timer == 0) { 3834 hc->chan[ch].nt_timer = -1; 3835 HFC_outb(hc, R_ST_SEL, 3836 hc->chan[ch].port); 3837 /* undocumented: delay after R_ST_SEL */ 3838 udelay(1); 3839 HFC_outb(hc, A_ST_WR_STATE, 4 | 3840 V_ST_LD_STA); /* G4 */ 3841 udelay(6); /* wait at least 5,21us */ 3842 HFC_outb(hc, A_ST_WR_STATE, 4); 3843 dch->state = 4; 3844 } else { 3845 /* one extra count for the next event */ 3846 hc->chan[ch].nt_timer = 3847 nt_t1_count[poll_timer] + 1; 3848 HFC_outb(hc, R_ST_SEL, 3849 hc->chan[ch].port); 3850 /* undocumented: delay after R_ST_SEL */ 3851 udelay(1); 3852 /* allow G2 -> G3 transition */ 3853 HFC_outb(hc, A_ST_WR_STATE, 2 | 3854 V_SET_G2_G3); 3855 } 3856 break; 3857 case (1): 3858 hc->chan[ch].nt_timer = -1; 3859 test_and_clear_bit(FLG_ACTIVE, &dch->Flags); 3860 _queue_data(&dch->dev.D, PH_DEACTIVATE_IND, 3861 MISDN_ID_ANY, 0, NULL, GFP_ATOMIC); 3862 break; 3863 case (4): 3864 hc->chan[ch].nt_timer = -1; 3865 break; 3866 case (3): 3867 hc->chan[ch].nt_timer = -1; 3868 test_and_set_bit(FLG_ACTIVE, &dch->Flags); 3869 _queue_data(&dch->dev.D, PH_ACTIVATE_IND, 3870 MISDN_ID_ANY, 0, NULL, GFP_ATOMIC); 3871 break; 3872 } 3873 } 3874 } 3875 } 3876 3877 /* 3878 * called for card mode init message 3879 */ 3880 3881 static void 3882 hfcmulti_initmode(struct dchannel *dch) 3883 { 3884 struct hfc_multi *hc = dch->hw; 3885 u_char a_st_wr_state, r_e1_wr_sta; 3886 int i, pt; 3887 3888 if (debug & DEBUG_HFCMULTI_INIT) 3889 printk(KERN_DEBUG "%s: entered\n", __func__); 3890 3891 i = dch->slot; 3892 pt = hc->chan[i].port; 3893 if (hc->ctype == HFC_TYPE_E1) { 3894 /* E1 */ 3895 hc->chan[hc->dnum[pt]].slot_tx = -1; 3896 hc->chan[hc->dnum[pt]].slot_rx = -1; 3897 hc->chan[hc->dnum[pt]].conf = -1; 3898 if (hc->dnum[pt]) { 3899 mode_hfcmulti(hc, dch->slot, dch->dev.D.protocol, 3900 -1, 0, -1, 0); 3901 dch->timer.function = (void *) hfcmulti_dbusy_timer; 3902 dch->timer.data = (long) dch; 3903 init_timer(&dch->timer); 3904 } 3905 for (i = 1; i <= 31; i++) { 3906 if (!((1 << i) & hc->bmask[pt])) /* skip unused chan */ 3907 continue; 3908 hc->chan[i].slot_tx = -1; 3909 hc->chan[i].slot_rx = -1; 3910 hc->chan[i].conf = -1; 3911 mode_hfcmulti(hc, i, ISDN_P_NONE, -1, 0, -1, 0); 3912 } 3913 } 3914 if (hc->ctype == HFC_TYPE_E1 && pt == 0) { 3915 /* E1, port 0 */ 3916 dch = hc->chan[hc->dnum[0]].dch; 3917 if (test_bit(HFC_CFG_REPORT_LOS, &hc->chan[hc->dnum[0]].cfg)) { 3918 HFC_outb(hc, R_LOS0, 255); /* 2 ms */ 3919 HFC_outb(hc, R_LOS1, 255); /* 512 ms */ 3920 } 3921 if (test_bit(HFC_CFG_OPTICAL, &hc->chan[hc->dnum[0]].cfg)) { 3922 HFC_outb(hc, R_RX0, 0); 3923 hc->hw.r_tx0 = 0 | V_OUT_EN; 3924 } else { 3925 HFC_outb(hc, R_RX0, 1); 3926 hc->hw.r_tx0 = 1 | V_OUT_EN; 3927 } 3928 hc->hw.r_tx1 = V_ATX | V_NTRI; 3929 HFC_outb(hc, R_TX0, hc->hw.r_tx0); 3930 HFC_outb(hc, R_TX1, hc->hw.r_tx1); 3931 HFC_outb(hc, R_TX_FR0, 0x00); 3932 HFC_outb(hc, R_TX_FR1, 0xf8); 3933 3934 if (test_bit(HFC_CFG_CRC4, &hc->chan[hc->dnum[0]].cfg)) 3935 HFC_outb(hc, R_TX_FR2, V_TX_MF | V_TX_E | V_NEG_E); 3936 3937 HFC_outb(hc, R_RX_FR0, V_AUTO_RESYNC | V_AUTO_RECO | 0); 3938 3939 if (test_bit(HFC_CFG_CRC4, &hc->chan[hc->dnum[0]].cfg)) 3940 HFC_outb(hc, R_RX_FR1, V_RX_MF | V_RX_MF_SYNC); 3941 3942 if (dch->dev.D.protocol == ISDN_P_NT_E1) { 3943 if (debug & DEBUG_HFCMULTI_INIT) 3944 printk(KERN_DEBUG "%s: E1 port is NT-mode\n", 3945 __func__); 3946 r_e1_wr_sta = 0; /* G0 */ 3947 hc->e1_getclock = 0; 3948 } else { 3949 if (debug & DEBUG_HFCMULTI_INIT) 3950 printk(KERN_DEBUG "%s: E1 port is TE-mode\n", 3951 __func__); 3952 r_e1_wr_sta = 0; /* F0 */ 3953 hc->e1_getclock = 1; 3954 } 3955 if (test_bit(HFC_CHIP_RX_SYNC, &hc->chip)) 3956 HFC_outb(hc, R_SYNC_OUT, V_SYNC_E1_RX); 3957 else 3958 HFC_outb(hc, R_SYNC_OUT, 0); 3959 if (test_bit(HFC_CHIP_E1CLOCK_GET, &hc->chip)) 3960 hc->e1_getclock = 1; 3961 if (test_bit(HFC_CHIP_E1CLOCK_PUT, &hc->chip)) 3962 hc->e1_getclock = 0; 3963 if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip)) { 3964 /* SLAVE (clock master) */ 3965 if (debug & DEBUG_HFCMULTI_INIT) 3966 printk(KERN_DEBUG 3967 "%s: E1 port is clock master " 3968 "(clock from PCM)\n", __func__); 3969 HFC_outb(hc, R_SYNC_CTRL, V_EXT_CLK_SYNC | V_PCM_SYNC); 3970 } else { 3971 if (hc->e1_getclock) { 3972 /* MASTER (clock slave) */ 3973 if (debug & DEBUG_HFCMULTI_INIT) 3974 printk(KERN_DEBUG 3975 "%s: E1 port is clock slave " 3976 "(clock to PCM)\n", __func__); 3977 HFC_outb(hc, R_SYNC_CTRL, V_SYNC_OFFS); 3978 } else { 3979 /* MASTER (clock master) */ 3980 if (debug & DEBUG_HFCMULTI_INIT) 3981 printk(KERN_DEBUG "%s: E1 port is " 3982 "clock master " 3983 "(clock from QUARTZ)\n", 3984 __func__); 3985 HFC_outb(hc, R_SYNC_CTRL, V_EXT_CLK_SYNC | 3986 V_PCM_SYNC | V_JATT_OFF); 3987 HFC_outb(hc, R_SYNC_OUT, 0); 3988 } 3989 } 3990 HFC_outb(hc, R_JATT_ATT, 0x9c); /* undoc register */ 3991 HFC_outb(hc, R_PWM_MD, V_PWM0_MD); 3992 HFC_outb(hc, R_PWM0, 0x50); 3993 HFC_outb(hc, R_PWM1, 0xff); 3994 /* state machine setup */ 3995 HFC_outb(hc, R_E1_WR_STA, r_e1_wr_sta | V_E1_LD_STA); 3996 udelay(6); /* wait at least 5,21us */ 3997 HFC_outb(hc, R_E1_WR_STA, r_e1_wr_sta); 3998 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) { 3999 hc->syncronized = 0; 4000 plxsd_checksync(hc, 0); 4001 } 4002 } 4003 if (hc->ctype != HFC_TYPE_E1) { 4004 /* ST */ 4005 hc->chan[i].slot_tx = -1; 4006 hc->chan[i].slot_rx = -1; 4007 hc->chan[i].conf = -1; 4008 mode_hfcmulti(hc, i, dch->dev.D.protocol, -1, 0, -1, 0); 4009 dch->timer.function = (void *) hfcmulti_dbusy_timer; 4010 dch->timer.data = (long) dch; 4011 init_timer(&dch->timer); 4012 hc->chan[i - 2].slot_tx = -1; 4013 hc->chan[i - 2].slot_rx = -1; 4014 hc->chan[i - 2].conf = -1; 4015 mode_hfcmulti(hc, i - 2, ISDN_P_NONE, -1, 0, -1, 0); 4016 hc->chan[i - 1].slot_tx = -1; 4017 hc->chan[i - 1].slot_rx = -1; 4018 hc->chan[i - 1].conf = -1; 4019 mode_hfcmulti(hc, i - 1, ISDN_P_NONE, -1, 0, -1, 0); 4020 /* select interface */ 4021 HFC_outb(hc, R_ST_SEL, pt); 4022 /* undocumented: delay after R_ST_SEL */ 4023 udelay(1); 4024 if (dch->dev.D.protocol == ISDN_P_NT_S0) { 4025 if (debug & DEBUG_HFCMULTI_INIT) 4026 printk(KERN_DEBUG 4027 "%s: ST port %d is NT-mode\n", 4028 __func__, pt); 4029 /* clock delay */ 4030 HFC_outb(hc, A_ST_CLK_DLY, clockdelay_nt); 4031 a_st_wr_state = 1; /* G1 */ 4032 hc->hw.a_st_ctrl0[pt] = V_ST_MD; 4033 } else { 4034 if (debug & DEBUG_HFCMULTI_INIT) 4035 printk(KERN_DEBUG 4036 "%s: ST port %d is TE-mode\n", 4037 __func__, pt); 4038 /* clock delay */ 4039 HFC_outb(hc, A_ST_CLK_DLY, clockdelay_te); 4040 a_st_wr_state = 2; /* F2 */ 4041 hc->hw.a_st_ctrl0[pt] = 0; 4042 } 4043 if (!test_bit(HFC_CFG_NONCAP_TX, &hc->chan[i].cfg)) 4044 hc->hw.a_st_ctrl0[pt] |= V_TX_LI; 4045 if (hc->ctype == HFC_TYPE_XHFC) { 4046 hc->hw.a_st_ctrl0[pt] |= 0x40 /* V_ST_PU_CTRL */; 4047 HFC_outb(hc, 0x35 /* A_ST_CTRL3 */, 4048 0x7c << 1 /* V_ST_PULSE */); 4049 } 4050 /* line setup */ 4051 HFC_outb(hc, A_ST_CTRL0, hc->hw.a_st_ctrl0[pt]); 4052 /* disable E-channel */ 4053 if ((dch->dev.D.protocol == ISDN_P_NT_S0) || 4054 test_bit(HFC_CFG_DIS_ECHANNEL, &hc->chan[i].cfg)) 4055 HFC_outb(hc, A_ST_CTRL1, V_E_IGNO); 4056 else 4057 HFC_outb(hc, A_ST_CTRL1, 0); 4058 /* enable B-channel receive */ 4059 HFC_outb(hc, A_ST_CTRL2, V_B1_RX_EN | V_B2_RX_EN); 4060 /* state machine setup */ 4061 HFC_outb(hc, A_ST_WR_STATE, a_st_wr_state | V_ST_LD_STA); 4062 udelay(6); /* wait at least 5,21us */ 4063 HFC_outb(hc, A_ST_WR_STATE, a_st_wr_state); 4064 hc->hw.r_sci_msk |= 1 << pt; 4065 /* state machine interrupts */ 4066 HFC_outb(hc, R_SCI_MSK, hc->hw.r_sci_msk); 4067 /* unset sync on port */ 4068 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) { 4069 hc->syncronized &= 4070 ~(1 << hc->chan[dch->slot].port); 4071 plxsd_checksync(hc, 0); 4072 } 4073 } 4074 if (debug & DEBUG_HFCMULTI_INIT) 4075 printk("%s: done\n", __func__); 4076 } 4077 4078 4079 static int 4080 open_dchannel(struct hfc_multi *hc, struct dchannel *dch, 4081 struct channel_req *rq) 4082 { 4083 int err = 0; 4084 u_long flags; 4085 4086 if (debug & DEBUG_HW_OPEN) 4087 printk(KERN_DEBUG "%s: dev(%d) open from %p\n", __func__, 4088 dch->dev.id, __builtin_return_address(0)); 4089 if (rq->protocol == ISDN_P_NONE) 4090 return -EINVAL; 4091 if ((dch->dev.D.protocol != ISDN_P_NONE) && 4092 (dch->dev.D.protocol != rq->protocol)) { 4093 if (debug & DEBUG_HFCMULTI_MODE) 4094 printk(KERN_DEBUG "%s: change protocol %x to %x\n", 4095 __func__, dch->dev.D.protocol, rq->protocol); 4096 } 4097 if ((dch->dev.D.protocol == ISDN_P_TE_S0) && 4098 (rq->protocol != ISDN_P_TE_S0)) 4099 l1_event(dch->l1, CLOSE_CHANNEL); 4100 if (dch->dev.D.protocol != rq->protocol) { 4101 if (rq->protocol == ISDN_P_TE_S0) { 4102 err = create_l1(dch, hfcm_l1callback); 4103 if (err) 4104 return err; 4105 } 4106 dch->dev.D.protocol = rq->protocol; 4107 spin_lock_irqsave(&hc->lock, flags); 4108 hfcmulti_initmode(dch); 4109 spin_unlock_irqrestore(&hc->lock, flags); 4110 } 4111 if (test_bit(FLG_ACTIVE, &dch->Flags)) 4112 _queue_data(&dch->dev.D, PH_ACTIVATE_IND, MISDN_ID_ANY, 4113 0, NULL, GFP_KERNEL); 4114 rq->ch = &dch->dev.D; 4115 if (!try_module_get(THIS_MODULE)) 4116 printk(KERN_WARNING "%s:cannot get module\n", __func__); 4117 return 0; 4118 } 4119 4120 static int 4121 open_bchannel(struct hfc_multi *hc, struct dchannel *dch, 4122 struct channel_req *rq) 4123 { 4124 struct bchannel *bch; 4125 int ch; 4126 4127 if (!test_channelmap(rq->adr.channel, dch->dev.channelmap)) 4128 return -EINVAL; 4129 if (rq->protocol == ISDN_P_NONE) 4130 return -EINVAL; 4131 if (hc->ctype == HFC_TYPE_E1) 4132 ch = rq->adr.channel; 4133 else 4134 ch = (rq->adr.channel - 1) + (dch->slot - 2); 4135 bch = hc->chan[ch].bch; 4136 if (!bch) { 4137 printk(KERN_ERR "%s:internal error ch %d has no bch\n", 4138 __func__, ch); 4139 return -EINVAL; 4140 } 4141 if (test_and_set_bit(FLG_OPEN, &bch->Flags)) 4142 return -EBUSY; /* b-channel can be only open once */ 4143 test_and_clear_bit(FLG_FILLEMPTY, &bch->Flags); 4144 bch->ch.protocol = rq->protocol; 4145 hc->chan[ch].rx_off = 0; 4146 rq->ch = &bch->ch; 4147 if (!try_module_get(THIS_MODULE)) 4148 printk(KERN_WARNING "%s:cannot get module\n", __func__); 4149 return 0; 4150 } 4151 4152 /* 4153 * device control function 4154 */ 4155 static int 4156 channel_dctrl(struct dchannel *dch, struct mISDN_ctrl_req *cq) 4157 { 4158 struct hfc_multi *hc = dch->hw; 4159 int ret = 0; 4160 int wd_mode, wd_cnt; 4161 4162 switch (cq->op) { 4163 case MISDN_CTRL_GETOP: 4164 cq->op = MISDN_CTRL_HFC_OP; 4165 break; 4166 case MISDN_CTRL_HFC_WD_INIT: /* init the watchdog */ 4167 wd_cnt = cq->p1 & 0xf; 4168 wd_mode = !!(cq->p1 >> 4); 4169 if (debug & DEBUG_HFCMULTI_MSG) 4170 printk(KERN_DEBUG "%s: MISDN_CTRL_HFC_WD_INIT mode %s" 4171 ", counter 0x%x\n", __func__, 4172 wd_mode ? "AUTO" : "MANUAL", wd_cnt); 4173 /* set the watchdog timer */ 4174 HFC_outb(hc, R_TI_WD, poll_timer | (wd_cnt << 4)); 4175 hc->hw.r_bert_wd_md = (wd_mode ? V_AUTO_WD_RES : 0); 4176 if (hc->ctype == HFC_TYPE_XHFC) 4177 hc->hw.r_bert_wd_md |= 0x40 /* V_WD_EN */; 4178 /* init the watchdog register and reset the counter */ 4179 HFC_outb(hc, R_BERT_WD_MD, hc->hw.r_bert_wd_md | V_WD_RES); 4180 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) { 4181 /* enable the watchdog output for Speech-Design */ 4182 HFC_outb(hc, R_GPIO_SEL, V_GPIO_SEL7); 4183 HFC_outb(hc, R_GPIO_EN1, V_GPIO_EN15); 4184 HFC_outb(hc, R_GPIO_OUT1, 0); 4185 HFC_outb(hc, R_GPIO_OUT1, V_GPIO_OUT15); 4186 } 4187 break; 4188 case MISDN_CTRL_HFC_WD_RESET: /* reset the watchdog counter */ 4189 if (debug & DEBUG_HFCMULTI_MSG) 4190 printk(KERN_DEBUG "%s: MISDN_CTRL_HFC_WD_RESET\n", 4191 __func__); 4192 HFC_outb(hc, R_BERT_WD_MD, hc->hw.r_bert_wd_md | V_WD_RES); 4193 break; 4194 default: 4195 printk(KERN_WARNING "%s: unknown Op %x\n", 4196 __func__, cq->op); 4197 ret = -EINVAL; 4198 break; 4199 } 4200 return ret; 4201 } 4202 4203 static int 4204 hfcm_dctrl(struct mISDNchannel *ch, u_int cmd, void *arg) 4205 { 4206 struct mISDNdevice *dev = container_of(ch, struct mISDNdevice, D); 4207 struct dchannel *dch = container_of(dev, struct dchannel, dev); 4208 struct hfc_multi *hc = dch->hw; 4209 struct channel_req *rq; 4210 int err = 0; 4211 u_long flags; 4212 4213 if (dch->debug & DEBUG_HW) 4214 printk(KERN_DEBUG "%s: cmd:%x %p\n", 4215 __func__, cmd, arg); 4216 switch (cmd) { 4217 case OPEN_CHANNEL: 4218 rq = arg; 4219 switch (rq->protocol) { 4220 case ISDN_P_TE_S0: 4221 case ISDN_P_NT_S0: 4222 if (hc->ctype == HFC_TYPE_E1) { 4223 err = -EINVAL; 4224 break; 4225 } 4226 err = open_dchannel(hc, dch, rq); /* locked there */ 4227 break; 4228 case ISDN_P_TE_E1: 4229 case ISDN_P_NT_E1: 4230 if (hc->ctype != HFC_TYPE_E1) { 4231 err = -EINVAL; 4232 break; 4233 } 4234 err = open_dchannel(hc, dch, rq); /* locked there */ 4235 break; 4236 default: 4237 spin_lock_irqsave(&hc->lock, flags); 4238 err = open_bchannel(hc, dch, rq); 4239 spin_unlock_irqrestore(&hc->lock, flags); 4240 } 4241 break; 4242 case CLOSE_CHANNEL: 4243 if (debug & DEBUG_HW_OPEN) 4244 printk(KERN_DEBUG "%s: dev(%d) close from %p\n", 4245 __func__, dch->dev.id, 4246 __builtin_return_address(0)); 4247 module_put(THIS_MODULE); 4248 break; 4249 case CONTROL_CHANNEL: 4250 spin_lock_irqsave(&hc->lock, flags); 4251 err = channel_dctrl(dch, arg); 4252 spin_unlock_irqrestore(&hc->lock, flags); 4253 break; 4254 default: 4255 if (dch->debug & DEBUG_HW) 4256 printk(KERN_DEBUG "%s: unknown command %x\n", 4257 __func__, cmd); 4258 err = -EINVAL; 4259 } 4260 return err; 4261 } 4262 4263 static int 4264 clockctl(void *priv, int enable) 4265 { 4266 struct hfc_multi *hc = priv; 4267 4268 hc->iclock_on = enable; 4269 return 0; 4270 } 4271 4272 /* 4273 * initialize the card 4274 */ 4275 4276 /* 4277 * start timer irq, wait some time and check if we have interrupts. 4278 * if not, reset chip and try again. 4279 */ 4280 static int 4281 init_card(struct hfc_multi *hc) 4282 { 4283 int err = -EIO; 4284 u_long flags; 4285 void __iomem *plx_acc; 4286 u_long plx_flags; 4287 4288 if (debug & DEBUG_HFCMULTI_INIT) 4289 printk(KERN_DEBUG "%s: entered\n", __func__); 4290 4291 spin_lock_irqsave(&hc->lock, flags); 4292 /* set interrupts but leave global interrupt disabled */ 4293 hc->hw.r_irq_ctrl = V_FIFO_IRQ; 4294 disable_hwirq(hc); 4295 spin_unlock_irqrestore(&hc->lock, flags); 4296 4297 if (request_irq(hc->irq, hfcmulti_interrupt, IRQF_SHARED, 4298 "HFC-multi", hc)) { 4299 printk(KERN_WARNING "mISDN: Could not get interrupt %d.\n", 4300 hc->irq); 4301 hc->irq = 0; 4302 return -EIO; 4303 } 4304 4305 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) { 4306 spin_lock_irqsave(&plx_lock, plx_flags); 4307 plx_acc = hc->plx_membase + PLX_INTCSR; 4308 writew((PLX_INTCSR_PCIINT_ENABLE | PLX_INTCSR_LINTI1_ENABLE), 4309 plx_acc); /* enable PCI & LINT1 irq */ 4310 spin_unlock_irqrestore(&plx_lock, plx_flags); 4311 } 4312 4313 if (debug & DEBUG_HFCMULTI_INIT) 4314 printk(KERN_DEBUG "%s: IRQ %d count %d\n", 4315 __func__, hc->irq, hc->irqcnt); 4316 err = init_chip(hc); 4317 if (err) 4318 goto error; 4319 /* 4320 * Finally enable IRQ output 4321 * this is only allowed, if an IRQ routine is already 4322 * established for this HFC, so don't do that earlier 4323 */ 4324 spin_lock_irqsave(&hc->lock, flags); 4325 enable_hwirq(hc); 4326 spin_unlock_irqrestore(&hc->lock, flags); 4327 /* printk(KERN_DEBUG "no master irq set!!!\n"); */ 4328 set_current_state(TASK_UNINTERRUPTIBLE); 4329 schedule_timeout((100 * HZ) / 1000); /* Timeout 100ms */ 4330 /* turn IRQ off until chip is completely initialized */ 4331 spin_lock_irqsave(&hc->lock, flags); 4332 disable_hwirq(hc); 4333 spin_unlock_irqrestore(&hc->lock, flags); 4334 if (debug & DEBUG_HFCMULTI_INIT) 4335 printk(KERN_DEBUG "%s: IRQ %d count %d\n", 4336 __func__, hc->irq, hc->irqcnt); 4337 if (hc->irqcnt) { 4338 if (debug & DEBUG_HFCMULTI_INIT) 4339 printk(KERN_DEBUG "%s: done\n", __func__); 4340 4341 return 0; 4342 } 4343 if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip)) { 4344 printk(KERN_INFO "ignoring missing interrupts\n"); 4345 return 0; 4346 } 4347 4348 printk(KERN_ERR "HFC PCI: IRQ(%d) getting no interrupts during init.\n", 4349 hc->irq); 4350 4351 err = -EIO; 4352 4353 error: 4354 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) { 4355 spin_lock_irqsave(&plx_lock, plx_flags); 4356 plx_acc = hc->plx_membase + PLX_INTCSR; 4357 writew(0x00, plx_acc); /*disable IRQs*/ 4358 spin_unlock_irqrestore(&plx_lock, plx_flags); 4359 } 4360 4361 if (debug & DEBUG_HFCMULTI_INIT) 4362 printk(KERN_DEBUG "%s: free irq %d\n", __func__, hc->irq); 4363 if (hc->irq) { 4364 free_irq(hc->irq, hc); 4365 hc->irq = 0; 4366 } 4367 4368 if (debug & DEBUG_HFCMULTI_INIT) 4369 printk(KERN_DEBUG "%s: done (err=%d)\n", __func__, err); 4370 return err; 4371 } 4372 4373 /* 4374 * find pci device and set it up 4375 */ 4376 4377 static int 4378 setup_pci(struct hfc_multi *hc, struct pci_dev *pdev, 4379 const struct pci_device_id *ent) 4380 { 4381 struct hm_map *m = (struct hm_map *)ent->driver_data; 4382 4383 printk(KERN_INFO 4384 "HFC-multi: card manufacturer: '%s' card name: '%s' clock: %s\n", 4385 m->vendor_name, m->card_name, m->clock2 ? "double" : "normal"); 4386 4387 hc->pci_dev = pdev; 4388 if (m->clock2) 4389 test_and_set_bit(HFC_CHIP_CLOCK2, &hc->chip); 4390 4391 if (ent->device == 0xB410) { 4392 test_and_set_bit(HFC_CHIP_B410P, &hc->chip); 4393 test_and_set_bit(HFC_CHIP_PCM_MASTER, &hc->chip); 4394 test_and_clear_bit(HFC_CHIP_PCM_SLAVE, &hc->chip); 4395 hc->slots = 32; 4396 } 4397 4398 if (hc->pci_dev->irq <= 0) { 4399 printk(KERN_WARNING "HFC-multi: No IRQ for PCI card found.\n"); 4400 return -EIO; 4401 } 4402 if (pci_enable_device(hc->pci_dev)) { 4403 printk(KERN_WARNING "HFC-multi: Error enabling PCI card.\n"); 4404 return -EIO; 4405 } 4406 hc->leds = m->leds; 4407 hc->ledstate = 0xAFFEAFFE; 4408 hc->opticalsupport = m->opticalsupport; 4409 4410 hc->pci_iobase = 0; 4411 hc->pci_membase = NULL; 4412 hc->plx_membase = NULL; 4413 4414 /* set memory access methods */ 4415 if (m->io_mode) /* use mode from card config */ 4416 hc->io_mode = m->io_mode; 4417 switch (hc->io_mode) { 4418 case HFC_IO_MODE_PLXSD: 4419 test_and_set_bit(HFC_CHIP_PLXSD, &hc->chip); 4420 hc->slots = 128; /* required */ 4421 hc->HFC_outb = HFC_outb_pcimem; 4422 hc->HFC_inb = HFC_inb_pcimem; 4423 hc->HFC_inw = HFC_inw_pcimem; 4424 hc->HFC_wait = HFC_wait_pcimem; 4425 hc->read_fifo = read_fifo_pcimem; 4426 hc->write_fifo = write_fifo_pcimem; 4427 hc->plx_origmembase = hc->pci_dev->resource[0].start; 4428 /* MEMBASE 1 is PLX PCI Bridge */ 4429 4430 if (!hc->plx_origmembase) { 4431 printk(KERN_WARNING 4432 "HFC-multi: No IO-Memory for PCI PLX bridge found\n"); 4433 pci_disable_device(hc->pci_dev); 4434 return -EIO; 4435 } 4436 4437 hc->plx_membase = ioremap(hc->plx_origmembase, 0x80); 4438 if (!hc->plx_membase) { 4439 printk(KERN_WARNING 4440 "HFC-multi: failed to remap plx address space. " 4441 "(internal error)\n"); 4442 pci_disable_device(hc->pci_dev); 4443 return -EIO; 4444 } 4445 printk(KERN_INFO 4446 "HFC-multi: plx_membase:%#lx plx_origmembase:%#lx\n", 4447 (u_long)hc->plx_membase, hc->plx_origmembase); 4448 4449 hc->pci_origmembase = hc->pci_dev->resource[2].start; 4450 /* MEMBASE 1 is PLX PCI Bridge */ 4451 if (!hc->pci_origmembase) { 4452 printk(KERN_WARNING 4453 "HFC-multi: No IO-Memory for PCI card found\n"); 4454 pci_disable_device(hc->pci_dev); 4455 return -EIO; 4456 } 4457 4458 hc->pci_membase = ioremap(hc->pci_origmembase, 0x400); 4459 if (!hc->pci_membase) { 4460 printk(KERN_WARNING "HFC-multi: failed to remap io " 4461 "address space. (internal error)\n"); 4462 pci_disable_device(hc->pci_dev); 4463 return -EIO; 4464 } 4465 4466 printk(KERN_INFO 4467 "card %d: defined at MEMBASE %#lx (%#lx) IRQ %d HZ %d " 4468 "leds-type %d\n", 4469 hc->id, (u_long)hc->pci_membase, hc->pci_origmembase, 4470 hc->pci_dev->irq, HZ, hc->leds); 4471 pci_write_config_word(hc->pci_dev, PCI_COMMAND, PCI_ENA_MEMIO); 4472 break; 4473 case HFC_IO_MODE_PCIMEM: 4474 hc->HFC_outb = HFC_outb_pcimem; 4475 hc->HFC_inb = HFC_inb_pcimem; 4476 hc->HFC_inw = HFC_inw_pcimem; 4477 hc->HFC_wait = HFC_wait_pcimem; 4478 hc->read_fifo = read_fifo_pcimem; 4479 hc->write_fifo = write_fifo_pcimem; 4480 hc->pci_origmembase = hc->pci_dev->resource[1].start; 4481 if (!hc->pci_origmembase) { 4482 printk(KERN_WARNING 4483 "HFC-multi: No IO-Memory for PCI card found\n"); 4484 pci_disable_device(hc->pci_dev); 4485 return -EIO; 4486 } 4487 4488 hc->pci_membase = ioremap(hc->pci_origmembase, 256); 4489 if (!hc->pci_membase) { 4490 printk(KERN_WARNING 4491 "HFC-multi: failed to remap io address space. " 4492 "(internal error)\n"); 4493 pci_disable_device(hc->pci_dev); 4494 return -EIO; 4495 } 4496 printk(KERN_INFO "card %d: defined at MEMBASE %#lx (%#lx) IRQ " 4497 "%d HZ %d leds-type %d\n", hc->id, (u_long)hc->pci_membase, 4498 hc->pci_origmembase, hc->pci_dev->irq, HZ, hc->leds); 4499 pci_write_config_word(hc->pci_dev, PCI_COMMAND, PCI_ENA_MEMIO); 4500 break; 4501 case HFC_IO_MODE_REGIO: 4502 hc->HFC_outb = HFC_outb_regio; 4503 hc->HFC_inb = HFC_inb_regio; 4504 hc->HFC_inw = HFC_inw_regio; 4505 hc->HFC_wait = HFC_wait_regio; 4506 hc->read_fifo = read_fifo_regio; 4507 hc->write_fifo = write_fifo_regio; 4508 hc->pci_iobase = (u_int) hc->pci_dev->resource[0].start; 4509 if (!hc->pci_iobase) { 4510 printk(KERN_WARNING 4511 "HFC-multi: No IO for PCI card found\n"); 4512 pci_disable_device(hc->pci_dev); 4513 return -EIO; 4514 } 4515 4516 if (!request_region(hc->pci_iobase, 8, "hfcmulti")) { 4517 printk(KERN_WARNING "HFC-multi: failed to request " 4518 "address space at 0x%08lx (internal error)\n", 4519 hc->pci_iobase); 4520 pci_disable_device(hc->pci_dev); 4521 return -EIO; 4522 } 4523 4524 printk(KERN_INFO 4525 "%s %s: defined at IOBASE %#x IRQ %d HZ %d leds-type %d\n", 4526 m->vendor_name, m->card_name, (u_int) hc->pci_iobase, 4527 hc->pci_dev->irq, HZ, hc->leds); 4528 pci_write_config_word(hc->pci_dev, PCI_COMMAND, PCI_ENA_REGIO); 4529 break; 4530 default: 4531 printk(KERN_WARNING "HFC-multi: Invalid IO mode.\n"); 4532 pci_disable_device(hc->pci_dev); 4533 return -EIO; 4534 } 4535 4536 pci_set_drvdata(hc->pci_dev, hc); 4537 4538 /* At this point the needed PCI config is done */ 4539 /* fifos are still not enabled */ 4540 return 0; 4541 } 4542 4543 4544 /* 4545 * remove port 4546 */ 4547 4548 static void 4549 release_port(struct hfc_multi *hc, struct dchannel *dch) 4550 { 4551 int pt, ci, i = 0; 4552 u_long flags; 4553 struct bchannel *pb; 4554 4555 ci = dch->slot; 4556 pt = hc->chan[ci].port; 4557 4558 if (debug & DEBUG_HFCMULTI_INIT) 4559 printk(KERN_DEBUG "%s: entered for port %d\n", 4560 __func__, pt + 1); 4561 4562 if (pt >= hc->ports) { 4563 printk(KERN_WARNING "%s: ERROR port out of range (%d).\n", 4564 __func__, pt + 1); 4565 return; 4566 } 4567 4568 if (debug & DEBUG_HFCMULTI_INIT) 4569 printk(KERN_DEBUG "%s: releasing port=%d\n", 4570 __func__, pt + 1); 4571 4572 if (dch->dev.D.protocol == ISDN_P_TE_S0) 4573 l1_event(dch->l1, CLOSE_CHANNEL); 4574 4575 hc->chan[ci].dch = NULL; 4576 4577 if (hc->created[pt]) { 4578 hc->created[pt] = 0; 4579 mISDN_unregister_device(&dch->dev); 4580 } 4581 4582 spin_lock_irqsave(&hc->lock, flags); 4583 4584 if (dch->timer.function) { 4585 del_timer(&dch->timer); 4586 dch->timer.function = NULL; 4587 } 4588 4589 if (hc->ctype == HFC_TYPE_E1) { /* E1 */ 4590 /* remove sync */ 4591 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) { 4592 hc->syncronized = 0; 4593 plxsd_checksync(hc, 1); 4594 } 4595 /* free channels */ 4596 for (i = 0; i <= 31; i++) { 4597 if (!((1 << i) & hc->bmask[pt])) /* skip unused chan */ 4598 continue; 4599 if (hc->chan[i].bch) { 4600 if (debug & DEBUG_HFCMULTI_INIT) 4601 printk(KERN_DEBUG 4602 "%s: free port %d channel %d\n", 4603 __func__, hc->chan[i].port + 1, i); 4604 pb = hc->chan[i].bch; 4605 hc->chan[i].bch = NULL; 4606 spin_unlock_irqrestore(&hc->lock, flags); 4607 mISDN_freebchannel(pb); 4608 kfree(pb); 4609 kfree(hc->chan[i].coeff); 4610 spin_lock_irqsave(&hc->lock, flags); 4611 } 4612 } 4613 } else { 4614 /* remove sync */ 4615 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) { 4616 hc->syncronized &= 4617 ~(1 << hc->chan[ci].port); 4618 plxsd_checksync(hc, 1); 4619 } 4620 /* free channels */ 4621 if (hc->chan[ci - 2].bch) { 4622 if (debug & DEBUG_HFCMULTI_INIT) 4623 printk(KERN_DEBUG 4624 "%s: free port %d channel %d\n", 4625 __func__, hc->chan[ci - 2].port + 1, 4626 ci - 2); 4627 pb = hc->chan[ci - 2].bch; 4628 hc->chan[ci - 2].bch = NULL; 4629 spin_unlock_irqrestore(&hc->lock, flags); 4630 mISDN_freebchannel(pb); 4631 kfree(pb); 4632 kfree(hc->chan[ci - 2].coeff); 4633 spin_lock_irqsave(&hc->lock, flags); 4634 } 4635 if (hc->chan[ci - 1].bch) { 4636 if (debug & DEBUG_HFCMULTI_INIT) 4637 printk(KERN_DEBUG 4638 "%s: free port %d channel %d\n", 4639 __func__, hc->chan[ci - 1].port + 1, 4640 ci - 1); 4641 pb = hc->chan[ci - 1].bch; 4642 hc->chan[ci - 1].bch = NULL; 4643 spin_unlock_irqrestore(&hc->lock, flags); 4644 mISDN_freebchannel(pb); 4645 kfree(pb); 4646 kfree(hc->chan[ci - 1].coeff); 4647 spin_lock_irqsave(&hc->lock, flags); 4648 } 4649 } 4650 4651 spin_unlock_irqrestore(&hc->lock, flags); 4652 4653 if (debug & DEBUG_HFCMULTI_INIT) 4654 printk(KERN_DEBUG "%s: free port %d channel D(%d)\n", __func__, 4655 pt+1, ci); 4656 mISDN_freedchannel(dch); 4657 kfree(dch); 4658 4659 if (debug & DEBUG_HFCMULTI_INIT) 4660 printk(KERN_DEBUG "%s: done!\n", __func__); 4661 } 4662 4663 static void 4664 release_card(struct hfc_multi *hc) 4665 { 4666 u_long flags; 4667 int ch; 4668 4669 if (debug & DEBUG_HFCMULTI_INIT) 4670 printk(KERN_DEBUG "%s: release card (%d) entered\n", 4671 __func__, hc->id); 4672 4673 /* unregister clock source */ 4674 if (hc->iclock) 4675 mISDN_unregister_clock(hc->iclock); 4676 4677 /* disable and free irq */ 4678 spin_lock_irqsave(&hc->lock, flags); 4679 disable_hwirq(hc); 4680 spin_unlock_irqrestore(&hc->lock, flags); 4681 udelay(1000); 4682 if (hc->irq) { 4683 if (debug & DEBUG_HFCMULTI_INIT) 4684 printk(KERN_DEBUG "%s: free irq %d (hc=%p)\n", 4685 __func__, hc->irq, hc); 4686 free_irq(hc->irq, hc); 4687 hc->irq = 0; 4688 4689 } 4690 4691 /* disable D-channels & B-channels */ 4692 if (debug & DEBUG_HFCMULTI_INIT) 4693 printk(KERN_DEBUG "%s: disable all channels (d and b)\n", 4694 __func__); 4695 for (ch = 0; ch <= 31; ch++) { 4696 if (hc->chan[ch].dch) 4697 release_port(hc, hc->chan[ch].dch); 4698 } 4699 4700 /* dimm leds */ 4701 if (hc->leds) 4702 hfcmulti_leds(hc); 4703 4704 /* release hardware */ 4705 release_io_hfcmulti(hc); 4706 4707 if (debug & DEBUG_HFCMULTI_INIT) 4708 printk(KERN_DEBUG "%s: remove instance from list\n", 4709 __func__); 4710 list_del(&hc->list); 4711 4712 if (debug & DEBUG_HFCMULTI_INIT) 4713 printk(KERN_DEBUG "%s: delete instance\n", __func__); 4714 if (hc == syncmaster) 4715 syncmaster = NULL; 4716 kfree(hc); 4717 if (debug & DEBUG_HFCMULTI_INIT) 4718 printk(KERN_DEBUG "%s: card successfully removed\n", 4719 __func__); 4720 } 4721 4722 static void 4723 init_e1_port_hw(struct hfc_multi *hc, struct hm_map *m) 4724 { 4725 /* set optical line type */ 4726 if (port[Port_cnt] & 0x001) { 4727 if (!m->opticalsupport) { 4728 printk(KERN_INFO 4729 "This board has no optical " 4730 "support\n"); 4731 } else { 4732 if (debug & DEBUG_HFCMULTI_INIT) 4733 printk(KERN_DEBUG 4734 "%s: PORT set optical " 4735 "interfacs: card(%d) " 4736 "port(%d)\n", 4737 __func__, 4738 HFC_cnt + 1, 1); 4739 test_and_set_bit(HFC_CFG_OPTICAL, 4740 &hc->chan[hc->dnum[0]].cfg); 4741 } 4742 } 4743 /* set LOS report */ 4744 if (port[Port_cnt] & 0x004) { 4745 if (debug & DEBUG_HFCMULTI_INIT) 4746 printk(KERN_DEBUG "%s: PORT set " 4747 "LOS report: card(%d) port(%d)\n", 4748 __func__, HFC_cnt + 1, 1); 4749 test_and_set_bit(HFC_CFG_REPORT_LOS, 4750 &hc->chan[hc->dnum[0]].cfg); 4751 } 4752 /* set AIS report */ 4753 if (port[Port_cnt] & 0x008) { 4754 if (debug & DEBUG_HFCMULTI_INIT) 4755 printk(KERN_DEBUG "%s: PORT set " 4756 "AIS report: card(%d) port(%d)\n", 4757 __func__, HFC_cnt + 1, 1); 4758 test_and_set_bit(HFC_CFG_REPORT_AIS, 4759 &hc->chan[hc->dnum[0]].cfg); 4760 } 4761 /* set SLIP report */ 4762 if (port[Port_cnt] & 0x010) { 4763 if (debug & DEBUG_HFCMULTI_INIT) 4764 printk(KERN_DEBUG 4765 "%s: PORT set SLIP report: " 4766 "card(%d) port(%d)\n", 4767 __func__, HFC_cnt + 1, 1); 4768 test_and_set_bit(HFC_CFG_REPORT_SLIP, 4769 &hc->chan[hc->dnum[0]].cfg); 4770 } 4771 /* set RDI report */ 4772 if (port[Port_cnt] & 0x020) { 4773 if (debug & DEBUG_HFCMULTI_INIT) 4774 printk(KERN_DEBUG 4775 "%s: PORT set RDI report: " 4776 "card(%d) port(%d)\n", 4777 __func__, HFC_cnt + 1, 1); 4778 test_and_set_bit(HFC_CFG_REPORT_RDI, 4779 &hc->chan[hc->dnum[0]].cfg); 4780 } 4781 /* set CRC-4 Mode */ 4782 if (!(port[Port_cnt] & 0x100)) { 4783 if (debug & DEBUG_HFCMULTI_INIT) 4784 printk(KERN_DEBUG "%s: PORT turn on CRC4 report:" 4785 " card(%d) port(%d)\n", 4786 __func__, HFC_cnt + 1, 1); 4787 test_and_set_bit(HFC_CFG_CRC4, 4788 &hc->chan[hc->dnum[0]].cfg); 4789 } else { 4790 if (debug & DEBUG_HFCMULTI_INIT) 4791 printk(KERN_DEBUG "%s: PORT turn off CRC4" 4792 " report: card(%d) port(%d)\n", 4793 __func__, HFC_cnt + 1, 1); 4794 } 4795 /* set forced clock */ 4796 if (port[Port_cnt] & 0x0200) { 4797 if (debug & DEBUG_HFCMULTI_INIT) 4798 printk(KERN_DEBUG "%s: PORT force getting clock from " 4799 "E1: card(%d) port(%d)\n", 4800 __func__, HFC_cnt + 1, 1); 4801 test_and_set_bit(HFC_CHIP_E1CLOCK_GET, &hc->chip); 4802 } else 4803 if (port[Port_cnt] & 0x0400) { 4804 if (debug & DEBUG_HFCMULTI_INIT) 4805 printk(KERN_DEBUG "%s: PORT force putting clock to " 4806 "E1: card(%d) port(%d)\n", 4807 __func__, HFC_cnt + 1, 1); 4808 test_and_set_bit(HFC_CHIP_E1CLOCK_PUT, &hc->chip); 4809 } 4810 /* set JATT PLL */ 4811 if (port[Port_cnt] & 0x0800) { 4812 if (debug & DEBUG_HFCMULTI_INIT) 4813 printk(KERN_DEBUG "%s: PORT disable JATT PLL on " 4814 "E1: card(%d) port(%d)\n", 4815 __func__, HFC_cnt + 1, 1); 4816 test_and_set_bit(HFC_CHIP_RX_SYNC, &hc->chip); 4817 } 4818 /* set elastic jitter buffer */ 4819 if (port[Port_cnt] & 0x3000) { 4820 hc->chan[hc->dnum[0]].jitter = (port[Port_cnt]>>12) & 0x3; 4821 if (debug & DEBUG_HFCMULTI_INIT) 4822 printk(KERN_DEBUG 4823 "%s: PORT set elastic " 4824 "buffer to %d: card(%d) port(%d)\n", 4825 __func__, hc->chan[hc->dnum[0]].jitter, 4826 HFC_cnt + 1, 1); 4827 } else 4828 hc->chan[hc->dnum[0]].jitter = 2; /* default */ 4829 } 4830 4831 static int 4832 init_e1_port(struct hfc_multi *hc, struct hm_map *m, int pt) 4833 { 4834 struct dchannel *dch; 4835 struct bchannel *bch; 4836 int ch, ret = 0; 4837 char name[MISDN_MAX_IDLEN]; 4838 int bcount = 0; 4839 4840 dch = kzalloc(sizeof(struct dchannel), GFP_KERNEL); 4841 if (!dch) 4842 return -ENOMEM; 4843 dch->debug = debug; 4844 mISDN_initdchannel(dch, MAX_DFRAME_LEN_L1, ph_state_change); 4845 dch->hw = hc; 4846 dch->dev.Dprotocols = (1 << ISDN_P_TE_E1) | (1 << ISDN_P_NT_E1); 4847 dch->dev.Bprotocols = (1 << (ISDN_P_B_RAW & ISDN_P_B_MASK)) | 4848 (1 << (ISDN_P_B_HDLC & ISDN_P_B_MASK)); 4849 dch->dev.D.send = handle_dmsg; 4850 dch->dev.D.ctrl = hfcm_dctrl; 4851 dch->slot = hc->dnum[pt]; 4852 hc->chan[hc->dnum[pt]].dch = dch; 4853 hc->chan[hc->dnum[pt]].port = pt; 4854 hc->chan[hc->dnum[pt]].nt_timer = -1; 4855 for (ch = 1; ch <= 31; ch++) { 4856 if (!((1 << ch) & hc->bmask[pt])) /* skip unused channel */ 4857 continue; 4858 bch = kzalloc(sizeof(struct bchannel), GFP_KERNEL); 4859 if (!bch) { 4860 printk(KERN_ERR "%s: no memory for bchannel\n", 4861 __func__); 4862 ret = -ENOMEM; 4863 goto free_chan; 4864 } 4865 hc->chan[ch].coeff = kzalloc(512, GFP_KERNEL); 4866 if (!hc->chan[ch].coeff) { 4867 printk(KERN_ERR "%s: no memory for coeffs\n", 4868 __func__); 4869 ret = -ENOMEM; 4870 kfree(bch); 4871 goto free_chan; 4872 } 4873 bch->nr = ch; 4874 bch->slot = ch; 4875 bch->debug = debug; 4876 mISDN_initbchannel(bch, MAX_DATA_MEM); 4877 bch->hw = hc; 4878 bch->ch.send = handle_bmsg; 4879 bch->ch.ctrl = hfcm_bctrl; 4880 bch->ch.nr = ch; 4881 list_add(&bch->ch.list, &dch->dev.bchannels); 4882 hc->chan[ch].bch = bch; 4883 hc->chan[ch].port = pt; 4884 set_channelmap(bch->nr, dch->dev.channelmap); 4885 bcount++; 4886 } 4887 dch->dev.nrbchan = bcount; 4888 if (pt == 0) 4889 init_e1_port_hw(hc, m); 4890 if (hc->ports > 1) 4891 snprintf(name, MISDN_MAX_IDLEN - 1, "hfc-e1.%d-%d", 4892 HFC_cnt + 1, pt+1); 4893 else 4894 snprintf(name, MISDN_MAX_IDLEN - 1, "hfc-e1.%d", HFC_cnt + 1); 4895 ret = mISDN_register_device(&dch->dev, &hc->pci_dev->dev, name); 4896 if (ret) 4897 goto free_chan; 4898 hc->created[pt] = 1; 4899 return ret; 4900 free_chan: 4901 release_port(hc, dch); 4902 return ret; 4903 } 4904 4905 static int 4906 init_multi_port(struct hfc_multi *hc, int pt) 4907 { 4908 struct dchannel *dch; 4909 struct bchannel *bch; 4910 int ch, i, ret = 0; 4911 char name[MISDN_MAX_IDLEN]; 4912 4913 dch = kzalloc(sizeof(struct dchannel), GFP_KERNEL); 4914 if (!dch) 4915 return -ENOMEM; 4916 dch->debug = debug; 4917 mISDN_initdchannel(dch, MAX_DFRAME_LEN_L1, ph_state_change); 4918 dch->hw = hc; 4919 dch->dev.Dprotocols = (1 << ISDN_P_TE_S0) | (1 << ISDN_P_NT_S0); 4920 dch->dev.Bprotocols = (1 << (ISDN_P_B_RAW & ISDN_P_B_MASK)) | 4921 (1 << (ISDN_P_B_HDLC & ISDN_P_B_MASK)); 4922 dch->dev.D.send = handle_dmsg; 4923 dch->dev.D.ctrl = hfcm_dctrl; 4924 dch->dev.nrbchan = 2; 4925 i = pt << 2; 4926 dch->slot = i + 2; 4927 hc->chan[i + 2].dch = dch; 4928 hc->chan[i + 2].port = pt; 4929 hc->chan[i + 2].nt_timer = -1; 4930 for (ch = 0; ch < dch->dev.nrbchan; ch++) { 4931 bch = kzalloc(sizeof(struct bchannel), GFP_KERNEL); 4932 if (!bch) { 4933 printk(KERN_ERR "%s: no memory for bchannel\n", 4934 __func__); 4935 ret = -ENOMEM; 4936 goto free_chan; 4937 } 4938 hc->chan[i + ch].coeff = kzalloc(512, GFP_KERNEL); 4939 if (!hc->chan[i + ch].coeff) { 4940 printk(KERN_ERR "%s: no memory for coeffs\n", 4941 __func__); 4942 ret = -ENOMEM; 4943 kfree(bch); 4944 goto free_chan; 4945 } 4946 bch->nr = ch + 1; 4947 bch->slot = i + ch; 4948 bch->debug = debug; 4949 mISDN_initbchannel(bch, MAX_DATA_MEM); 4950 bch->hw = hc; 4951 bch->ch.send = handle_bmsg; 4952 bch->ch.ctrl = hfcm_bctrl; 4953 bch->ch.nr = ch + 1; 4954 list_add(&bch->ch.list, &dch->dev.bchannels); 4955 hc->chan[i + ch].bch = bch; 4956 hc->chan[i + ch].port = pt; 4957 set_channelmap(bch->nr, dch->dev.channelmap); 4958 } 4959 /* set master clock */ 4960 if (port[Port_cnt] & 0x001) { 4961 if (debug & DEBUG_HFCMULTI_INIT) 4962 printk(KERN_DEBUG 4963 "%s: PROTOCOL set master clock: " 4964 "card(%d) port(%d)\n", 4965 __func__, HFC_cnt + 1, pt + 1); 4966 if (dch->dev.D.protocol != ISDN_P_TE_S0) { 4967 printk(KERN_ERR "Error: Master clock " 4968 "for port(%d) of card(%d) is only" 4969 " possible with TE-mode\n", 4970 pt + 1, HFC_cnt + 1); 4971 ret = -EINVAL; 4972 goto free_chan; 4973 } 4974 if (hc->masterclk >= 0) { 4975 printk(KERN_ERR "Error: Master clock " 4976 "for port(%d) of card(%d) already " 4977 "defined for port(%d)\n", 4978 pt + 1, HFC_cnt + 1, hc->masterclk + 1); 4979 ret = -EINVAL; 4980 goto free_chan; 4981 } 4982 hc->masterclk = pt; 4983 } 4984 /* set transmitter line to non capacitive */ 4985 if (port[Port_cnt] & 0x002) { 4986 if (debug & DEBUG_HFCMULTI_INIT) 4987 printk(KERN_DEBUG 4988 "%s: PROTOCOL set non capacitive " 4989 "transmitter: card(%d) port(%d)\n", 4990 __func__, HFC_cnt + 1, pt + 1); 4991 test_and_set_bit(HFC_CFG_NONCAP_TX, 4992 &hc->chan[i + 2].cfg); 4993 } 4994 /* disable E-channel */ 4995 if (port[Port_cnt] & 0x004) { 4996 if (debug & DEBUG_HFCMULTI_INIT) 4997 printk(KERN_DEBUG 4998 "%s: PROTOCOL disable E-channel: " 4999 "card(%d) port(%d)\n", 5000 __func__, HFC_cnt + 1, pt + 1); 5001 test_and_set_bit(HFC_CFG_DIS_ECHANNEL, 5002 &hc->chan[i + 2].cfg); 5003 } 5004 if (hc->ctype == HFC_TYPE_XHFC) { 5005 snprintf(name, MISDN_MAX_IDLEN - 1, "xhfc.%d-%d", 5006 HFC_cnt + 1, pt + 1); 5007 ret = mISDN_register_device(&dch->dev, NULL, name); 5008 } else { 5009 snprintf(name, MISDN_MAX_IDLEN - 1, "hfc-%ds.%d-%d", 5010 hc->ctype, HFC_cnt + 1, pt + 1); 5011 ret = mISDN_register_device(&dch->dev, &hc->pci_dev->dev, name); 5012 } 5013 if (ret) 5014 goto free_chan; 5015 hc->created[pt] = 1; 5016 return ret; 5017 free_chan: 5018 release_port(hc, dch); 5019 return ret; 5020 } 5021 5022 static int 5023 hfcmulti_init(struct hm_map *m, struct pci_dev *pdev, 5024 const struct pci_device_id *ent) 5025 { 5026 int ret_err = 0; 5027 int pt; 5028 struct hfc_multi *hc; 5029 u_long flags; 5030 u_char dips = 0, pmj = 0; /* dip settings, port mode Jumpers */ 5031 int i, ch; 5032 u_int maskcheck; 5033 5034 if (HFC_cnt >= MAX_CARDS) { 5035 printk(KERN_ERR "too many cards (max=%d).\n", 5036 MAX_CARDS); 5037 return -EINVAL; 5038 } 5039 if ((type[HFC_cnt] & 0xff) && (type[HFC_cnt] & 0xff) != m->type) { 5040 printk(KERN_WARNING "HFC-MULTI: Card '%s:%s' type %d found but " 5041 "type[%d] %d was supplied as module parameter\n", 5042 m->vendor_name, m->card_name, m->type, HFC_cnt, 5043 type[HFC_cnt] & 0xff); 5044 printk(KERN_WARNING "HFC-MULTI: Load module without parameters " 5045 "first, to see cards and their types."); 5046 return -EINVAL; 5047 } 5048 if (debug & DEBUG_HFCMULTI_INIT) 5049 printk(KERN_DEBUG "%s: Registering %s:%s chip type %d (0x%x)\n", 5050 __func__, m->vendor_name, m->card_name, m->type, 5051 type[HFC_cnt]); 5052 5053 /* allocate card+fifo structure */ 5054 hc = kzalloc(sizeof(struct hfc_multi), GFP_KERNEL); 5055 if (!hc) { 5056 printk(KERN_ERR "No kmem for HFC-Multi card\n"); 5057 return -ENOMEM; 5058 } 5059 spin_lock_init(&hc->lock); 5060 hc->mtyp = m; 5061 hc->ctype = m->type; 5062 hc->ports = m->ports; 5063 hc->id = HFC_cnt; 5064 hc->pcm = pcm[HFC_cnt]; 5065 hc->io_mode = iomode[HFC_cnt]; 5066 if (hc->ctype == HFC_TYPE_E1 && dmask[E1_cnt]) { 5067 /* fragment card */ 5068 pt = 0; 5069 maskcheck = 0; 5070 for (ch = 0; ch <= 31; ch++) { 5071 if (!((1 << ch) & dmask[E1_cnt])) 5072 continue; 5073 hc->dnum[pt] = ch; 5074 hc->bmask[pt] = bmask[bmask_cnt++]; 5075 if ((maskcheck & hc->bmask[pt]) 5076 || (dmask[E1_cnt] & hc->bmask[pt])) { 5077 printk(KERN_INFO 5078 "HFC-E1 #%d has overlapping B-channels on fragment #%d\n", 5079 E1_cnt + 1, pt); 5080 return -EINVAL; 5081 } 5082 maskcheck |= hc->bmask[pt]; 5083 printk(KERN_INFO 5084 "HFC-E1 #%d uses D-channel on slot %d and a B-channel map of 0x%08x\n", 5085 E1_cnt + 1, ch, hc->bmask[pt]); 5086 pt++; 5087 } 5088 hc->ports = pt; 5089 } 5090 if (hc->ctype == HFC_TYPE_E1 && !dmask[E1_cnt]) { 5091 /* default card layout */ 5092 hc->dnum[0] = 16; 5093 hc->bmask[0] = 0xfffefffe; 5094 hc->ports = 1; 5095 } 5096 5097 /* set chip specific features */ 5098 hc->masterclk = -1; 5099 if (type[HFC_cnt] & 0x100) { 5100 test_and_set_bit(HFC_CHIP_ULAW, &hc->chip); 5101 hc->silence = 0xff; /* ulaw silence */ 5102 } else 5103 hc->silence = 0x2a; /* alaw silence */ 5104 if ((poll >> 1) > sizeof(hc->silence_data)) { 5105 printk(KERN_ERR "HFCMULTI error: silence_data too small, " 5106 "please fix\n"); 5107 return -EINVAL; 5108 } 5109 for (i = 0; i < (poll >> 1); i++) 5110 hc->silence_data[i] = hc->silence; 5111 5112 if (hc->ctype != HFC_TYPE_XHFC) { 5113 if (!(type[HFC_cnt] & 0x200)) 5114 test_and_set_bit(HFC_CHIP_DTMF, &hc->chip); 5115 test_and_set_bit(HFC_CHIP_CONF, &hc->chip); 5116 } 5117 5118 if (type[HFC_cnt] & 0x800) 5119 test_and_set_bit(HFC_CHIP_PCM_SLAVE, &hc->chip); 5120 if (type[HFC_cnt] & 0x1000) { 5121 test_and_set_bit(HFC_CHIP_PCM_MASTER, &hc->chip); 5122 test_and_clear_bit(HFC_CHIP_PCM_SLAVE, &hc->chip); 5123 } 5124 if (type[HFC_cnt] & 0x4000) 5125 test_and_set_bit(HFC_CHIP_EXRAM_128, &hc->chip); 5126 if (type[HFC_cnt] & 0x8000) 5127 test_and_set_bit(HFC_CHIP_EXRAM_512, &hc->chip); 5128 hc->slots = 32; 5129 if (type[HFC_cnt] & 0x10000) 5130 hc->slots = 64; 5131 if (type[HFC_cnt] & 0x20000) 5132 hc->slots = 128; 5133 if (type[HFC_cnt] & 0x80000) { 5134 test_and_set_bit(HFC_CHIP_WATCHDOG, &hc->chip); 5135 hc->wdcount = 0; 5136 hc->wdbyte = V_GPIO_OUT2; 5137 printk(KERN_NOTICE "Watchdog enabled\n"); 5138 } 5139 5140 if (pdev && ent) 5141 /* setup pci, hc->slots may change due to PLXSD */ 5142 ret_err = setup_pci(hc, pdev, ent); 5143 else 5144 #ifdef CONFIG_MISDN_HFCMULTI_8xx 5145 ret_err = setup_embedded(hc, m); 5146 #else 5147 { 5148 printk(KERN_WARNING "Embedded IO Mode not selected\n"); 5149 ret_err = -EIO; 5150 } 5151 #endif 5152 if (ret_err) { 5153 if (hc == syncmaster) 5154 syncmaster = NULL; 5155 kfree(hc); 5156 return ret_err; 5157 } 5158 5159 hc->HFC_outb_nodebug = hc->HFC_outb; 5160 hc->HFC_inb_nodebug = hc->HFC_inb; 5161 hc->HFC_inw_nodebug = hc->HFC_inw; 5162 hc->HFC_wait_nodebug = hc->HFC_wait; 5163 #ifdef HFC_REGISTER_DEBUG 5164 hc->HFC_outb = HFC_outb_debug; 5165 hc->HFC_inb = HFC_inb_debug; 5166 hc->HFC_inw = HFC_inw_debug; 5167 hc->HFC_wait = HFC_wait_debug; 5168 #endif 5169 /* create channels */ 5170 for (pt = 0; pt < hc->ports; pt++) { 5171 if (Port_cnt >= MAX_PORTS) { 5172 printk(KERN_ERR "too many ports (max=%d).\n", 5173 MAX_PORTS); 5174 ret_err = -EINVAL; 5175 goto free_card; 5176 } 5177 if (hc->ctype == HFC_TYPE_E1) 5178 ret_err = init_e1_port(hc, m, pt); 5179 else 5180 ret_err = init_multi_port(hc, pt); 5181 if (debug & DEBUG_HFCMULTI_INIT) 5182 printk(KERN_DEBUG 5183 "%s: Registering D-channel, card(%d) port(%d) " 5184 "result %d\n", 5185 __func__, HFC_cnt + 1, pt + 1, ret_err); 5186 5187 if (ret_err) { 5188 while (pt) { /* release already registered ports */ 5189 pt--; 5190 if (hc->ctype == HFC_TYPE_E1) 5191 release_port(hc, 5192 hc->chan[hc->dnum[pt]].dch); 5193 else 5194 release_port(hc, 5195 hc->chan[(pt << 2) + 2].dch); 5196 } 5197 goto free_card; 5198 } 5199 if (hc->ctype != HFC_TYPE_E1) 5200 Port_cnt++; /* for each S0 port */ 5201 } 5202 if (hc->ctype == HFC_TYPE_E1) { 5203 Port_cnt++; /* for each E1 port */ 5204 E1_cnt++; 5205 } 5206 5207 /* disp switches */ 5208 switch (m->dip_type) { 5209 case DIP_4S: 5210 /* 5211 * Get DIP setting for beroNet 1S/2S/4S cards 5212 * DIP Setting: (collect GPIO 13/14/15 (R_GPIO_IN1) + 5213 * GPI 19/23 (R_GPI_IN2)) 5214 */ 5215 dips = ((~HFC_inb(hc, R_GPIO_IN1) & 0xE0) >> 5) | 5216 ((~HFC_inb(hc, R_GPI_IN2) & 0x80) >> 3) | 5217 (~HFC_inb(hc, R_GPI_IN2) & 0x08); 5218 5219 /* Port mode (TE/NT) jumpers */ 5220 pmj = ((HFC_inb(hc, R_GPI_IN3) >> 4) & 0xf); 5221 5222 if (test_bit(HFC_CHIP_B410P, &hc->chip)) 5223 pmj = ~pmj & 0xf; 5224 5225 printk(KERN_INFO "%s: %s DIPs(0x%x) jumpers(0x%x)\n", 5226 m->vendor_name, m->card_name, dips, pmj); 5227 break; 5228 case DIP_8S: 5229 /* 5230 * Get DIP Setting for beroNet 8S0+ cards 5231 * Enable PCI auxbridge function 5232 */ 5233 HFC_outb(hc, R_BRG_PCM_CFG, 1 | V_PCM_CLK); 5234 /* prepare access to auxport */ 5235 outw(0x4000, hc->pci_iobase + 4); 5236 /* 5237 * some dummy reads are required to 5238 * read valid DIP switch data 5239 */ 5240 dips = inb(hc->pci_iobase); 5241 dips = inb(hc->pci_iobase); 5242 dips = inb(hc->pci_iobase); 5243 dips = ~inb(hc->pci_iobase) & 0x3F; 5244 outw(0x0, hc->pci_iobase + 4); 5245 /* disable PCI auxbridge function */ 5246 HFC_outb(hc, R_BRG_PCM_CFG, V_PCM_CLK); 5247 printk(KERN_INFO "%s: %s DIPs(0x%x)\n", 5248 m->vendor_name, m->card_name, dips); 5249 break; 5250 case DIP_E1: 5251 /* 5252 * get DIP Setting for beroNet E1 cards 5253 * DIP Setting: collect GPI 4/5/6/7 (R_GPI_IN0) 5254 */ 5255 dips = (~HFC_inb(hc, R_GPI_IN0) & 0xF0) >> 4; 5256 printk(KERN_INFO "%s: %s DIPs(0x%x)\n", 5257 m->vendor_name, m->card_name, dips); 5258 break; 5259 } 5260 5261 /* add to list */ 5262 spin_lock_irqsave(&HFClock, flags); 5263 list_add_tail(&hc->list, &HFClist); 5264 spin_unlock_irqrestore(&HFClock, flags); 5265 5266 /* use as clock source */ 5267 if (clock == HFC_cnt + 1) 5268 hc->iclock = mISDN_register_clock("HFCMulti", 0, clockctl, hc); 5269 5270 /* initialize hardware */ 5271 hc->irq = (m->irq) ? : hc->pci_dev->irq; 5272 ret_err = init_card(hc); 5273 if (ret_err) { 5274 printk(KERN_ERR "init card returns %d\n", ret_err); 5275 release_card(hc); 5276 return ret_err; 5277 } 5278 5279 /* start IRQ and return */ 5280 spin_lock_irqsave(&hc->lock, flags); 5281 enable_hwirq(hc); 5282 spin_unlock_irqrestore(&hc->lock, flags); 5283 return 0; 5284 5285 free_card: 5286 release_io_hfcmulti(hc); 5287 if (hc == syncmaster) 5288 syncmaster = NULL; 5289 kfree(hc); 5290 return ret_err; 5291 } 5292 5293 static void __devexit hfc_remove_pci(struct pci_dev *pdev) 5294 { 5295 struct hfc_multi *card = pci_get_drvdata(pdev); 5296 u_long flags; 5297 5298 if (debug) 5299 printk(KERN_INFO "removing hfc_multi card vendor:%x " 5300 "device:%x subvendor:%x subdevice:%x\n", 5301 pdev->vendor, pdev->device, 5302 pdev->subsystem_vendor, pdev->subsystem_device); 5303 5304 if (card) { 5305 spin_lock_irqsave(&HFClock, flags); 5306 release_card(card); 5307 spin_unlock_irqrestore(&HFClock, flags); 5308 } else { 5309 if (debug) 5310 printk(KERN_DEBUG "%s: drvdata already removed\n", 5311 __func__); 5312 } 5313 } 5314 5315 #define VENDOR_CCD "Cologne Chip AG" 5316 #define VENDOR_BN "beroNet GmbH" 5317 #define VENDOR_DIG "Digium Inc." 5318 #define VENDOR_JH "Junghanns.NET GmbH" 5319 #define VENDOR_PRIM "PrimuX" 5320 5321 static const struct hm_map hfcm_map[] = { 5322 /*0*/ {VENDOR_BN, "HFC-1S Card (mini PCI)", 4, 1, 1, 3, 0, DIP_4S, 0, 0}, 5323 /*1*/ {VENDOR_BN, "HFC-2S Card", 4, 2, 1, 3, 0, DIP_4S, 0, 0}, 5324 /*2*/ {VENDOR_BN, "HFC-2S Card (mini PCI)", 4, 2, 1, 3, 0, DIP_4S, 0, 0}, 5325 /*3*/ {VENDOR_BN, "HFC-4S Card", 4, 4, 1, 2, 0, DIP_4S, 0, 0}, 5326 /*4*/ {VENDOR_BN, "HFC-4S Card (mini PCI)", 4, 4, 1, 2, 0, 0, 0, 0}, 5327 /*5*/ {VENDOR_CCD, "HFC-4S Eval (old)", 4, 4, 0, 0, 0, 0, 0, 0}, 5328 /*6*/ {VENDOR_CCD, "HFC-4S IOB4ST", 4, 4, 1, 2, 0, DIP_4S, 0, 0}, 5329 /*7*/ {VENDOR_CCD, "HFC-4S", 4, 4, 1, 2, 0, 0, 0, 0}, 5330 /*8*/ {VENDOR_DIG, "HFC-4S Card", 4, 4, 0, 2, 0, 0, HFC_IO_MODE_REGIO, 0}, 5331 /*9*/ {VENDOR_CCD, "HFC-4S Swyx 4xS0 SX2 QuadBri", 4, 4, 1, 2, 0, 0, 0, 0}, 5332 /*10*/ {VENDOR_JH, "HFC-4S (junghanns 2.0)", 4, 4, 1, 2, 0, 0, 0, 0}, 5333 /*11*/ {VENDOR_PRIM, "HFC-2S Primux Card", 4, 2, 0, 0, 0, 0, 0, 0}, 5334 5335 /*12*/ {VENDOR_BN, "HFC-8S Card", 8, 8, 1, 0, 0, 0, 0, 0}, 5336 /*13*/ {VENDOR_BN, "HFC-8S Card (+)", 8, 8, 1, 8, 0, DIP_8S, 5337 HFC_IO_MODE_REGIO, 0}, 5338 /*14*/ {VENDOR_CCD, "HFC-8S Eval (old)", 8, 8, 0, 0, 0, 0, 0, 0}, 5339 /*15*/ {VENDOR_CCD, "HFC-8S IOB4ST Recording", 8, 8, 1, 0, 0, 0, 0, 0}, 5340 5341 /*16*/ {VENDOR_CCD, "HFC-8S IOB8ST", 8, 8, 1, 0, 0, 0, 0, 0}, 5342 /*17*/ {VENDOR_CCD, "HFC-8S", 8, 8, 1, 0, 0, 0, 0, 0}, 5343 /*18*/ {VENDOR_CCD, "HFC-8S", 8, 8, 1, 0, 0, 0, 0, 0}, 5344 5345 /*19*/ {VENDOR_BN, "HFC-E1 Card", 1, 1, 0, 1, 0, DIP_E1, 0, 0}, 5346 /*20*/ {VENDOR_BN, "HFC-E1 Card (mini PCI)", 1, 1, 0, 1, 0, 0, 0, 0}, 5347 /*21*/ {VENDOR_BN, "HFC-E1+ Card (Dual)", 1, 1, 0, 1, 0, DIP_E1, 0, 0}, 5348 /*22*/ {VENDOR_BN, "HFC-E1 Card (Dual)", 1, 1, 0, 1, 0, DIP_E1, 0, 0}, 5349 5350 /*23*/ {VENDOR_CCD, "HFC-E1 Eval (old)", 1, 1, 0, 0, 0, 0, 0, 0}, 5351 /*24*/ {VENDOR_CCD, "HFC-E1 IOB1E1", 1, 1, 0, 1, 0, 0, 0, 0}, 5352 /*25*/ {VENDOR_CCD, "HFC-E1", 1, 1, 0, 1, 0, 0, 0, 0}, 5353 5354 /*26*/ {VENDOR_CCD, "HFC-4S Speech Design", 4, 4, 0, 0, 0, 0, 5355 HFC_IO_MODE_PLXSD, 0}, 5356 /*27*/ {VENDOR_CCD, "HFC-E1 Speech Design", 1, 1, 0, 0, 0, 0, 5357 HFC_IO_MODE_PLXSD, 0}, 5358 /*28*/ {VENDOR_CCD, "HFC-4S OpenVox", 4, 4, 1, 0, 0, 0, 0, 0}, 5359 /*29*/ {VENDOR_CCD, "HFC-2S OpenVox", 4, 2, 1, 0, 0, 0, 0, 0}, 5360 /*30*/ {VENDOR_CCD, "HFC-8S OpenVox", 8, 8, 1, 0, 0, 0, 0, 0}, 5361 /*31*/ {VENDOR_CCD, "XHFC-4S Speech Design", 5, 4, 0, 0, 0, 0, 5362 HFC_IO_MODE_EMBSD, XHFC_IRQ}, 5363 /*32*/ {VENDOR_JH, "HFC-8S (junghanns)", 8, 8, 1, 0, 0, 0, 0, 0}, 5364 /*33*/ {VENDOR_BN, "HFC-2S Beronet Card PCIe", 4, 2, 1, 3, 0, DIP_4S, 0, 0}, 5365 /*34*/ {VENDOR_BN, "HFC-4S Beronet Card PCIe", 4, 4, 1, 2, 0, DIP_4S, 0, 0}, 5366 }; 5367 5368 #undef H 5369 #define H(x) ((unsigned long)&hfcm_map[x]) 5370 static struct pci_device_id hfmultipci_ids[] __devinitdata = { 5371 5372 /* Cards with HFC-4S Chip */ 5373 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD, 5374 PCI_SUBDEVICE_ID_CCD_BN1SM, 0, 0, H(0)}, /* BN1S mini PCI */ 5375 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD, 5376 PCI_SUBDEVICE_ID_CCD_BN2S, 0, 0, H(1)}, /* BN2S */ 5377 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD, 5378 PCI_SUBDEVICE_ID_CCD_BN2SM, 0, 0, H(2)}, /* BN2S mini PCI */ 5379 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD, 5380 PCI_SUBDEVICE_ID_CCD_BN4S, 0, 0, H(3)}, /* BN4S */ 5381 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD, 5382 PCI_SUBDEVICE_ID_CCD_BN4SM, 0, 0, H(4)}, /* BN4S mini PCI */ 5383 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD, 5384 PCI_DEVICE_ID_CCD_HFC4S, 0, 0, H(5)}, /* Old Eval */ 5385 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD, 5386 PCI_SUBDEVICE_ID_CCD_IOB4ST, 0, 0, H(6)}, /* IOB4ST */ 5387 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD, 5388 PCI_SUBDEVICE_ID_CCD_HFC4S, 0, 0, H(7)}, /* 4S */ 5389 { PCI_VENDOR_ID_DIGIUM, PCI_DEVICE_ID_DIGIUM_HFC4S, 5390 PCI_VENDOR_ID_DIGIUM, PCI_DEVICE_ID_DIGIUM_HFC4S, 0, 0, H(8)}, 5391 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD, 5392 PCI_SUBDEVICE_ID_CCD_SWYX4S, 0, 0, H(9)}, /* 4S Swyx */ 5393 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD, 5394 PCI_SUBDEVICE_ID_CCD_JH4S20, 0, 0, H(10)}, 5395 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD, 5396 PCI_SUBDEVICE_ID_CCD_PMX2S, 0, 0, H(11)}, /* Primux */ 5397 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD, 5398 PCI_SUBDEVICE_ID_CCD_OV4S, 0, 0, H(28)}, /* OpenVox 4 */ 5399 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD, 5400 PCI_SUBDEVICE_ID_CCD_OV2S, 0, 0, H(29)}, /* OpenVox 2 */ 5401 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD, 5402 0xb761, 0, 0, H(33)}, /* BN2S PCIe */ 5403 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD, 5404 0xb762, 0, 0, H(34)}, /* BN4S PCIe */ 5405 5406 /* Cards with HFC-8S Chip */ 5407 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD, 5408 PCI_SUBDEVICE_ID_CCD_BN8S, 0, 0, H(12)}, /* BN8S */ 5409 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD, 5410 PCI_SUBDEVICE_ID_CCD_BN8SP, 0, 0, H(13)}, /* BN8S+ */ 5411 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD, 5412 PCI_DEVICE_ID_CCD_HFC8S, 0, 0, H(14)}, /* old Eval */ 5413 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD, 5414 PCI_SUBDEVICE_ID_CCD_IOB8STR, 0, 0, H(15)}, /* IOB8ST Recording */ 5415 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD, 5416 PCI_SUBDEVICE_ID_CCD_IOB8ST, 0, 0, H(16)}, /* IOB8ST */ 5417 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD, 5418 PCI_SUBDEVICE_ID_CCD_IOB8ST_1, 0, 0, H(17)}, /* IOB8ST */ 5419 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD, 5420 PCI_SUBDEVICE_ID_CCD_HFC8S, 0, 0, H(18)}, /* 8S */ 5421 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD, 5422 PCI_SUBDEVICE_ID_CCD_OV8S, 0, 0, H(30)}, /* OpenVox 8 */ 5423 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD, 5424 PCI_SUBDEVICE_ID_CCD_JH8S, 0, 0, H(32)}, /* Junganns 8S */ 5425 5426 5427 /* Cards with HFC-E1 Chip */ 5428 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD, 5429 PCI_SUBDEVICE_ID_CCD_BNE1, 0, 0, H(19)}, /* BNE1 */ 5430 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD, 5431 PCI_SUBDEVICE_ID_CCD_BNE1M, 0, 0, H(20)}, /* BNE1 mini PCI */ 5432 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD, 5433 PCI_SUBDEVICE_ID_CCD_BNE1DP, 0, 0, H(21)}, /* BNE1 + (Dual) */ 5434 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD, 5435 PCI_SUBDEVICE_ID_CCD_BNE1D, 0, 0, H(22)}, /* BNE1 (Dual) */ 5436 5437 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD, 5438 PCI_DEVICE_ID_CCD_HFCE1, 0, 0, H(23)}, /* Old Eval */ 5439 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD, 5440 PCI_SUBDEVICE_ID_CCD_IOB1E1, 0, 0, H(24)}, /* IOB1E1 */ 5441 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD, 5442 PCI_SUBDEVICE_ID_CCD_HFCE1, 0, 0, H(25)}, /* E1 */ 5443 5444 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, PCI_VENDOR_ID_CCD, 5445 PCI_SUBDEVICE_ID_CCD_SPD4S, 0, 0, H(26)}, /* PLX PCI Bridge */ 5446 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, PCI_VENDOR_ID_CCD, 5447 PCI_SUBDEVICE_ID_CCD_SPDE1, 0, 0, H(27)}, /* PLX PCI Bridge */ 5448 5449 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD, 5450 PCI_SUBDEVICE_ID_CCD_JHSE1, 0, 0, H(25)}, /* Junghanns E1 */ 5451 5452 { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_HFC4S), 0 }, 5453 { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_HFC8S), 0 }, 5454 { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_HFCE1), 0 }, 5455 {0, } 5456 }; 5457 #undef H 5458 5459 MODULE_DEVICE_TABLE(pci, hfmultipci_ids); 5460 5461 static int 5462 hfcmulti_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 5463 { 5464 struct hm_map *m = (struct hm_map *)ent->driver_data; 5465 int ret; 5466 5467 if (m == NULL && ent->vendor == PCI_VENDOR_ID_CCD && ( 5468 ent->device == PCI_DEVICE_ID_CCD_HFC4S || 5469 ent->device == PCI_DEVICE_ID_CCD_HFC8S || 5470 ent->device == PCI_DEVICE_ID_CCD_HFCE1)) { 5471 printk(KERN_ERR 5472 "Unknown HFC multiport controller (vendor:%04x device:%04x " 5473 "subvendor:%04x subdevice:%04x)\n", pdev->vendor, 5474 pdev->device, pdev->subsystem_vendor, 5475 pdev->subsystem_device); 5476 printk(KERN_ERR 5477 "Please contact the driver maintainer for support.\n"); 5478 return -ENODEV; 5479 } 5480 ret = hfcmulti_init(m, pdev, ent); 5481 if (ret) 5482 return ret; 5483 HFC_cnt++; 5484 printk(KERN_INFO "%d devices registered\n", HFC_cnt); 5485 return 0; 5486 } 5487 5488 static struct pci_driver hfcmultipci_driver = { 5489 .name = "hfc_multi", 5490 .probe = hfcmulti_probe, 5491 .remove = __devexit_p(hfc_remove_pci), 5492 .id_table = hfmultipci_ids, 5493 }; 5494 5495 static void __exit 5496 HFCmulti_cleanup(void) 5497 { 5498 struct hfc_multi *card, *next; 5499 5500 /* get rid of all devices of this driver */ 5501 list_for_each_entry_safe(card, next, &HFClist, list) 5502 release_card(card); 5503 pci_unregister_driver(&hfcmultipci_driver); 5504 } 5505 5506 static int __init 5507 HFCmulti_init(void) 5508 { 5509 int err; 5510 int i, xhfc = 0; 5511 struct hm_map m; 5512 5513 printk(KERN_INFO "mISDN: HFC-multi driver %s\n", HFC_MULTI_VERSION); 5514 5515 #ifdef IRQ_DEBUG 5516 printk(KERN_DEBUG "%s: IRQ_DEBUG IS ENABLED!\n", __func__); 5517 #endif 5518 5519 spin_lock_init(&HFClock); 5520 spin_lock_init(&plx_lock); 5521 5522 if (debug & DEBUG_HFCMULTI_INIT) 5523 printk(KERN_DEBUG "%s: init entered\n", __func__); 5524 5525 switch (poll) { 5526 case 0: 5527 poll_timer = 6; 5528 poll = 128; 5529 break; 5530 case 8: 5531 poll_timer = 2; 5532 break; 5533 case 16: 5534 poll_timer = 3; 5535 break; 5536 case 32: 5537 poll_timer = 4; 5538 break; 5539 case 64: 5540 poll_timer = 5; 5541 break; 5542 case 128: 5543 poll_timer = 6; 5544 break; 5545 case 256: 5546 poll_timer = 7; 5547 break; 5548 default: 5549 printk(KERN_ERR 5550 "%s: Wrong poll value (%d).\n", __func__, poll); 5551 err = -EINVAL; 5552 return err; 5553 5554 } 5555 5556 if (!clock) 5557 clock = 1; 5558 5559 /* Register the embedded devices. 5560 * This should be done before the PCI cards registration */ 5561 switch (hwid) { 5562 case HWID_MINIP4: 5563 xhfc = 1; 5564 m = hfcm_map[31]; 5565 break; 5566 case HWID_MINIP8: 5567 xhfc = 2; 5568 m = hfcm_map[31]; 5569 break; 5570 case HWID_MINIP16: 5571 xhfc = 4; 5572 m = hfcm_map[31]; 5573 break; 5574 default: 5575 xhfc = 0; 5576 } 5577 5578 for (i = 0; i < xhfc; ++i) { 5579 err = hfcmulti_init(&m, NULL, NULL); 5580 if (err) { 5581 printk(KERN_ERR "error registering embedded driver: " 5582 "%x\n", err); 5583 return err; 5584 } 5585 HFC_cnt++; 5586 printk(KERN_INFO "%d devices registered\n", HFC_cnt); 5587 } 5588 5589 /* Register the PCI cards */ 5590 err = pci_register_driver(&hfcmultipci_driver); 5591 if (err < 0) { 5592 printk(KERN_ERR "error registering pci driver: %x\n", err); 5593 return err; 5594 } 5595 5596 return 0; 5597 } 5598 5599 5600 module_init(HFCmulti_init); 5601 module_exit(HFCmulti_cleanup); 5602