1 /*
2  * avm_fritz.c    low level stuff for AVM FRITZ!CARD PCI ISDN cards
3  *                Thanks to AVM, Berlin for informations
4  *
5  * Author       Karsten Keil <keil@isdn4linux.de>
6  *
7  * Copyright 2009  by Karsten Keil <keil@isdn4linux.de>
8  *
9  * This program is free software; you can redistribute it and/or modify
10  * it under the terms of the GNU General Public License version 2 as
11  * published by the Free Software Foundation.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  * You should have received a copy of the GNU General Public License
19  * along with this program; if not, write to the Free Software
20  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21  *
22  */
23 #include <linux/interrupt.h>
24 #include <linux/module.h>
25 #include <linux/pci.h>
26 #include <linux/delay.h>
27 #include <linux/mISDNhw.h>
28 #include <linux/slab.h>
29 #include <asm/unaligned.h>
30 #include "ipac.h"
31 
32 
33 #define AVMFRITZ_REV	"2.3"
34 
35 static int AVM_cnt;
36 static int debug;
37 
38 enum {
39 	AVM_FRITZ_PCI,
40 	AVM_FRITZ_PCIV2,
41 };
42 
43 #define HDLC_FIFO		0x0
44 #define HDLC_STATUS		0x4
45 #define CHIP_WINDOW		0x10
46 
47 #define CHIP_INDEX		0x4
48 #define AVM_HDLC_1		0x00
49 #define AVM_HDLC_2		0x01
50 #define AVM_ISAC_FIFO		0x02
51 #define AVM_ISAC_REG_LOW	0x04
52 #define AVM_ISAC_REG_HIGH	0x06
53 
54 #define AVM_STATUS0_IRQ_ISAC	0x01
55 #define AVM_STATUS0_IRQ_HDLC	0x02
56 #define AVM_STATUS0_IRQ_TIMER	0x04
57 #define AVM_STATUS0_IRQ_MASK	0x07
58 
59 #define AVM_STATUS0_RESET	0x01
60 #define AVM_STATUS0_DIS_TIMER	0x02
61 #define AVM_STATUS0_RES_TIMER	0x04
62 #define AVM_STATUS0_ENA_IRQ	0x08
63 #define AVM_STATUS0_TESTBIT	0x10
64 
65 #define AVM_STATUS1_INT_SEL	0x0f
66 #define AVM_STATUS1_ENA_IOM	0x80
67 
68 #define HDLC_MODE_ITF_FLG	0x01
69 #define HDLC_MODE_TRANS		0x02
70 #define HDLC_MODE_CCR_7		0x04
71 #define HDLC_MODE_CCR_16	0x08
72 #define HDLC_FIFO_SIZE_128	0x20
73 #define HDLC_MODE_TESTLOOP	0x80
74 
75 #define HDLC_INT_XPR		0x80
76 #define HDLC_INT_XDU		0x40
77 #define HDLC_INT_RPR		0x20
78 #define HDLC_INT_MASK		0xE0
79 
80 #define HDLC_STAT_RME		0x01
81 #define HDLC_STAT_RDO		0x10
82 #define HDLC_STAT_CRCVFRRAB	0x0E
83 #define HDLC_STAT_CRCVFR	0x06
84 #define HDLC_STAT_RML_MASK_V1	0x3f00
85 #define HDLC_STAT_RML_MASK_V2	0x7f00
86 
87 #define HDLC_CMD_XRS		0x80
88 #define HDLC_CMD_XME		0x01
89 #define HDLC_CMD_RRS		0x20
90 #define HDLC_CMD_XML_MASK	0x3f00
91 
92 #define HDLC_FIFO_SIZE_V1	32
93 #define HDLC_FIFO_SIZE_V2	128
94 
95 /* Fritz PCI v2.0 */
96 
97 #define AVM_HDLC_FIFO_1		0x10
98 #define AVM_HDLC_FIFO_2		0x18
99 
100 #define AVM_HDLC_STATUS_1	0x14
101 #define AVM_HDLC_STATUS_2	0x1c
102 
103 #define AVM_ISACX_INDEX		0x04
104 #define AVM_ISACX_DATA		0x08
105 
106 /* data struct */
107 #define LOG_SIZE		63
108 
109 struct hdlc_stat_reg {
110 #ifdef __BIG_ENDIAN
111 	u8 fill;
112 	u8 mode;
113 	u8 xml;
114 	u8 cmd;
115 #else
116 	u8 cmd;
117 	u8 xml;
118 	u8 mode;
119 	u8 fill;
120 #endif
121 } __attribute__((packed));
122 
123 struct hdlc_hw {
124 	union {
125 		u32 ctrl;
126 		struct hdlc_stat_reg sr;
127 	} ctrl;
128 	u32 stat;
129 };
130 
131 struct fritzcard {
132 	struct list_head	list;
133 	struct pci_dev		*pdev;
134 	char			name[MISDN_MAX_IDLEN];
135 	u8			type;
136 	u8			ctrlreg;
137 	u16			irq;
138 	u32			irqcnt;
139 	u32			addr;
140 	spinlock_t		lock; /* hw lock */
141 	struct isac_hw		isac;
142 	struct hdlc_hw		hdlc[2];
143 	struct bchannel		bch[2];
144 	char			log[LOG_SIZE + 1];
145 };
146 
147 static LIST_HEAD(Cards);
148 static DEFINE_RWLOCK(card_lock); /* protect Cards */
149 
150 static void
151 _set_debug(struct fritzcard *card)
152 {
153 	card->isac.dch.debug = debug;
154 	card->bch[0].debug = debug;
155 	card->bch[1].debug = debug;
156 }
157 
158 static int
159 set_debug(const char *val, const struct kernel_param *kp)
160 {
161 	int ret;
162 	struct fritzcard *card;
163 
164 	ret = param_set_uint(val, kp);
165 	if (!ret) {
166 		read_lock(&card_lock);
167 		list_for_each_entry(card, &Cards, list)
168 			_set_debug(card);
169 		read_unlock(&card_lock);
170 	}
171 	return ret;
172 }
173 
174 MODULE_AUTHOR("Karsten Keil");
175 MODULE_LICENSE("GPL v2");
176 MODULE_VERSION(AVMFRITZ_REV);
177 module_param_call(debug, set_debug, param_get_uint, &debug, S_IRUGO | S_IWUSR);
178 MODULE_PARM_DESC(debug, "avmfritz debug mask");
179 
180 /* Interface functions */
181 
182 static u8
183 ReadISAC_V1(void *p, u8 offset)
184 {
185 	struct fritzcard *fc = p;
186 	u8 idx = (offset > 0x2f) ? AVM_ISAC_REG_HIGH : AVM_ISAC_REG_LOW;
187 
188 	outb(idx, fc->addr + CHIP_INDEX);
189 	return inb(fc->addr + CHIP_WINDOW + (offset & 0xf));
190 }
191 
192 static void
193 WriteISAC_V1(void *p, u8 offset, u8 value)
194 {
195 	struct fritzcard *fc = p;
196 	u8 idx = (offset > 0x2f) ? AVM_ISAC_REG_HIGH : AVM_ISAC_REG_LOW;
197 
198 	outb(idx, fc->addr + CHIP_INDEX);
199 	outb(value, fc->addr + CHIP_WINDOW + (offset & 0xf));
200 }
201 
202 static void
203 ReadFiFoISAC_V1(void *p, u8 off, u8 *data, int size)
204 {
205 	struct fritzcard *fc = p;
206 
207 	outb(AVM_ISAC_FIFO, fc->addr + CHIP_INDEX);
208 	insb(fc->addr + CHIP_WINDOW, data, size);
209 }
210 
211 static void
212 WriteFiFoISAC_V1(void *p, u8 off, u8 *data, int size)
213 {
214 	struct fritzcard *fc = p;
215 
216 	outb(AVM_ISAC_FIFO, fc->addr + CHIP_INDEX);
217 	outsb(fc->addr + CHIP_WINDOW, data, size);
218 }
219 
220 static u8
221 ReadISAC_V2(void *p, u8 offset)
222 {
223 	struct fritzcard *fc = p;
224 
225 	outl(offset, fc->addr + AVM_ISACX_INDEX);
226 	return 0xff & inl(fc->addr + AVM_ISACX_DATA);
227 }
228 
229 static void
230 WriteISAC_V2(void *p, u8 offset, u8 value)
231 {
232 	struct fritzcard *fc = p;
233 
234 	outl(offset, fc->addr + AVM_ISACX_INDEX);
235 	outl(value, fc->addr + AVM_ISACX_DATA);
236 }
237 
238 static void
239 ReadFiFoISAC_V2(void *p, u8 off, u8 *data, int size)
240 {
241 	struct fritzcard *fc = p;
242 	int i;
243 
244 	outl(off, fc->addr + AVM_ISACX_INDEX);
245 	for (i = 0; i < size; i++)
246 		data[i] = 0xff & inl(fc->addr + AVM_ISACX_DATA);
247 }
248 
249 static void
250 WriteFiFoISAC_V2(void *p, u8 off, u8 *data, int size)
251 {
252 	struct fritzcard *fc = p;
253 	int i;
254 
255 	outl(off, fc->addr + AVM_ISACX_INDEX);
256 	for (i = 0; i < size; i++)
257 		outl(data[i], fc->addr + AVM_ISACX_DATA);
258 }
259 
260 static struct bchannel *
261 Sel_BCS(struct fritzcard *fc, u32 channel)
262 {
263 	if (test_bit(FLG_ACTIVE, &fc->bch[0].Flags) &&
264 	    (fc->bch[0].nr & channel))
265 		return &fc->bch[0];
266 	else if (test_bit(FLG_ACTIVE, &fc->bch[1].Flags) &&
267 		 (fc->bch[1].nr & channel))
268 		return &fc->bch[1];
269 	else
270 		return NULL;
271 }
272 
273 static inline void
274 __write_ctrl_pci(struct fritzcard *fc, struct hdlc_hw *hdlc, u32 channel) {
275 	u32 idx = channel == 2 ? AVM_HDLC_2 : AVM_HDLC_1;
276 
277 	outl(idx, fc->addr + CHIP_INDEX);
278 	outl(hdlc->ctrl.ctrl, fc->addr + CHIP_WINDOW + HDLC_STATUS);
279 }
280 
281 static inline void
282 __write_ctrl_pciv2(struct fritzcard *fc, struct hdlc_hw *hdlc, u32 channel) {
283 	outl(hdlc->ctrl.ctrl, fc->addr + (channel == 2 ? AVM_HDLC_STATUS_2 :
284 					  AVM_HDLC_STATUS_1));
285 }
286 
287 static void
288 write_ctrl(struct bchannel *bch, int which) {
289 	struct fritzcard *fc = bch->hw;
290 	struct hdlc_hw *hdlc;
291 
292 	hdlc = &fc->hdlc[(bch->nr - 1) & 1];
293 	pr_debug("%s: hdlc %c wr%x ctrl %x\n", fc->name, '@' + bch->nr,
294 		 which, hdlc->ctrl.ctrl);
295 	switch (fc->type) {
296 	case AVM_FRITZ_PCIV2:
297 		__write_ctrl_pciv2(fc, hdlc, bch->nr);
298 		break;
299 	case AVM_FRITZ_PCI:
300 		__write_ctrl_pci(fc, hdlc, bch->nr);
301 		break;
302 	}
303 }
304 
305 
306 static inline u32
307 __read_status_pci(u_long addr, u32 channel)
308 {
309 	outl(channel == 2 ? AVM_HDLC_2 : AVM_HDLC_1, addr + CHIP_INDEX);
310 	return inl(addr + CHIP_WINDOW + HDLC_STATUS);
311 }
312 
313 static inline u32
314 __read_status_pciv2(u_long addr, u32 channel)
315 {
316 	return inl(addr + (channel == 2 ? AVM_HDLC_STATUS_2 :
317 			   AVM_HDLC_STATUS_1));
318 }
319 
320 
321 static u32
322 read_status(struct fritzcard *fc, u32 channel)
323 {
324 	switch (fc->type) {
325 	case AVM_FRITZ_PCIV2:
326 		return __read_status_pciv2(fc->addr, channel);
327 	case AVM_FRITZ_PCI:
328 		return __read_status_pci(fc->addr, channel);
329 	}
330 	/* dummy */
331 	return 0;
332 }
333 
334 static void
335 enable_hwirq(struct fritzcard *fc)
336 {
337 	fc->ctrlreg |= AVM_STATUS0_ENA_IRQ;
338 	outb(fc->ctrlreg, fc->addr + 2);
339 }
340 
341 static void
342 disable_hwirq(struct fritzcard *fc)
343 {
344 	fc->ctrlreg &= ~AVM_STATUS0_ENA_IRQ;
345 	outb(fc->ctrlreg, fc->addr + 2);
346 }
347 
348 static int
349 modehdlc(struct bchannel *bch, int protocol)
350 {
351 	struct fritzcard *fc = bch->hw;
352 	struct hdlc_hw *hdlc;
353 	u8 mode;
354 
355 	hdlc = &fc->hdlc[(bch->nr - 1) & 1];
356 	pr_debug("%s: hdlc %c protocol %x-->%x ch %d\n", fc->name,
357 		 '@' + bch->nr, bch->state, protocol, bch->nr);
358 	hdlc->ctrl.ctrl = 0;
359 	mode = (fc->type == AVM_FRITZ_PCIV2) ? HDLC_FIFO_SIZE_128 : 0;
360 
361 	switch (protocol) {
362 	case -1: /* used for init */
363 		bch->state = -1;
364 		/* fall through */
365 	case ISDN_P_NONE:
366 		if (bch->state == ISDN_P_NONE)
367 			break;
368 		hdlc->ctrl.sr.cmd  = HDLC_CMD_XRS | HDLC_CMD_RRS;
369 		hdlc->ctrl.sr.mode = mode | HDLC_MODE_TRANS;
370 		write_ctrl(bch, 5);
371 		bch->state = ISDN_P_NONE;
372 		test_and_clear_bit(FLG_HDLC, &bch->Flags);
373 		test_and_clear_bit(FLG_TRANSPARENT, &bch->Flags);
374 		break;
375 	case ISDN_P_B_RAW:
376 		bch->state = protocol;
377 		hdlc->ctrl.sr.cmd  = HDLC_CMD_XRS | HDLC_CMD_RRS;
378 		hdlc->ctrl.sr.mode = mode | HDLC_MODE_TRANS;
379 		write_ctrl(bch, 5);
380 		hdlc->ctrl.sr.cmd = HDLC_CMD_XRS;
381 		write_ctrl(bch, 1);
382 		hdlc->ctrl.sr.cmd = 0;
383 		test_and_set_bit(FLG_TRANSPARENT, &bch->Flags);
384 		break;
385 	case ISDN_P_B_HDLC:
386 		bch->state = protocol;
387 		hdlc->ctrl.sr.cmd  = HDLC_CMD_XRS | HDLC_CMD_RRS;
388 		hdlc->ctrl.sr.mode = mode | HDLC_MODE_ITF_FLG;
389 		write_ctrl(bch, 5);
390 		hdlc->ctrl.sr.cmd = HDLC_CMD_XRS;
391 		write_ctrl(bch, 1);
392 		hdlc->ctrl.sr.cmd = 0;
393 		test_and_set_bit(FLG_HDLC, &bch->Flags);
394 		break;
395 	default:
396 		pr_info("%s: protocol not known %x\n", fc->name, protocol);
397 		return -ENOPROTOOPT;
398 	}
399 	return 0;
400 }
401 
402 static void
403 hdlc_empty_fifo(struct bchannel *bch, int count)
404 {
405 	u32 *ptr;
406 	u8 *p;
407 	u32  val, addr;
408 	int cnt;
409 	struct fritzcard *fc = bch->hw;
410 
411 	pr_debug("%s: %s %d\n", fc->name, __func__, count);
412 	if (test_bit(FLG_RX_OFF, &bch->Flags)) {
413 		p = NULL;
414 		bch->dropcnt += count;
415 	} else {
416 		cnt = bchannel_get_rxbuf(bch, count);
417 		if (cnt < 0) {
418 			pr_warning("%s.B%d: No bufferspace for %d bytes\n",
419 				   fc->name, bch->nr, count);
420 			return;
421 		}
422 		p = skb_put(bch->rx_skb, count);
423 	}
424 	ptr = (u32 *)p;
425 	if (fc->type == AVM_FRITZ_PCIV2)
426 		addr = fc->addr + (bch->nr == 2 ?
427 				   AVM_HDLC_FIFO_2 : AVM_HDLC_FIFO_1);
428 	else {
429 		addr = fc->addr + CHIP_WINDOW;
430 		outl(bch->nr == 2 ? AVM_HDLC_2 : AVM_HDLC_1, fc->addr);
431 	}
432 	cnt = 0;
433 	while (cnt < count) {
434 		val = le32_to_cpu(inl(addr));
435 		if (p) {
436 			put_unaligned(val, ptr);
437 			ptr++;
438 		}
439 		cnt += 4;
440 	}
441 	if (p && (debug & DEBUG_HW_BFIFO)) {
442 		snprintf(fc->log, LOG_SIZE, "B%1d-recv %s %d ",
443 			 bch->nr, fc->name, count);
444 		print_hex_dump_bytes(fc->log, DUMP_PREFIX_OFFSET, p, count);
445 	}
446 }
447 
448 static void
449 hdlc_fill_fifo(struct bchannel *bch)
450 {
451 	struct fritzcard *fc = bch->hw;
452 	struct hdlc_hw *hdlc;
453 	int count, fs, cnt = 0, idx;
454 	bool fillempty = false;
455 	u8 *p;
456 	u32 *ptr, val, addr;
457 
458 	idx = (bch->nr - 1) & 1;
459 	hdlc = &fc->hdlc[idx];
460 	fs = (fc->type == AVM_FRITZ_PCIV2) ?
461 		HDLC_FIFO_SIZE_V2 : HDLC_FIFO_SIZE_V1;
462 	if (!bch->tx_skb) {
463 		if (!test_bit(FLG_TX_EMPTY, &bch->Flags))
464 			return;
465 		count = fs;
466 		p = bch->fill;
467 		fillempty = true;
468 	} else {
469 		count = bch->tx_skb->len - bch->tx_idx;
470 		if (count <= 0)
471 			return;
472 		p = bch->tx_skb->data + bch->tx_idx;
473 	}
474 	hdlc->ctrl.sr.cmd &= ~HDLC_CMD_XME;
475 	if (count > fs) {
476 		count = fs;
477 	} else {
478 		if (test_bit(FLG_HDLC, &bch->Flags))
479 			hdlc->ctrl.sr.cmd |= HDLC_CMD_XME;
480 	}
481 	ptr = (u32 *)p;
482 	if (!fillempty) {
483 		pr_debug("%s.B%d: %d/%d/%d", fc->name, bch->nr, count,
484 			 bch->tx_idx, bch->tx_skb->len);
485 		bch->tx_idx += count;
486 	} else {
487 		pr_debug("%s.B%d: fillempty %d\n", fc->name, bch->nr, count);
488 	}
489 	hdlc->ctrl.sr.xml = ((count == fs) ? 0 : count);
490 	if (fc->type == AVM_FRITZ_PCIV2) {
491 		__write_ctrl_pciv2(fc, hdlc, bch->nr);
492 		addr = fc->addr + (bch->nr == 2 ?
493 				   AVM_HDLC_FIFO_2 : AVM_HDLC_FIFO_1);
494 	} else {
495 		__write_ctrl_pci(fc, hdlc, bch->nr);
496 		addr = fc->addr + CHIP_WINDOW;
497 	}
498 	if (fillempty) {
499 		while (cnt < count) {
500 			/* all bytes the same - no worry about endian */
501 			outl(*ptr, addr);
502 			cnt += 4;
503 		}
504 	} else {
505 		while (cnt < count) {
506 			val = get_unaligned(ptr);
507 			outl(cpu_to_le32(val), addr);
508 			ptr++;
509 			cnt += 4;
510 		}
511 	}
512 	if ((debug & DEBUG_HW_BFIFO) && !fillempty) {
513 		snprintf(fc->log, LOG_SIZE, "B%1d-send %s %d ",
514 			 bch->nr, fc->name, count);
515 		print_hex_dump_bytes(fc->log, DUMP_PREFIX_OFFSET, p, count);
516 	}
517 }
518 
519 static void
520 HDLC_irq_xpr(struct bchannel *bch)
521 {
522 	if (bch->tx_skb && bch->tx_idx < bch->tx_skb->len) {
523 		hdlc_fill_fifo(bch);
524 	} else {
525 		if (bch->tx_skb)
526 			dev_kfree_skb(bch->tx_skb);
527 		if (get_next_bframe(bch)) {
528 			hdlc_fill_fifo(bch);
529 			test_and_clear_bit(FLG_TX_EMPTY, &bch->Flags);
530 		} else if (test_bit(FLG_TX_EMPTY, &bch->Flags)) {
531 			hdlc_fill_fifo(bch);
532 		}
533 	}
534 }
535 
536 static void
537 HDLC_irq(struct bchannel *bch, u32 stat)
538 {
539 	struct fritzcard *fc = bch->hw;
540 	int		len, fs;
541 	u32		rmlMask;
542 	struct hdlc_hw	*hdlc;
543 
544 	hdlc = &fc->hdlc[(bch->nr - 1) & 1];
545 	pr_debug("%s: ch%d stat %#x\n", fc->name, bch->nr, stat);
546 	if (fc->type == AVM_FRITZ_PCIV2) {
547 		rmlMask = HDLC_STAT_RML_MASK_V2;
548 		fs = HDLC_FIFO_SIZE_V2;
549 	} else {
550 		rmlMask = HDLC_STAT_RML_MASK_V1;
551 		fs = HDLC_FIFO_SIZE_V1;
552 	}
553 	if (stat & HDLC_INT_RPR) {
554 		if (stat & HDLC_STAT_RDO) {
555 			pr_warning("%s: ch%d stat %x RDO\n",
556 				   fc->name, bch->nr, stat);
557 			hdlc->ctrl.sr.xml = 0;
558 			hdlc->ctrl.sr.cmd |= HDLC_CMD_RRS;
559 			write_ctrl(bch, 1);
560 			hdlc->ctrl.sr.cmd &= ~HDLC_CMD_RRS;
561 			write_ctrl(bch, 1);
562 			if (bch->rx_skb)
563 				skb_trim(bch->rx_skb, 0);
564 		} else {
565 			len = (stat & rmlMask) >> 8;
566 			if (!len)
567 				len = fs;
568 			hdlc_empty_fifo(bch, len);
569 			if (!bch->rx_skb)
570 				goto handle_tx;
571 			if (test_bit(FLG_TRANSPARENT, &bch->Flags)) {
572 				recv_Bchannel(bch, 0, false);
573 			} else if (stat & HDLC_STAT_RME) {
574 				if ((stat & HDLC_STAT_CRCVFRRAB) ==
575 				    HDLC_STAT_CRCVFR) {
576 					recv_Bchannel(bch, 0, false);
577 				} else {
578 					pr_warning("%s: got invalid frame\n",
579 						   fc->name);
580 					skb_trim(bch->rx_skb, 0);
581 				}
582 			}
583 		}
584 	}
585 handle_tx:
586 	if (stat & HDLC_INT_XDU) {
587 		/* Here we lost an TX interrupt, so
588 		 * restart transmitting the whole frame on HDLC
589 		 * in transparent mode we send the next data
590 		 */
591 		pr_warning("%s: ch%d stat %x XDU %s\n", fc->name, bch->nr,
592 			   stat, bch->tx_skb ? "tx_skb" : "no tx_skb");
593 		if (bch->tx_skb && bch->tx_skb->len) {
594 			if (!test_bit(FLG_TRANSPARENT, &bch->Flags))
595 				bch->tx_idx = 0;
596 		} else if (test_bit(FLG_FILLEMPTY, &bch->Flags)) {
597 			test_and_set_bit(FLG_TX_EMPTY, &bch->Flags);
598 		}
599 		hdlc->ctrl.sr.xml = 0;
600 		hdlc->ctrl.sr.cmd |= HDLC_CMD_XRS;
601 		write_ctrl(bch, 1);
602 		hdlc->ctrl.sr.cmd &= ~HDLC_CMD_XRS;
603 		HDLC_irq_xpr(bch);
604 		return;
605 	} else if (stat & HDLC_INT_XPR)
606 		HDLC_irq_xpr(bch);
607 }
608 
609 static inline void
610 HDLC_irq_main(struct fritzcard *fc)
611 {
612 	u32 stat;
613 	struct bchannel *bch;
614 
615 	stat = read_status(fc, 1);
616 	if (stat & HDLC_INT_MASK) {
617 		bch = Sel_BCS(fc, 1);
618 		if (bch)
619 			HDLC_irq(bch, stat);
620 		else
621 			pr_debug("%s: spurious ch1 IRQ\n", fc->name);
622 	}
623 	stat = read_status(fc, 2);
624 	if (stat & HDLC_INT_MASK) {
625 		bch = Sel_BCS(fc, 2);
626 		if (bch)
627 			HDLC_irq(bch, stat);
628 		else
629 			pr_debug("%s: spurious ch2 IRQ\n", fc->name);
630 	}
631 }
632 
633 static irqreturn_t
634 avm_fritz_interrupt(int intno, void *dev_id)
635 {
636 	struct fritzcard *fc = dev_id;
637 	u8 val;
638 	u8 sval;
639 
640 	spin_lock(&fc->lock);
641 	sval = inb(fc->addr + 2);
642 	pr_debug("%s: irq stat0 %x\n", fc->name, sval);
643 	if ((sval & AVM_STATUS0_IRQ_MASK) == AVM_STATUS0_IRQ_MASK) {
644 		/* shared  IRQ from other HW */
645 		spin_unlock(&fc->lock);
646 		return IRQ_NONE;
647 	}
648 	fc->irqcnt++;
649 
650 	if (!(sval & AVM_STATUS0_IRQ_ISAC)) {
651 		val = ReadISAC_V1(fc, ISAC_ISTA);
652 		mISDNisac_irq(&fc->isac, val);
653 	}
654 	if (!(sval & AVM_STATUS0_IRQ_HDLC))
655 		HDLC_irq_main(fc);
656 	spin_unlock(&fc->lock);
657 	return IRQ_HANDLED;
658 }
659 
660 static irqreturn_t
661 avm_fritzv2_interrupt(int intno, void *dev_id)
662 {
663 	struct fritzcard *fc = dev_id;
664 	u8 val;
665 	u8 sval;
666 
667 	spin_lock(&fc->lock);
668 	sval = inb(fc->addr + 2);
669 	pr_debug("%s: irq stat0 %x\n", fc->name, sval);
670 	if (!(sval & AVM_STATUS0_IRQ_MASK)) {
671 		/* shared  IRQ from other HW */
672 		spin_unlock(&fc->lock);
673 		return IRQ_NONE;
674 	}
675 	fc->irqcnt++;
676 
677 	if (sval & AVM_STATUS0_IRQ_HDLC)
678 		HDLC_irq_main(fc);
679 	if (sval & AVM_STATUS0_IRQ_ISAC) {
680 		val = ReadISAC_V2(fc, ISACX_ISTA);
681 		mISDNisac_irq(&fc->isac, val);
682 	}
683 	if (sval & AVM_STATUS0_IRQ_TIMER) {
684 		pr_debug("%s: timer irq\n", fc->name);
685 		outb(fc->ctrlreg | AVM_STATUS0_RES_TIMER, fc->addr + 2);
686 		udelay(1);
687 		outb(fc->ctrlreg, fc->addr + 2);
688 	}
689 	spin_unlock(&fc->lock);
690 	return IRQ_HANDLED;
691 }
692 
693 static int
694 avm_l2l1B(struct mISDNchannel *ch, struct sk_buff *skb)
695 {
696 	struct bchannel *bch = container_of(ch, struct bchannel, ch);
697 	struct fritzcard *fc = bch->hw;
698 	int ret = -EINVAL;
699 	struct mISDNhead *hh = mISDN_HEAD_P(skb);
700 	unsigned long flags;
701 
702 	switch (hh->prim) {
703 	case PH_DATA_REQ:
704 		spin_lock_irqsave(&fc->lock, flags);
705 		ret = bchannel_senddata(bch, skb);
706 		if (ret > 0) { /* direct TX */
707 			hdlc_fill_fifo(bch);
708 			ret = 0;
709 		}
710 		spin_unlock_irqrestore(&fc->lock, flags);
711 		return ret;
712 	case PH_ACTIVATE_REQ:
713 		spin_lock_irqsave(&fc->lock, flags);
714 		if (!test_and_set_bit(FLG_ACTIVE, &bch->Flags))
715 			ret = modehdlc(bch, ch->protocol);
716 		else
717 			ret = 0;
718 		spin_unlock_irqrestore(&fc->lock, flags);
719 		if (!ret)
720 			_queue_data(ch, PH_ACTIVATE_IND, MISDN_ID_ANY, 0,
721 				    NULL, GFP_KERNEL);
722 		break;
723 	case PH_DEACTIVATE_REQ:
724 		spin_lock_irqsave(&fc->lock, flags);
725 		mISDN_clear_bchannel(bch);
726 		modehdlc(bch, ISDN_P_NONE);
727 		spin_unlock_irqrestore(&fc->lock, flags);
728 		_queue_data(ch, PH_DEACTIVATE_IND, MISDN_ID_ANY, 0,
729 			    NULL, GFP_KERNEL);
730 		ret = 0;
731 		break;
732 	}
733 	if (!ret)
734 		dev_kfree_skb(skb);
735 	return ret;
736 }
737 
738 static void
739 inithdlc(struct fritzcard *fc)
740 {
741 	modehdlc(&fc->bch[0], -1);
742 	modehdlc(&fc->bch[1], -1);
743 }
744 
745 static void
746 clear_pending_hdlc_ints(struct fritzcard *fc)
747 {
748 	u32 val;
749 
750 	val = read_status(fc, 1);
751 	pr_debug("%s: HDLC 1 STA %x\n", fc->name, val);
752 	val = read_status(fc, 2);
753 	pr_debug("%s: HDLC 2 STA %x\n", fc->name, val);
754 }
755 
756 static void
757 reset_avm(struct fritzcard *fc)
758 {
759 	switch (fc->type) {
760 	case AVM_FRITZ_PCI:
761 		fc->ctrlreg = AVM_STATUS0_RESET | AVM_STATUS0_DIS_TIMER;
762 		break;
763 	case AVM_FRITZ_PCIV2:
764 		fc->ctrlreg = AVM_STATUS0_RESET;
765 		break;
766 	}
767 	if (debug & DEBUG_HW)
768 		pr_notice("%s: reset\n", fc->name);
769 	disable_hwirq(fc);
770 	mdelay(5);
771 	switch (fc->type) {
772 	case AVM_FRITZ_PCI:
773 		fc->ctrlreg = AVM_STATUS0_DIS_TIMER | AVM_STATUS0_RES_TIMER;
774 		disable_hwirq(fc);
775 		outb(AVM_STATUS1_ENA_IOM, fc->addr + 3);
776 		break;
777 	case AVM_FRITZ_PCIV2:
778 		fc->ctrlreg = 0;
779 		disable_hwirq(fc);
780 		break;
781 	}
782 	mdelay(1);
783 	if (debug & DEBUG_HW)
784 		pr_notice("%s: S0/S1 %x/%x\n", fc->name,
785 			  inb(fc->addr + 2), inb(fc->addr + 3));
786 }
787 
788 static int
789 init_card(struct fritzcard *fc)
790 {
791 	int		ret, cnt = 3;
792 	u_long		flags;
793 
794 	reset_avm(fc); /* disable IRQ */
795 	if (fc->type == AVM_FRITZ_PCIV2)
796 		ret = request_irq(fc->irq, avm_fritzv2_interrupt,
797 				  IRQF_SHARED, fc->name, fc);
798 	else
799 		ret = request_irq(fc->irq, avm_fritz_interrupt,
800 				  IRQF_SHARED, fc->name, fc);
801 	if (ret) {
802 		pr_info("%s: couldn't get interrupt %d\n",
803 			fc->name, fc->irq);
804 		return ret;
805 	}
806 	while (cnt--) {
807 		spin_lock_irqsave(&fc->lock, flags);
808 		ret = fc->isac.init(&fc->isac);
809 		if (ret) {
810 			spin_unlock_irqrestore(&fc->lock, flags);
811 			pr_info("%s: ISAC init failed with %d\n",
812 				fc->name, ret);
813 			break;
814 		}
815 		clear_pending_hdlc_ints(fc);
816 		inithdlc(fc);
817 		enable_hwirq(fc);
818 		/* RESET Receiver and Transmitter */
819 		if (fc->type == AVM_FRITZ_PCIV2) {
820 			WriteISAC_V2(fc, ISACX_MASK, 0);
821 			WriteISAC_V2(fc, ISACX_CMDRD, 0x41);
822 		} else {
823 			WriteISAC_V1(fc, ISAC_MASK, 0);
824 			WriteISAC_V1(fc, ISAC_CMDR, 0x41);
825 		}
826 		spin_unlock_irqrestore(&fc->lock, flags);
827 		/* Timeout 10ms */
828 		msleep_interruptible(10);
829 		if (debug & DEBUG_HW)
830 			pr_notice("%s: IRQ %d count %d\n", fc->name,
831 				  fc->irq, fc->irqcnt);
832 		if (!fc->irqcnt) {
833 			pr_info("%s: IRQ(%d) getting no IRQs during init %d\n",
834 				fc->name, fc->irq, 3 - cnt);
835 			reset_avm(fc);
836 		} else
837 			return 0;
838 	}
839 	free_irq(fc->irq, fc);
840 	return -EIO;
841 }
842 
843 static int
844 channel_bctrl(struct bchannel *bch, struct mISDN_ctrl_req *cq)
845 {
846 	return mISDN_ctrl_bchannel(bch, cq);
847 }
848 
849 static int
850 avm_bctrl(struct mISDNchannel *ch, u32 cmd, void *arg)
851 {
852 	struct bchannel *bch = container_of(ch, struct bchannel, ch);
853 	struct fritzcard *fc = bch->hw;
854 	int ret = -EINVAL;
855 	u_long flags;
856 
857 	pr_debug("%s: %s cmd:%x %p\n", fc->name, __func__, cmd, arg);
858 	switch (cmd) {
859 	case CLOSE_CHANNEL:
860 		test_and_clear_bit(FLG_OPEN, &bch->Flags);
861 		cancel_work_sync(&bch->workq);
862 		spin_lock_irqsave(&fc->lock, flags);
863 		mISDN_clear_bchannel(bch);
864 		modehdlc(bch, ISDN_P_NONE);
865 		spin_unlock_irqrestore(&fc->lock, flags);
866 		ch->protocol = ISDN_P_NONE;
867 		ch->peer = NULL;
868 		module_put(THIS_MODULE);
869 		ret = 0;
870 		break;
871 	case CONTROL_CHANNEL:
872 		ret = channel_bctrl(bch, arg);
873 		break;
874 	default:
875 		pr_info("%s: %s unknown prim(%x)\n", fc->name, __func__, cmd);
876 	}
877 	return ret;
878 }
879 
880 static int
881 channel_ctrl(struct fritzcard  *fc, struct mISDN_ctrl_req *cq)
882 {
883 	int	ret = 0;
884 
885 	switch (cq->op) {
886 	case MISDN_CTRL_GETOP:
887 		cq->op = MISDN_CTRL_LOOP | MISDN_CTRL_L1_TIMER3;
888 		break;
889 	case MISDN_CTRL_LOOP:
890 		/* cq->channel: 0 disable, 1 B1 loop 2 B2 loop, 3 both */
891 		if (cq->channel < 0 || cq->channel > 3) {
892 			ret = -EINVAL;
893 			break;
894 		}
895 		ret = fc->isac.ctrl(&fc->isac, HW_TESTLOOP, cq->channel);
896 		break;
897 	case MISDN_CTRL_L1_TIMER3:
898 		ret = fc->isac.ctrl(&fc->isac, HW_TIMER3_VALUE, cq->p1);
899 		break;
900 	default:
901 		pr_info("%s: %s unknown Op %x\n", fc->name, __func__, cq->op);
902 		ret = -EINVAL;
903 		break;
904 	}
905 	return ret;
906 }
907 
908 static int
909 open_bchannel(struct fritzcard *fc, struct channel_req *rq)
910 {
911 	struct bchannel		*bch;
912 
913 	if (rq->adr.channel == 0 || rq->adr.channel > 2)
914 		return -EINVAL;
915 	if (rq->protocol == ISDN_P_NONE)
916 		return -EINVAL;
917 	bch = &fc->bch[rq->adr.channel - 1];
918 	if (test_and_set_bit(FLG_OPEN, &bch->Flags))
919 		return -EBUSY; /* b-channel can be only open once */
920 	bch->ch.protocol = rq->protocol;
921 	rq->ch = &bch->ch;
922 	return 0;
923 }
924 
925 /*
926  * device control function
927  */
928 static int
929 avm_dctrl(struct mISDNchannel *ch, u32 cmd, void *arg)
930 {
931 	struct mISDNdevice	*dev = container_of(ch, struct mISDNdevice, D);
932 	struct dchannel		*dch = container_of(dev, struct dchannel, dev);
933 	struct fritzcard	*fc = dch->hw;
934 	struct channel_req	*rq;
935 	int			err = 0;
936 
937 	pr_debug("%s: %s cmd:%x %p\n", fc->name, __func__, cmd, arg);
938 	switch (cmd) {
939 	case OPEN_CHANNEL:
940 		rq = arg;
941 		if (rq->protocol == ISDN_P_TE_S0)
942 			err = fc->isac.open(&fc->isac, rq);
943 		else
944 			err = open_bchannel(fc, rq);
945 		if (err)
946 			break;
947 		if (!try_module_get(THIS_MODULE))
948 			pr_info("%s: cannot get module\n", fc->name);
949 		break;
950 	case CLOSE_CHANNEL:
951 		pr_debug("%s: dev(%d) close from %p\n", fc->name, dch->dev.id,
952 			 __builtin_return_address(0));
953 		module_put(THIS_MODULE);
954 		break;
955 	case CONTROL_CHANNEL:
956 		err = channel_ctrl(fc, arg);
957 		break;
958 	default:
959 		pr_debug("%s: %s unknown command %x\n",
960 			 fc->name, __func__, cmd);
961 		return -EINVAL;
962 	}
963 	return err;
964 }
965 
966 static int
967 setup_fritz(struct fritzcard *fc)
968 {
969 	u32 val, ver;
970 
971 	if (!request_region(fc->addr, 32, fc->name)) {
972 		pr_info("%s: AVM config port %x-%x already in use\n",
973 			fc->name, fc->addr, fc->addr + 31);
974 		return -EIO;
975 	}
976 	switch (fc->type) {
977 	case AVM_FRITZ_PCI:
978 		val = inl(fc->addr);
979 		outl(AVM_HDLC_1, fc->addr + CHIP_INDEX);
980 		ver = inl(fc->addr + CHIP_WINDOW + HDLC_STATUS) >> 24;
981 		if (debug & DEBUG_HW) {
982 			pr_notice("%s: PCI stat %#x\n", fc->name, val);
983 			pr_notice("%s: PCI Class %X Rev %d\n", fc->name,
984 				  val & 0xff, (val >> 8) & 0xff);
985 			pr_notice("%s: HDLC version %x\n", fc->name, ver & 0xf);
986 		}
987 		ASSIGN_FUNC(V1, ISAC, fc->isac);
988 		fc->isac.type = IPAC_TYPE_ISAC;
989 		break;
990 	case AVM_FRITZ_PCIV2:
991 		val = inl(fc->addr);
992 		ver = inl(fc->addr + AVM_HDLC_STATUS_1) >> 24;
993 		if (debug & DEBUG_HW) {
994 			pr_notice("%s: PCI V2 stat %#x\n", fc->name, val);
995 			pr_notice("%s: PCI V2 Class %X Rev %d\n", fc->name,
996 				  val & 0xff, (val >> 8) & 0xff);
997 			pr_notice("%s: HDLC version %x\n", fc->name, ver & 0xf);
998 		}
999 		ASSIGN_FUNC(V2, ISAC, fc->isac);
1000 		fc->isac.type = IPAC_TYPE_ISACX;
1001 		break;
1002 	default:
1003 		release_region(fc->addr, 32);
1004 		pr_info("%s: AVM unknown type %d\n", fc->name, fc->type);
1005 		return -ENODEV;
1006 	}
1007 	pr_notice("%s: %s config irq:%d base:0x%X\n", fc->name,
1008 		  (fc->type == AVM_FRITZ_PCI) ? "AVM Fritz!CARD PCI" :
1009 		  "AVM Fritz!CARD PCIv2", fc->irq, fc->addr);
1010 	return 0;
1011 }
1012 
1013 static void
1014 release_card(struct fritzcard *card)
1015 {
1016 	u_long flags;
1017 
1018 	disable_hwirq(card);
1019 	spin_lock_irqsave(&card->lock, flags);
1020 	modehdlc(&card->bch[0], ISDN_P_NONE);
1021 	modehdlc(&card->bch[1], ISDN_P_NONE);
1022 	spin_unlock_irqrestore(&card->lock, flags);
1023 	card->isac.release(&card->isac);
1024 	free_irq(card->irq, card);
1025 	mISDN_freebchannel(&card->bch[1]);
1026 	mISDN_freebchannel(&card->bch[0]);
1027 	mISDN_unregister_device(&card->isac.dch.dev);
1028 	release_region(card->addr, 32);
1029 	pci_disable_device(card->pdev);
1030 	pci_set_drvdata(card->pdev, NULL);
1031 	write_lock_irqsave(&card_lock, flags);
1032 	list_del(&card->list);
1033 	write_unlock_irqrestore(&card_lock, flags);
1034 	kfree(card);
1035 	AVM_cnt--;
1036 }
1037 
1038 static int
1039 setup_instance(struct fritzcard *card)
1040 {
1041 	int i, err;
1042 	unsigned short minsize;
1043 	u_long flags;
1044 
1045 	snprintf(card->name, MISDN_MAX_IDLEN - 1, "AVM.%d", AVM_cnt + 1);
1046 	write_lock_irqsave(&card_lock, flags);
1047 	list_add_tail(&card->list, &Cards);
1048 	write_unlock_irqrestore(&card_lock, flags);
1049 
1050 	_set_debug(card);
1051 	card->isac.name = card->name;
1052 	spin_lock_init(&card->lock);
1053 	card->isac.hwlock = &card->lock;
1054 	mISDNisac_init(&card->isac, card);
1055 
1056 	card->isac.dch.dev.Bprotocols = (1 << (ISDN_P_B_RAW & ISDN_P_B_MASK)) |
1057 		(1 << (ISDN_P_B_HDLC & ISDN_P_B_MASK));
1058 	card->isac.dch.dev.D.ctrl = avm_dctrl;
1059 	for (i = 0; i < 2; i++) {
1060 		card->bch[i].nr = i + 1;
1061 		set_channelmap(i + 1, card->isac.dch.dev.channelmap);
1062 		if (AVM_FRITZ_PCIV2 == card->type)
1063 			minsize = HDLC_FIFO_SIZE_V2;
1064 		else
1065 			minsize = HDLC_FIFO_SIZE_V1;
1066 		mISDN_initbchannel(&card->bch[i], MAX_DATA_MEM, minsize);
1067 		card->bch[i].hw = card;
1068 		card->bch[i].ch.send = avm_l2l1B;
1069 		card->bch[i].ch.ctrl = avm_bctrl;
1070 		card->bch[i].ch.nr = i + 1;
1071 		list_add(&card->bch[i].ch.list, &card->isac.dch.dev.bchannels);
1072 	}
1073 	err = setup_fritz(card);
1074 	if (err)
1075 		goto error;
1076 	err = mISDN_register_device(&card->isac.dch.dev, &card->pdev->dev,
1077 				    card->name);
1078 	if (err)
1079 		goto error_reg;
1080 	err = init_card(card);
1081 	if (!err)  {
1082 		AVM_cnt++;
1083 		pr_notice("AVM %d cards installed DEBUG\n", AVM_cnt);
1084 		return 0;
1085 	}
1086 	mISDN_unregister_device(&card->isac.dch.dev);
1087 error_reg:
1088 	release_region(card->addr, 32);
1089 error:
1090 	card->isac.release(&card->isac);
1091 	mISDN_freebchannel(&card->bch[1]);
1092 	mISDN_freebchannel(&card->bch[0]);
1093 	write_lock_irqsave(&card_lock, flags);
1094 	list_del(&card->list);
1095 	write_unlock_irqrestore(&card_lock, flags);
1096 	kfree(card);
1097 	return err;
1098 }
1099 
1100 static int
1101 fritzpci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1102 {
1103 	int err = -ENOMEM;
1104 	struct fritzcard *card;
1105 
1106 	card = kzalloc(sizeof(struct fritzcard), GFP_KERNEL);
1107 	if (!card) {
1108 		pr_info("No kmem for fritzcard\n");
1109 		return err;
1110 	}
1111 	if (pdev->device == PCI_DEVICE_ID_AVM_A1_V2)
1112 		card->type = AVM_FRITZ_PCIV2;
1113 	else
1114 		card->type = AVM_FRITZ_PCI;
1115 	card->pdev = pdev;
1116 	err = pci_enable_device(pdev);
1117 	if (err) {
1118 		kfree(card);
1119 		return err;
1120 	}
1121 
1122 	pr_notice("mISDN: found adapter %s at %s\n",
1123 		  (char *) ent->driver_data, pci_name(pdev));
1124 
1125 	card->addr = pci_resource_start(pdev, 1);
1126 	card->irq = pdev->irq;
1127 	pci_set_drvdata(pdev, card);
1128 	err = setup_instance(card);
1129 	if (err)
1130 		pci_set_drvdata(pdev, NULL);
1131 	return err;
1132 }
1133 
1134 static void
1135 fritz_remove_pci(struct pci_dev *pdev)
1136 {
1137 	struct fritzcard *card = pci_get_drvdata(pdev);
1138 
1139 	if (card)
1140 		release_card(card);
1141 	else
1142 		if (debug)
1143 			pr_info("%s: drvdata already removed\n", __func__);
1144 }
1145 
1146 static const struct pci_device_id fcpci_ids[] = {
1147 	{ PCI_VENDOR_ID_AVM, PCI_DEVICE_ID_AVM_A1, PCI_ANY_ID, PCI_ANY_ID,
1148 	  0, 0, (unsigned long) "Fritz!Card PCI"},
1149 	{ PCI_VENDOR_ID_AVM, PCI_DEVICE_ID_AVM_A1_V2, PCI_ANY_ID, PCI_ANY_ID,
1150 	  0, 0, (unsigned long) "Fritz!Card PCI v2" },
1151 	{ }
1152 };
1153 MODULE_DEVICE_TABLE(pci, fcpci_ids);
1154 
1155 static struct pci_driver fcpci_driver = {
1156 	.name = "fcpci",
1157 	.probe = fritzpci_probe,
1158 	.remove = fritz_remove_pci,
1159 	.id_table = fcpci_ids,
1160 };
1161 
1162 static int __init AVM_init(void)
1163 {
1164 	int err;
1165 
1166 	pr_notice("AVM Fritz PCI driver Rev. %s\n", AVMFRITZ_REV);
1167 	err = pci_register_driver(&fcpci_driver);
1168 	return err;
1169 }
1170 
1171 static void __exit AVM_cleanup(void)
1172 {
1173 	pci_unregister_driver(&fcpci_driver);
1174 }
1175 
1176 module_init(AVM_init);
1177 module_exit(AVM_cleanup);
1178