1df1590d9SViresh Kumar /*
2df1590d9SViresh Kumar * SPEAr platform shared irq layer source file
3df1590d9SViresh Kumar *
4df1590d9SViresh Kumar * Copyright (C) 2009-2012 ST Microelectronics
5da89947bSViresh Kumar * Viresh Kumar <vireshk@kernel.org>
6df1590d9SViresh Kumar *
7df1590d9SViresh Kumar * Copyright (C) 2012 ST Microelectronics
89cc23682SViresh Kumar * Shiraz Hashim <shiraz.linux.kernel@gmail.com>
9df1590d9SViresh Kumar *
10df1590d9SViresh Kumar * This file is licensed under the terms of the GNU General Public
11df1590d9SViresh Kumar * License version 2. This program is licensed "as is" without any
12df1590d9SViresh Kumar * warranty of any kind, whether express or implied.
13df1590d9SViresh Kumar */
14df1590d9SViresh Kumar #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
15df1590d9SViresh Kumar
16df1590d9SViresh Kumar #include <linux/err.h>
17df1590d9SViresh Kumar #include <linux/export.h>
18df1590d9SViresh Kumar #include <linux/interrupt.h>
19df1590d9SViresh Kumar #include <linux/io.h>
20df1590d9SViresh Kumar #include <linux/irq.h>
2141a83e06SJoel Porquet #include <linux/irqchip.h>
22df1590d9SViresh Kumar #include <linux/irqdomain.h>
23df1590d9SViresh Kumar #include <linux/of.h>
24df1590d9SViresh Kumar #include <linux/of_address.h>
25df1590d9SViresh Kumar #include <linux/of_irq.h>
26df1590d9SViresh Kumar #include <linux/spinlock.h>
27df1590d9SViresh Kumar
28078bc005SThomas Gleixner /*
29078bc005SThomas Gleixner * struct spear_shirq: shared irq structure
30078bc005SThomas Gleixner *
31c5d1d857SThomas Gleixner * base: Base register address
321b0a76c1SThomas Gleixner * status_reg: Status register offset for chained interrupt handler
331b0a76c1SThomas Gleixner * mask_reg: Mask register offset for irq chip
344ecc832fSThomas Gleixner * mask: Mask to apply to the status register
35c5d1d857SThomas Gleixner * virq_base: Base virtual interrupt number
36c5d1d857SThomas Gleixner * nr_irqs: Number of interrupts handled by this block
37c5d1d857SThomas Gleixner * offset: Bit offset of the first interrupt
38f07e42f9SThomas Gleixner * irq_chip: Interrupt controller chip used for this instance,
39f07e42f9SThomas Gleixner * if NULL group is disabled, but accounted
40078bc005SThomas Gleixner */
41078bc005SThomas Gleixner struct spear_shirq {
42078bc005SThomas Gleixner void __iomem *base;
431b0a76c1SThomas Gleixner u32 status_reg;
441b0a76c1SThomas Gleixner u32 mask_reg;
454ecc832fSThomas Gleixner u32 mask;
46c5d1d857SThomas Gleixner u32 virq_base;
47c5d1d857SThomas Gleixner u32 nr_irqs;
48c5d1d857SThomas Gleixner u32 offset;
49f07e42f9SThomas Gleixner struct irq_chip *irq_chip;
50078bc005SThomas Gleixner };
51078bc005SThomas Gleixner
52df1590d9SViresh Kumar /* spear300 shared irq registers offsets and masks */
53df1590d9SViresh Kumar #define SPEAR300_INT_ENB_MASK_REG 0x54
54df1590d9SViresh Kumar #define SPEAR300_INT_STS_MASK_REG 0x58
55df1590d9SViresh Kumar
56f07e42f9SThomas Gleixner static DEFINE_RAW_SPINLOCK(shirq_lock);
57f07e42f9SThomas Gleixner
shirq_irq_mask(struct irq_data * d)58f07e42f9SThomas Gleixner static void shirq_irq_mask(struct irq_data *d)
59f07e42f9SThomas Gleixner {
60f07e42f9SThomas Gleixner struct spear_shirq *shirq = irq_data_get_irq_chip_data(d);
61f07e42f9SThomas Gleixner u32 val, shift = d->irq - shirq->virq_base + shirq->offset;
621b0a76c1SThomas Gleixner u32 __iomem *reg = shirq->base + shirq->mask_reg;
63f07e42f9SThomas Gleixner
64f07e42f9SThomas Gleixner raw_spin_lock(&shirq_lock);
65f07e42f9SThomas Gleixner val = readl(reg) & ~(0x1 << shift);
66f07e42f9SThomas Gleixner writel(val, reg);
67f07e42f9SThomas Gleixner raw_spin_unlock(&shirq_lock);
68f07e42f9SThomas Gleixner }
69f07e42f9SThomas Gleixner
shirq_irq_unmask(struct irq_data * d)70f07e42f9SThomas Gleixner static void shirq_irq_unmask(struct irq_data *d)
71f07e42f9SThomas Gleixner {
72f07e42f9SThomas Gleixner struct spear_shirq *shirq = irq_data_get_irq_chip_data(d);
73f07e42f9SThomas Gleixner u32 val, shift = d->irq - shirq->virq_base + shirq->offset;
741b0a76c1SThomas Gleixner u32 __iomem *reg = shirq->base + shirq->mask_reg;
75f07e42f9SThomas Gleixner
76f07e42f9SThomas Gleixner raw_spin_lock(&shirq_lock);
77f07e42f9SThomas Gleixner val = readl(reg) | (0x1 << shift);
78f07e42f9SThomas Gleixner writel(val, reg);
79f07e42f9SThomas Gleixner raw_spin_unlock(&shirq_lock);
80f07e42f9SThomas Gleixner }
81f07e42f9SThomas Gleixner
82f07e42f9SThomas Gleixner static struct irq_chip shirq_chip = {
83f07e42f9SThomas Gleixner .name = "spear-shirq",
84f07e42f9SThomas Gleixner .irq_mask = shirq_irq_mask,
85f07e42f9SThomas Gleixner .irq_unmask = shirq_irq_unmask,
86f07e42f9SThomas Gleixner };
87f07e42f9SThomas Gleixner
88df1590d9SViresh Kumar static struct spear_shirq spear300_shirq_ras1 = {
89c5d1d857SThomas Gleixner .offset = 0,
90c5d1d857SThomas Gleixner .nr_irqs = 9,
914ecc832fSThomas Gleixner .mask = ((0x1 << 9) - 1) << 0,
92f07e42f9SThomas Gleixner .irq_chip = &shirq_chip,
93df1590d9SViresh Kumar .status_reg = SPEAR300_INT_STS_MASK_REG,
941b0a76c1SThomas Gleixner .mask_reg = SPEAR300_INT_ENB_MASK_REG,
95df1590d9SViresh Kumar };
96df1590d9SViresh Kumar
97df1590d9SViresh Kumar static struct spear_shirq *spear300_shirq_blocks[] = {
98df1590d9SViresh Kumar &spear300_shirq_ras1,
99df1590d9SViresh Kumar };
100df1590d9SViresh Kumar
101df1590d9SViresh Kumar /* spear310 shared irq registers offsets and masks */
102df1590d9SViresh Kumar #define SPEAR310_INT_STS_MASK_REG 0x04
103df1590d9SViresh Kumar
104df1590d9SViresh Kumar static struct spear_shirq spear310_shirq_ras1 = {
105c5d1d857SThomas Gleixner .offset = 0,
106c5d1d857SThomas Gleixner .nr_irqs = 8,
1074ecc832fSThomas Gleixner .mask = ((0x1 << 8) - 1) << 0,
108f07e42f9SThomas Gleixner .irq_chip = &dummy_irq_chip,
109df1590d9SViresh Kumar .status_reg = SPEAR310_INT_STS_MASK_REG,
110df1590d9SViresh Kumar };
111df1590d9SViresh Kumar
112df1590d9SViresh Kumar static struct spear_shirq spear310_shirq_ras2 = {
113c5d1d857SThomas Gleixner .offset = 8,
114c5d1d857SThomas Gleixner .nr_irqs = 5,
1154ecc832fSThomas Gleixner .mask = ((0x1 << 5) - 1) << 8,
116f07e42f9SThomas Gleixner .irq_chip = &dummy_irq_chip,
117df1590d9SViresh Kumar .status_reg = SPEAR310_INT_STS_MASK_REG,
118df1590d9SViresh Kumar };
119df1590d9SViresh Kumar
120df1590d9SViresh Kumar static struct spear_shirq spear310_shirq_ras3 = {
121c5d1d857SThomas Gleixner .offset = 13,
122c5d1d857SThomas Gleixner .nr_irqs = 1,
1234ecc832fSThomas Gleixner .mask = ((0x1 << 1) - 1) << 13,
124f07e42f9SThomas Gleixner .irq_chip = &dummy_irq_chip,
125df1590d9SViresh Kumar .status_reg = SPEAR310_INT_STS_MASK_REG,
126df1590d9SViresh Kumar };
127df1590d9SViresh Kumar
128df1590d9SViresh Kumar static struct spear_shirq spear310_shirq_intrcomm_ras = {
129c5d1d857SThomas Gleixner .offset = 14,
130c5d1d857SThomas Gleixner .nr_irqs = 3,
1314ecc832fSThomas Gleixner .mask = ((0x1 << 3) - 1) << 14,
132f07e42f9SThomas Gleixner .irq_chip = &dummy_irq_chip,
133df1590d9SViresh Kumar .status_reg = SPEAR310_INT_STS_MASK_REG,
134df1590d9SViresh Kumar };
135df1590d9SViresh Kumar
136df1590d9SViresh Kumar static struct spear_shirq *spear310_shirq_blocks[] = {
137df1590d9SViresh Kumar &spear310_shirq_ras1,
138df1590d9SViresh Kumar &spear310_shirq_ras2,
139df1590d9SViresh Kumar &spear310_shirq_ras3,
140df1590d9SViresh Kumar &spear310_shirq_intrcomm_ras,
141df1590d9SViresh Kumar };
142df1590d9SViresh Kumar
143df1590d9SViresh Kumar /* spear320 shared irq registers offsets and masks */
144df1590d9SViresh Kumar #define SPEAR320_INT_STS_MASK_REG 0x04
145df1590d9SViresh Kumar #define SPEAR320_INT_CLR_MASK_REG 0x04
146df1590d9SViresh Kumar #define SPEAR320_INT_ENB_MASK_REG 0x08
147df1590d9SViresh Kumar
14803319a1aSThomas Gleixner static struct spear_shirq spear320_shirq_ras3 = {
14903319a1aSThomas Gleixner .offset = 0,
15003319a1aSThomas Gleixner .nr_irqs = 7,
1514ecc832fSThomas Gleixner .mask = ((0x1 << 7) - 1) << 0,
152*f63c8625SHerve Codina .irq_chip = &dummy_irq_chip,
153*f63c8625SHerve Codina .status_reg = SPEAR320_INT_STS_MASK_REG,
15403319a1aSThomas Gleixner };
15503319a1aSThomas Gleixner
156df1590d9SViresh Kumar static struct spear_shirq spear320_shirq_ras1 = {
157c5d1d857SThomas Gleixner .offset = 7,
158c5d1d857SThomas Gleixner .nr_irqs = 3,
1594ecc832fSThomas Gleixner .mask = ((0x1 << 3) - 1) << 7,
160f07e42f9SThomas Gleixner .irq_chip = &dummy_irq_chip,
161df1590d9SViresh Kumar .status_reg = SPEAR320_INT_STS_MASK_REG,
162df1590d9SViresh Kumar };
163df1590d9SViresh Kumar
164df1590d9SViresh Kumar static struct spear_shirq spear320_shirq_ras2 = {
165c5d1d857SThomas Gleixner .offset = 10,
166c5d1d857SThomas Gleixner .nr_irqs = 1,
1674ecc832fSThomas Gleixner .mask = ((0x1 << 1) - 1) << 10,
168f07e42f9SThomas Gleixner .irq_chip = &dummy_irq_chip,
169df1590d9SViresh Kumar .status_reg = SPEAR320_INT_STS_MASK_REG,
170df1590d9SViresh Kumar };
171df1590d9SViresh Kumar
172df1590d9SViresh Kumar static struct spear_shirq spear320_shirq_intrcomm_ras = {
173c5d1d857SThomas Gleixner .offset = 11,
174c5d1d857SThomas Gleixner .nr_irqs = 11,
1754ecc832fSThomas Gleixner .mask = ((0x1 << 11) - 1) << 11,
176f07e42f9SThomas Gleixner .irq_chip = &dummy_irq_chip,
177df1590d9SViresh Kumar .status_reg = SPEAR320_INT_STS_MASK_REG,
178df1590d9SViresh Kumar };
179df1590d9SViresh Kumar
180df1590d9SViresh Kumar static struct spear_shirq *spear320_shirq_blocks[] = {
181df1590d9SViresh Kumar &spear320_shirq_ras3,
182df1590d9SViresh Kumar &spear320_shirq_ras1,
183df1590d9SViresh Kumar &spear320_shirq_ras2,
184df1590d9SViresh Kumar &spear320_shirq_intrcomm_ras,
185df1590d9SViresh Kumar };
186df1590d9SViresh Kumar
shirq_handler(struct irq_desc * desc)187bd0b9ac4SThomas Gleixner static void shirq_handler(struct irq_desc *desc)
188df1590d9SViresh Kumar {
1895b29264cSJiang Liu struct spear_shirq *shirq = irq_desc_get_handler_data(desc);
19025dc49e3SThomas Gleixner u32 pend;
191df1590d9SViresh Kumar
1921b0a76c1SThomas Gleixner pend = readl(shirq->base + shirq->status_reg) & shirq->mask;
19325dc49e3SThomas Gleixner pend >>= shirq->offset;
194df1590d9SViresh Kumar
19525dc49e3SThomas Gleixner while (pend) {
19625dc49e3SThomas Gleixner int irq = __ffs(pend);
197df1590d9SViresh Kumar
19825dc49e3SThomas Gleixner pend &= ~(0x1 << irq);
19925dc49e3SThomas Gleixner generic_handle_irq(shirq->virq_base + irq);
200df1590d9SViresh Kumar }
201df1590d9SViresh Kumar }
202df1590d9SViresh Kumar
spear_shirq_register(struct spear_shirq * shirq,int parent_irq)203f37ecbceSThomas Gleixner static void __init spear_shirq_register(struct spear_shirq *shirq,
204f37ecbceSThomas Gleixner int parent_irq)
205df1590d9SViresh Kumar {
206df1590d9SViresh Kumar int i;
207df1590d9SViresh Kumar
208f07e42f9SThomas Gleixner if (!shirq->irq_chip)
209df1590d9SViresh Kumar return;
210df1590d9SViresh Kumar
2112aedd0fdSRussell King irq_set_chained_handler_and_data(parent_irq, shirq_handler, shirq);
212f37ecbceSThomas Gleixner
213c5d1d857SThomas Gleixner for (i = 0; i < shirq->nr_irqs; i++) {
214c5d1d857SThomas Gleixner irq_set_chip_and_handler(shirq->virq_base + i,
215f07e42f9SThomas Gleixner shirq->irq_chip, handle_simple_irq);
216c5d1d857SThomas Gleixner irq_set_chip_data(shirq->virq_base + i, shirq);
217df1590d9SViresh Kumar }
218df1590d9SViresh Kumar }
219df1590d9SViresh Kumar
shirq_init(struct spear_shirq ** shirq_blocks,int block_nr,struct device_node * np)220df1590d9SViresh Kumar static int __init shirq_init(struct spear_shirq **shirq_blocks, int block_nr,
221df1590d9SViresh Kumar struct device_node *np)
222df1590d9SViresh Kumar {
223c5d1d857SThomas Gleixner int i, parent_irq, virq_base, hwirq = 0, nr_irqs = 0;
224a26c06f9SThomas Gleixner struct irq_domain *shirq_domain;
225df1590d9SViresh Kumar void __iomem *base;
226df1590d9SViresh Kumar
227df1590d9SViresh Kumar base = of_iomap(np, 0);
228df1590d9SViresh Kumar if (!base) {
229df1590d9SViresh Kumar pr_err("%s: failed to map shirq registers\n", __func__);
230df1590d9SViresh Kumar return -ENXIO;
231df1590d9SViresh Kumar }
232df1590d9SViresh Kumar
233df1590d9SViresh Kumar for (i = 0; i < block_nr; i++)
234c5d1d857SThomas Gleixner nr_irqs += shirq_blocks[i]->nr_irqs;
235df1590d9SViresh Kumar
236c5d1d857SThomas Gleixner virq_base = irq_alloc_descs(-1, 0, nr_irqs, 0);
237287980e4SArnd Bergmann if (virq_base < 0) {
238df1590d9SViresh Kumar pr_err("%s: irq desc alloc failed\n", __func__);
239df1590d9SViresh Kumar goto err_unmap;
240df1590d9SViresh Kumar }
241df1590d9SViresh Kumar
242c5d1d857SThomas Gleixner shirq_domain = irq_domain_add_legacy(np, nr_irqs, virq_base, 0,
243df1590d9SViresh Kumar &irq_domain_simple_ops, NULL);
244df1590d9SViresh Kumar if (WARN_ON(!shirq_domain)) {
245df1590d9SViresh Kumar pr_warn("%s: irq domain init failed\n", __func__);
246df1590d9SViresh Kumar goto err_free_desc;
247df1590d9SViresh Kumar }
248df1590d9SViresh Kumar
249df1590d9SViresh Kumar for (i = 0; i < block_nr; i++) {
250df1590d9SViresh Kumar shirq_blocks[i]->base = base;
251c5d1d857SThomas Gleixner shirq_blocks[i]->virq_base = irq_find_mapping(shirq_domain,
252df1590d9SViresh Kumar hwirq);
253df1590d9SViresh Kumar
254f37ecbceSThomas Gleixner parent_irq = irq_of_parse_and_map(np, i);
255f37ecbceSThomas Gleixner spear_shirq_register(shirq_blocks[i], parent_irq);
256c5d1d857SThomas Gleixner hwirq += shirq_blocks[i]->nr_irqs;
257df1590d9SViresh Kumar }
258df1590d9SViresh Kumar
259df1590d9SViresh Kumar return 0;
260df1590d9SViresh Kumar
261df1590d9SViresh Kumar err_free_desc:
262c5d1d857SThomas Gleixner irq_free_descs(virq_base, nr_irqs);
263df1590d9SViresh Kumar err_unmap:
264df1590d9SViresh Kumar iounmap(base);
265df1590d9SViresh Kumar return -ENXIO;
266df1590d9SViresh Kumar }
267df1590d9SViresh Kumar
spear300_shirq_of_init(struct device_node * np,struct device_node * parent)268078bc005SThomas Gleixner static int __init spear300_shirq_of_init(struct device_node *np,
269df1590d9SViresh Kumar struct device_node *parent)
270df1590d9SViresh Kumar {
271df1590d9SViresh Kumar return shirq_init(spear300_shirq_blocks,
272df1590d9SViresh Kumar ARRAY_SIZE(spear300_shirq_blocks), np);
273df1590d9SViresh Kumar }
274e9c51558SRob Herring IRQCHIP_DECLARE(spear300_shirq, "st,spear300-shirq", spear300_shirq_of_init);
275df1590d9SViresh Kumar
spear310_shirq_of_init(struct device_node * np,struct device_node * parent)276078bc005SThomas Gleixner static int __init spear310_shirq_of_init(struct device_node *np,
277df1590d9SViresh Kumar struct device_node *parent)
278df1590d9SViresh Kumar {
279df1590d9SViresh Kumar return shirq_init(spear310_shirq_blocks,
280df1590d9SViresh Kumar ARRAY_SIZE(spear310_shirq_blocks), np);
281df1590d9SViresh Kumar }
282e9c51558SRob Herring IRQCHIP_DECLARE(spear310_shirq, "st,spear310-shirq", spear310_shirq_of_init);
283df1590d9SViresh Kumar
spear320_shirq_of_init(struct device_node * np,struct device_node * parent)284078bc005SThomas Gleixner static int __init spear320_shirq_of_init(struct device_node *np,
285df1590d9SViresh Kumar struct device_node *parent)
286df1590d9SViresh Kumar {
287df1590d9SViresh Kumar return shirq_init(spear320_shirq_blocks,
288df1590d9SViresh Kumar ARRAY_SIZE(spear320_shirq_blocks), np);
289df1590d9SViresh Kumar }
290e9c51558SRob Herring IRQCHIP_DECLARE(spear320_shirq, "st,spear320-shirq", spear320_shirq_of_init);
291