1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/err.h> 7 #include <linux/init.h> 8 #include <linux/irq.h> 9 #include <linux/irqchip.h> 10 #include <linux/irqdomain.h> 11 #include <linux/io.h> 12 #include <linux/kernel.h> 13 #include <linux/of.h> 14 #include <linux/of_address.h> 15 #include <linux/of_device.h> 16 #include <linux/spinlock.h> 17 #include <linux/platform_device.h> 18 #include <linux/slab.h> 19 #include <linux/types.h> 20 21 #define PDC_MAX_IRQS 168 22 23 #define CLEAR_INTR(reg, intr) (reg & ~(1 << intr)) 24 #define ENABLE_INTR(reg, intr) (reg | (1 << intr)) 25 26 #define IRQ_ENABLE_BANK 0x10 27 #define IRQ_i_CFG 0x110 28 29 struct pdc_pin_region { 30 u32 pin_base; 31 u32 parent_base; 32 u32 cnt; 33 }; 34 35 static DEFINE_RAW_SPINLOCK(pdc_lock); 36 static void __iomem *pdc_base; 37 static struct pdc_pin_region *pdc_region; 38 static int pdc_region_cnt; 39 40 static void pdc_reg_write(int reg, u32 i, u32 val) 41 { 42 writel_relaxed(val, pdc_base + reg + i * sizeof(u32)); 43 } 44 45 static u32 pdc_reg_read(int reg, u32 i) 46 { 47 return readl_relaxed(pdc_base + reg + i * sizeof(u32)); 48 } 49 50 static void pdc_enable_intr(struct irq_data *d, bool on) 51 { 52 int pin_out = d->hwirq; 53 u32 index, mask; 54 u32 enable; 55 56 index = pin_out / 32; 57 mask = pin_out % 32; 58 59 raw_spin_lock(&pdc_lock); 60 enable = pdc_reg_read(IRQ_ENABLE_BANK, index); 61 enable = on ? ENABLE_INTR(enable, mask) : CLEAR_INTR(enable, mask); 62 pdc_reg_write(IRQ_ENABLE_BANK, index, enable); 63 raw_spin_unlock(&pdc_lock); 64 } 65 66 static void qcom_pdc_gic_disable(struct irq_data *d) 67 { 68 pdc_enable_intr(d, false); 69 irq_chip_disable_parent(d); 70 } 71 72 static void qcom_pdc_gic_enable(struct irq_data *d) 73 { 74 pdc_enable_intr(d, true); 75 irq_chip_enable_parent(d); 76 } 77 78 static void qcom_pdc_gic_mask(struct irq_data *d) 79 { 80 irq_chip_mask_parent(d); 81 } 82 83 static void qcom_pdc_gic_unmask(struct irq_data *d) 84 { 85 irq_chip_unmask_parent(d); 86 } 87 88 /* 89 * GIC does not handle falling edge or active low. To allow falling edge and 90 * active low interrupts to be handled at GIC, PDC has an inverter that inverts 91 * falling edge into a rising edge and active low into an active high. 92 * For the inverter to work, the polarity bit in the IRQ_CONFIG register has to 93 * set as per the table below. 94 * Level sensitive active low LOW 95 * Rising edge sensitive NOT USED 96 * Falling edge sensitive LOW 97 * Dual Edge sensitive NOT USED 98 * Level sensitive active High HIGH 99 * Falling Edge sensitive NOT USED 100 * Rising edge sensitive HIGH 101 * Dual Edge sensitive HIGH 102 */ 103 enum pdc_irq_config_bits { 104 PDC_LEVEL_LOW = 0b000, 105 PDC_EDGE_FALLING = 0b010, 106 PDC_LEVEL_HIGH = 0b100, 107 PDC_EDGE_RISING = 0b110, 108 PDC_EDGE_DUAL = 0b111, 109 }; 110 111 /** 112 * qcom_pdc_gic_set_type: Configure PDC for the interrupt 113 * 114 * @d: the interrupt data 115 * @type: the interrupt type 116 * 117 * If @type is edge triggered, forward that as Rising edge as PDC 118 * takes care of converting falling edge to rising edge signal 119 * If @type is level, then forward that as level high as PDC 120 * takes care of converting falling edge to rising edge signal 121 */ 122 static int qcom_pdc_gic_set_type(struct irq_data *d, unsigned int type) 123 { 124 int pin_out = d->hwirq; 125 enum pdc_irq_config_bits pdc_type; 126 127 switch (type) { 128 case IRQ_TYPE_EDGE_RISING: 129 pdc_type = PDC_EDGE_RISING; 130 break; 131 case IRQ_TYPE_EDGE_FALLING: 132 pdc_type = PDC_EDGE_FALLING; 133 type = IRQ_TYPE_EDGE_RISING; 134 break; 135 case IRQ_TYPE_EDGE_BOTH: 136 pdc_type = PDC_EDGE_DUAL; 137 type = IRQ_TYPE_EDGE_RISING; 138 break; 139 case IRQ_TYPE_LEVEL_HIGH: 140 pdc_type = PDC_LEVEL_HIGH; 141 break; 142 case IRQ_TYPE_LEVEL_LOW: 143 pdc_type = PDC_LEVEL_LOW; 144 type = IRQ_TYPE_LEVEL_HIGH; 145 break; 146 default: 147 WARN_ON(1); 148 return -EINVAL; 149 } 150 151 pdc_reg_write(IRQ_i_CFG, pin_out, pdc_type); 152 153 return irq_chip_set_type_parent(d, type); 154 } 155 156 static struct irq_chip qcom_pdc_gic_chip = { 157 .name = "PDC", 158 .irq_eoi = irq_chip_eoi_parent, 159 .irq_mask = qcom_pdc_gic_mask, 160 .irq_unmask = qcom_pdc_gic_unmask, 161 .irq_disable = qcom_pdc_gic_disable, 162 .irq_enable = qcom_pdc_gic_enable, 163 .irq_retrigger = irq_chip_retrigger_hierarchy, 164 .irq_set_type = qcom_pdc_gic_set_type, 165 .flags = IRQCHIP_MASK_ON_SUSPEND | 166 IRQCHIP_SET_TYPE_MASKED | 167 IRQCHIP_SKIP_SET_WAKE, 168 .irq_set_vcpu_affinity = irq_chip_set_vcpu_affinity_parent, 169 .irq_set_affinity = irq_chip_set_affinity_parent, 170 }; 171 172 static irq_hw_number_t get_parent_hwirq(int pin) 173 { 174 int i; 175 struct pdc_pin_region *region; 176 177 for (i = 0; i < pdc_region_cnt; i++) { 178 region = &pdc_region[i]; 179 if (pin >= region->pin_base && 180 pin < region->pin_base + region->cnt) 181 return (region->parent_base + pin - region->pin_base); 182 } 183 184 WARN_ON(1); 185 return ~0UL; 186 } 187 188 static int qcom_pdc_translate(struct irq_domain *d, struct irq_fwspec *fwspec, 189 unsigned long *hwirq, unsigned int *type) 190 { 191 if (is_of_node(fwspec->fwnode)) { 192 if (fwspec->param_count != 2) 193 return -EINVAL; 194 195 *hwirq = fwspec->param[0]; 196 *type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK; 197 return 0; 198 } 199 200 return -EINVAL; 201 } 202 203 static int qcom_pdc_alloc(struct irq_domain *domain, unsigned int virq, 204 unsigned int nr_irqs, void *data) 205 { 206 struct irq_fwspec *fwspec = data; 207 struct irq_fwspec parent_fwspec; 208 irq_hw_number_t hwirq, parent_hwirq; 209 unsigned int type; 210 int ret; 211 212 ret = qcom_pdc_translate(domain, fwspec, &hwirq, &type); 213 if (ret) 214 return -EINVAL; 215 216 parent_hwirq = get_parent_hwirq(hwirq); 217 if (parent_hwirq == ~0UL) 218 return -EINVAL; 219 220 ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq, 221 &qcom_pdc_gic_chip, NULL); 222 if (ret) 223 return ret; 224 225 if (type & IRQ_TYPE_EDGE_BOTH) 226 type = IRQ_TYPE_EDGE_RISING; 227 228 if (type & IRQ_TYPE_LEVEL_MASK) 229 type = IRQ_TYPE_LEVEL_HIGH; 230 231 parent_fwspec.fwnode = domain->parent->fwnode; 232 parent_fwspec.param_count = 3; 233 parent_fwspec.param[0] = 0; 234 parent_fwspec.param[1] = parent_hwirq; 235 parent_fwspec.param[2] = type; 236 237 return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, 238 &parent_fwspec); 239 } 240 241 static const struct irq_domain_ops qcom_pdc_ops = { 242 .translate = qcom_pdc_translate, 243 .alloc = qcom_pdc_alloc, 244 .free = irq_domain_free_irqs_common, 245 }; 246 247 static int pdc_setup_pin_mapping(struct device_node *np) 248 { 249 int ret, n; 250 251 n = of_property_count_elems_of_size(np, "qcom,pdc-ranges", sizeof(u32)); 252 if (n <= 0 || n % 3) 253 return -EINVAL; 254 255 pdc_region_cnt = n / 3; 256 pdc_region = kcalloc(pdc_region_cnt, sizeof(*pdc_region), GFP_KERNEL); 257 if (!pdc_region) { 258 pdc_region_cnt = 0; 259 return -ENOMEM; 260 } 261 262 for (n = 0; n < pdc_region_cnt; n++) { 263 ret = of_property_read_u32_index(np, "qcom,pdc-ranges", 264 n * 3 + 0, 265 &pdc_region[n].pin_base); 266 if (ret) 267 return ret; 268 ret = of_property_read_u32_index(np, "qcom,pdc-ranges", 269 n * 3 + 1, 270 &pdc_region[n].parent_base); 271 if (ret) 272 return ret; 273 ret = of_property_read_u32_index(np, "qcom,pdc-ranges", 274 n * 3 + 2, 275 &pdc_region[n].cnt); 276 if (ret) 277 return ret; 278 } 279 280 return 0; 281 } 282 283 static int qcom_pdc_init(struct device_node *node, struct device_node *parent) 284 { 285 struct irq_domain *parent_domain, *pdc_domain; 286 int ret; 287 288 pdc_base = of_iomap(node, 0); 289 if (!pdc_base) { 290 pr_err("%pOF: unable to map PDC registers\n", node); 291 return -ENXIO; 292 } 293 294 parent_domain = irq_find_host(parent); 295 if (!parent_domain) { 296 pr_err("%pOF: unable to find PDC's parent domain\n", node); 297 ret = -ENXIO; 298 goto fail; 299 } 300 301 ret = pdc_setup_pin_mapping(node); 302 if (ret) { 303 pr_err("%pOF: failed to init PDC pin-hwirq mapping\n", node); 304 goto fail; 305 } 306 307 pdc_domain = irq_domain_create_hierarchy(parent_domain, 0, PDC_MAX_IRQS, 308 of_fwnode_handle(node), 309 &qcom_pdc_ops, NULL); 310 if (!pdc_domain) { 311 pr_err("%pOF: GIC domain add failed\n", node); 312 ret = -ENOMEM; 313 goto fail; 314 } 315 316 return 0; 317 318 fail: 319 kfree(pdc_region); 320 iounmap(pdc_base); 321 return ret; 322 } 323 324 IRQCHIP_DECLARE(qcom_pdc, "qcom,pdc", qcom_pdc_init); 325