1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/err.h> 7 #include <linux/init.h> 8 #include <linux/interrupt.h> 9 #include <linux/irq.h> 10 #include <linux/irqchip.h> 11 #include <linux/irqdomain.h> 12 #include <linux/io.h> 13 #include <linux/kernel.h> 14 #include <linux/module.h> 15 #include <linux/of.h> 16 #include <linux/of_address.h> 17 #include <linux/of_device.h> 18 #include <linux/of_irq.h> 19 #include <linux/soc/qcom/irq.h> 20 #include <linux/spinlock.h> 21 #include <linux/slab.h> 22 #include <linux/types.h> 23 24 #define PDC_MAX_GPIO_IRQS 256 25 26 #define CLEAR_INTR(reg, intr) (reg & ~(1 << intr)) 27 #define ENABLE_INTR(reg, intr) (reg | (1 << intr)) 28 29 #define IRQ_ENABLE_BANK 0x10 30 #define IRQ_i_CFG 0x110 31 32 struct pdc_pin_region { 33 u32 pin_base; 34 u32 parent_base; 35 u32 cnt; 36 }; 37 38 #define pin_to_hwirq(r, p) ((r)->parent_base + (p) - (r)->pin_base) 39 40 static DEFINE_RAW_SPINLOCK(pdc_lock); 41 static void __iomem *pdc_base; 42 static struct pdc_pin_region *pdc_region; 43 static int pdc_region_cnt; 44 45 static void pdc_reg_write(int reg, u32 i, u32 val) 46 { 47 writel_relaxed(val, pdc_base + reg + i * sizeof(u32)); 48 } 49 50 static u32 pdc_reg_read(int reg, u32 i) 51 { 52 return readl_relaxed(pdc_base + reg + i * sizeof(u32)); 53 } 54 55 static void pdc_enable_intr(struct irq_data *d, bool on) 56 { 57 int pin_out = d->hwirq; 58 unsigned long flags; 59 u32 index, mask; 60 u32 enable; 61 62 index = pin_out / 32; 63 mask = pin_out % 32; 64 65 raw_spin_lock_irqsave(&pdc_lock, flags); 66 enable = pdc_reg_read(IRQ_ENABLE_BANK, index); 67 enable = on ? ENABLE_INTR(enable, mask) : CLEAR_INTR(enable, mask); 68 pdc_reg_write(IRQ_ENABLE_BANK, index, enable); 69 raw_spin_unlock_irqrestore(&pdc_lock, flags); 70 } 71 72 static void qcom_pdc_gic_disable(struct irq_data *d) 73 { 74 pdc_enable_intr(d, false); 75 irq_chip_disable_parent(d); 76 } 77 78 static void qcom_pdc_gic_enable(struct irq_data *d) 79 { 80 pdc_enable_intr(d, true); 81 irq_chip_enable_parent(d); 82 } 83 84 /* 85 * GIC does not handle falling edge or active low. To allow falling edge and 86 * active low interrupts to be handled at GIC, PDC has an inverter that inverts 87 * falling edge into a rising edge and active low into an active high. 88 * For the inverter to work, the polarity bit in the IRQ_CONFIG register has to 89 * set as per the table below. 90 * Level sensitive active low LOW 91 * Rising edge sensitive NOT USED 92 * Falling edge sensitive LOW 93 * Dual Edge sensitive NOT USED 94 * Level sensitive active High HIGH 95 * Falling Edge sensitive NOT USED 96 * Rising edge sensitive HIGH 97 * Dual Edge sensitive HIGH 98 */ 99 enum pdc_irq_config_bits { 100 PDC_LEVEL_LOW = 0b000, 101 PDC_EDGE_FALLING = 0b010, 102 PDC_LEVEL_HIGH = 0b100, 103 PDC_EDGE_RISING = 0b110, 104 PDC_EDGE_DUAL = 0b111, 105 }; 106 107 /** 108 * qcom_pdc_gic_set_type: Configure PDC for the interrupt 109 * 110 * @d: the interrupt data 111 * @type: the interrupt type 112 * 113 * If @type is edge triggered, forward that as Rising edge as PDC 114 * takes care of converting falling edge to rising edge signal 115 * If @type is level, then forward that as level high as PDC 116 * takes care of converting falling edge to rising edge signal 117 */ 118 static int qcom_pdc_gic_set_type(struct irq_data *d, unsigned int type) 119 { 120 enum pdc_irq_config_bits pdc_type; 121 enum pdc_irq_config_bits old_pdc_type; 122 int ret; 123 124 switch (type) { 125 case IRQ_TYPE_EDGE_RISING: 126 pdc_type = PDC_EDGE_RISING; 127 break; 128 case IRQ_TYPE_EDGE_FALLING: 129 pdc_type = PDC_EDGE_FALLING; 130 type = IRQ_TYPE_EDGE_RISING; 131 break; 132 case IRQ_TYPE_EDGE_BOTH: 133 pdc_type = PDC_EDGE_DUAL; 134 type = IRQ_TYPE_EDGE_RISING; 135 break; 136 case IRQ_TYPE_LEVEL_HIGH: 137 pdc_type = PDC_LEVEL_HIGH; 138 break; 139 case IRQ_TYPE_LEVEL_LOW: 140 pdc_type = PDC_LEVEL_LOW; 141 type = IRQ_TYPE_LEVEL_HIGH; 142 break; 143 default: 144 WARN_ON(1); 145 return -EINVAL; 146 } 147 148 old_pdc_type = pdc_reg_read(IRQ_i_CFG, d->hwirq); 149 pdc_reg_write(IRQ_i_CFG, d->hwirq, pdc_type); 150 151 ret = irq_chip_set_type_parent(d, type); 152 if (ret) 153 return ret; 154 155 /* 156 * When we change types the PDC can give a phantom interrupt. 157 * Clear it. Specifically the phantom shows up when reconfiguring 158 * polarity of interrupt without changing the state of the signal 159 * but let's be consistent and clear it always. 160 * 161 * Doing this works because we have IRQCHIP_SET_TYPE_MASKED so the 162 * interrupt will be cleared before the rest of the system sees it. 163 */ 164 if (old_pdc_type != pdc_type) 165 irq_chip_set_parent_state(d, IRQCHIP_STATE_PENDING, false); 166 167 return 0; 168 } 169 170 static struct irq_chip qcom_pdc_gic_chip = { 171 .name = "PDC", 172 .irq_eoi = irq_chip_eoi_parent, 173 .irq_mask = irq_chip_mask_parent, 174 .irq_unmask = irq_chip_unmask_parent, 175 .irq_disable = qcom_pdc_gic_disable, 176 .irq_enable = qcom_pdc_gic_enable, 177 .irq_get_irqchip_state = irq_chip_get_parent_state, 178 .irq_set_irqchip_state = irq_chip_set_parent_state, 179 .irq_retrigger = irq_chip_retrigger_hierarchy, 180 .irq_set_type = qcom_pdc_gic_set_type, 181 .flags = IRQCHIP_MASK_ON_SUSPEND | 182 IRQCHIP_SET_TYPE_MASKED | 183 IRQCHIP_SKIP_SET_WAKE | 184 IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND, 185 .irq_set_vcpu_affinity = irq_chip_set_vcpu_affinity_parent, 186 .irq_set_affinity = irq_chip_set_affinity_parent, 187 }; 188 189 static struct pdc_pin_region *get_pin_region(int pin) 190 { 191 int i; 192 193 for (i = 0; i < pdc_region_cnt; i++) { 194 if (pin >= pdc_region[i].pin_base && 195 pin < pdc_region[i].pin_base + pdc_region[i].cnt) 196 return &pdc_region[i]; 197 } 198 199 return NULL; 200 } 201 202 static int qcom_pdc_alloc(struct irq_domain *domain, unsigned int virq, 203 unsigned int nr_irqs, void *data) 204 { 205 struct irq_fwspec *fwspec = data; 206 struct irq_fwspec parent_fwspec; 207 struct pdc_pin_region *region; 208 irq_hw_number_t hwirq; 209 unsigned int type; 210 int ret; 211 212 ret = irq_domain_translate_twocell(domain, fwspec, &hwirq, &type); 213 if (ret) 214 return ret; 215 216 if (hwirq == GPIO_NO_WAKE_IRQ) 217 return irq_domain_disconnect_hierarchy(domain, virq); 218 219 ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq, 220 &qcom_pdc_gic_chip, NULL); 221 if (ret) 222 return ret; 223 224 region = get_pin_region(hwirq); 225 if (!region) 226 return irq_domain_disconnect_hierarchy(domain->parent, virq); 227 228 if (type & IRQ_TYPE_EDGE_BOTH) 229 type = IRQ_TYPE_EDGE_RISING; 230 231 if (type & IRQ_TYPE_LEVEL_MASK) 232 type = IRQ_TYPE_LEVEL_HIGH; 233 234 parent_fwspec.fwnode = domain->parent->fwnode; 235 parent_fwspec.param_count = 3; 236 parent_fwspec.param[0] = 0; 237 parent_fwspec.param[1] = pin_to_hwirq(region, hwirq); 238 parent_fwspec.param[2] = type; 239 240 return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, 241 &parent_fwspec); 242 } 243 244 static const struct irq_domain_ops qcom_pdc_ops = { 245 .translate = irq_domain_translate_twocell, 246 .alloc = qcom_pdc_alloc, 247 .free = irq_domain_free_irqs_common, 248 }; 249 250 static int pdc_setup_pin_mapping(struct device_node *np) 251 { 252 int ret, n, i; 253 u32 irq_index, reg_index, val; 254 255 n = of_property_count_elems_of_size(np, "qcom,pdc-ranges", sizeof(u32)); 256 if (n <= 0 || n % 3) 257 return -EINVAL; 258 259 pdc_region_cnt = n / 3; 260 pdc_region = kcalloc(pdc_region_cnt, sizeof(*pdc_region), GFP_KERNEL); 261 if (!pdc_region) { 262 pdc_region_cnt = 0; 263 return -ENOMEM; 264 } 265 266 for (n = 0; n < pdc_region_cnt; n++) { 267 ret = of_property_read_u32_index(np, "qcom,pdc-ranges", 268 n * 3 + 0, 269 &pdc_region[n].pin_base); 270 if (ret) 271 return ret; 272 ret = of_property_read_u32_index(np, "qcom,pdc-ranges", 273 n * 3 + 1, 274 &pdc_region[n].parent_base); 275 if (ret) 276 return ret; 277 ret = of_property_read_u32_index(np, "qcom,pdc-ranges", 278 n * 3 + 2, 279 &pdc_region[n].cnt); 280 if (ret) 281 return ret; 282 283 for (i = 0; i < pdc_region[n].cnt; i++) { 284 reg_index = (i + pdc_region[n].pin_base) >> 5; 285 irq_index = (i + pdc_region[n].pin_base) & 0x1f; 286 val = pdc_reg_read(IRQ_ENABLE_BANK, reg_index); 287 val &= ~BIT(irq_index); 288 pdc_reg_write(IRQ_ENABLE_BANK, reg_index, val); 289 } 290 } 291 292 return 0; 293 } 294 295 static int qcom_pdc_init(struct device_node *node, struct device_node *parent) 296 { 297 struct irq_domain *parent_domain, *pdc_domain; 298 int ret; 299 300 pdc_base = of_iomap(node, 0); 301 if (!pdc_base) { 302 pr_err("%pOF: unable to map PDC registers\n", node); 303 return -ENXIO; 304 } 305 306 parent_domain = irq_find_host(parent); 307 if (!parent_domain) { 308 pr_err("%pOF: unable to find PDC's parent domain\n", node); 309 ret = -ENXIO; 310 goto fail; 311 } 312 313 ret = pdc_setup_pin_mapping(node); 314 if (ret) { 315 pr_err("%pOF: failed to init PDC pin-hwirq mapping\n", node); 316 goto fail; 317 } 318 319 pdc_domain = irq_domain_create_hierarchy(parent_domain, 320 IRQ_DOMAIN_FLAG_QCOM_PDC_WAKEUP, 321 PDC_MAX_GPIO_IRQS, 322 of_fwnode_handle(node), 323 &qcom_pdc_ops, NULL); 324 if (!pdc_domain) { 325 pr_err("%pOF: PDC domain add failed\n", node); 326 ret = -ENOMEM; 327 goto fail; 328 } 329 330 irq_domain_update_bus_token(pdc_domain, DOMAIN_BUS_WAKEUP); 331 332 return 0; 333 334 fail: 335 kfree(pdc_region); 336 iounmap(pdc_base); 337 return ret; 338 } 339 340 IRQCHIP_PLATFORM_DRIVER_BEGIN(qcom_pdc) 341 IRQCHIP_MATCH("qcom,pdc", qcom_pdc_init) 342 IRQCHIP_PLATFORM_DRIVER_END(qcom_pdc) 343 MODULE_DESCRIPTION("Qualcomm Technologies, Inc. Power Domain Controller"); 344 MODULE_LICENSE("GPL v2"); 345