1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/err.h> 7 #include <linux/init.h> 8 #include <linux/interrupt.h> 9 #include <linux/irq.h> 10 #include <linux/irqchip.h> 11 #include <linux/irqdomain.h> 12 #include <linux/io.h> 13 #include <linux/kernel.h> 14 #include <linux/module.h> 15 #include <linux/of.h> 16 #include <linux/of_address.h> 17 #include <linux/of_device.h> 18 #include <linux/of_irq.h> 19 #include <linux/soc/qcom/irq.h> 20 #include <linux/spinlock.h> 21 #include <linux/slab.h> 22 #include <linux/types.h> 23 24 #define PDC_MAX_GPIO_IRQS 256 25 26 #define IRQ_ENABLE_BANK 0x10 27 #define IRQ_i_CFG 0x110 28 29 struct pdc_pin_region { 30 u32 pin_base; 31 u32 parent_base; 32 u32 cnt; 33 }; 34 35 #define pin_to_hwirq(r, p) ((r)->parent_base + (p) - (r)->pin_base) 36 37 static DEFINE_RAW_SPINLOCK(pdc_lock); 38 static void __iomem *pdc_base; 39 static struct pdc_pin_region *pdc_region; 40 static int pdc_region_cnt; 41 42 static void pdc_reg_write(int reg, u32 i, u32 val) 43 { 44 writel_relaxed(val, pdc_base + reg + i * sizeof(u32)); 45 } 46 47 static u32 pdc_reg_read(int reg, u32 i) 48 { 49 return readl_relaxed(pdc_base + reg + i * sizeof(u32)); 50 } 51 52 static void pdc_enable_intr(struct irq_data *d, bool on) 53 { 54 int pin_out = d->hwirq; 55 unsigned long enable; 56 unsigned long flags; 57 u32 index, mask; 58 59 index = pin_out / 32; 60 mask = pin_out % 32; 61 62 raw_spin_lock_irqsave(&pdc_lock, flags); 63 enable = pdc_reg_read(IRQ_ENABLE_BANK, index); 64 __assign_bit(mask, &enable, on); 65 pdc_reg_write(IRQ_ENABLE_BANK, index, enable); 66 raw_spin_unlock_irqrestore(&pdc_lock, flags); 67 } 68 69 static void qcom_pdc_gic_disable(struct irq_data *d) 70 { 71 pdc_enable_intr(d, false); 72 irq_chip_disable_parent(d); 73 } 74 75 static void qcom_pdc_gic_enable(struct irq_data *d) 76 { 77 pdc_enable_intr(d, true); 78 irq_chip_enable_parent(d); 79 } 80 81 /* 82 * GIC does not handle falling edge or active low. To allow falling edge and 83 * active low interrupts to be handled at GIC, PDC has an inverter that inverts 84 * falling edge into a rising edge and active low into an active high. 85 * For the inverter to work, the polarity bit in the IRQ_CONFIG register has to 86 * set as per the table below. 87 * Level sensitive active low LOW 88 * Rising edge sensitive NOT USED 89 * Falling edge sensitive LOW 90 * Dual Edge sensitive NOT USED 91 * Level sensitive active High HIGH 92 * Falling Edge sensitive NOT USED 93 * Rising edge sensitive HIGH 94 * Dual Edge sensitive HIGH 95 */ 96 enum pdc_irq_config_bits { 97 PDC_LEVEL_LOW = 0b000, 98 PDC_EDGE_FALLING = 0b010, 99 PDC_LEVEL_HIGH = 0b100, 100 PDC_EDGE_RISING = 0b110, 101 PDC_EDGE_DUAL = 0b111, 102 }; 103 104 /** 105 * qcom_pdc_gic_set_type: Configure PDC for the interrupt 106 * 107 * @d: the interrupt data 108 * @type: the interrupt type 109 * 110 * If @type is edge triggered, forward that as Rising edge as PDC 111 * takes care of converting falling edge to rising edge signal 112 * If @type is level, then forward that as level high as PDC 113 * takes care of converting falling edge to rising edge signal 114 */ 115 static int qcom_pdc_gic_set_type(struct irq_data *d, unsigned int type) 116 { 117 enum pdc_irq_config_bits pdc_type; 118 enum pdc_irq_config_bits old_pdc_type; 119 int ret; 120 121 switch (type) { 122 case IRQ_TYPE_EDGE_RISING: 123 pdc_type = PDC_EDGE_RISING; 124 break; 125 case IRQ_TYPE_EDGE_FALLING: 126 pdc_type = PDC_EDGE_FALLING; 127 type = IRQ_TYPE_EDGE_RISING; 128 break; 129 case IRQ_TYPE_EDGE_BOTH: 130 pdc_type = PDC_EDGE_DUAL; 131 type = IRQ_TYPE_EDGE_RISING; 132 break; 133 case IRQ_TYPE_LEVEL_HIGH: 134 pdc_type = PDC_LEVEL_HIGH; 135 break; 136 case IRQ_TYPE_LEVEL_LOW: 137 pdc_type = PDC_LEVEL_LOW; 138 type = IRQ_TYPE_LEVEL_HIGH; 139 break; 140 default: 141 WARN_ON(1); 142 return -EINVAL; 143 } 144 145 old_pdc_type = pdc_reg_read(IRQ_i_CFG, d->hwirq); 146 pdc_reg_write(IRQ_i_CFG, d->hwirq, pdc_type); 147 148 ret = irq_chip_set_type_parent(d, type); 149 if (ret) 150 return ret; 151 152 /* 153 * When we change types the PDC can give a phantom interrupt. 154 * Clear it. Specifically the phantom shows up when reconfiguring 155 * polarity of interrupt without changing the state of the signal 156 * but let's be consistent and clear it always. 157 * 158 * Doing this works because we have IRQCHIP_SET_TYPE_MASKED so the 159 * interrupt will be cleared before the rest of the system sees it. 160 */ 161 if (old_pdc_type != pdc_type) 162 irq_chip_set_parent_state(d, IRQCHIP_STATE_PENDING, false); 163 164 return 0; 165 } 166 167 static struct irq_chip qcom_pdc_gic_chip = { 168 .name = "PDC", 169 .irq_eoi = irq_chip_eoi_parent, 170 .irq_mask = irq_chip_mask_parent, 171 .irq_unmask = irq_chip_unmask_parent, 172 .irq_disable = qcom_pdc_gic_disable, 173 .irq_enable = qcom_pdc_gic_enable, 174 .irq_get_irqchip_state = irq_chip_get_parent_state, 175 .irq_set_irqchip_state = irq_chip_set_parent_state, 176 .irq_retrigger = irq_chip_retrigger_hierarchy, 177 .irq_set_type = qcom_pdc_gic_set_type, 178 .flags = IRQCHIP_MASK_ON_SUSPEND | 179 IRQCHIP_SET_TYPE_MASKED | 180 IRQCHIP_SKIP_SET_WAKE | 181 IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND, 182 .irq_set_vcpu_affinity = irq_chip_set_vcpu_affinity_parent, 183 .irq_set_affinity = irq_chip_set_affinity_parent, 184 }; 185 186 static struct pdc_pin_region *get_pin_region(int pin) 187 { 188 int i; 189 190 for (i = 0; i < pdc_region_cnt; i++) { 191 if (pin >= pdc_region[i].pin_base && 192 pin < pdc_region[i].pin_base + pdc_region[i].cnt) 193 return &pdc_region[i]; 194 } 195 196 return NULL; 197 } 198 199 static int qcom_pdc_alloc(struct irq_domain *domain, unsigned int virq, 200 unsigned int nr_irqs, void *data) 201 { 202 struct irq_fwspec *fwspec = data; 203 struct irq_fwspec parent_fwspec; 204 struct pdc_pin_region *region; 205 irq_hw_number_t hwirq; 206 unsigned int type; 207 int ret; 208 209 ret = irq_domain_translate_twocell(domain, fwspec, &hwirq, &type); 210 if (ret) 211 return ret; 212 213 if (hwirq == GPIO_NO_WAKE_IRQ) 214 return irq_domain_disconnect_hierarchy(domain, virq); 215 216 ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq, 217 &qcom_pdc_gic_chip, NULL); 218 if (ret) 219 return ret; 220 221 region = get_pin_region(hwirq); 222 if (!region) 223 return irq_domain_disconnect_hierarchy(domain->parent, virq); 224 225 if (type & IRQ_TYPE_EDGE_BOTH) 226 type = IRQ_TYPE_EDGE_RISING; 227 228 if (type & IRQ_TYPE_LEVEL_MASK) 229 type = IRQ_TYPE_LEVEL_HIGH; 230 231 parent_fwspec.fwnode = domain->parent->fwnode; 232 parent_fwspec.param_count = 3; 233 parent_fwspec.param[0] = 0; 234 parent_fwspec.param[1] = pin_to_hwirq(region, hwirq); 235 parent_fwspec.param[2] = type; 236 237 return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, 238 &parent_fwspec); 239 } 240 241 static const struct irq_domain_ops qcom_pdc_ops = { 242 .translate = irq_domain_translate_twocell, 243 .alloc = qcom_pdc_alloc, 244 .free = irq_domain_free_irqs_common, 245 }; 246 247 static int pdc_setup_pin_mapping(struct device_node *np) 248 { 249 int ret, n, i; 250 u32 irq_index, reg_index, val; 251 252 n = of_property_count_elems_of_size(np, "qcom,pdc-ranges", sizeof(u32)); 253 if (n <= 0 || n % 3) 254 return -EINVAL; 255 256 pdc_region_cnt = n / 3; 257 pdc_region = kcalloc(pdc_region_cnt, sizeof(*pdc_region), GFP_KERNEL); 258 if (!pdc_region) { 259 pdc_region_cnt = 0; 260 return -ENOMEM; 261 } 262 263 for (n = 0; n < pdc_region_cnt; n++) { 264 ret = of_property_read_u32_index(np, "qcom,pdc-ranges", 265 n * 3 + 0, 266 &pdc_region[n].pin_base); 267 if (ret) 268 return ret; 269 ret = of_property_read_u32_index(np, "qcom,pdc-ranges", 270 n * 3 + 1, 271 &pdc_region[n].parent_base); 272 if (ret) 273 return ret; 274 ret = of_property_read_u32_index(np, "qcom,pdc-ranges", 275 n * 3 + 2, 276 &pdc_region[n].cnt); 277 if (ret) 278 return ret; 279 280 for (i = 0; i < pdc_region[n].cnt; i++) { 281 reg_index = (i + pdc_region[n].pin_base) >> 5; 282 irq_index = (i + pdc_region[n].pin_base) & 0x1f; 283 val = pdc_reg_read(IRQ_ENABLE_BANK, reg_index); 284 val &= ~BIT(irq_index); 285 pdc_reg_write(IRQ_ENABLE_BANK, reg_index, val); 286 } 287 } 288 289 return 0; 290 } 291 292 static int qcom_pdc_init(struct device_node *node, struct device_node *parent) 293 { 294 struct irq_domain *parent_domain, *pdc_domain; 295 int ret; 296 297 pdc_base = of_iomap(node, 0); 298 if (!pdc_base) { 299 pr_err("%pOF: unable to map PDC registers\n", node); 300 return -ENXIO; 301 } 302 303 parent_domain = irq_find_host(parent); 304 if (!parent_domain) { 305 pr_err("%pOF: unable to find PDC's parent domain\n", node); 306 ret = -ENXIO; 307 goto fail; 308 } 309 310 ret = pdc_setup_pin_mapping(node); 311 if (ret) { 312 pr_err("%pOF: failed to init PDC pin-hwirq mapping\n", node); 313 goto fail; 314 } 315 316 pdc_domain = irq_domain_create_hierarchy(parent_domain, 317 IRQ_DOMAIN_FLAG_QCOM_PDC_WAKEUP, 318 PDC_MAX_GPIO_IRQS, 319 of_fwnode_handle(node), 320 &qcom_pdc_ops, NULL); 321 if (!pdc_domain) { 322 pr_err("%pOF: PDC domain add failed\n", node); 323 ret = -ENOMEM; 324 goto fail; 325 } 326 327 irq_domain_update_bus_token(pdc_domain, DOMAIN_BUS_WAKEUP); 328 329 return 0; 330 331 fail: 332 kfree(pdc_region); 333 iounmap(pdc_base); 334 return ret; 335 } 336 337 IRQCHIP_PLATFORM_DRIVER_BEGIN(qcom_pdc) 338 IRQCHIP_MATCH("qcom,pdc", qcom_pdc_init) 339 IRQCHIP_PLATFORM_DRIVER_END(qcom_pdc) 340 MODULE_DESCRIPTION("Qualcomm Technologies, Inc. Power Domain Controller"); 341 MODULE_LICENSE("GPL v2"); 342