1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/err.h> 7 #include <linux/init.h> 8 #include <linux/interrupt.h> 9 #include <linux/irq.h> 10 #include <linux/irqchip.h> 11 #include <linux/irqdomain.h> 12 #include <linux/io.h> 13 #include <linux/kernel.h> 14 #include <linux/module.h> 15 #include <linux/of.h> 16 #include <linux/of_address.h> 17 #include <linux/of_device.h> 18 #include <linux/of_irq.h> 19 #include <linux/soc/qcom/irq.h> 20 #include <linux/spinlock.h> 21 #include <linux/slab.h> 22 #include <linux/types.h> 23 24 #define PDC_MAX_GPIO_IRQS 256 25 26 #define CLEAR_INTR(reg, intr) (reg & ~(1 << intr)) 27 #define ENABLE_INTR(reg, intr) (reg | (1 << intr)) 28 29 #define IRQ_ENABLE_BANK 0x10 30 #define IRQ_i_CFG 0x110 31 32 struct pdc_pin_region { 33 u32 pin_base; 34 u32 parent_base; 35 u32 cnt; 36 }; 37 38 #define pin_to_hwirq(r, p) ((r)->parent_base + (p) - (r)->pin_base) 39 40 static DEFINE_RAW_SPINLOCK(pdc_lock); 41 static void __iomem *pdc_base; 42 static struct pdc_pin_region *pdc_region; 43 static int pdc_region_cnt; 44 45 static void pdc_reg_write(int reg, u32 i, u32 val) 46 { 47 writel_relaxed(val, pdc_base + reg + i * sizeof(u32)); 48 } 49 50 static u32 pdc_reg_read(int reg, u32 i) 51 { 52 return readl_relaxed(pdc_base + reg + i * sizeof(u32)); 53 } 54 55 static void pdc_enable_intr(struct irq_data *d, bool on) 56 { 57 int pin_out = d->hwirq; 58 u32 index, mask; 59 u32 enable; 60 61 index = pin_out / 32; 62 mask = pin_out % 32; 63 64 raw_spin_lock(&pdc_lock); 65 enable = pdc_reg_read(IRQ_ENABLE_BANK, index); 66 enable = on ? ENABLE_INTR(enable, mask) : CLEAR_INTR(enable, mask); 67 pdc_reg_write(IRQ_ENABLE_BANK, index, enable); 68 raw_spin_unlock(&pdc_lock); 69 } 70 71 static void qcom_pdc_gic_disable(struct irq_data *d) 72 { 73 pdc_enable_intr(d, false); 74 irq_chip_disable_parent(d); 75 } 76 77 static void qcom_pdc_gic_enable(struct irq_data *d) 78 { 79 pdc_enable_intr(d, true); 80 irq_chip_enable_parent(d); 81 } 82 83 /* 84 * GIC does not handle falling edge or active low. To allow falling edge and 85 * active low interrupts to be handled at GIC, PDC has an inverter that inverts 86 * falling edge into a rising edge and active low into an active high. 87 * For the inverter to work, the polarity bit in the IRQ_CONFIG register has to 88 * set as per the table below. 89 * Level sensitive active low LOW 90 * Rising edge sensitive NOT USED 91 * Falling edge sensitive LOW 92 * Dual Edge sensitive NOT USED 93 * Level sensitive active High HIGH 94 * Falling Edge sensitive NOT USED 95 * Rising edge sensitive HIGH 96 * Dual Edge sensitive HIGH 97 */ 98 enum pdc_irq_config_bits { 99 PDC_LEVEL_LOW = 0b000, 100 PDC_EDGE_FALLING = 0b010, 101 PDC_LEVEL_HIGH = 0b100, 102 PDC_EDGE_RISING = 0b110, 103 PDC_EDGE_DUAL = 0b111, 104 }; 105 106 /** 107 * qcom_pdc_gic_set_type: Configure PDC for the interrupt 108 * 109 * @d: the interrupt data 110 * @type: the interrupt type 111 * 112 * If @type is edge triggered, forward that as Rising edge as PDC 113 * takes care of converting falling edge to rising edge signal 114 * If @type is level, then forward that as level high as PDC 115 * takes care of converting falling edge to rising edge signal 116 */ 117 static int qcom_pdc_gic_set_type(struct irq_data *d, unsigned int type) 118 { 119 enum pdc_irq_config_bits pdc_type; 120 enum pdc_irq_config_bits old_pdc_type; 121 int ret; 122 123 switch (type) { 124 case IRQ_TYPE_EDGE_RISING: 125 pdc_type = PDC_EDGE_RISING; 126 break; 127 case IRQ_TYPE_EDGE_FALLING: 128 pdc_type = PDC_EDGE_FALLING; 129 type = IRQ_TYPE_EDGE_RISING; 130 break; 131 case IRQ_TYPE_EDGE_BOTH: 132 pdc_type = PDC_EDGE_DUAL; 133 type = IRQ_TYPE_EDGE_RISING; 134 break; 135 case IRQ_TYPE_LEVEL_HIGH: 136 pdc_type = PDC_LEVEL_HIGH; 137 break; 138 case IRQ_TYPE_LEVEL_LOW: 139 pdc_type = PDC_LEVEL_LOW; 140 type = IRQ_TYPE_LEVEL_HIGH; 141 break; 142 default: 143 WARN_ON(1); 144 return -EINVAL; 145 } 146 147 old_pdc_type = pdc_reg_read(IRQ_i_CFG, d->hwirq); 148 pdc_reg_write(IRQ_i_CFG, d->hwirq, pdc_type); 149 150 ret = irq_chip_set_type_parent(d, type); 151 if (ret) 152 return ret; 153 154 /* 155 * When we change types the PDC can give a phantom interrupt. 156 * Clear it. Specifically the phantom shows up when reconfiguring 157 * polarity of interrupt without changing the state of the signal 158 * but let's be consistent and clear it always. 159 * 160 * Doing this works because we have IRQCHIP_SET_TYPE_MASKED so the 161 * interrupt will be cleared before the rest of the system sees it. 162 */ 163 if (old_pdc_type != pdc_type) 164 irq_chip_set_parent_state(d, IRQCHIP_STATE_PENDING, false); 165 166 return 0; 167 } 168 169 static struct irq_chip qcom_pdc_gic_chip = { 170 .name = "PDC", 171 .irq_eoi = irq_chip_eoi_parent, 172 .irq_mask = irq_chip_mask_parent, 173 .irq_unmask = irq_chip_unmask_parent, 174 .irq_disable = qcom_pdc_gic_disable, 175 .irq_enable = qcom_pdc_gic_enable, 176 .irq_get_irqchip_state = irq_chip_get_parent_state, 177 .irq_set_irqchip_state = irq_chip_set_parent_state, 178 .irq_retrigger = irq_chip_retrigger_hierarchy, 179 .irq_set_type = qcom_pdc_gic_set_type, 180 .flags = IRQCHIP_MASK_ON_SUSPEND | 181 IRQCHIP_SET_TYPE_MASKED | 182 IRQCHIP_SKIP_SET_WAKE | 183 IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND, 184 .irq_set_vcpu_affinity = irq_chip_set_vcpu_affinity_parent, 185 .irq_set_affinity = irq_chip_set_affinity_parent, 186 }; 187 188 static struct pdc_pin_region *get_pin_region(int pin) 189 { 190 int i; 191 192 for (i = 0; i < pdc_region_cnt; i++) { 193 if (pin >= pdc_region[i].pin_base && 194 pin < pdc_region[i].pin_base + pdc_region[i].cnt) 195 return &pdc_region[i]; 196 } 197 198 return NULL; 199 } 200 201 static int qcom_pdc_translate(struct irq_domain *d, struct irq_fwspec *fwspec, 202 unsigned long *hwirq, unsigned int *type) 203 { 204 if (is_of_node(fwspec->fwnode)) { 205 if (fwspec->param_count != 2) 206 return -EINVAL; 207 208 *hwirq = fwspec->param[0]; 209 *type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK; 210 return 0; 211 } 212 213 return -EINVAL; 214 } 215 216 static int qcom_pdc_alloc(struct irq_domain *domain, unsigned int virq, 217 unsigned int nr_irqs, void *data) 218 { 219 struct irq_fwspec *fwspec = data; 220 struct irq_fwspec parent_fwspec; 221 struct pdc_pin_region *region; 222 irq_hw_number_t hwirq; 223 unsigned int type; 224 int ret; 225 226 ret = qcom_pdc_translate(domain, fwspec, &hwirq, &type); 227 if (ret) 228 return ret; 229 230 if (hwirq == GPIO_NO_WAKE_IRQ) 231 return irq_domain_disconnect_hierarchy(domain, virq); 232 233 ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq, 234 &qcom_pdc_gic_chip, NULL); 235 if (ret) 236 return ret; 237 238 region = get_pin_region(hwirq); 239 if (!region) 240 return irq_domain_disconnect_hierarchy(domain->parent, virq); 241 242 if (type & IRQ_TYPE_EDGE_BOTH) 243 type = IRQ_TYPE_EDGE_RISING; 244 245 if (type & IRQ_TYPE_LEVEL_MASK) 246 type = IRQ_TYPE_LEVEL_HIGH; 247 248 parent_fwspec.fwnode = domain->parent->fwnode; 249 parent_fwspec.param_count = 3; 250 parent_fwspec.param[0] = 0; 251 parent_fwspec.param[1] = pin_to_hwirq(region, hwirq); 252 parent_fwspec.param[2] = type; 253 254 return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, 255 &parent_fwspec); 256 } 257 258 static const struct irq_domain_ops qcom_pdc_ops = { 259 .translate = qcom_pdc_translate, 260 .alloc = qcom_pdc_alloc, 261 .free = irq_domain_free_irqs_common, 262 }; 263 264 static int pdc_setup_pin_mapping(struct device_node *np) 265 { 266 int ret, n, i; 267 u32 irq_index, reg_index, val; 268 269 n = of_property_count_elems_of_size(np, "qcom,pdc-ranges", sizeof(u32)); 270 if (n <= 0 || n % 3) 271 return -EINVAL; 272 273 pdc_region_cnt = n / 3; 274 pdc_region = kcalloc(pdc_region_cnt, sizeof(*pdc_region), GFP_KERNEL); 275 if (!pdc_region) { 276 pdc_region_cnt = 0; 277 return -ENOMEM; 278 } 279 280 for (n = 0; n < pdc_region_cnt; n++) { 281 ret = of_property_read_u32_index(np, "qcom,pdc-ranges", 282 n * 3 + 0, 283 &pdc_region[n].pin_base); 284 if (ret) 285 return ret; 286 ret = of_property_read_u32_index(np, "qcom,pdc-ranges", 287 n * 3 + 1, 288 &pdc_region[n].parent_base); 289 if (ret) 290 return ret; 291 ret = of_property_read_u32_index(np, "qcom,pdc-ranges", 292 n * 3 + 2, 293 &pdc_region[n].cnt); 294 if (ret) 295 return ret; 296 297 for (i = 0; i < pdc_region[n].cnt; i++) { 298 reg_index = (i + pdc_region[n].pin_base) >> 5; 299 irq_index = (i + pdc_region[n].pin_base) & 0x1f; 300 val = pdc_reg_read(IRQ_ENABLE_BANK, reg_index); 301 val &= ~BIT(irq_index); 302 pdc_reg_write(IRQ_ENABLE_BANK, reg_index, val); 303 } 304 } 305 306 return 0; 307 } 308 309 static int qcom_pdc_init(struct device_node *node, struct device_node *parent) 310 { 311 struct irq_domain *parent_domain, *pdc_domain; 312 int ret; 313 314 pdc_base = of_iomap(node, 0); 315 if (!pdc_base) { 316 pr_err("%pOF: unable to map PDC registers\n", node); 317 return -ENXIO; 318 } 319 320 parent_domain = irq_find_host(parent); 321 if (!parent_domain) { 322 pr_err("%pOF: unable to find PDC's parent domain\n", node); 323 ret = -ENXIO; 324 goto fail; 325 } 326 327 ret = pdc_setup_pin_mapping(node); 328 if (ret) { 329 pr_err("%pOF: failed to init PDC pin-hwirq mapping\n", node); 330 goto fail; 331 } 332 333 pdc_domain = irq_domain_create_hierarchy(parent_domain, 334 IRQ_DOMAIN_FLAG_QCOM_PDC_WAKEUP, 335 PDC_MAX_GPIO_IRQS, 336 of_fwnode_handle(node), 337 &qcom_pdc_ops, NULL); 338 if (!pdc_domain) { 339 pr_err("%pOF: PDC domain add failed\n", node); 340 ret = -ENOMEM; 341 goto fail; 342 } 343 344 irq_domain_update_bus_token(pdc_domain, DOMAIN_BUS_WAKEUP); 345 346 return 0; 347 348 fail: 349 kfree(pdc_region); 350 iounmap(pdc_base); 351 return ret; 352 } 353 354 IRQCHIP_PLATFORM_DRIVER_BEGIN(qcom_pdc) 355 IRQCHIP_MATCH("qcom,pdc", qcom_pdc_init) 356 IRQCHIP_PLATFORM_DRIVER_END(qcom_pdc) 357 MODULE_DESCRIPTION("Qualcomm Technologies, Inc. Power Domain Controller"); 358 MODULE_LICENSE("GPL v2"); 359