1f55c73aeSArchana Sathyakumar // SPDX-License-Identifier: GPL-2.0 2f55c73aeSArchana Sathyakumar /* 3b2bb01edSLina Iyer * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. 4f55c73aeSArchana Sathyakumar */ 5f55c73aeSArchana Sathyakumar 6f55c73aeSArchana Sathyakumar #include <linux/err.h> 7f55c73aeSArchana Sathyakumar #include <linux/init.h> 8e71374c0SMaulik Shah #include <linux/interrupt.h> 9f55c73aeSArchana Sathyakumar #include <linux/irq.h> 10f55c73aeSArchana Sathyakumar #include <linux/irqchip.h> 11f55c73aeSArchana Sathyakumar #include <linux/irqdomain.h> 12f55c73aeSArchana Sathyakumar #include <linux/io.h> 13f55c73aeSArchana Sathyakumar #include <linux/kernel.h> 144acd8a4bSSaravana Kannan #include <linux/module.h> 15f55c73aeSArchana Sathyakumar #include <linux/of.h> 16f55c73aeSArchana Sathyakumar #include <linux/of_address.h> 17f55c73aeSArchana Sathyakumar #include <linux/of_device.h> 184acd8a4bSSaravana Kannan #include <linux/of_irq.h> 1981ef8bf8SLina Iyer #include <linux/soc/qcom/irq.h> 20f55c73aeSArchana Sathyakumar #include <linux/spinlock.h> 21f55c73aeSArchana Sathyakumar #include <linux/slab.h> 22f55c73aeSArchana Sathyakumar #include <linux/types.h> 23f55c73aeSArchana Sathyakumar 2481ef8bf8SLina Iyer #define PDC_MAX_GPIO_IRQS 256 25f55c73aeSArchana Sathyakumar 26f55c73aeSArchana Sathyakumar #define CLEAR_INTR(reg, intr) (reg & ~(1 << intr)) 27f55c73aeSArchana Sathyakumar #define ENABLE_INTR(reg, intr) (reg | (1 << intr)) 28f55c73aeSArchana Sathyakumar 29f55c73aeSArchana Sathyakumar #define IRQ_ENABLE_BANK 0x10 30f55c73aeSArchana Sathyakumar #define IRQ_i_CFG 0x110 31f55c73aeSArchana Sathyakumar 32f55c73aeSArchana Sathyakumar struct pdc_pin_region { 33f55c73aeSArchana Sathyakumar u32 pin_base; 34f55c73aeSArchana Sathyakumar u32 parent_base; 35f55c73aeSArchana Sathyakumar u32 cnt; 36f55c73aeSArchana Sathyakumar }; 37f55c73aeSArchana Sathyakumar 388d4c9989SMarc Zyngier #define pin_to_hwirq(r, p) ((r)->parent_base + (p) - (r)->pin_base) 398d4c9989SMarc Zyngier 40f55c73aeSArchana Sathyakumar static DEFINE_RAW_SPINLOCK(pdc_lock); 41f55c73aeSArchana Sathyakumar static void __iomem *pdc_base; 42f55c73aeSArchana Sathyakumar static struct pdc_pin_region *pdc_region; 43f55c73aeSArchana Sathyakumar static int pdc_region_cnt; 44f55c73aeSArchana Sathyakumar 45f55c73aeSArchana Sathyakumar static void pdc_reg_write(int reg, u32 i, u32 val) 46f55c73aeSArchana Sathyakumar { 47f55c73aeSArchana Sathyakumar writel_relaxed(val, pdc_base + reg + i * sizeof(u32)); 48f55c73aeSArchana Sathyakumar } 49f55c73aeSArchana Sathyakumar 50f55c73aeSArchana Sathyakumar static u32 pdc_reg_read(int reg, u32 i) 51f55c73aeSArchana Sathyakumar { 52f55c73aeSArchana Sathyakumar return readl_relaxed(pdc_base + reg + i * sizeof(u32)); 53f55c73aeSArchana Sathyakumar } 54f55c73aeSArchana Sathyakumar 55f55c73aeSArchana Sathyakumar static void pdc_enable_intr(struct irq_data *d, bool on) 56f55c73aeSArchana Sathyakumar { 57f55c73aeSArchana Sathyakumar int pin_out = d->hwirq; 58f55c73aeSArchana Sathyakumar u32 index, mask; 59f55c73aeSArchana Sathyakumar u32 enable; 60f55c73aeSArchana Sathyakumar 61f55c73aeSArchana Sathyakumar index = pin_out / 32; 62f55c73aeSArchana Sathyakumar mask = pin_out % 32; 63f55c73aeSArchana Sathyakumar 64f55c73aeSArchana Sathyakumar raw_spin_lock(&pdc_lock); 65f55c73aeSArchana Sathyakumar enable = pdc_reg_read(IRQ_ENABLE_BANK, index); 66f55c73aeSArchana Sathyakumar enable = on ? ENABLE_INTR(enable, mask) : CLEAR_INTR(enable, mask); 67f55c73aeSArchana Sathyakumar pdc_reg_write(IRQ_ENABLE_BANK, index, enable); 68f55c73aeSArchana Sathyakumar raw_spin_unlock(&pdc_lock); 69f55c73aeSArchana Sathyakumar } 70f55c73aeSArchana Sathyakumar 71da3f875aSLina Iyer static void qcom_pdc_gic_disable(struct irq_data *d) 72f55c73aeSArchana Sathyakumar { 73f55c73aeSArchana Sathyakumar pdc_enable_intr(d, false); 74da3f875aSLina Iyer irq_chip_disable_parent(d); 75da3f875aSLina Iyer } 76da3f875aSLina Iyer 77da3f875aSLina Iyer static void qcom_pdc_gic_enable(struct irq_data *d) 78da3f875aSLina Iyer { 79da3f875aSLina Iyer pdc_enable_intr(d, true); 80da3f875aSLina Iyer irq_chip_enable_parent(d); 81da3f875aSLina Iyer } 82da3f875aSLina Iyer 83f55c73aeSArchana Sathyakumar /* 84f55c73aeSArchana Sathyakumar * GIC does not handle falling edge or active low. To allow falling edge and 85f55c73aeSArchana Sathyakumar * active low interrupts to be handled at GIC, PDC has an inverter that inverts 86f55c73aeSArchana Sathyakumar * falling edge into a rising edge and active low into an active high. 87f55c73aeSArchana Sathyakumar * For the inverter to work, the polarity bit in the IRQ_CONFIG register has to 88f55c73aeSArchana Sathyakumar * set as per the table below. 89f55c73aeSArchana Sathyakumar * Level sensitive active low LOW 90f55c73aeSArchana Sathyakumar * Rising edge sensitive NOT USED 91f55c73aeSArchana Sathyakumar * Falling edge sensitive LOW 92f55c73aeSArchana Sathyakumar * Dual Edge sensitive NOT USED 93f55c73aeSArchana Sathyakumar * Level sensitive active High HIGH 94f55c73aeSArchana Sathyakumar * Falling Edge sensitive NOT USED 95f55c73aeSArchana Sathyakumar * Rising edge sensitive HIGH 96f55c73aeSArchana Sathyakumar * Dual Edge sensitive HIGH 97f55c73aeSArchana Sathyakumar */ 98f55c73aeSArchana Sathyakumar enum pdc_irq_config_bits { 99f55c73aeSArchana Sathyakumar PDC_LEVEL_LOW = 0b000, 100f55c73aeSArchana Sathyakumar PDC_EDGE_FALLING = 0b010, 101f55c73aeSArchana Sathyakumar PDC_LEVEL_HIGH = 0b100, 102f55c73aeSArchana Sathyakumar PDC_EDGE_RISING = 0b110, 103f55c73aeSArchana Sathyakumar PDC_EDGE_DUAL = 0b111, 104f55c73aeSArchana Sathyakumar }; 105f55c73aeSArchana Sathyakumar 106f55c73aeSArchana Sathyakumar /** 107f55c73aeSArchana Sathyakumar * qcom_pdc_gic_set_type: Configure PDC for the interrupt 108f55c73aeSArchana Sathyakumar * 109f55c73aeSArchana Sathyakumar * @d: the interrupt data 110f55c73aeSArchana Sathyakumar * @type: the interrupt type 111f55c73aeSArchana Sathyakumar * 112f55c73aeSArchana Sathyakumar * If @type is edge triggered, forward that as Rising edge as PDC 113f55c73aeSArchana Sathyakumar * takes care of converting falling edge to rising edge signal 114f55c73aeSArchana Sathyakumar * If @type is level, then forward that as level high as PDC 115f55c73aeSArchana Sathyakumar * takes care of converting falling edge to rising edge signal 116f55c73aeSArchana Sathyakumar */ 117f55c73aeSArchana Sathyakumar static int qcom_pdc_gic_set_type(struct irq_data *d, unsigned int type) 118f55c73aeSArchana Sathyakumar { 119f55c73aeSArchana Sathyakumar enum pdc_irq_config_bits pdc_type; 1202f5fbc43SDouglas Anderson enum pdc_irq_config_bits old_pdc_type; 1212f5fbc43SDouglas Anderson int ret; 122f55c73aeSArchana Sathyakumar 123f55c73aeSArchana Sathyakumar switch (type) { 124f55c73aeSArchana Sathyakumar case IRQ_TYPE_EDGE_RISING: 125f55c73aeSArchana Sathyakumar pdc_type = PDC_EDGE_RISING; 126f55c73aeSArchana Sathyakumar break; 127f55c73aeSArchana Sathyakumar case IRQ_TYPE_EDGE_FALLING: 128f55c73aeSArchana Sathyakumar pdc_type = PDC_EDGE_FALLING; 129f55c73aeSArchana Sathyakumar type = IRQ_TYPE_EDGE_RISING; 130f55c73aeSArchana Sathyakumar break; 131f55c73aeSArchana Sathyakumar case IRQ_TYPE_EDGE_BOTH: 132f55c73aeSArchana Sathyakumar pdc_type = PDC_EDGE_DUAL; 1337bae48b2SLina Iyer type = IRQ_TYPE_EDGE_RISING; 134f55c73aeSArchana Sathyakumar break; 135f55c73aeSArchana Sathyakumar case IRQ_TYPE_LEVEL_HIGH: 136f55c73aeSArchana Sathyakumar pdc_type = PDC_LEVEL_HIGH; 137f55c73aeSArchana Sathyakumar break; 138f55c73aeSArchana Sathyakumar case IRQ_TYPE_LEVEL_LOW: 139f55c73aeSArchana Sathyakumar pdc_type = PDC_LEVEL_LOW; 140f55c73aeSArchana Sathyakumar type = IRQ_TYPE_LEVEL_HIGH; 141f55c73aeSArchana Sathyakumar break; 142f55c73aeSArchana Sathyakumar default: 143f55c73aeSArchana Sathyakumar WARN_ON(1); 144f55c73aeSArchana Sathyakumar return -EINVAL; 145f55c73aeSArchana Sathyakumar } 146f55c73aeSArchana Sathyakumar 1479d4f24bfSMarc Zyngier old_pdc_type = pdc_reg_read(IRQ_i_CFG, d->hwirq); 1489d4f24bfSMarc Zyngier pdc_reg_write(IRQ_i_CFG, d->hwirq, pdc_type); 149f55c73aeSArchana Sathyakumar 1502f5fbc43SDouglas Anderson ret = irq_chip_set_type_parent(d, type); 1512f5fbc43SDouglas Anderson if (ret) 1522f5fbc43SDouglas Anderson return ret; 1532f5fbc43SDouglas Anderson 1542f5fbc43SDouglas Anderson /* 1552f5fbc43SDouglas Anderson * When we change types the PDC can give a phantom interrupt. 1562f5fbc43SDouglas Anderson * Clear it. Specifically the phantom shows up when reconfiguring 1572f5fbc43SDouglas Anderson * polarity of interrupt without changing the state of the signal 1582f5fbc43SDouglas Anderson * but let's be consistent and clear it always. 1592f5fbc43SDouglas Anderson * 1602f5fbc43SDouglas Anderson * Doing this works because we have IRQCHIP_SET_TYPE_MASKED so the 1612f5fbc43SDouglas Anderson * interrupt will be cleared before the rest of the system sees it. 1622f5fbc43SDouglas Anderson */ 1632f5fbc43SDouglas Anderson if (old_pdc_type != pdc_type) 1642f5fbc43SDouglas Anderson irq_chip_set_parent_state(d, IRQCHIP_STATE_PENDING, false); 1652f5fbc43SDouglas Anderson 1662f5fbc43SDouglas Anderson return 0; 167f55c73aeSArchana Sathyakumar } 168f55c73aeSArchana Sathyakumar 169f55c73aeSArchana Sathyakumar static struct irq_chip qcom_pdc_gic_chip = { 170f55c73aeSArchana Sathyakumar .name = "PDC", 171f55c73aeSArchana Sathyakumar .irq_eoi = irq_chip_eoi_parent, 1729d4f24bfSMarc Zyngier .irq_mask = irq_chip_mask_parent, 1739d4f24bfSMarc Zyngier .irq_unmask = irq_chip_unmask_parent, 174da3f875aSLina Iyer .irq_disable = qcom_pdc_gic_disable, 175da3f875aSLina Iyer .irq_enable = qcom_pdc_gic_enable, 1769d4f24bfSMarc Zyngier .irq_get_irqchip_state = irq_chip_get_parent_state, 1779d4f24bfSMarc Zyngier .irq_set_irqchip_state = irq_chip_set_parent_state, 178f55c73aeSArchana Sathyakumar .irq_retrigger = irq_chip_retrigger_hierarchy, 179f55c73aeSArchana Sathyakumar .irq_set_type = qcom_pdc_gic_set_type, 180f55c73aeSArchana Sathyakumar .flags = IRQCHIP_MASK_ON_SUSPEND | 181f55c73aeSArchana Sathyakumar IRQCHIP_SET_TYPE_MASKED | 182299d7890SMaulik Shah IRQCHIP_SKIP_SET_WAKE | 183299d7890SMaulik Shah IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND, 184f55c73aeSArchana Sathyakumar .irq_set_vcpu_affinity = irq_chip_set_vcpu_affinity_parent, 185f55c73aeSArchana Sathyakumar .irq_set_affinity = irq_chip_set_affinity_parent, 186f55c73aeSArchana Sathyakumar }; 187f55c73aeSArchana Sathyakumar 1888d4c9989SMarc Zyngier static struct pdc_pin_region *get_pin_region(int pin) 189f55c73aeSArchana Sathyakumar { 190f55c73aeSArchana Sathyakumar int i; 191f55c73aeSArchana Sathyakumar 192f55c73aeSArchana Sathyakumar for (i = 0; i < pdc_region_cnt; i++) { 1938d4c9989SMarc Zyngier if (pin >= pdc_region[i].pin_base && 1948d4c9989SMarc Zyngier pin < pdc_region[i].pin_base + pdc_region[i].cnt) 1958d4c9989SMarc Zyngier return &pdc_region[i]; 196f55c73aeSArchana Sathyakumar } 197f55c73aeSArchana Sathyakumar 1988d4c9989SMarc Zyngier return NULL; 199f55c73aeSArchana Sathyakumar } 200f55c73aeSArchana Sathyakumar 201f55c73aeSArchana Sathyakumar static int qcom_pdc_alloc(struct irq_domain *domain, unsigned int virq, 202f55c73aeSArchana Sathyakumar unsigned int nr_irqs, void *data) 203f55c73aeSArchana Sathyakumar { 204f55c73aeSArchana Sathyakumar struct irq_fwspec *fwspec = data; 205f55c73aeSArchana Sathyakumar struct irq_fwspec parent_fwspec; 2068d4c9989SMarc Zyngier struct pdc_pin_region *region; 2078d4c9989SMarc Zyngier irq_hw_number_t hwirq; 208f55c73aeSArchana Sathyakumar unsigned int type; 209f55c73aeSArchana Sathyakumar int ret; 210f55c73aeSArchana Sathyakumar 211*d494d088SMarc Zyngier ret = irq_domain_translate_twocell(domain, fwspec, &hwirq, &type); 212f55c73aeSArchana Sathyakumar if (ret) 21381ef8bf8SLina Iyer return ret; 214f55c73aeSArchana Sathyakumar 2159d4f24bfSMarc Zyngier if (hwirq == GPIO_NO_WAKE_IRQ) 2169d4f24bfSMarc Zyngier return irq_domain_disconnect_hierarchy(domain, virq); 2179d4f24bfSMarc Zyngier 21881ef8bf8SLina Iyer ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq, 21981ef8bf8SLina Iyer &qcom_pdc_gic_chip, NULL); 22081ef8bf8SLina Iyer if (ret) 22181ef8bf8SLina Iyer return ret; 22281ef8bf8SLina Iyer 2238d4c9989SMarc Zyngier region = get_pin_region(hwirq); 2248d4c9989SMarc Zyngier if (!region) 2259d4f24bfSMarc Zyngier return irq_domain_disconnect_hierarchy(domain->parent, virq); 22681ef8bf8SLina Iyer 22781ef8bf8SLina Iyer if (type & IRQ_TYPE_EDGE_BOTH) 22881ef8bf8SLina Iyer type = IRQ_TYPE_EDGE_RISING; 22981ef8bf8SLina Iyer 23081ef8bf8SLina Iyer if (type & IRQ_TYPE_LEVEL_MASK) 23181ef8bf8SLina Iyer type = IRQ_TYPE_LEVEL_HIGH; 23281ef8bf8SLina Iyer 23381ef8bf8SLina Iyer parent_fwspec.fwnode = domain->parent->fwnode; 23481ef8bf8SLina Iyer parent_fwspec.param_count = 3; 23581ef8bf8SLina Iyer parent_fwspec.param[0] = 0; 2368d4c9989SMarc Zyngier parent_fwspec.param[1] = pin_to_hwirq(region, hwirq); 23781ef8bf8SLina Iyer parent_fwspec.param[2] = type; 23881ef8bf8SLina Iyer 23981ef8bf8SLina Iyer return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, 24081ef8bf8SLina Iyer &parent_fwspec); 24181ef8bf8SLina Iyer } 24281ef8bf8SLina Iyer 2434dc70713SMarc Zyngier static const struct irq_domain_ops qcom_pdc_ops = { 244*d494d088SMarc Zyngier .translate = irq_domain_translate_twocell, 2454dc70713SMarc Zyngier .alloc = qcom_pdc_alloc, 24681ef8bf8SLina Iyer .free = irq_domain_free_irqs_common, 24781ef8bf8SLina Iyer }; 24881ef8bf8SLina Iyer 249f55c73aeSArchana Sathyakumar static int pdc_setup_pin_mapping(struct device_node *np) 250f55c73aeSArchana Sathyakumar { 251d7bc63faSMaulik Shah int ret, n, i; 252d7bc63faSMaulik Shah u32 irq_index, reg_index, val; 253f55c73aeSArchana Sathyakumar 254f55c73aeSArchana Sathyakumar n = of_property_count_elems_of_size(np, "qcom,pdc-ranges", sizeof(u32)); 255f55c73aeSArchana Sathyakumar if (n <= 0 || n % 3) 256f55c73aeSArchana Sathyakumar return -EINVAL; 257f55c73aeSArchana Sathyakumar 258f55c73aeSArchana Sathyakumar pdc_region_cnt = n / 3; 259f55c73aeSArchana Sathyakumar pdc_region = kcalloc(pdc_region_cnt, sizeof(*pdc_region), GFP_KERNEL); 260f55c73aeSArchana Sathyakumar if (!pdc_region) { 261f55c73aeSArchana Sathyakumar pdc_region_cnt = 0; 262f55c73aeSArchana Sathyakumar return -ENOMEM; 263f55c73aeSArchana Sathyakumar } 264f55c73aeSArchana Sathyakumar 265f55c73aeSArchana Sathyakumar for (n = 0; n < pdc_region_cnt; n++) { 266f55c73aeSArchana Sathyakumar ret = of_property_read_u32_index(np, "qcom,pdc-ranges", 267f55c73aeSArchana Sathyakumar n * 3 + 0, 268f55c73aeSArchana Sathyakumar &pdc_region[n].pin_base); 269f55c73aeSArchana Sathyakumar if (ret) 270f55c73aeSArchana Sathyakumar return ret; 271f55c73aeSArchana Sathyakumar ret = of_property_read_u32_index(np, "qcom,pdc-ranges", 272f55c73aeSArchana Sathyakumar n * 3 + 1, 273f55c73aeSArchana Sathyakumar &pdc_region[n].parent_base); 274f55c73aeSArchana Sathyakumar if (ret) 275f55c73aeSArchana Sathyakumar return ret; 276f55c73aeSArchana Sathyakumar ret = of_property_read_u32_index(np, "qcom,pdc-ranges", 277f55c73aeSArchana Sathyakumar n * 3 + 2, 278f55c73aeSArchana Sathyakumar &pdc_region[n].cnt); 279f55c73aeSArchana Sathyakumar if (ret) 280f55c73aeSArchana Sathyakumar return ret; 281d7bc63faSMaulik Shah 282d7bc63faSMaulik Shah for (i = 0; i < pdc_region[n].cnt; i++) { 283d7bc63faSMaulik Shah reg_index = (i + pdc_region[n].pin_base) >> 5; 284d7bc63faSMaulik Shah irq_index = (i + pdc_region[n].pin_base) & 0x1f; 285d7bc63faSMaulik Shah val = pdc_reg_read(IRQ_ENABLE_BANK, reg_index); 286d7bc63faSMaulik Shah val &= ~BIT(irq_index); 287d7bc63faSMaulik Shah pdc_reg_write(IRQ_ENABLE_BANK, reg_index, val); 288d7bc63faSMaulik Shah } 289f55c73aeSArchana Sathyakumar } 290f55c73aeSArchana Sathyakumar 291f55c73aeSArchana Sathyakumar return 0; 292f55c73aeSArchana Sathyakumar } 293f55c73aeSArchana Sathyakumar 294f55c73aeSArchana Sathyakumar static int qcom_pdc_init(struct device_node *node, struct device_node *parent) 295f55c73aeSArchana Sathyakumar { 2964dc70713SMarc Zyngier struct irq_domain *parent_domain, *pdc_domain; 297f55c73aeSArchana Sathyakumar int ret; 298f55c73aeSArchana Sathyakumar 299f55c73aeSArchana Sathyakumar pdc_base = of_iomap(node, 0); 300f55c73aeSArchana Sathyakumar if (!pdc_base) { 301f55c73aeSArchana Sathyakumar pr_err("%pOF: unable to map PDC registers\n", node); 302f55c73aeSArchana Sathyakumar return -ENXIO; 303f55c73aeSArchana Sathyakumar } 304f55c73aeSArchana Sathyakumar 305f55c73aeSArchana Sathyakumar parent_domain = irq_find_host(parent); 306f55c73aeSArchana Sathyakumar if (!parent_domain) { 307f55c73aeSArchana Sathyakumar pr_err("%pOF: unable to find PDC's parent domain\n", node); 308f55c73aeSArchana Sathyakumar ret = -ENXIO; 309f55c73aeSArchana Sathyakumar goto fail; 310f55c73aeSArchana Sathyakumar } 311f55c73aeSArchana Sathyakumar 312f55c73aeSArchana Sathyakumar ret = pdc_setup_pin_mapping(node); 313f55c73aeSArchana Sathyakumar if (ret) { 314f55c73aeSArchana Sathyakumar pr_err("%pOF: failed to init PDC pin-hwirq mapping\n", node); 315f55c73aeSArchana Sathyakumar goto fail; 316f55c73aeSArchana Sathyakumar } 317f55c73aeSArchana Sathyakumar 3184dc70713SMarc Zyngier pdc_domain = irq_domain_create_hierarchy(parent_domain, 3194dc70713SMarc Zyngier IRQ_DOMAIN_FLAG_QCOM_PDC_WAKEUP, 3204dc70713SMarc Zyngier PDC_MAX_GPIO_IRQS, 321f55c73aeSArchana Sathyakumar of_fwnode_handle(node), 322f55c73aeSArchana Sathyakumar &qcom_pdc_ops, NULL); 323f55c73aeSArchana Sathyakumar if (!pdc_domain) { 3244dc70713SMarc Zyngier pr_err("%pOF: PDC domain add failed\n", node); 325f55c73aeSArchana Sathyakumar ret = -ENOMEM; 326f55c73aeSArchana Sathyakumar goto fail; 327f55c73aeSArchana Sathyakumar } 328f55c73aeSArchana Sathyakumar 3294dc70713SMarc Zyngier irq_domain_update_bus_token(pdc_domain, DOMAIN_BUS_WAKEUP); 33081ef8bf8SLina Iyer 331f55c73aeSArchana Sathyakumar return 0; 332f55c73aeSArchana Sathyakumar 333f55c73aeSArchana Sathyakumar fail: 334f55c73aeSArchana Sathyakumar kfree(pdc_region); 335f55c73aeSArchana Sathyakumar iounmap(pdc_base); 336f55c73aeSArchana Sathyakumar return ret; 337f55c73aeSArchana Sathyakumar } 338f55c73aeSArchana Sathyakumar 3394acd8a4bSSaravana Kannan IRQCHIP_PLATFORM_DRIVER_BEGIN(qcom_pdc) 3404acd8a4bSSaravana Kannan IRQCHIP_MATCH("qcom,pdc", qcom_pdc_init) 3414acd8a4bSSaravana Kannan IRQCHIP_PLATFORM_DRIVER_END(qcom_pdc) 3424acd8a4bSSaravana Kannan MODULE_DESCRIPTION("Qualcomm Technologies, Inc. Power Domain Controller"); 3434acd8a4bSSaravana Kannan MODULE_LICENSE("GPL v2"); 344