1f55c73aeSArchana Sathyakumar // SPDX-License-Identifier: GPL-2.0 2f55c73aeSArchana Sathyakumar /* 3b2bb01edSLina Iyer * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. 4f55c73aeSArchana Sathyakumar */ 5f55c73aeSArchana Sathyakumar 6f55c73aeSArchana Sathyakumar #include <linux/err.h> 7f55c73aeSArchana Sathyakumar #include <linux/init.h> 8e71374c0SMaulik Shah #include <linux/interrupt.h> 9f55c73aeSArchana Sathyakumar #include <linux/irq.h> 10f55c73aeSArchana Sathyakumar #include <linux/irqchip.h> 11f55c73aeSArchana Sathyakumar #include <linux/irqdomain.h> 12f55c73aeSArchana Sathyakumar #include <linux/io.h> 13f55c73aeSArchana Sathyakumar #include <linux/kernel.h> 144acd8a4bSSaravana Kannan #include <linux/module.h> 15f55c73aeSArchana Sathyakumar #include <linux/of.h> 16f55c73aeSArchana Sathyakumar #include <linux/of_address.h> 17f55c73aeSArchana Sathyakumar #include <linux/of_device.h> 184acd8a4bSSaravana Kannan #include <linux/of_irq.h> 1981ef8bf8SLina Iyer #include <linux/soc/qcom/irq.h> 20f55c73aeSArchana Sathyakumar #include <linux/spinlock.h> 21f55c73aeSArchana Sathyakumar #include <linux/slab.h> 22f55c73aeSArchana Sathyakumar #include <linux/types.h> 23f55c73aeSArchana Sathyakumar 24b2bb01edSLina Iyer #define PDC_MAX_IRQS 168 2581ef8bf8SLina Iyer #define PDC_MAX_GPIO_IRQS 256 26f55c73aeSArchana Sathyakumar 27f55c73aeSArchana Sathyakumar #define CLEAR_INTR(reg, intr) (reg & ~(1 << intr)) 28f55c73aeSArchana Sathyakumar #define ENABLE_INTR(reg, intr) (reg | (1 << intr)) 29f55c73aeSArchana Sathyakumar 30f55c73aeSArchana Sathyakumar #define IRQ_ENABLE_BANK 0x10 31f55c73aeSArchana Sathyakumar #define IRQ_i_CFG 0x110 32f55c73aeSArchana Sathyakumar 33f55c73aeSArchana Sathyakumar struct pdc_pin_region { 34f55c73aeSArchana Sathyakumar u32 pin_base; 35f55c73aeSArchana Sathyakumar u32 parent_base; 36f55c73aeSArchana Sathyakumar u32 cnt; 37f55c73aeSArchana Sathyakumar }; 38f55c73aeSArchana Sathyakumar 39*8d4c9989SMarc Zyngier #define pin_to_hwirq(r, p) ((r)->parent_base + (p) - (r)->pin_base) 40*8d4c9989SMarc Zyngier 41f55c73aeSArchana Sathyakumar static DEFINE_RAW_SPINLOCK(pdc_lock); 42f55c73aeSArchana Sathyakumar static void __iomem *pdc_base; 43f55c73aeSArchana Sathyakumar static struct pdc_pin_region *pdc_region; 44f55c73aeSArchana Sathyakumar static int pdc_region_cnt; 45f55c73aeSArchana Sathyakumar 46f55c73aeSArchana Sathyakumar static void pdc_reg_write(int reg, u32 i, u32 val) 47f55c73aeSArchana Sathyakumar { 48f55c73aeSArchana Sathyakumar writel_relaxed(val, pdc_base + reg + i * sizeof(u32)); 49f55c73aeSArchana Sathyakumar } 50f55c73aeSArchana Sathyakumar 51f55c73aeSArchana Sathyakumar static u32 pdc_reg_read(int reg, u32 i) 52f55c73aeSArchana Sathyakumar { 53f55c73aeSArchana Sathyakumar return readl_relaxed(pdc_base + reg + i * sizeof(u32)); 54f55c73aeSArchana Sathyakumar } 55f55c73aeSArchana Sathyakumar 56f55c73aeSArchana Sathyakumar static void pdc_enable_intr(struct irq_data *d, bool on) 57f55c73aeSArchana Sathyakumar { 58f55c73aeSArchana Sathyakumar int pin_out = d->hwirq; 59f55c73aeSArchana Sathyakumar u32 index, mask; 60f55c73aeSArchana Sathyakumar u32 enable; 61f55c73aeSArchana Sathyakumar 62f55c73aeSArchana Sathyakumar index = pin_out / 32; 63f55c73aeSArchana Sathyakumar mask = pin_out % 32; 64f55c73aeSArchana Sathyakumar 65f55c73aeSArchana Sathyakumar raw_spin_lock(&pdc_lock); 66f55c73aeSArchana Sathyakumar enable = pdc_reg_read(IRQ_ENABLE_BANK, index); 67f55c73aeSArchana Sathyakumar enable = on ? ENABLE_INTR(enable, mask) : CLEAR_INTR(enable, mask); 68f55c73aeSArchana Sathyakumar pdc_reg_write(IRQ_ENABLE_BANK, index, enable); 69f55c73aeSArchana Sathyakumar raw_spin_unlock(&pdc_lock); 70f55c73aeSArchana Sathyakumar } 71f55c73aeSArchana Sathyakumar 72da3f875aSLina Iyer static void qcom_pdc_gic_disable(struct irq_data *d) 73f55c73aeSArchana Sathyakumar { 74f55c73aeSArchana Sathyakumar pdc_enable_intr(d, false); 75da3f875aSLina Iyer irq_chip_disable_parent(d); 76da3f875aSLina Iyer } 77da3f875aSLina Iyer 78da3f875aSLina Iyer static void qcom_pdc_gic_enable(struct irq_data *d) 79da3f875aSLina Iyer { 80da3f875aSLina Iyer pdc_enable_intr(d, true); 81da3f875aSLina Iyer irq_chip_enable_parent(d); 82da3f875aSLina Iyer } 83da3f875aSLina Iyer 84f55c73aeSArchana Sathyakumar /* 85f55c73aeSArchana Sathyakumar * GIC does not handle falling edge or active low. To allow falling edge and 86f55c73aeSArchana Sathyakumar * active low interrupts to be handled at GIC, PDC has an inverter that inverts 87f55c73aeSArchana Sathyakumar * falling edge into a rising edge and active low into an active high. 88f55c73aeSArchana Sathyakumar * For the inverter to work, the polarity bit in the IRQ_CONFIG register has to 89f55c73aeSArchana Sathyakumar * set as per the table below. 90f55c73aeSArchana Sathyakumar * Level sensitive active low LOW 91f55c73aeSArchana Sathyakumar * Rising edge sensitive NOT USED 92f55c73aeSArchana Sathyakumar * Falling edge sensitive LOW 93f55c73aeSArchana Sathyakumar * Dual Edge sensitive NOT USED 94f55c73aeSArchana Sathyakumar * Level sensitive active High HIGH 95f55c73aeSArchana Sathyakumar * Falling Edge sensitive NOT USED 96f55c73aeSArchana Sathyakumar * Rising edge sensitive HIGH 97f55c73aeSArchana Sathyakumar * Dual Edge sensitive HIGH 98f55c73aeSArchana Sathyakumar */ 99f55c73aeSArchana Sathyakumar enum pdc_irq_config_bits { 100f55c73aeSArchana Sathyakumar PDC_LEVEL_LOW = 0b000, 101f55c73aeSArchana Sathyakumar PDC_EDGE_FALLING = 0b010, 102f55c73aeSArchana Sathyakumar PDC_LEVEL_HIGH = 0b100, 103f55c73aeSArchana Sathyakumar PDC_EDGE_RISING = 0b110, 104f55c73aeSArchana Sathyakumar PDC_EDGE_DUAL = 0b111, 105f55c73aeSArchana Sathyakumar }; 106f55c73aeSArchana Sathyakumar 107f55c73aeSArchana Sathyakumar /** 108f55c73aeSArchana Sathyakumar * qcom_pdc_gic_set_type: Configure PDC for the interrupt 109f55c73aeSArchana Sathyakumar * 110f55c73aeSArchana Sathyakumar * @d: the interrupt data 111f55c73aeSArchana Sathyakumar * @type: the interrupt type 112f55c73aeSArchana Sathyakumar * 113f55c73aeSArchana Sathyakumar * If @type is edge triggered, forward that as Rising edge as PDC 114f55c73aeSArchana Sathyakumar * takes care of converting falling edge to rising edge signal 115f55c73aeSArchana Sathyakumar * If @type is level, then forward that as level high as PDC 116f55c73aeSArchana Sathyakumar * takes care of converting falling edge to rising edge signal 117f55c73aeSArchana Sathyakumar */ 118f55c73aeSArchana Sathyakumar static int qcom_pdc_gic_set_type(struct irq_data *d, unsigned int type) 119f55c73aeSArchana Sathyakumar { 120f55c73aeSArchana Sathyakumar enum pdc_irq_config_bits pdc_type; 1212f5fbc43SDouglas Anderson enum pdc_irq_config_bits old_pdc_type; 1222f5fbc43SDouglas Anderson int ret; 123f55c73aeSArchana Sathyakumar 124f55c73aeSArchana Sathyakumar switch (type) { 125f55c73aeSArchana Sathyakumar case IRQ_TYPE_EDGE_RISING: 126f55c73aeSArchana Sathyakumar pdc_type = PDC_EDGE_RISING; 127f55c73aeSArchana Sathyakumar break; 128f55c73aeSArchana Sathyakumar case IRQ_TYPE_EDGE_FALLING: 129f55c73aeSArchana Sathyakumar pdc_type = PDC_EDGE_FALLING; 130f55c73aeSArchana Sathyakumar type = IRQ_TYPE_EDGE_RISING; 131f55c73aeSArchana Sathyakumar break; 132f55c73aeSArchana Sathyakumar case IRQ_TYPE_EDGE_BOTH: 133f55c73aeSArchana Sathyakumar pdc_type = PDC_EDGE_DUAL; 1347bae48b2SLina Iyer type = IRQ_TYPE_EDGE_RISING; 135f55c73aeSArchana Sathyakumar break; 136f55c73aeSArchana Sathyakumar case IRQ_TYPE_LEVEL_HIGH: 137f55c73aeSArchana Sathyakumar pdc_type = PDC_LEVEL_HIGH; 138f55c73aeSArchana Sathyakumar break; 139f55c73aeSArchana Sathyakumar case IRQ_TYPE_LEVEL_LOW: 140f55c73aeSArchana Sathyakumar pdc_type = PDC_LEVEL_LOW; 141f55c73aeSArchana Sathyakumar type = IRQ_TYPE_LEVEL_HIGH; 142f55c73aeSArchana Sathyakumar break; 143f55c73aeSArchana Sathyakumar default: 144f55c73aeSArchana Sathyakumar WARN_ON(1); 145f55c73aeSArchana Sathyakumar return -EINVAL; 146f55c73aeSArchana Sathyakumar } 147f55c73aeSArchana Sathyakumar 1489d4f24bfSMarc Zyngier old_pdc_type = pdc_reg_read(IRQ_i_CFG, d->hwirq); 1499d4f24bfSMarc Zyngier pdc_reg_write(IRQ_i_CFG, d->hwirq, pdc_type); 150f55c73aeSArchana Sathyakumar 1512f5fbc43SDouglas Anderson ret = irq_chip_set_type_parent(d, type); 1522f5fbc43SDouglas Anderson if (ret) 1532f5fbc43SDouglas Anderson return ret; 1542f5fbc43SDouglas Anderson 1552f5fbc43SDouglas Anderson /* 1562f5fbc43SDouglas Anderson * When we change types the PDC can give a phantom interrupt. 1572f5fbc43SDouglas Anderson * Clear it. Specifically the phantom shows up when reconfiguring 1582f5fbc43SDouglas Anderson * polarity of interrupt without changing the state of the signal 1592f5fbc43SDouglas Anderson * but let's be consistent and clear it always. 1602f5fbc43SDouglas Anderson * 1612f5fbc43SDouglas Anderson * Doing this works because we have IRQCHIP_SET_TYPE_MASKED so the 1622f5fbc43SDouglas Anderson * interrupt will be cleared before the rest of the system sees it. 1632f5fbc43SDouglas Anderson */ 1642f5fbc43SDouglas Anderson if (old_pdc_type != pdc_type) 1652f5fbc43SDouglas Anderson irq_chip_set_parent_state(d, IRQCHIP_STATE_PENDING, false); 1662f5fbc43SDouglas Anderson 1672f5fbc43SDouglas Anderson return 0; 168f55c73aeSArchana Sathyakumar } 169f55c73aeSArchana Sathyakumar 170f55c73aeSArchana Sathyakumar static struct irq_chip qcom_pdc_gic_chip = { 171f55c73aeSArchana Sathyakumar .name = "PDC", 172f55c73aeSArchana Sathyakumar .irq_eoi = irq_chip_eoi_parent, 1739d4f24bfSMarc Zyngier .irq_mask = irq_chip_mask_parent, 1749d4f24bfSMarc Zyngier .irq_unmask = irq_chip_unmask_parent, 175da3f875aSLina Iyer .irq_disable = qcom_pdc_gic_disable, 176da3f875aSLina Iyer .irq_enable = qcom_pdc_gic_enable, 1779d4f24bfSMarc Zyngier .irq_get_irqchip_state = irq_chip_get_parent_state, 1789d4f24bfSMarc Zyngier .irq_set_irqchip_state = irq_chip_set_parent_state, 179f55c73aeSArchana Sathyakumar .irq_retrigger = irq_chip_retrigger_hierarchy, 180f55c73aeSArchana Sathyakumar .irq_set_type = qcom_pdc_gic_set_type, 181f55c73aeSArchana Sathyakumar .flags = IRQCHIP_MASK_ON_SUSPEND | 182f55c73aeSArchana Sathyakumar IRQCHIP_SET_TYPE_MASKED | 183299d7890SMaulik Shah IRQCHIP_SKIP_SET_WAKE | 184299d7890SMaulik Shah IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND, 185f55c73aeSArchana Sathyakumar .irq_set_vcpu_affinity = irq_chip_set_vcpu_affinity_parent, 186f55c73aeSArchana Sathyakumar .irq_set_affinity = irq_chip_set_affinity_parent, 187f55c73aeSArchana Sathyakumar }; 188f55c73aeSArchana Sathyakumar 189*8d4c9989SMarc Zyngier static struct pdc_pin_region *get_pin_region(int pin) 190f55c73aeSArchana Sathyakumar { 191f55c73aeSArchana Sathyakumar int i; 192f55c73aeSArchana Sathyakumar 193f55c73aeSArchana Sathyakumar for (i = 0; i < pdc_region_cnt; i++) { 194*8d4c9989SMarc Zyngier if (pin >= pdc_region[i].pin_base && 195*8d4c9989SMarc Zyngier pin < pdc_region[i].pin_base + pdc_region[i].cnt) 196*8d4c9989SMarc Zyngier return &pdc_region[i]; 197f55c73aeSArchana Sathyakumar } 198f55c73aeSArchana Sathyakumar 199*8d4c9989SMarc Zyngier return NULL; 200f55c73aeSArchana Sathyakumar } 201f55c73aeSArchana Sathyakumar 202f55c73aeSArchana Sathyakumar static int qcom_pdc_translate(struct irq_domain *d, struct irq_fwspec *fwspec, 203f55c73aeSArchana Sathyakumar unsigned long *hwirq, unsigned int *type) 204f55c73aeSArchana Sathyakumar { 205f55c73aeSArchana Sathyakumar if (is_of_node(fwspec->fwnode)) { 206f55c73aeSArchana Sathyakumar if (fwspec->param_count != 2) 207f55c73aeSArchana Sathyakumar return -EINVAL; 208f55c73aeSArchana Sathyakumar 209f55c73aeSArchana Sathyakumar *hwirq = fwspec->param[0]; 210f55c73aeSArchana Sathyakumar *type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK; 211f55c73aeSArchana Sathyakumar return 0; 212f55c73aeSArchana Sathyakumar } 213f55c73aeSArchana Sathyakumar 214f55c73aeSArchana Sathyakumar return -EINVAL; 215f55c73aeSArchana Sathyakumar } 216f55c73aeSArchana Sathyakumar 217f55c73aeSArchana Sathyakumar static int qcom_pdc_alloc(struct irq_domain *domain, unsigned int virq, 218f55c73aeSArchana Sathyakumar unsigned int nr_irqs, void *data) 219f55c73aeSArchana Sathyakumar { 220f55c73aeSArchana Sathyakumar struct irq_fwspec *fwspec = data; 221f55c73aeSArchana Sathyakumar struct irq_fwspec parent_fwspec; 222*8d4c9989SMarc Zyngier struct pdc_pin_region *region; 223*8d4c9989SMarc Zyngier irq_hw_number_t hwirq; 224f55c73aeSArchana Sathyakumar unsigned int type; 225f55c73aeSArchana Sathyakumar int ret; 226f55c73aeSArchana Sathyakumar 227f55c73aeSArchana Sathyakumar ret = qcom_pdc_translate(domain, fwspec, &hwirq, &type); 228f55c73aeSArchana Sathyakumar if (ret) 22981ef8bf8SLina Iyer return ret; 230f55c73aeSArchana Sathyakumar 231f55c73aeSArchana Sathyakumar ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq, 232f55c73aeSArchana Sathyakumar &qcom_pdc_gic_chip, NULL); 233f55c73aeSArchana Sathyakumar if (ret) 234f55c73aeSArchana Sathyakumar return ret; 235f55c73aeSArchana Sathyakumar 236*8d4c9989SMarc Zyngier region = get_pin_region(hwirq); 237*8d4c9989SMarc Zyngier if (!region) 2389d4f24bfSMarc Zyngier return irq_domain_disconnect_hierarchy(domain->parent, virq); 23981ef8bf8SLina Iyer 240f55c73aeSArchana Sathyakumar if (type & IRQ_TYPE_EDGE_BOTH) 241f55c73aeSArchana Sathyakumar type = IRQ_TYPE_EDGE_RISING; 242f55c73aeSArchana Sathyakumar 243f55c73aeSArchana Sathyakumar if (type & IRQ_TYPE_LEVEL_MASK) 244f55c73aeSArchana Sathyakumar type = IRQ_TYPE_LEVEL_HIGH; 245f55c73aeSArchana Sathyakumar 246f55c73aeSArchana Sathyakumar parent_fwspec.fwnode = domain->parent->fwnode; 247f55c73aeSArchana Sathyakumar parent_fwspec.param_count = 3; 248f55c73aeSArchana Sathyakumar parent_fwspec.param[0] = 0; 249*8d4c9989SMarc Zyngier parent_fwspec.param[1] = pin_to_hwirq(region, hwirq); 250f55c73aeSArchana Sathyakumar parent_fwspec.param[2] = type; 251f55c73aeSArchana Sathyakumar 252f55c73aeSArchana Sathyakumar return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, 253f55c73aeSArchana Sathyakumar &parent_fwspec); 254f55c73aeSArchana Sathyakumar } 255f55c73aeSArchana Sathyakumar 256f55c73aeSArchana Sathyakumar static const struct irq_domain_ops qcom_pdc_ops = { 257f55c73aeSArchana Sathyakumar .translate = qcom_pdc_translate, 258f55c73aeSArchana Sathyakumar .alloc = qcom_pdc_alloc, 259f55c73aeSArchana Sathyakumar .free = irq_domain_free_irqs_common, 260f55c73aeSArchana Sathyakumar }; 261f55c73aeSArchana Sathyakumar 26281ef8bf8SLina Iyer static int qcom_pdc_gpio_alloc(struct irq_domain *domain, unsigned int virq, 26381ef8bf8SLina Iyer unsigned int nr_irqs, void *data) 26481ef8bf8SLina Iyer { 26581ef8bf8SLina Iyer struct irq_fwspec *fwspec = data; 26681ef8bf8SLina Iyer struct irq_fwspec parent_fwspec; 267*8d4c9989SMarc Zyngier struct pdc_pin_region *region; 268*8d4c9989SMarc Zyngier irq_hw_number_t hwirq; 26981ef8bf8SLina Iyer unsigned int type; 27081ef8bf8SLina Iyer int ret; 27181ef8bf8SLina Iyer 27281ef8bf8SLina Iyer ret = qcom_pdc_translate(domain, fwspec, &hwirq, &type); 27381ef8bf8SLina Iyer if (ret) 27481ef8bf8SLina Iyer return ret; 27581ef8bf8SLina Iyer 2769d4f24bfSMarc Zyngier if (hwirq == GPIO_NO_WAKE_IRQ) 2779d4f24bfSMarc Zyngier return irq_domain_disconnect_hierarchy(domain, virq); 2789d4f24bfSMarc Zyngier 27981ef8bf8SLina Iyer ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq, 28081ef8bf8SLina Iyer &qcom_pdc_gic_chip, NULL); 28181ef8bf8SLina Iyer if (ret) 28281ef8bf8SLina Iyer return ret; 28381ef8bf8SLina Iyer 284*8d4c9989SMarc Zyngier region = get_pin_region(hwirq); 285*8d4c9989SMarc Zyngier if (!region) 2869d4f24bfSMarc Zyngier return irq_domain_disconnect_hierarchy(domain->parent, virq); 28781ef8bf8SLina Iyer 28881ef8bf8SLina Iyer if (type & IRQ_TYPE_EDGE_BOTH) 28981ef8bf8SLina Iyer type = IRQ_TYPE_EDGE_RISING; 29081ef8bf8SLina Iyer 29181ef8bf8SLina Iyer if (type & IRQ_TYPE_LEVEL_MASK) 29281ef8bf8SLina Iyer type = IRQ_TYPE_LEVEL_HIGH; 29381ef8bf8SLina Iyer 29481ef8bf8SLina Iyer parent_fwspec.fwnode = domain->parent->fwnode; 29581ef8bf8SLina Iyer parent_fwspec.param_count = 3; 29681ef8bf8SLina Iyer parent_fwspec.param[0] = 0; 297*8d4c9989SMarc Zyngier parent_fwspec.param[1] = pin_to_hwirq(region, hwirq); 29881ef8bf8SLina Iyer parent_fwspec.param[2] = type; 29981ef8bf8SLina Iyer 30081ef8bf8SLina Iyer return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, 30181ef8bf8SLina Iyer &parent_fwspec); 30281ef8bf8SLina Iyer } 30381ef8bf8SLina Iyer 30481ef8bf8SLina Iyer static int qcom_pdc_gpio_domain_select(struct irq_domain *d, 30581ef8bf8SLina Iyer struct irq_fwspec *fwspec, 30681ef8bf8SLina Iyer enum irq_domain_bus_token bus_token) 30781ef8bf8SLina Iyer { 30881ef8bf8SLina Iyer return bus_token == DOMAIN_BUS_WAKEUP; 30981ef8bf8SLina Iyer } 31081ef8bf8SLina Iyer 31181ef8bf8SLina Iyer static const struct irq_domain_ops qcom_pdc_gpio_ops = { 31281ef8bf8SLina Iyer .select = qcom_pdc_gpio_domain_select, 31381ef8bf8SLina Iyer .alloc = qcom_pdc_gpio_alloc, 31481ef8bf8SLina Iyer .free = irq_domain_free_irqs_common, 31581ef8bf8SLina Iyer }; 31681ef8bf8SLina Iyer 317f55c73aeSArchana Sathyakumar static int pdc_setup_pin_mapping(struct device_node *np) 318f55c73aeSArchana Sathyakumar { 319d7bc63faSMaulik Shah int ret, n, i; 320d7bc63faSMaulik Shah u32 irq_index, reg_index, val; 321f55c73aeSArchana Sathyakumar 322f55c73aeSArchana Sathyakumar n = of_property_count_elems_of_size(np, "qcom,pdc-ranges", sizeof(u32)); 323f55c73aeSArchana Sathyakumar if (n <= 0 || n % 3) 324f55c73aeSArchana Sathyakumar return -EINVAL; 325f55c73aeSArchana Sathyakumar 326f55c73aeSArchana Sathyakumar pdc_region_cnt = n / 3; 327f55c73aeSArchana Sathyakumar pdc_region = kcalloc(pdc_region_cnt, sizeof(*pdc_region), GFP_KERNEL); 328f55c73aeSArchana Sathyakumar if (!pdc_region) { 329f55c73aeSArchana Sathyakumar pdc_region_cnt = 0; 330f55c73aeSArchana Sathyakumar return -ENOMEM; 331f55c73aeSArchana Sathyakumar } 332f55c73aeSArchana Sathyakumar 333f55c73aeSArchana Sathyakumar for (n = 0; n < pdc_region_cnt; n++) { 334f55c73aeSArchana Sathyakumar ret = of_property_read_u32_index(np, "qcom,pdc-ranges", 335f55c73aeSArchana Sathyakumar n * 3 + 0, 336f55c73aeSArchana Sathyakumar &pdc_region[n].pin_base); 337f55c73aeSArchana Sathyakumar if (ret) 338f55c73aeSArchana Sathyakumar return ret; 339f55c73aeSArchana Sathyakumar ret = of_property_read_u32_index(np, "qcom,pdc-ranges", 340f55c73aeSArchana Sathyakumar n * 3 + 1, 341f55c73aeSArchana Sathyakumar &pdc_region[n].parent_base); 342f55c73aeSArchana Sathyakumar if (ret) 343f55c73aeSArchana Sathyakumar return ret; 344f55c73aeSArchana Sathyakumar ret = of_property_read_u32_index(np, "qcom,pdc-ranges", 345f55c73aeSArchana Sathyakumar n * 3 + 2, 346f55c73aeSArchana Sathyakumar &pdc_region[n].cnt); 347f55c73aeSArchana Sathyakumar if (ret) 348f55c73aeSArchana Sathyakumar return ret; 349d7bc63faSMaulik Shah 350d7bc63faSMaulik Shah for (i = 0; i < pdc_region[n].cnt; i++) { 351d7bc63faSMaulik Shah reg_index = (i + pdc_region[n].pin_base) >> 5; 352d7bc63faSMaulik Shah irq_index = (i + pdc_region[n].pin_base) & 0x1f; 353d7bc63faSMaulik Shah val = pdc_reg_read(IRQ_ENABLE_BANK, reg_index); 354d7bc63faSMaulik Shah val &= ~BIT(irq_index); 355d7bc63faSMaulik Shah pdc_reg_write(IRQ_ENABLE_BANK, reg_index, val); 356d7bc63faSMaulik Shah } 357f55c73aeSArchana Sathyakumar } 358f55c73aeSArchana Sathyakumar 359f55c73aeSArchana Sathyakumar return 0; 360f55c73aeSArchana Sathyakumar } 361f55c73aeSArchana Sathyakumar 362f55c73aeSArchana Sathyakumar static int qcom_pdc_init(struct device_node *node, struct device_node *parent) 363f55c73aeSArchana Sathyakumar { 36481ef8bf8SLina Iyer struct irq_domain *parent_domain, *pdc_domain, *pdc_gpio_domain; 365f55c73aeSArchana Sathyakumar int ret; 366f55c73aeSArchana Sathyakumar 367f55c73aeSArchana Sathyakumar pdc_base = of_iomap(node, 0); 368f55c73aeSArchana Sathyakumar if (!pdc_base) { 369f55c73aeSArchana Sathyakumar pr_err("%pOF: unable to map PDC registers\n", node); 370f55c73aeSArchana Sathyakumar return -ENXIO; 371f55c73aeSArchana Sathyakumar } 372f55c73aeSArchana Sathyakumar 373f55c73aeSArchana Sathyakumar parent_domain = irq_find_host(parent); 374f55c73aeSArchana Sathyakumar if (!parent_domain) { 375f55c73aeSArchana Sathyakumar pr_err("%pOF: unable to find PDC's parent domain\n", node); 376f55c73aeSArchana Sathyakumar ret = -ENXIO; 377f55c73aeSArchana Sathyakumar goto fail; 378f55c73aeSArchana Sathyakumar } 379f55c73aeSArchana Sathyakumar 380f55c73aeSArchana Sathyakumar ret = pdc_setup_pin_mapping(node); 381f55c73aeSArchana Sathyakumar if (ret) { 382f55c73aeSArchana Sathyakumar pr_err("%pOF: failed to init PDC pin-hwirq mapping\n", node); 383f55c73aeSArchana Sathyakumar goto fail; 384f55c73aeSArchana Sathyakumar } 385f55c73aeSArchana Sathyakumar 386f55c73aeSArchana Sathyakumar pdc_domain = irq_domain_create_hierarchy(parent_domain, 0, PDC_MAX_IRQS, 387f55c73aeSArchana Sathyakumar of_fwnode_handle(node), 388f55c73aeSArchana Sathyakumar &qcom_pdc_ops, NULL); 389f55c73aeSArchana Sathyakumar if (!pdc_domain) { 390f55c73aeSArchana Sathyakumar pr_err("%pOF: GIC domain add failed\n", node); 391f55c73aeSArchana Sathyakumar ret = -ENOMEM; 392f55c73aeSArchana Sathyakumar goto fail; 393f55c73aeSArchana Sathyakumar } 394f55c73aeSArchana Sathyakumar 39581ef8bf8SLina Iyer pdc_gpio_domain = irq_domain_create_hierarchy(parent_domain, 39681ef8bf8SLina Iyer IRQ_DOMAIN_FLAG_QCOM_PDC_WAKEUP, 39781ef8bf8SLina Iyer PDC_MAX_GPIO_IRQS, 39881ef8bf8SLina Iyer of_fwnode_handle(node), 39981ef8bf8SLina Iyer &qcom_pdc_gpio_ops, NULL); 40081ef8bf8SLina Iyer if (!pdc_gpio_domain) { 40181ef8bf8SLina Iyer pr_err("%pOF: PDC domain add failed for GPIO domain\n", node); 40281ef8bf8SLina Iyer ret = -ENOMEM; 40381ef8bf8SLina Iyer goto remove; 40481ef8bf8SLina Iyer } 40581ef8bf8SLina Iyer 40681ef8bf8SLina Iyer irq_domain_update_bus_token(pdc_gpio_domain, DOMAIN_BUS_WAKEUP); 40781ef8bf8SLina Iyer 408f55c73aeSArchana Sathyakumar return 0; 409f55c73aeSArchana Sathyakumar 41081ef8bf8SLina Iyer remove: 41181ef8bf8SLina Iyer irq_domain_remove(pdc_domain); 412f55c73aeSArchana Sathyakumar fail: 413f55c73aeSArchana Sathyakumar kfree(pdc_region); 414f55c73aeSArchana Sathyakumar iounmap(pdc_base); 415f55c73aeSArchana Sathyakumar return ret; 416f55c73aeSArchana Sathyakumar } 417f55c73aeSArchana Sathyakumar 4184acd8a4bSSaravana Kannan IRQCHIP_PLATFORM_DRIVER_BEGIN(qcom_pdc) 4194acd8a4bSSaravana Kannan IRQCHIP_MATCH("qcom,pdc", qcom_pdc_init) 4204acd8a4bSSaravana Kannan IRQCHIP_PLATFORM_DRIVER_END(qcom_pdc) 4214acd8a4bSSaravana Kannan MODULE_DESCRIPTION("Qualcomm Technologies, Inc. Power Domain Controller"); 4224acd8a4bSSaravana Kannan MODULE_LICENSE("GPL v2"); 423