1f55c73aeSArchana Sathyakumar // SPDX-License-Identifier: GPL-2.0 2f55c73aeSArchana Sathyakumar /* 3b2bb01edSLina Iyer * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. 4f55c73aeSArchana Sathyakumar */ 5f55c73aeSArchana Sathyakumar 6f55c73aeSArchana Sathyakumar #include <linux/err.h> 7f55c73aeSArchana Sathyakumar #include <linux/init.h> 8f55c73aeSArchana Sathyakumar #include <linux/irq.h> 9f55c73aeSArchana Sathyakumar #include <linux/irqchip.h> 10f55c73aeSArchana Sathyakumar #include <linux/irqdomain.h> 11f55c73aeSArchana Sathyakumar #include <linux/io.h> 12f55c73aeSArchana Sathyakumar #include <linux/kernel.h> 13f55c73aeSArchana Sathyakumar #include <linux/of.h> 14f55c73aeSArchana Sathyakumar #include <linux/of_address.h> 15f55c73aeSArchana Sathyakumar #include <linux/of_device.h> 1681ef8bf8SLina Iyer #include <linux/soc/qcom/irq.h> 17f55c73aeSArchana Sathyakumar #include <linux/spinlock.h> 18f55c73aeSArchana Sathyakumar #include <linux/slab.h> 19f55c73aeSArchana Sathyakumar #include <linux/types.h> 20f55c73aeSArchana Sathyakumar 21b2bb01edSLina Iyer #define PDC_MAX_IRQS 168 2281ef8bf8SLina Iyer #define PDC_MAX_GPIO_IRQS 256 23f55c73aeSArchana Sathyakumar 24f55c73aeSArchana Sathyakumar #define CLEAR_INTR(reg, intr) (reg & ~(1 << intr)) 25f55c73aeSArchana Sathyakumar #define ENABLE_INTR(reg, intr) (reg | (1 << intr)) 26f55c73aeSArchana Sathyakumar 27f55c73aeSArchana Sathyakumar #define IRQ_ENABLE_BANK 0x10 28f55c73aeSArchana Sathyakumar #define IRQ_i_CFG 0x110 29f55c73aeSArchana Sathyakumar 3081ef8bf8SLina Iyer #define PDC_NO_PARENT_IRQ ~0UL 3181ef8bf8SLina Iyer 32f55c73aeSArchana Sathyakumar struct pdc_pin_region { 33f55c73aeSArchana Sathyakumar u32 pin_base; 34f55c73aeSArchana Sathyakumar u32 parent_base; 35f55c73aeSArchana Sathyakumar u32 cnt; 36f55c73aeSArchana Sathyakumar }; 37f55c73aeSArchana Sathyakumar 38f55c73aeSArchana Sathyakumar static DEFINE_RAW_SPINLOCK(pdc_lock); 39f55c73aeSArchana Sathyakumar static void __iomem *pdc_base; 40f55c73aeSArchana Sathyakumar static struct pdc_pin_region *pdc_region; 41f55c73aeSArchana Sathyakumar static int pdc_region_cnt; 42f55c73aeSArchana Sathyakumar 43f55c73aeSArchana Sathyakumar static void pdc_reg_write(int reg, u32 i, u32 val) 44f55c73aeSArchana Sathyakumar { 45f55c73aeSArchana Sathyakumar writel_relaxed(val, pdc_base + reg + i * sizeof(u32)); 46f55c73aeSArchana Sathyakumar } 47f55c73aeSArchana Sathyakumar 48f55c73aeSArchana Sathyakumar static u32 pdc_reg_read(int reg, u32 i) 49f55c73aeSArchana Sathyakumar { 50f55c73aeSArchana Sathyakumar return readl_relaxed(pdc_base + reg + i * sizeof(u32)); 51f55c73aeSArchana Sathyakumar } 52f55c73aeSArchana Sathyakumar 53f55c73aeSArchana Sathyakumar static void pdc_enable_intr(struct irq_data *d, bool on) 54f55c73aeSArchana Sathyakumar { 55f55c73aeSArchana Sathyakumar int pin_out = d->hwirq; 56f55c73aeSArchana Sathyakumar u32 index, mask; 57f55c73aeSArchana Sathyakumar u32 enable; 58f55c73aeSArchana Sathyakumar 59f55c73aeSArchana Sathyakumar index = pin_out / 32; 60f55c73aeSArchana Sathyakumar mask = pin_out % 32; 61f55c73aeSArchana Sathyakumar 62f55c73aeSArchana Sathyakumar raw_spin_lock(&pdc_lock); 63f55c73aeSArchana Sathyakumar enable = pdc_reg_read(IRQ_ENABLE_BANK, index); 64f55c73aeSArchana Sathyakumar enable = on ? ENABLE_INTR(enable, mask) : CLEAR_INTR(enable, mask); 65f55c73aeSArchana Sathyakumar pdc_reg_write(IRQ_ENABLE_BANK, index, enable); 66f55c73aeSArchana Sathyakumar raw_spin_unlock(&pdc_lock); 67f55c73aeSArchana Sathyakumar } 68f55c73aeSArchana Sathyakumar 69da3f875aSLina Iyer static void qcom_pdc_gic_disable(struct irq_data *d) 70f55c73aeSArchana Sathyakumar { 7181ef8bf8SLina Iyer if (d->hwirq == GPIO_NO_WAKE_IRQ) 7281ef8bf8SLina Iyer return; 7381ef8bf8SLina Iyer 74f55c73aeSArchana Sathyakumar pdc_enable_intr(d, false); 75da3f875aSLina Iyer irq_chip_disable_parent(d); 76da3f875aSLina Iyer } 77da3f875aSLina Iyer 78da3f875aSLina Iyer static void qcom_pdc_gic_enable(struct irq_data *d) 79da3f875aSLina Iyer { 8081ef8bf8SLina Iyer if (d->hwirq == GPIO_NO_WAKE_IRQ) 8181ef8bf8SLina Iyer return; 8281ef8bf8SLina Iyer 83da3f875aSLina Iyer pdc_enable_intr(d, true); 84da3f875aSLina Iyer irq_chip_enable_parent(d); 85da3f875aSLina Iyer } 86da3f875aSLina Iyer 87da3f875aSLina Iyer static void qcom_pdc_gic_mask(struct irq_data *d) 88da3f875aSLina Iyer { 8981ef8bf8SLina Iyer if (d->hwirq == GPIO_NO_WAKE_IRQ) 9081ef8bf8SLina Iyer return; 9181ef8bf8SLina Iyer 92f55c73aeSArchana Sathyakumar irq_chip_mask_parent(d); 93f55c73aeSArchana Sathyakumar } 94f55c73aeSArchana Sathyakumar 95f55c73aeSArchana Sathyakumar static void qcom_pdc_gic_unmask(struct irq_data *d) 96f55c73aeSArchana Sathyakumar { 9781ef8bf8SLina Iyer if (d->hwirq == GPIO_NO_WAKE_IRQ) 9881ef8bf8SLina Iyer return; 9981ef8bf8SLina Iyer 100f55c73aeSArchana Sathyakumar irq_chip_unmask_parent(d); 101f55c73aeSArchana Sathyakumar } 102f55c73aeSArchana Sathyakumar 103f55c73aeSArchana Sathyakumar /* 104f55c73aeSArchana Sathyakumar * GIC does not handle falling edge or active low. To allow falling edge and 105f55c73aeSArchana Sathyakumar * active low interrupts to be handled at GIC, PDC has an inverter that inverts 106f55c73aeSArchana Sathyakumar * falling edge into a rising edge and active low into an active high. 107f55c73aeSArchana Sathyakumar * For the inverter to work, the polarity bit in the IRQ_CONFIG register has to 108f55c73aeSArchana Sathyakumar * set as per the table below. 109f55c73aeSArchana Sathyakumar * Level sensitive active low LOW 110f55c73aeSArchana Sathyakumar * Rising edge sensitive NOT USED 111f55c73aeSArchana Sathyakumar * Falling edge sensitive LOW 112f55c73aeSArchana Sathyakumar * Dual Edge sensitive NOT USED 113f55c73aeSArchana Sathyakumar * Level sensitive active High HIGH 114f55c73aeSArchana Sathyakumar * Falling Edge sensitive NOT USED 115f55c73aeSArchana Sathyakumar * Rising edge sensitive HIGH 116f55c73aeSArchana Sathyakumar * Dual Edge sensitive HIGH 117f55c73aeSArchana Sathyakumar */ 118f55c73aeSArchana Sathyakumar enum pdc_irq_config_bits { 119f55c73aeSArchana Sathyakumar PDC_LEVEL_LOW = 0b000, 120f55c73aeSArchana Sathyakumar PDC_EDGE_FALLING = 0b010, 121f55c73aeSArchana Sathyakumar PDC_LEVEL_HIGH = 0b100, 122f55c73aeSArchana Sathyakumar PDC_EDGE_RISING = 0b110, 123f55c73aeSArchana Sathyakumar PDC_EDGE_DUAL = 0b111, 124f55c73aeSArchana Sathyakumar }; 125f55c73aeSArchana Sathyakumar 126f55c73aeSArchana Sathyakumar /** 127f55c73aeSArchana Sathyakumar * qcom_pdc_gic_set_type: Configure PDC for the interrupt 128f55c73aeSArchana Sathyakumar * 129f55c73aeSArchana Sathyakumar * @d: the interrupt data 130f55c73aeSArchana Sathyakumar * @type: the interrupt type 131f55c73aeSArchana Sathyakumar * 132f55c73aeSArchana Sathyakumar * If @type is edge triggered, forward that as Rising edge as PDC 133f55c73aeSArchana Sathyakumar * takes care of converting falling edge to rising edge signal 134f55c73aeSArchana Sathyakumar * If @type is level, then forward that as level high as PDC 135f55c73aeSArchana Sathyakumar * takes care of converting falling edge to rising edge signal 136f55c73aeSArchana Sathyakumar */ 137f55c73aeSArchana Sathyakumar static int qcom_pdc_gic_set_type(struct irq_data *d, unsigned int type) 138f55c73aeSArchana Sathyakumar { 139f55c73aeSArchana Sathyakumar int pin_out = d->hwirq; 140f55c73aeSArchana Sathyakumar enum pdc_irq_config_bits pdc_type; 141f55c73aeSArchana Sathyakumar 14281ef8bf8SLina Iyer if (pin_out == GPIO_NO_WAKE_IRQ) 14381ef8bf8SLina Iyer return 0; 14481ef8bf8SLina Iyer 145f55c73aeSArchana Sathyakumar switch (type) { 146f55c73aeSArchana Sathyakumar case IRQ_TYPE_EDGE_RISING: 147f55c73aeSArchana Sathyakumar pdc_type = PDC_EDGE_RISING; 148f55c73aeSArchana Sathyakumar break; 149f55c73aeSArchana Sathyakumar case IRQ_TYPE_EDGE_FALLING: 150f55c73aeSArchana Sathyakumar pdc_type = PDC_EDGE_FALLING; 151f55c73aeSArchana Sathyakumar type = IRQ_TYPE_EDGE_RISING; 152f55c73aeSArchana Sathyakumar break; 153f55c73aeSArchana Sathyakumar case IRQ_TYPE_EDGE_BOTH: 154f55c73aeSArchana Sathyakumar pdc_type = PDC_EDGE_DUAL; 1557bae48b2SLina Iyer type = IRQ_TYPE_EDGE_RISING; 156f55c73aeSArchana Sathyakumar break; 157f55c73aeSArchana Sathyakumar case IRQ_TYPE_LEVEL_HIGH: 158f55c73aeSArchana Sathyakumar pdc_type = PDC_LEVEL_HIGH; 159f55c73aeSArchana Sathyakumar break; 160f55c73aeSArchana Sathyakumar case IRQ_TYPE_LEVEL_LOW: 161f55c73aeSArchana Sathyakumar pdc_type = PDC_LEVEL_LOW; 162f55c73aeSArchana Sathyakumar type = IRQ_TYPE_LEVEL_HIGH; 163f55c73aeSArchana Sathyakumar break; 164f55c73aeSArchana Sathyakumar default: 165f55c73aeSArchana Sathyakumar WARN_ON(1); 166f55c73aeSArchana Sathyakumar return -EINVAL; 167f55c73aeSArchana Sathyakumar } 168f55c73aeSArchana Sathyakumar 169f55c73aeSArchana Sathyakumar pdc_reg_write(IRQ_i_CFG, pin_out, pdc_type); 170f55c73aeSArchana Sathyakumar 171f55c73aeSArchana Sathyakumar return irq_chip_set_type_parent(d, type); 172f55c73aeSArchana Sathyakumar } 173f55c73aeSArchana Sathyakumar 174f55c73aeSArchana Sathyakumar static struct irq_chip qcom_pdc_gic_chip = { 175f55c73aeSArchana Sathyakumar .name = "PDC", 176f55c73aeSArchana Sathyakumar .irq_eoi = irq_chip_eoi_parent, 177f55c73aeSArchana Sathyakumar .irq_mask = qcom_pdc_gic_mask, 178f55c73aeSArchana Sathyakumar .irq_unmask = qcom_pdc_gic_unmask, 179da3f875aSLina Iyer .irq_disable = qcom_pdc_gic_disable, 180da3f875aSLina Iyer .irq_enable = qcom_pdc_gic_enable, 181f55c73aeSArchana Sathyakumar .irq_retrigger = irq_chip_retrigger_hierarchy, 182f55c73aeSArchana Sathyakumar .irq_set_type = qcom_pdc_gic_set_type, 183f55c73aeSArchana Sathyakumar .flags = IRQCHIP_MASK_ON_SUSPEND | 184f55c73aeSArchana Sathyakumar IRQCHIP_SET_TYPE_MASKED | 185f55c73aeSArchana Sathyakumar IRQCHIP_SKIP_SET_WAKE, 186f55c73aeSArchana Sathyakumar .irq_set_vcpu_affinity = irq_chip_set_vcpu_affinity_parent, 187f55c73aeSArchana Sathyakumar .irq_set_affinity = irq_chip_set_affinity_parent, 188f55c73aeSArchana Sathyakumar }; 189f55c73aeSArchana Sathyakumar 190f55c73aeSArchana Sathyakumar static irq_hw_number_t get_parent_hwirq(int pin) 191f55c73aeSArchana Sathyakumar { 192f55c73aeSArchana Sathyakumar int i; 193f55c73aeSArchana Sathyakumar struct pdc_pin_region *region; 194f55c73aeSArchana Sathyakumar 195f55c73aeSArchana Sathyakumar for (i = 0; i < pdc_region_cnt; i++) { 196f55c73aeSArchana Sathyakumar region = &pdc_region[i]; 197f55c73aeSArchana Sathyakumar if (pin >= region->pin_base && 198f55c73aeSArchana Sathyakumar pin < region->pin_base + region->cnt) 199f55c73aeSArchana Sathyakumar return (region->parent_base + pin - region->pin_base); 200f55c73aeSArchana Sathyakumar } 201f55c73aeSArchana Sathyakumar 20281ef8bf8SLina Iyer return PDC_NO_PARENT_IRQ; 203f55c73aeSArchana Sathyakumar } 204f55c73aeSArchana Sathyakumar 205f55c73aeSArchana Sathyakumar static int qcom_pdc_translate(struct irq_domain *d, struct irq_fwspec *fwspec, 206f55c73aeSArchana Sathyakumar unsigned long *hwirq, unsigned int *type) 207f55c73aeSArchana Sathyakumar { 208f55c73aeSArchana Sathyakumar if (is_of_node(fwspec->fwnode)) { 209f55c73aeSArchana Sathyakumar if (fwspec->param_count != 2) 210f55c73aeSArchana Sathyakumar return -EINVAL; 211f55c73aeSArchana Sathyakumar 212f55c73aeSArchana Sathyakumar *hwirq = fwspec->param[0]; 213f55c73aeSArchana Sathyakumar *type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK; 214f55c73aeSArchana Sathyakumar return 0; 215f55c73aeSArchana Sathyakumar } 216f55c73aeSArchana Sathyakumar 217f55c73aeSArchana Sathyakumar return -EINVAL; 218f55c73aeSArchana Sathyakumar } 219f55c73aeSArchana Sathyakumar 220f55c73aeSArchana Sathyakumar static int qcom_pdc_alloc(struct irq_domain *domain, unsigned int virq, 221f55c73aeSArchana Sathyakumar unsigned int nr_irqs, void *data) 222f55c73aeSArchana Sathyakumar { 223f55c73aeSArchana Sathyakumar struct irq_fwspec *fwspec = data; 224f55c73aeSArchana Sathyakumar struct irq_fwspec parent_fwspec; 225f55c73aeSArchana Sathyakumar irq_hw_number_t hwirq, parent_hwirq; 226f55c73aeSArchana Sathyakumar unsigned int type; 227f55c73aeSArchana Sathyakumar int ret; 228f55c73aeSArchana Sathyakumar 229f55c73aeSArchana Sathyakumar ret = qcom_pdc_translate(domain, fwspec, &hwirq, &type); 230f55c73aeSArchana Sathyakumar if (ret) 23181ef8bf8SLina Iyer return ret; 232f55c73aeSArchana Sathyakumar 233f55c73aeSArchana Sathyakumar ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq, 234f55c73aeSArchana Sathyakumar &qcom_pdc_gic_chip, NULL); 235f55c73aeSArchana Sathyakumar if (ret) 236f55c73aeSArchana Sathyakumar return ret; 237f55c73aeSArchana Sathyakumar 23881ef8bf8SLina Iyer parent_hwirq = get_parent_hwirq(hwirq); 23981ef8bf8SLina Iyer if (parent_hwirq == PDC_NO_PARENT_IRQ) 24081ef8bf8SLina Iyer return 0; 24181ef8bf8SLina Iyer 242f55c73aeSArchana Sathyakumar if (type & IRQ_TYPE_EDGE_BOTH) 243f55c73aeSArchana Sathyakumar type = IRQ_TYPE_EDGE_RISING; 244f55c73aeSArchana Sathyakumar 245f55c73aeSArchana Sathyakumar if (type & IRQ_TYPE_LEVEL_MASK) 246f55c73aeSArchana Sathyakumar type = IRQ_TYPE_LEVEL_HIGH; 247f55c73aeSArchana Sathyakumar 248f55c73aeSArchana Sathyakumar parent_fwspec.fwnode = domain->parent->fwnode; 249f55c73aeSArchana Sathyakumar parent_fwspec.param_count = 3; 250f55c73aeSArchana Sathyakumar parent_fwspec.param[0] = 0; 251f55c73aeSArchana Sathyakumar parent_fwspec.param[1] = parent_hwirq; 252f55c73aeSArchana Sathyakumar parent_fwspec.param[2] = type; 253f55c73aeSArchana Sathyakumar 254f55c73aeSArchana Sathyakumar return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, 255f55c73aeSArchana Sathyakumar &parent_fwspec); 256f55c73aeSArchana Sathyakumar } 257f55c73aeSArchana Sathyakumar 258f55c73aeSArchana Sathyakumar static const struct irq_domain_ops qcom_pdc_ops = { 259f55c73aeSArchana Sathyakumar .translate = qcom_pdc_translate, 260f55c73aeSArchana Sathyakumar .alloc = qcom_pdc_alloc, 261f55c73aeSArchana Sathyakumar .free = irq_domain_free_irqs_common, 262f55c73aeSArchana Sathyakumar }; 263f55c73aeSArchana Sathyakumar 26481ef8bf8SLina Iyer static int qcom_pdc_gpio_alloc(struct irq_domain *domain, unsigned int virq, 26581ef8bf8SLina Iyer unsigned int nr_irqs, void *data) 26681ef8bf8SLina Iyer { 26781ef8bf8SLina Iyer struct irq_fwspec *fwspec = data; 26881ef8bf8SLina Iyer struct irq_fwspec parent_fwspec; 26981ef8bf8SLina Iyer irq_hw_number_t hwirq, parent_hwirq; 27081ef8bf8SLina Iyer unsigned int type; 27181ef8bf8SLina Iyer int ret; 27281ef8bf8SLina Iyer 27381ef8bf8SLina Iyer ret = qcom_pdc_translate(domain, fwspec, &hwirq, &type); 27481ef8bf8SLina Iyer if (ret) 27581ef8bf8SLina Iyer return ret; 27681ef8bf8SLina Iyer 27781ef8bf8SLina Iyer ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq, 27881ef8bf8SLina Iyer &qcom_pdc_gic_chip, NULL); 27981ef8bf8SLina Iyer if (ret) 28081ef8bf8SLina Iyer return ret; 28181ef8bf8SLina Iyer 28281ef8bf8SLina Iyer if (hwirq == GPIO_NO_WAKE_IRQ) 28381ef8bf8SLina Iyer return 0; 28481ef8bf8SLina Iyer 28581ef8bf8SLina Iyer parent_hwirq = get_parent_hwirq(hwirq); 28681ef8bf8SLina Iyer if (parent_hwirq == PDC_NO_PARENT_IRQ) 28781ef8bf8SLina Iyer return 0; 28881ef8bf8SLina Iyer 28981ef8bf8SLina Iyer if (type & IRQ_TYPE_EDGE_BOTH) 29081ef8bf8SLina Iyer type = IRQ_TYPE_EDGE_RISING; 29181ef8bf8SLina Iyer 29281ef8bf8SLina Iyer if (type & IRQ_TYPE_LEVEL_MASK) 29381ef8bf8SLina Iyer type = IRQ_TYPE_LEVEL_HIGH; 29481ef8bf8SLina Iyer 29581ef8bf8SLina Iyer parent_fwspec.fwnode = domain->parent->fwnode; 29681ef8bf8SLina Iyer parent_fwspec.param_count = 3; 29781ef8bf8SLina Iyer parent_fwspec.param[0] = 0; 29881ef8bf8SLina Iyer parent_fwspec.param[1] = parent_hwirq; 29981ef8bf8SLina Iyer parent_fwspec.param[2] = type; 30081ef8bf8SLina Iyer 30181ef8bf8SLina Iyer return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, 30281ef8bf8SLina Iyer &parent_fwspec); 30381ef8bf8SLina Iyer } 30481ef8bf8SLina Iyer 30581ef8bf8SLina Iyer static int qcom_pdc_gpio_domain_select(struct irq_domain *d, 30681ef8bf8SLina Iyer struct irq_fwspec *fwspec, 30781ef8bf8SLina Iyer enum irq_domain_bus_token bus_token) 30881ef8bf8SLina Iyer { 30981ef8bf8SLina Iyer return bus_token == DOMAIN_BUS_WAKEUP; 31081ef8bf8SLina Iyer } 31181ef8bf8SLina Iyer 31281ef8bf8SLina Iyer static const struct irq_domain_ops qcom_pdc_gpio_ops = { 31381ef8bf8SLina Iyer .select = qcom_pdc_gpio_domain_select, 31481ef8bf8SLina Iyer .alloc = qcom_pdc_gpio_alloc, 31581ef8bf8SLina Iyer .free = irq_domain_free_irqs_common, 31681ef8bf8SLina Iyer }; 31781ef8bf8SLina Iyer 318f55c73aeSArchana Sathyakumar static int pdc_setup_pin_mapping(struct device_node *np) 319f55c73aeSArchana Sathyakumar { 320f55c73aeSArchana Sathyakumar int ret, n; 321f55c73aeSArchana Sathyakumar 322f55c73aeSArchana Sathyakumar n = of_property_count_elems_of_size(np, "qcom,pdc-ranges", sizeof(u32)); 323f55c73aeSArchana Sathyakumar if (n <= 0 || n % 3) 324f55c73aeSArchana Sathyakumar return -EINVAL; 325f55c73aeSArchana Sathyakumar 326f55c73aeSArchana Sathyakumar pdc_region_cnt = n / 3; 327f55c73aeSArchana Sathyakumar pdc_region = kcalloc(pdc_region_cnt, sizeof(*pdc_region), GFP_KERNEL); 328f55c73aeSArchana Sathyakumar if (!pdc_region) { 329f55c73aeSArchana Sathyakumar pdc_region_cnt = 0; 330f55c73aeSArchana Sathyakumar return -ENOMEM; 331f55c73aeSArchana Sathyakumar } 332f55c73aeSArchana Sathyakumar 333f55c73aeSArchana Sathyakumar for (n = 0; n < pdc_region_cnt; n++) { 334f55c73aeSArchana Sathyakumar ret = of_property_read_u32_index(np, "qcom,pdc-ranges", 335f55c73aeSArchana Sathyakumar n * 3 + 0, 336f55c73aeSArchana Sathyakumar &pdc_region[n].pin_base); 337f55c73aeSArchana Sathyakumar if (ret) 338f55c73aeSArchana Sathyakumar return ret; 339f55c73aeSArchana Sathyakumar ret = of_property_read_u32_index(np, "qcom,pdc-ranges", 340f55c73aeSArchana Sathyakumar n * 3 + 1, 341f55c73aeSArchana Sathyakumar &pdc_region[n].parent_base); 342f55c73aeSArchana Sathyakumar if (ret) 343f55c73aeSArchana Sathyakumar return ret; 344f55c73aeSArchana Sathyakumar ret = of_property_read_u32_index(np, "qcom,pdc-ranges", 345f55c73aeSArchana Sathyakumar n * 3 + 2, 346f55c73aeSArchana Sathyakumar &pdc_region[n].cnt); 347f55c73aeSArchana Sathyakumar if (ret) 348f55c73aeSArchana Sathyakumar return ret; 349f55c73aeSArchana Sathyakumar } 350f55c73aeSArchana Sathyakumar 351f55c73aeSArchana Sathyakumar return 0; 352f55c73aeSArchana Sathyakumar } 353f55c73aeSArchana Sathyakumar 354f55c73aeSArchana Sathyakumar static int qcom_pdc_init(struct device_node *node, struct device_node *parent) 355f55c73aeSArchana Sathyakumar { 35681ef8bf8SLina Iyer struct irq_domain *parent_domain, *pdc_domain, *pdc_gpio_domain; 357f55c73aeSArchana Sathyakumar int ret; 358f55c73aeSArchana Sathyakumar 359f55c73aeSArchana Sathyakumar pdc_base = of_iomap(node, 0); 360f55c73aeSArchana Sathyakumar if (!pdc_base) { 361f55c73aeSArchana Sathyakumar pr_err("%pOF: unable to map PDC registers\n", node); 362f55c73aeSArchana Sathyakumar return -ENXIO; 363f55c73aeSArchana Sathyakumar } 364f55c73aeSArchana Sathyakumar 365f55c73aeSArchana Sathyakumar parent_domain = irq_find_host(parent); 366f55c73aeSArchana Sathyakumar if (!parent_domain) { 367f55c73aeSArchana Sathyakumar pr_err("%pOF: unable to find PDC's parent domain\n", node); 368f55c73aeSArchana Sathyakumar ret = -ENXIO; 369f55c73aeSArchana Sathyakumar goto fail; 370f55c73aeSArchana Sathyakumar } 371f55c73aeSArchana Sathyakumar 372f55c73aeSArchana Sathyakumar ret = pdc_setup_pin_mapping(node); 373f55c73aeSArchana Sathyakumar if (ret) { 374f55c73aeSArchana Sathyakumar pr_err("%pOF: failed to init PDC pin-hwirq mapping\n", node); 375f55c73aeSArchana Sathyakumar goto fail; 376f55c73aeSArchana Sathyakumar } 377f55c73aeSArchana Sathyakumar 378f55c73aeSArchana Sathyakumar pdc_domain = irq_domain_create_hierarchy(parent_domain, 0, PDC_MAX_IRQS, 379f55c73aeSArchana Sathyakumar of_fwnode_handle(node), 380f55c73aeSArchana Sathyakumar &qcom_pdc_ops, NULL); 381f55c73aeSArchana Sathyakumar if (!pdc_domain) { 382f55c73aeSArchana Sathyakumar pr_err("%pOF: GIC domain add failed\n", node); 383f55c73aeSArchana Sathyakumar ret = -ENOMEM; 384f55c73aeSArchana Sathyakumar goto fail; 385f55c73aeSArchana Sathyakumar } 386f55c73aeSArchana Sathyakumar 38781ef8bf8SLina Iyer pdc_gpio_domain = irq_domain_create_hierarchy(parent_domain, 38881ef8bf8SLina Iyer IRQ_DOMAIN_FLAG_QCOM_PDC_WAKEUP, 38981ef8bf8SLina Iyer PDC_MAX_GPIO_IRQS, 39081ef8bf8SLina Iyer of_fwnode_handle(node), 39181ef8bf8SLina Iyer &qcom_pdc_gpio_ops, NULL); 39281ef8bf8SLina Iyer if (!pdc_gpio_domain) { 39381ef8bf8SLina Iyer pr_err("%pOF: PDC domain add failed for GPIO domain\n", node); 39481ef8bf8SLina Iyer ret = -ENOMEM; 39581ef8bf8SLina Iyer goto remove; 39681ef8bf8SLina Iyer } 39781ef8bf8SLina Iyer 39881ef8bf8SLina Iyer irq_domain_update_bus_token(pdc_gpio_domain, DOMAIN_BUS_WAKEUP); 39981ef8bf8SLina Iyer 400f55c73aeSArchana Sathyakumar return 0; 401f55c73aeSArchana Sathyakumar 40281ef8bf8SLina Iyer remove: 40381ef8bf8SLina Iyer irq_domain_remove(pdc_domain); 404f55c73aeSArchana Sathyakumar fail: 405f55c73aeSArchana Sathyakumar kfree(pdc_region); 406f55c73aeSArchana Sathyakumar iounmap(pdc_base); 407f55c73aeSArchana Sathyakumar return ret; 408f55c73aeSArchana Sathyakumar } 409f55c73aeSArchana Sathyakumar 4108e4d5a5bSRajendra Nayak IRQCHIP_DECLARE(qcom_pdc, "qcom,pdc", qcom_pdc_init); 411