1f55c73aeSArchana Sathyakumar // SPDX-License-Identifier: GPL-2.0 2f55c73aeSArchana Sathyakumar /* 3b2bb01edSLina Iyer * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. 4f55c73aeSArchana Sathyakumar */ 5f55c73aeSArchana Sathyakumar 6f55c73aeSArchana Sathyakumar #include <linux/err.h> 7f55c73aeSArchana Sathyakumar #include <linux/init.h> 8e71374c0SMaulik Shah #include <linux/interrupt.h> 9f55c73aeSArchana Sathyakumar #include <linux/irq.h> 10f55c73aeSArchana Sathyakumar #include <linux/irqchip.h> 11f55c73aeSArchana Sathyakumar #include <linux/irqdomain.h> 12f55c73aeSArchana Sathyakumar #include <linux/io.h> 13f55c73aeSArchana Sathyakumar #include <linux/kernel.h> 14f55c73aeSArchana Sathyakumar #include <linux/of.h> 15f55c73aeSArchana Sathyakumar #include <linux/of_address.h> 16f55c73aeSArchana Sathyakumar #include <linux/of_device.h> 1781ef8bf8SLina Iyer #include <linux/soc/qcom/irq.h> 18f55c73aeSArchana Sathyakumar #include <linux/spinlock.h> 19f55c73aeSArchana Sathyakumar #include <linux/slab.h> 20f55c73aeSArchana Sathyakumar #include <linux/types.h> 21f55c73aeSArchana Sathyakumar 22b2bb01edSLina Iyer #define PDC_MAX_IRQS 168 2381ef8bf8SLina Iyer #define PDC_MAX_GPIO_IRQS 256 24f55c73aeSArchana Sathyakumar 25f55c73aeSArchana Sathyakumar #define CLEAR_INTR(reg, intr) (reg & ~(1 << intr)) 26f55c73aeSArchana Sathyakumar #define ENABLE_INTR(reg, intr) (reg | (1 << intr)) 27f55c73aeSArchana Sathyakumar 28f55c73aeSArchana Sathyakumar #define IRQ_ENABLE_BANK 0x10 29f55c73aeSArchana Sathyakumar #define IRQ_i_CFG 0x110 30f55c73aeSArchana Sathyakumar 3181ef8bf8SLina Iyer #define PDC_NO_PARENT_IRQ ~0UL 3281ef8bf8SLina Iyer 33f55c73aeSArchana Sathyakumar struct pdc_pin_region { 34f55c73aeSArchana Sathyakumar u32 pin_base; 35f55c73aeSArchana Sathyakumar u32 parent_base; 36f55c73aeSArchana Sathyakumar u32 cnt; 37f55c73aeSArchana Sathyakumar }; 38f55c73aeSArchana Sathyakumar 39f55c73aeSArchana Sathyakumar static DEFINE_RAW_SPINLOCK(pdc_lock); 40f55c73aeSArchana Sathyakumar static void __iomem *pdc_base; 41f55c73aeSArchana Sathyakumar static struct pdc_pin_region *pdc_region; 42f55c73aeSArchana Sathyakumar static int pdc_region_cnt; 43f55c73aeSArchana Sathyakumar 44f55c73aeSArchana Sathyakumar static void pdc_reg_write(int reg, u32 i, u32 val) 45f55c73aeSArchana Sathyakumar { 46f55c73aeSArchana Sathyakumar writel_relaxed(val, pdc_base + reg + i * sizeof(u32)); 47f55c73aeSArchana Sathyakumar } 48f55c73aeSArchana Sathyakumar 49f55c73aeSArchana Sathyakumar static u32 pdc_reg_read(int reg, u32 i) 50f55c73aeSArchana Sathyakumar { 51f55c73aeSArchana Sathyakumar return readl_relaxed(pdc_base + reg + i * sizeof(u32)); 52f55c73aeSArchana Sathyakumar } 53f55c73aeSArchana Sathyakumar 54e71374c0SMaulik Shah static int qcom_pdc_gic_get_irqchip_state(struct irq_data *d, 55e71374c0SMaulik Shah enum irqchip_irq_state which, 56e71374c0SMaulik Shah bool *state) 57e71374c0SMaulik Shah { 58e71374c0SMaulik Shah if (d->hwirq == GPIO_NO_WAKE_IRQ) 59e71374c0SMaulik Shah return 0; 60e71374c0SMaulik Shah 61e71374c0SMaulik Shah return irq_chip_get_parent_state(d, which, state); 62e71374c0SMaulik Shah } 63e71374c0SMaulik Shah 64e71374c0SMaulik Shah static int qcom_pdc_gic_set_irqchip_state(struct irq_data *d, 65e71374c0SMaulik Shah enum irqchip_irq_state which, 66e71374c0SMaulik Shah bool value) 67e71374c0SMaulik Shah { 68e71374c0SMaulik Shah if (d->hwirq == GPIO_NO_WAKE_IRQ) 69e71374c0SMaulik Shah return 0; 70e71374c0SMaulik Shah 71e71374c0SMaulik Shah return irq_chip_set_parent_state(d, which, value); 72e71374c0SMaulik Shah } 73e71374c0SMaulik Shah 74f55c73aeSArchana Sathyakumar static void pdc_enable_intr(struct irq_data *d, bool on) 75f55c73aeSArchana Sathyakumar { 76f55c73aeSArchana Sathyakumar int pin_out = d->hwirq; 77f55c73aeSArchana Sathyakumar u32 index, mask; 78f55c73aeSArchana Sathyakumar u32 enable; 79f55c73aeSArchana Sathyakumar 80f55c73aeSArchana Sathyakumar index = pin_out / 32; 81f55c73aeSArchana Sathyakumar mask = pin_out % 32; 82f55c73aeSArchana Sathyakumar 83f55c73aeSArchana Sathyakumar raw_spin_lock(&pdc_lock); 84f55c73aeSArchana Sathyakumar enable = pdc_reg_read(IRQ_ENABLE_BANK, index); 85f55c73aeSArchana Sathyakumar enable = on ? ENABLE_INTR(enable, mask) : CLEAR_INTR(enable, mask); 86f55c73aeSArchana Sathyakumar pdc_reg_write(IRQ_ENABLE_BANK, index, enable); 87f55c73aeSArchana Sathyakumar raw_spin_unlock(&pdc_lock); 88f55c73aeSArchana Sathyakumar } 89f55c73aeSArchana Sathyakumar 90da3f875aSLina Iyer static void qcom_pdc_gic_disable(struct irq_data *d) 91f55c73aeSArchana Sathyakumar { 9281ef8bf8SLina Iyer if (d->hwirq == GPIO_NO_WAKE_IRQ) 9381ef8bf8SLina Iyer return; 9481ef8bf8SLina Iyer 95f55c73aeSArchana Sathyakumar pdc_enable_intr(d, false); 96da3f875aSLina Iyer irq_chip_disable_parent(d); 97da3f875aSLina Iyer } 98da3f875aSLina Iyer 99da3f875aSLina Iyer static void qcom_pdc_gic_enable(struct irq_data *d) 100da3f875aSLina Iyer { 10181ef8bf8SLina Iyer if (d->hwirq == GPIO_NO_WAKE_IRQ) 10281ef8bf8SLina Iyer return; 10381ef8bf8SLina Iyer 104da3f875aSLina Iyer pdc_enable_intr(d, true); 105da3f875aSLina Iyer irq_chip_enable_parent(d); 106da3f875aSLina Iyer } 107da3f875aSLina Iyer 108da3f875aSLina Iyer static void qcom_pdc_gic_mask(struct irq_data *d) 109da3f875aSLina Iyer { 11081ef8bf8SLina Iyer if (d->hwirq == GPIO_NO_WAKE_IRQ) 11181ef8bf8SLina Iyer return; 11281ef8bf8SLina Iyer 113f55c73aeSArchana Sathyakumar irq_chip_mask_parent(d); 114f55c73aeSArchana Sathyakumar } 115f55c73aeSArchana Sathyakumar 116f55c73aeSArchana Sathyakumar static void qcom_pdc_gic_unmask(struct irq_data *d) 117f55c73aeSArchana Sathyakumar { 11881ef8bf8SLina Iyer if (d->hwirq == GPIO_NO_WAKE_IRQ) 11981ef8bf8SLina Iyer return; 12081ef8bf8SLina Iyer 121f55c73aeSArchana Sathyakumar irq_chip_unmask_parent(d); 122f55c73aeSArchana Sathyakumar } 123f55c73aeSArchana Sathyakumar 124f55c73aeSArchana Sathyakumar /* 125f55c73aeSArchana Sathyakumar * GIC does not handle falling edge or active low. To allow falling edge and 126f55c73aeSArchana Sathyakumar * active low interrupts to be handled at GIC, PDC has an inverter that inverts 127f55c73aeSArchana Sathyakumar * falling edge into a rising edge and active low into an active high. 128f55c73aeSArchana Sathyakumar * For the inverter to work, the polarity bit in the IRQ_CONFIG register has to 129f55c73aeSArchana Sathyakumar * set as per the table below. 130f55c73aeSArchana Sathyakumar * Level sensitive active low LOW 131f55c73aeSArchana Sathyakumar * Rising edge sensitive NOT USED 132f55c73aeSArchana Sathyakumar * Falling edge sensitive LOW 133f55c73aeSArchana Sathyakumar * Dual Edge sensitive NOT USED 134f55c73aeSArchana Sathyakumar * Level sensitive active High HIGH 135f55c73aeSArchana Sathyakumar * Falling Edge sensitive NOT USED 136f55c73aeSArchana Sathyakumar * Rising edge sensitive HIGH 137f55c73aeSArchana Sathyakumar * Dual Edge sensitive HIGH 138f55c73aeSArchana Sathyakumar */ 139f55c73aeSArchana Sathyakumar enum pdc_irq_config_bits { 140f55c73aeSArchana Sathyakumar PDC_LEVEL_LOW = 0b000, 141f55c73aeSArchana Sathyakumar PDC_EDGE_FALLING = 0b010, 142f55c73aeSArchana Sathyakumar PDC_LEVEL_HIGH = 0b100, 143f55c73aeSArchana Sathyakumar PDC_EDGE_RISING = 0b110, 144f55c73aeSArchana Sathyakumar PDC_EDGE_DUAL = 0b111, 145f55c73aeSArchana Sathyakumar }; 146f55c73aeSArchana Sathyakumar 147f55c73aeSArchana Sathyakumar /** 148f55c73aeSArchana Sathyakumar * qcom_pdc_gic_set_type: Configure PDC for the interrupt 149f55c73aeSArchana Sathyakumar * 150f55c73aeSArchana Sathyakumar * @d: the interrupt data 151f55c73aeSArchana Sathyakumar * @type: the interrupt type 152f55c73aeSArchana Sathyakumar * 153f55c73aeSArchana Sathyakumar * If @type is edge triggered, forward that as Rising edge as PDC 154f55c73aeSArchana Sathyakumar * takes care of converting falling edge to rising edge signal 155f55c73aeSArchana Sathyakumar * If @type is level, then forward that as level high as PDC 156f55c73aeSArchana Sathyakumar * takes care of converting falling edge to rising edge signal 157f55c73aeSArchana Sathyakumar */ 158f55c73aeSArchana Sathyakumar static int qcom_pdc_gic_set_type(struct irq_data *d, unsigned int type) 159f55c73aeSArchana Sathyakumar { 160f55c73aeSArchana Sathyakumar int pin_out = d->hwirq; 161f55c73aeSArchana Sathyakumar enum pdc_irq_config_bits pdc_type; 162*2f5fbc43SDouglas Anderson enum pdc_irq_config_bits old_pdc_type; 163*2f5fbc43SDouglas Anderson int ret; 164f55c73aeSArchana Sathyakumar 16581ef8bf8SLina Iyer if (pin_out == GPIO_NO_WAKE_IRQ) 16681ef8bf8SLina Iyer return 0; 16781ef8bf8SLina Iyer 168f55c73aeSArchana Sathyakumar switch (type) { 169f55c73aeSArchana Sathyakumar case IRQ_TYPE_EDGE_RISING: 170f55c73aeSArchana Sathyakumar pdc_type = PDC_EDGE_RISING; 171f55c73aeSArchana Sathyakumar break; 172f55c73aeSArchana Sathyakumar case IRQ_TYPE_EDGE_FALLING: 173f55c73aeSArchana Sathyakumar pdc_type = PDC_EDGE_FALLING; 174f55c73aeSArchana Sathyakumar type = IRQ_TYPE_EDGE_RISING; 175f55c73aeSArchana Sathyakumar break; 176f55c73aeSArchana Sathyakumar case IRQ_TYPE_EDGE_BOTH: 177f55c73aeSArchana Sathyakumar pdc_type = PDC_EDGE_DUAL; 1787bae48b2SLina Iyer type = IRQ_TYPE_EDGE_RISING; 179f55c73aeSArchana Sathyakumar break; 180f55c73aeSArchana Sathyakumar case IRQ_TYPE_LEVEL_HIGH: 181f55c73aeSArchana Sathyakumar pdc_type = PDC_LEVEL_HIGH; 182f55c73aeSArchana Sathyakumar break; 183f55c73aeSArchana Sathyakumar case IRQ_TYPE_LEVEL_LOW: 184f55c73aeSArchana Sathyakumar pdc_type = PDC_LEVEL_LOW; 185f55c73aeSArchana Sathyakumar type = IRQ_TYPE_LEVEL_HIGH; 186f55c73aeSArchana Sathyakumar break; 187f55c73aeSArchana Sathyakumar default: 188f55c73aeSArchana Sathyakumar WARN_ON(1); 189f55c73aeSArchana Sathyakumar return -EINVAL; 190f55c73aeSArchana Sathyakumar } 191f55c73aeSArchana Sathyakumar 192*2f5fbc43SDouglas Anderson old_pdc_type = pdc_reg_read(IRQ_i_CFG, pin_out); 193f55c73aeSArchana Sathyakumar pdc_reg_write(IRQ_i_CFG, pin_out, pdc_type); 194f55c73aeSArchana Sathyakumar 195*2f5fbc43SDouglas Anderson ret = irq_chip_set_type_parent(d, type); 196*2f5fbc43SDouglas Anderson if (ret) 197*2f5fbc43SDouglas Anderson return ret; 198*2f5fbc43SDouglas Anderson 199*2f5fbc43SDouglas Anderson /* 200*2f5fbc43SDouglas Anderson * When we change types the PDC can give a phantom interrupt. 201*2f5fbc43SDouglas Anderson * Clear it. Specifically the phantom shows up when reconfiguring 202*2f5fbc43SDouglas Anderson * polarity of interrupt without changing the state of the signal 203*2f5fbc43SDouglas Anderson * but let's be consistent and clear it always. 204*2f5fbc43SDouglas Anderson * 205*2f5fbc43SDouglas Anderson * Doing this works because we have IRQCHIP_SET_TYPE_MASKED so the 206*2f5fbc43SDouglas Anderson * interrupt will be cleared before the rest of the system sees it. 207*2f5fbc43SDouglas Anderson */ 208*2f5fbc43SDouglas Anderson if (old_pdc_type != pdc_type) 209*2f5fbc43SDouglas Anderson irq_chip_set_parent_state(d, IRQCHIP_STATE_PENDING, false); 210*2f5fbc43SDouglas Anderson 211*2f5fbc43SDouglas Anderson return 0; 212f55c73aeSArchana Sathyakumar } 213f55c73aeSArchana Sathyakumar 214f55c73aeSArchana Sathyakumar static struct irq_chip qcom_pdc_gic_chip = { 215f55c73aeSArchana Sathyakumar .name = "PDC", 216f55c73aeSArchana Sathyakumar .irq_eoi = irq_chip_eoi_parent, 217f55c73aeSArchana Sathyakumar .irq_mask = qcom_pdc_gic_mask, 218f55c73aeSArchana Sathyakumar .irq_unmask = qcom_pdc_gic_unmask, 219da3f875aSLina Iyer .irq_disable = qcom_pdc_gic_disable, 220da3f875aSLina Iyer .irq_enable = qcom_pdc_gic_enable, 221e71374c0SMaulik Shah .irq_get_irqchip_state = qcom_pdc_gic_get_irqchip_state, 222e71374c0SMaulik Shah .irq_set_irqchip_state = qcom_pdc_gic_set_irqchip_state, 223f55c73aeSArchana Sathyakumar .irq_retrigger = irq_chip_retrigger_hierarchy, 224f55c73aeSArchana Sathyakumar .irq_set_type = qcom_pdc_gic_set_type, 225f55c73aeSArchana Sathyakumar .flags = IRQCHIP_MASK_ON_SUSPEND | 226f55c73aeSArchana Sathyakumar IRQCHIP_SET_TYPE_MASKED | 227299d7890SMaulik Shah IRQCHIP_SKIP_SET_WAKE | 228299d7890SMaulik Shah IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND, 229f55c73aeSArchana Sathyakumar .irq_set_vcpu_affinity = irq_chip_set_vcpu_affinity_parent, 230f55c73aeSArchana Sathyakumar .irq_set_affinity = irq_chip_set_affinity_parent, 231f55c73aeSArchana Sathyakumar }; 232f55c73aeSArchana Sathyakumar 233f55c73aeSArchana Sathyakumar static irq_hw_number_t get_parent_hwirq(int pin) 234f55c73aeSArchana Sathyakumar { 235f55c73aeSArchana Sathyakumar int i; 236f55c73aeSArchana Sathyakumar struct pdc_pin_region *region; 237f55c73aeSArchana Sathyakumar 238f55c73aeSArchana Sathyakumar for (i = 0; i < pdc_region_cnt; i++) { 239f55c73aeSArchana Sathyakumar region = &pdc_region[i]; 240f55c73aeSArchana Sathyakumar if (pin >= region->pin_base && 241f55c73aeSArchana Sathyakumar pin < region->pin_base + region->cnt) 242f55c73aeSArchana Sathyakumar return (region->parent_base + pin - region->pin_base); 243f55c73aeSArchana Sathyakumar } 244f55c73aeSArchana Sathyakumar 24581ef8bf8SLina Iyer return PDC_NO_PARENT_IRQ; 246f55c73aeSArchana Sathyakumar } 247f55c73aeSArchana Sathyakumar 248f55c73aeSArchana Sathyakumar static int qcom_pdc_translate(struct irq_domain *d, struct irq_fwspec *fwspec, 249f55c73aeSArchana Sathyakumar unsigned long *hwirq, unsigned int *type) 250f55c73aeSArchana Sathyakumar { 251f55c73aeSArchana Sathyakumar if (is_of_node(fwspec->fwnode)) { 252f55c73aeSArchana Sathyakumar if (fwspec->param_count != 2) 253f55c73aeSArchana Sathyakumar return -EINVAL; 254f55c73aeSArchana Sathyakumar 255f55c73aeSArchana Sathyakumar *hwirq = fwspec->param[0]; 256f55c73aeSArchana Sathyakumar *type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK; 257f55c73aeSArchana Sathyakumar return 0; 258f55c73aeSArchana Sathyakumar } 259f55c73aeSArchana Sathyakumar 260f55c73aeSArchana Sathyakumar return -EINVAL; 261f55c73aeSArchana Sathyakumar } 262f55c73aeSArchana Sathyakumar 263f55c73aeSArchana Sathyakumar static int qcom_pdc_alloc(struct irq_domain *domain, unsigned int virq, 264f55c73aeSArchana Sathyakumar unsigned int nr_irqs, void *data) 265f55c73aeSArchana Sathyakumar { 266f55c73aeSArchana Sathyakumar struct irq_fwspec *fwspec = data; 267f55c73aeSArchana Sathyakumar struct irq_fwspec parent_fwspec; 268f55c73aeSArchana Sathyakumar irq_hw_number_t hwirq, parent_hwirq; 269f55c73aeSArchana Sathyakumar unsigned int type; 270f55c73aeSArchana Sathyakumar int ret; 271f55c73aeSArchana Sathyakumar 272f55c73aeSArchana Sathyakumar ret = qcom_pdc_translate(domain, fwspec, &hwirq, &type); 273f55c73aeSArchana Sathyakumar if (ret) 27481ef8bf8SLina Iyer return ret; 275f55c73aeSArchana Sathyakumar 276f55c73aeSArchana Sathyakumar ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq, 277f55c73aeSArchana Sathyakumar &qcom_pdc_gic_chip, NULL); 278f55c73aeSArchana Sathyakumar if (ret) 279f55c73aeSArchana Sathyakumar return ret; 280f55c73aeSArchana Sathyakumar 28181ef8bf8SLina Iyer parent_hwirq = get_parent_hwirq(hwirq); 28281ef8bf8SLina Iyer if (parent_hwirq == PDC_NO_PARENT_IRQ) 28381ef8bf8SLina Iyer return 0; 28481ef8bf8SLina Iyer 285f55c73aeSArchana Sathyakumar if (type & IRQ_TYPE_EDGE_BOTH) 286f55c73aeSArchana Sathyakumar type = IRQ_TYPE_EDGE_RISING; 287f55c73aeSArchana Sathyakumar 288f55c73aeSArchana Sathyakumar if (type & IRQ_TYPE_LEVEL_MASK) 289f55c73aeSArchana Sathyakumar type = IRQ_TYPE_LEVEL_HIGH; 290f55c73aeSArchana Sathyakumar 291f55c73aeSArchana Sathyakumar parent_fwspec.fwnode = domain->parent->fwnode; 292f55c73aeSArchana Sathyakumar parent_fwspec.param_count = 3; 293f55c73aeSArchana Sathyakumar parent_fwspec.param[0] = 0; 294f55c73aeSArchana Sathyakumar parent_fwspec.param[1] = parent_hwirq; 295f55c73aeSArchana Sathyakumar parent_fwspec.param[2] = type; 296f55c73aeSArchana Sathyakumar 297f55c73aeSArchana Sathyakumar return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, 298f55c73aeSArchana Sathyakumar &parent_fwspec); 299f55c73aeSArchana Sathyakumar } 300f55c73aeSArchana Sathyakumar 301f55c73aeSArchana Sathyakumar static const struct irq_domain_ops qcom_pdc_ops = { 302f55c73aeSArchana Sathyakumar .translate = qcom_pdc_translate, 303f55c73aeSArchana Sathyakumar .alloc = qcom_pdc_alloc, 304f55c73aeSArchana Sathyakumar .free = irq_domain_free_irqs_common, 305f55c73aeSArchana Sathyakumar }; 306f55c73aeSArchana Sathyakumar 30781ef8bf8SLina Iyer static int qcom_pdc_gpio_alloc(struct irq_domain *domain, unsigned int virq, 30881ef8bf8SLina Iyer unsigned int nr_irqs, void *data) 30981ef8bf8SLina Iyer { 31081ef8bf8SLina Iyer struct irq_fwspec *fwspec = data; 31181ef8bf8SLina Iyer struct irq_fwspec parent_fwspec; 31281ef8bf8SLina Iyer irq_hw_number_t hwirq, parent_hwirq; 31381ef8bf8SLina Iyer unsigned int type; 31481ef8bf8SLina Iyer int ret; 31581ef8bf8SLina Iyer 31681ef8bf8SLina Iyer ret = qcom_pdc_translate(domain, fwspec, &hwirq, &type); 31781ef8bf8SLina Iyer if (ret) 31881ef8bf8SLina Iyer return ret; 31981ef8bf8SLina Iyer 32081ef8bf8SLina Iyer ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq, 32181ef8bf8SLina Iyer &qcom_pdc_gic_chip, NULL); 32281ef8bf8SLina Iyer if (ret) 32381ef8bf8SLina Iyer return ret; 32481ef8bf8SLina Iyer 32581ef8bf8SLina Iyer if (hwirq == GPIO_NO_WAKE_IRQ) 32681ef8bf8SLina Iyer return 0; 32781ef8bf8SLina Iyer 32881ef8bf8SLina Iyer parent_hwirq = get_parent_hwirq(hwirq); 32981ef8bf8SLina Iyer if (parent_hwirq == PDC_NO_PARENT_IRQ) 33081ef8bf8SLina Iyer return 0; 33181ef8bf8SLina Iyer 33281ef8bf8SLina Iyer if (type & IRQ_TYPE_EDGE_BOTH) 33381ef8bf8SLina Iyer type = IRQ_TYPE_EDGE_RISING; 33481ef8bf8SLina Iyer 33581ef8bf8SLina Iyer if (type & IRQ_TYPE_LEVEL_MASK) 33681ef8bf8SLina Iyer type = IRQ_TYPE_LEVEL_HIGH; 33781ef8bf8SLina Iyer 33881ef8bf8SLina Iyer parent_fwspec.fwnode = domain->parent->fwnode; 33981ef8bf8SLina Iyer parent_fwspec.param_count = 3; 34081ef8bf8SLina Iyer parent_fwspec.param[0] = 0; 34181ef8bf8SLina Iyer parent_fwspec.param[1] = parent_hwirq; 34281ef8bf8SLina Iyer parent_fwspec.param[2] = type; 34381ef8bf8SLina Iyer 34481ef8bf8SLina Iyer return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, 34581ef8bf8SLina Iyer &parent_fwspec); 34681ef8bf8SLina Iyer } 34781ef8bf8SLina Iyer 34881ef8bf8SLina Iyer static int qcom_pdc_gpio_domain_select(struct irq_domain *d, 34981ef8bf8SLina Iyer struct irq_fwspec *fwspec, 35081ef8bf8SLina Iyer enum irq_domain_bus_token bus_token) 35181ef8bf8SLina Iyer { 35281ef8bf8SLina Iyer return bus_token == DOMAIN_BUS_WAKEUP; 35381ef8bf8SLina Iyer } 35481ef8bf8SLina Iyer 35581ef8bf8SLina Iyer static const struct irq_domain_ops qcom_pdc_gpio_ops = { 35681ef8bf8SLina Iyer .select = qcom_pdc_gpio_domain_select, 35781ef8bf8SLina Iyer .alloc = qcom_pdc_gpio_alloc, 35881ef8bf8SLina Iyer .free = irq_domain_free_irqs_common, 35981ef8bf8SLina Iyer }; 36081ef8bf8SLina Iyer 361f55c73aeSArchana Sathyakumar static int pdc_setup_pin_mapping(struct device_node *np) 362f55c73aeSArchana Sathyakumar { 363d7bc63faSMaulik Shah int ret, n, i; 364d7bc63faSMaulik Shah u32 irq_index, reg_index, val; 365f55c73aeSArchana Sathyakumar 366f55c73aeSArchana Sathyakumar n = of_property_count_elems_of_size(np, "qcom,pdc-ranges", sizeof(u32)); 367f55c73aeSArchana Sathyakumar if (n <= 0 || n % 3) 368f55c73aeSArchana Sathyakumar return -EINVAL; 369f55c73aeSArchana Sathyakumar 370f55c73aeSArchana Sathyakumar pdc_region_cnt = n / 3; 371f55c73aeSArchana Sathyakumar pdc_region = kcalloc(pdc_region_cnt, sizeof(*pdc_region), GFP_KERNEL); 372f55c73aeSArchana Sathyakumar if (!pdc_region) { 373f55c73aeSArchana Sathyakumar pdc_region_cnt = 0; 374f55c73aeSArchana Sathyakumar return -ENOMEM; 375f55c73aeSArchana Sathyakumar } 376f55c73aeSArchana Sathyakumar 377f55c73aeSArchana Sathyakumar for (n = 0; n < pdc_region_cnt; n++) { 378f55c73aeSArchana Sathyakumar ret = of_property_read_u32_index(np, "qcom,pdc-ranges", 379f55c73aeSArchana Sathyakumar n * 3 + 0, 380f55c73aeSArchana Sathyakumar &pdc_region[n].pin_base); 381f55c73aeSArchana Sathyakumar if (ret) 382f55c73aeSArchana Sathyakumar return ret; 383f55c73aeSArchana Sathyakumar ret = of_property_read_u32_index(np, "qcom,pdc-ranges", 384f55c73aeSArchana Sathyakumar n * 3 + 1, 385f55c73aeSArchana Sathyakumar &pdc_region[n].parent_base); 386f55c73aeSArchana Sathyakumar if (ret) 387f55c73aeSArchana Sathyakumar return ret; 388f55c73aeSArchana Sathyakumar ret = of_property_read_u32_index(np, "qcom,pdc-ranges", 389f55c73aeSArchana Sathyakumar n * 3 + 2, 390f55c73aeSArchana Sathyakumar &pdc_region[n].cnt); 391f55c73aeSArchana Sathyakumar if (ret) 392f55c73aeSArchana Sathyakumar return ret; 393d7bc63faSMaulik Shah 394d7bc63faSMaulik Shah for (i = 0; i < pdc_region[n].cnt; i++) { 395d7bc63faSMaulik Shah reg_index = (i + pdc_region[n].pin_base) >> 5; 396d7bc63faSMaulik Shah irq_index = (i + pdc_region[n].pin_base) & 0x1f; 397d7bc63faSMaulik Shah val = pdc_reg_read(IRQ_ENABLE_BANK, reg_index); 398d7bc63faSMaulik Shah val &= ~BIT(irq_index); 399d7bc63faSMaulik Shah pdc_reg_write(IRQ_ENABLE_BANK, reg_index, val); 400d7bc63faSMaulik Shah } 401f55c73aeSArchana Sathyakumar } 402f55c73aeSArchana Sathyakumar 403f55c73aeSArchana Sathyakumar return 0; 404f55c73aeSArchana Sathyakumar } 405f55c73aeSArchana Sathyakumar 406f55c73aeSArchana Sathyakumar static int qcom_pdc_init(struct device_node *node, struct device_node *parent) 407f55c73aeSArchana Sathyakumar { 40881ef8bf8SLina Iyer struct irq_domain *parent_domain, *pdc_domain, *pdc_gpio_domain; 409f55c73aeSArchana Sathyakumar int ret; 410f55c73aeSArchana Sathyakumar 411f55c73aeSArchana Sathyakumar pdc_base = of_iomap(node, 0); 412f55c73aeSArchana Sathyakumar if (!pdc_base) { 413f55c73aeSArchana Sathyakumar pr_err("%pOF: unable to map PDC registers\n", node); 414f55c73aeSArchana Sathyakumar return -ENXIO; 415f55c73aeSArchana Sathyakumar } 416f55c73aeSArchana Sathyakumar 417f55c73aeSArchana Sathyakumar parent_domain = irq_find_host(parent); 418f55c73aeSArchana Sathyakumar if (!parent_domain) { 419f55c73aeSArchana Sathyakumar pr_err("%pOF: unable to find PDC's parent domain\n", node); 420f55c73aeSArchana Sathyakumar ret = -ENXIO; 421f55c73aeSArchana Sathyakumar goto fail; 422f55c73aeSArchana Sathyakumar } 423f55c73aeSArchana Sathyakumar 424f55c73aeSArchana Sathyakumar ret = pdc_setup_pin_mapping(node); 425f55c73aeSArchana Sathyakumar if (ret) { 426f55c73aeSArchana Sathyakumar pr_err("%pOF: failed to init PDC pin-hwirq mapping\n", node); 427f55c73aeSArchana Sathyakumar goto fail; 428f55c73aeSArchana Sathyakumar } 429f55c73aeSArchana Sathyakumar 430f55c73aeSArchana Sathyakumar pdc_domain = irq_domain_create_hierarchy(parent_domain, 0, PDC_MAX_IRQS, 431f55c73aeSArchana Sathyakumar of_fwnode_handle(node), 432f55c73aeSArchana Sathyakumar &qcom_pdc_ops, NULL); 433f55c73aeSArchana Sathyakumar if (!pdc_domain) { 434f55c73aeSArchana Sathyakumar pr_err("%pOF: GIC domain add failed\n", node); 435f55c73aeSArchana Sathyakumar ret = -ENOMEM; 436f55c73aeSArchana Sathyakumar goto fail; 437f55c73aeSArchana Sathyakumar } 438f55c73aeSArchana Sathyakumar 43981ef8bf8SLina Iyer pdc_gpio_domain = irq_domain_create_hierarchy(parent_domain, 44081ef8bf8SLina Iyer IRQ_DOMAIN_FLAG_QCOM_PDC_WAKEUP, 44181ef8bf8SLina Iyer PDC_MAX_GPIO_IRQS, 44281ef8bf8SLina Iyer of_fwnode_handle(node), 44381ef8bf8SLina Iyer &qcom_pdc_gpio_ops, NULL); 44481ef8bf8SLina Iyer if (!pdc_gpio_domain) { 44581ef8bf8SLina Iyer pr_err("%pOF: PDC domain add failed for GPIO domain\n", node); 44681ef8bf8SLina Iyer ret = -ENOMEM; 44781ef8bf8SLina Iyer goto remove; 44881ef8bf8SLina Iyer } 44981ef8bf8SLina Iyer 45081ef8bf8SLina Iyer irq_domain_update_bus_token(pdc_gpio_domain, DOMAIN_BUS_WAKEUP); 45181ef8bf8SLina Iyer 452f55c73aeSArchana Sathyakumar return 0; 453f55c73aeSArchana Sathyakumar 45481ef8bf8SLina Iyer remove: 45581ef8bf8SLina Iyer irq_domain_remove(pdc_domain); 456f55c73aeSArchana Sathyakumar fail: 457f55c73aeSArchana Sathyakumar kfree(pdc_region); 458f55c73aeSArchana Sathyakumar iounmap(pdc_base); 459f55c73aeSArchana Sathyakumar return ret; 460f55c73aeSArchana Sathyakumar } 461f55c73aeSArchana Sathyakumar 462a150dac5SMarc Zyngier IRQCHIP_DECLARE(qcom_pdc, "qcom,pdc", qcom_pdc_init); 463