1 /* 2 * linux/drivers/irqchip/irq-zevio.c 3 * 4 * Copyright (C) 2013 Daniel Tang <tangrs@tangrs.id.au> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2, as 8 * published by the Free Software Foundation. 9 * 10 */ 11 12 #include <linux/io.h> 13 #include <linux/irq.h> 14 #include <linux/of.h> 15 #include <linux/of_address.h> 16 #include <linux/of_irq.h> 17 18 #include <asm/mach/irq.h> 19 #include <asm/exception.h> 20 21 #include "irqchip.h" 22 23 #define IO_STATUS 0x000 24 #define IO_RAW_STATUS 0x004 25 #define IO_ENABLE 0x008 26 #define IO_DISABLE 0x00C 27 #define IO_CURRENT 0x020 28 #define IO_RESET 0x028 29 #define IO_MAX_PRIOTY 0x02C 30 31 #define IO_IRQ_BASE 0x000 32 #define IO_FIQ_BASE 0x100 33 34 #define IO_INVERT_SEL 0x200 35 #define IO_STICKY_SEL 0x204 36 #define IO_PRIORITY_SEL 0x300 37 38 #define MAX_INTRS 32 39 #define FIQ_START MAX_INTRS 40 41 static struct irq_domain *zevio_irq_domain; 42 static void __iomem *zevio_irq_io; 43 44 static void zevio_irq_ack(struct irq_data *irqd) 45 { 46 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(irqd); 47 struct irq_chip_regs *regs = 48 &container_of(irqd->chip, struct irq_chip_type, chip)->regs; 49 50 readl(gc->reg_base + regs->ack); 51 } 52 53 static void __exception_irq_entry zevio_handle_irq(struct pt_regs *regs) 54 { 55 int irqnr; 56 57 while (readl(zevio_irq_io + IO_STATUS)) { 58 irqnr = readl(zevio_irq_io + IO_CURRENT); 59 handle_domain_irq(zevio_irq_domain, irqnr, regs); 60 }; 61 } 62 63 static void __init zevio_init_irq_base(void __iomem *base) 64 { 65 /* Disable all interrupts */ 66 writel(~0, base + IO_DISABLE); 67 68 /* Accept interrupts of all priorities */ 69 writel(0xF, base + IO_MAX_PRIOTY); 70 71 /* Reset existing interrupts */ 72 readl(base + IO_RESET); 73 } 74 75 static int __init zevio_of_init(struct device_node *node, 76 struct device_node *parent) 77 { 78 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; 79 struct irq_chip_generic *gc; 80 int ret; 81 82 if (WARN_ON(zevio_irq_io || zevio_irq_domain)) 83 return -EBUSY; 84 85 zevio_irq_io = of_iomap(node, 0); 86 BUG_ON(!zevio_irq_io); 87 88 /* Do not invert interrupt status bits */ 89 writel(~0, zevio_irq_io + IO_INVERT_SEL); 90 91 /* Disable sticky interrupts */ 92 writel(0, zevio_irq_io + IO_STICKY_SEL); 93 94 /* We don't use IRQ priorities. Set each IRQ to highest priority. */ 95 memset_io(zevio_irq_io + IO_PRIORITY_SEL, 0, MAX_INTRS * sizeof(u32)); 96 97 /* Init IRQ and FIQ */ 98 zevio_init_irq_base(zevio_irq_io + IO_IRQ_BASE); 99 zevio_init_irq_base(zevio_irq_io + IO_FIQ_BASE); 100 101 zevio_irq_domain = irq_domain_add_linear(node, MAX_INTRS, 102 &irq_generic_chip_ops, NULL); 103 BUG_ON(!zevio_irq_domain); 104 105 ret = irq_alloc_domain_generic_chips(zevio_irq_domain, MAX_INTRS, 1, 106 "zevio_intc", handle_level_irq, 107 clr, 0, IRQ_GC_INIT_MASK_CACHE); 108 BUG_ON(ret); 109 110 gc = irq_get_domain_generic_chip(zevio_irq_domain, 0); 111 gc->reg_base = zevio_irq_io; 112 gc->chip_types[0].chip.irq_ack = zevio_irq_ack; 113 gc->chip_types[0].chip.irq_mask = irq_gc_mask_disable_reg; 114 gc->chip_types[0].chip.irq_unmask = irq_gc_unmask_enable_reg; 115 gc->chip_types[0].regs.mask = IO_IRQ_BASE + IO_ENABLE; 116 gc->chip_types[0].regs.enable = IO_IRQ_BASE + IO_ENABLE; 117 gc->chip_types[0].regs.disable = IO_IRQ_BASE + IO_DISABLE; 118 gc->chip_types[0].regs.ack = IO_IRQ_BASE + IO_RESET; 119 120 set_handle_irq(zevio_handle_irq); 121 122 pr_info("TI-NSPIRE classic IRQ controller\n"); 123 return 0; 124 } 125 126 IRQCHIP_DECLARE(zevio_irq, "lsi,zevio-intc", zevio_of_init); 127