1cbd1de2eSMax Filippov /* 2cbd1de2eSMax Filippov * Xtensa built-in interrupt controller 3cbd1de2eSMax Filippov * 4cbd1de2eSMax Filippov * Copyright (C) 2002 - 2013 Tensilica, Inc. 5cbd1de2eSMax Filippov * Copyright (C) 1992, 1998 Linus Torvalds, Ingo Molnar 6cbd1de2eSMax Filippov * 7cbd1de2eSMax Filippov * This file is subject to the terms and conditions of the GNU General Public 8cbd1de2eSMax Filippov * License. See the file "COPYING" in the main directory of this archive 9cbd1de2eSMax Filippov * for more details. 10cbd1de2eSMax Filippov * 11cbd1de2eSMax Filippov * Chris Zankel <chris@zankel.net> 12cbd1de2eSMax Filippov * Kevin Chea 13cbd1de2eSMax Filippov */ 14cbd1de2eSMax Filippov 15cbd1de2eSMax Filippov #include <linux/interrupt.h> 16cbd1de2eSMax Filippov #include <linux/irqdomain.h> 17cbd1de2eSMax Filippov #include <linux/irq.h> 1841a83e06SJoel Porquet #include <linux/irqchip.h> 19cbd1de2eSMax Filippov #include <linux/of.h> 20cbd1de2eSMax Filippov 21cbd1de2eSMax Filippov unsigned int cached_irq_mask; 22cbd1de2eSMax Filippov 23cbd1de2eSMax Filippov /* 24cbd1de2eSMax Filippov * Device Tree IRQ specifier translation function which works with one or 25cbd1de2eSMax Filippov * two cell bindings. First cell value maps directly to the hwirq number. 26cbd1de2eSMax Filippov * Second cell if present specifies whether hwirq number is external (1) or 27cbd1de2eSMax Filippov * internal (0). 28cbd1de2eSMax Filippov */ 29cbd1de2eSMax Filippov static int xtensa_pic_irq_domain_xlate(struct irq_domain *d, 30cbd1de2eSMax Filippov struct device_node *ctrlr, 31cbd1de2eSMax Filippov const u32 *intspec, unsigned int intsize, 32cbd1de2eSMax Filippov unsigned long *out_hwirq, unsigned int *out_type) 33cbd1de2eSMax Filippov { 34cbd1de2eSMax Filippov return xtensa_irq_domain_xlate(intspec, intsize, 35cbd1de2eSMax Filippov intspec[0], intspec[0], 36cbd1de2eSMax Filippov out_hwirq, out_type); 37cbd1de2eSMax Filippov } 38cbd1de2eSMax Filippov 39cbd1de2eSMax Filippov static const struct irq_domain_ops xtensa_irq_domain_ops = { 40cbd1de2eSMax Filippov .xlate = xtensa_pic_irq_domain_xlate, 41cbd1de2eSMax Filippov .map = xtensa_irq_map, 42cbd1de2eSMax Filippov }; 43cbd1de2eSMax Filippov 44cbd1de2eSMax Filippov static void xtensa_irq_mask(struct irq_data *d) 45cbd1de2eSMax Filippov { 46cbd1de2eSMax Filippov cached_irq_mask &= ~(1 << d->hwirq); 47cbd1de2eSMax Filippov set_sr(cached_irq_mask, intenable); 48cbd1de2eSMax Filippov } 49cbd1de2eSMax Filippov 50cbd1de2eSMax Filippov static void xtensa_irq_unmask(struct irq_data *d) 51cbd1de2eSMax Filippov { 52cbd1de2eSMax Filippov cached_irq_mask |= 1 << d->hwirq; 53cbd1de2eSMax Filippov set_sr(cached_irq_mask, intenable); 54cbd1de2eSMax Filippov } 55cbd1de2eSMax Filippov 56cbd1de2eSMax Filippov static void xtensa_irq_enable(struct irq_data *d) 57cbd1de2eSMax Filippov { 58cbd1de2eSMax Filippov variant_irq_enable(d->hwirq); 59cbd1de2eSMax Filippov xtensa_irq_unmask(d); 60cbd1de2eSMax Filippov } 61cbd1de2eSMax Filippov 62cbd1de2eSMax Filippov static void xtensa_irq_disable(struct irq_data *d) 63cbd1de2eSMax Filippov { 64cbd1de2eSMax Filippov xtensa_irq_mask(d); 65cbd1de2eSMax Filippov variant_irq_disable(d->hwirq); 66cbd1de2eSMax Filippov } 67cbd1de2eSMax Filippov 68cbd1de2eSMax Filippov static void xtensa_irq_ack(struct irq_data *d) 69cbd1de2eSMax Filippov { 70cbd1de2eSMax Filippov set_sr(1 << d->hwirq, intclear); 71cbd1de2eSMax Filippov } 72cbd1de2eSMax Filippov 73cbd1de2eSMax Filippov static int xtensa_irq_retrigger(struct irq_data *d) 74cbd1de2eSMax Filippov { 75cbd1de2eSMax Filippov set_sr(1 << d->hwirq, intset); 76cbd1de2eSMax Filippov return 1; 77cbd1de2eSMax Filippov } 78cbd1de2eSMax Filippov 79cbd1de2eSMax Filippov static struct irq_chip xtensa_irq_chip = { 80cbd1de2eSMax Filippov .name = "xtensa", 81cbd1de2eSMax Filippov .irq_enable = xtensa_irq_enable, 82cbd1de2eSMax Filippov .irq_disable = xtensa_irq_disable, 83cbd1de2eSMax Filippov .irq_mask = xtensa_irq_mask, 84cbd1de2eSMax Filippov .irq_unmask = xtensa_irq_unmask, 85cbd1de2eSMax Filippov .irq_ack = xtensa_irq_ack, 86cbd1de2eSMax Filippov .irq_retrigger = xtensa_irq_retrigger, 87cbd1de2eSMax Filippov }; 88cbd1de2eSMax Filippov 89cbd1de2eSMax Filippov int __init xtensa_pic_init_legacy(struct device_node *interrupt_parent) 90cbd1de2eSMax Filippov { 91cbd1de2eSMax Filippov struct irq_domain *root_domain = 92e5c86679SMax Filippov irq_domain_add_legacy(NULL, NR_IRQS - 1, 1, 0, 93cbd1de2eSMax Filippov &xtensa_irq_domain_ops, &xtensa_irq_chip); 94cbd1de2eSMax Filippov irq_set_default_host(root_domain); 95cbd1de2eSMax Filippov return 0; 96cbd1de2eSMax Filippov } 97cbd1de2eSMax Filippov 98cbd1de2eSMax Filippov static int __init xtensa_pic_init(struct device_node *np, 99cbd1de2eSMax Filippov struct device_node *interrupt_parent) 100cbd1de2eSMax Filippov { 101cbd1de2eSMax Filippov struct irq_domain *root_domain = 102cbd1de2eSMax Filippov irq_domain_add_linear(np, NR_IRQS, &xtensa_irq_domain_ops, 103cbd1de2eSMax Filippov &xtensa_irq_chip); 104cbd1de2eSMax Filippov irq_set_default_host(root_domain); 105cbd1de2eSMax Filippov return 0; 106cbd1de2eSMax Filippov } 107cbd1de2eSMax Filippov IRQCHIP_DECLARE(xtensa_irq_chip, "cdns,xtensa-pic", xtensa_pic_init); 108