1cbd1de2eSMax Filippov /*
2cbd1de2eSMax Filippov  * Xtensa built-in interrupt controller
3cbd1de2eSMax Filippov  *
4cbd1de2eSMax Filippov  * Copyright (C) 2002 - 2013 Tensilica, Inc.
5cbd1de2eSMax Filippov  * Copyright (C) 1992, 1998 Linus Torvalds, Ingo Molnar
6cbd1de2eSMax Filippov  *
7cbd1de2eSMax Filippov  * This file is subject to the terms and conditions of the GNU General Public
8cbd1de2eSMax Filippov  * License.  See the file "COPYING" in the main directory of this archive
9cbd1de2eSMax Filippov  * for more details.
10cbd1de2eSMax Filippov  *
11cbd1de2eSMax Filippov  * Chris Zankel <chris@zankel.net>
12cbd1de2eSMax Filippov  * Kevin Chea
13cbd1de2eSMax Filippov  */
14cbd1de2eSMax Filippov 
15cbd1de2eSMax Filippov #include <linux/interrupt.h>
16cbd1de2eSMax Filippov #include <linux/irqdomain.h>
17cbd1de2eSMax Filippov #include <linux/irq.h>
1841a83e06SJoel Porquet #include <linux/irqchip.h>
19*9bdd26b6SArnd Bergmann #include <linux/irqchip/xtensa-pic.h>
20cbd1de2eSMax Filippov #include <linux/of.h>
21cbd1de2eSMax Filippov 
22cbd1de2eSMax Filippov unsigned int cached_irq_mask;
23cbd1de2eSMax Filippov 
24cbd1de2eSMax Filippov /*
25cbd1de2eSMax Filippov  * Device Tree IRQ specifier translation function which works with one or
26cbd1de2eSMax Filippov  * two cell bindings. First cell value maps directly to the hwirq number.
27cbd1de2eSMax Filippov  * Second cell if present specifies whether hwirq number is external (1) or
28cbd1de2eSMax Filippov  * internal (0).
29cbd1de2eSMax Filippov  */
xtensa_pic_irq_domain_xlate(struct irq_domain * d,struct device_node * ctrlr,const u32 * intspec,unsigned int intsize,unsigned long * out_hwirq,unsigned int * out_type)30cbd1de2eSMax Filippov static int xtensa_pic_irq_domain_xlate(struct irq_domain *d,
31cbd1de2eSMax Filippov 		struct device_node *ctrlr,
32cbd1de2eSMax Filippov 		const u32 *intspec, unsigned int intsize,
33cbd1de2eSMax Filippov 		unsigned long *out_hwirq, unsigned int *out_type)
34cbd1de2eSMax Filippov {
35cbd1de2eSMax Filippov 	return xtensa_irq_domain_xlate(intspec, intsize,
36cbd1de2eSMax Filippov 			intspec[0], intspec[0],
37cbd1de2eSMax Filippov 			out_hwirq, out_type);
38cbd1de2eSMax Filippov }
39cbd1de2eSMax Filippov 
40cbd1de2eSMax Filippov static const struct irq_domain_ops xtensa_irq_domain_ops = {
41cbd1de2eSMax Filippov 	.xlate = xtensa_pic_irq_domain_xlate,
42cbd1de2eSMax Filippov 	.map = xtensa_irq_map,
43cbd1de2eSMax Filippov };
44cbd1de2eSMax Filippov 
xtensa_irq_mask(struct irq_data * d)45cbd1de2eSMax Filippov static void xtensa_irq_mask(struct irq_data *d)
46cbd1de2eSMax Filippov {
47cbd1de2eSMax Filippov 	cached_irq_mask &= ~(1 << d->hwirq);
48cad6fadeSMax Filippov 	xtensa_set_sr(cached_irq_mask, intenable);
49cbd1de2eSMax Filippov }
50cbd1de2eSMax Filippov 
xtensa_irq_unmask(struct irq_data * d)51cbd1de2eSMax Filippov static void xtensa_irq_unmask(struct irq_data *d)
52cbd1de2eSMax Filippov {
53cbd1de2eSMax Filippov 	cached_irq_mask |= 1 << d->hwirq;
54cad6fadeSMax Filippov 	xtensa_set_sr(cached_irq_mask, intenable);
55cbd1de2eSMax Filippov }
56cbd1de2eSMax Filippov 
xtensa_irq_enable(struct irq_data * d)57cbd1de2eSMax Filippov static void xtensa_irq_enable(struct irq_data *d)
58cbd1de2eSMax Filippov {
59cbd1de2eSMax Filippov 	xtensa_irq_unmask(d);
60cbd1de2eSMax Filippov }
61cbd1de2eSMax Filippov 
xtensa_irq_disable(struct irq_data * d)62cbd1de2eSMax Filippov static void xtensa_irq_disable(struct irq_data *d)
63cbd1de2eSMax Filippov {
64cbd1de2eSMax Filippov 	xtensa_irq_mask(d);
65cbd1de2eSMax Filippov }
66cbd1de2eSMax Filippov 
xtensa_irq_ack(struct irq_data * d)67cbd1de2eSMax Filippov static void xtensa_irq_ack(struct irq_data *d)
68cbd1de2eSMax Filippov {
69cad6fadeSMax Filippov 	xtensa_set_sr(1 << d->hwirq, intclear);
70cbd1de2eSMax Filippov }
71cbd1de2eSMax Filippov 
xtensa_irq_retrigger(struct irq_data * d)72cbd1de2eSMax Filippov static int xtensa_irq_retrigger(struct irq_data *d)
73cbd1de2eSMax Filippov {
74bb665236SMax Filippov 	unsigned int mask = 1u << d->hwirq;
75bb665236SMax Filippov 
76bb665236SMax Filippov 	if (WARN_ON(mask & ~XCHAL_INTTYPE_MASK_SOFTWARE))
77bb665236SMax Filippov 		return 0;
78bb665236SMax Filippov 	xtensa_set_sr(mask, intset);
79cbd1de2eSMax Filippov 	return 1;
80cbd1de2eSMax Filippov }
81cbd1de2eSMax Filippov 
82cbd1de2eSMax Filippov static struct irq_chip xtensa_irq_chip = {
83cbd1de2eSMax Filippov 	.name		= "xtensa",
84cbd1de2eSMax Filippov 	.irq_enable	= xtensa_irq_enable,
85cbd1de2eSMax Filippov 	.irq_disable	= xtensa_irq_disable,
86cbd1de2eSMax Filippov 	.irq_mask	= xtensa_irq_mask,
87cbd1de2eSMax Filippov 	.irq_unmask	= xtensa_irq_unmask,
88cbd1de2eSMax Filippov 	.irq_ack	= xtensa_irq_ack,
89cbd1de2eSMax Filippov 	.irq_retrigger	= xtensa_irq_retrigger,
90cbd1de2eSMax Filippov };
91cbd1de2eSMax Filippov 
xtensa_pic_init_legacy(struct device_node * interrupt_parent)92cbd1de2eSMax Filippov int __init xtensa_pic_init_legacy(struct device_node *interrupt_parent)
93cbd1de2eSMax Filippov {
94cbd1de2eSMax Filippov 	struct irq_domain *root_domain =
95e5c86679SMax Filippov 		irq_domain_add_legacy(NULL, NR_IRQS - 1, 1, 0,
96cbd1de2eSMax Filippov 				&xtensa_irq_domain_ops, &xtensa_irq_chip);
97cbd1de2eSMax Filippov 	irq_set_default_host(root_domain);
98cbd1de2eSMax Filippov 	return 0;
99cbd1de2eSMax Filippov }
100cbd1de2eSMax Filippov 
xtensa_pic_init(struct device_node * np,struct device_node * interrupt_parent)101cbd1de2eSMax Filippov static int __init xtensa_pic_init(struct device_node *np,
102cbd1de2eSMax Filippov 		struct device_node *interrupt_parent)
103cbd1de2eSMax Filippov {
104cbd1de2eSMax Filippov 	struct irq_domain *root_domain =
105cbd1de2eSMax Filippov 		irq_domain_add_linear(np, NR_IRQS, &xtensa_irq_domain_ops,
106cbd1de2eSMax Filippov 				&xtensa_irq_chip);
107cbd1de2eSMax Filippov 	irq_set_default_host(root_domain);
108cbd1de2eSMax Filippov 	return 0;
109cbd1de2eSMax Filippov }
110cbd1de2eSMax Filippov IRQCHIP_DECLARE(xtensa_irq_chip, "cdns,xtensa-pic", xtensa_pic_init);
111