126a8e96aSMax Filippov /*
226a8e96aSMax Filippov * Xtensa MX interrupt distributor
326a8e96aSMax Filippov *
426a8e96aSMax Filippov * Copyright (C) 2002 - 2013 Tensilica, Inc.
526a8e96aSMax Filippov *
626a8e96aSMax Filippov * This file is subject to the terms and conditions of the GNU General Public
726a8e96aSMax Filippov * License. See the file "COPYING" in the main directory of this archive
826a8e96aSMax Filippov * for more details.
926a8e96aSMax Filippov */
1026a8e96aSMax Filippov
1126a8e96aSMax Filippov #include <linux/interrupt.h>
1226a8e96aSMax Filippov #include <linux/irqdomain.h>
1326a8e96aSMax Filippov #include <linux/irq.h>
1441a83e06SJoel Porquet #include <linux/irqchip.h>
15*373e4163SRandy Dunlap #include <linux/irqchip/xtensa-mx.h>
1626a8e96aSMax Filippov #include <linux/of.h>
1726a8e96aSMax Filippov
1826a8e96aSMax Filippov #include <asm/mxregs.h>
1926a8e96aSMax Filippov
2026a8e96aSMax Filippov #define HW_IRQ_IPI_COUNT 2
2126a8e96aSMax Filippov #define HW_IRQ_MX_BASE 2
2226a8e96aSMax Filippov #define HW_IRQ_EXTERN_BASE 3
2326a8e96aSMax Filippov
2426a8e96aSMax Filippov static DEFINE_PER_CPU(unsigned int, cached_irq_mask);
2526a8e96aSMax Filippov
xtensa_mx_irq_map(struct irq_domain * d,unsigned int irq,irq_hw_number_t hw)2626a8e96aSMax Filippov static int xtensa_mx_irq_map(struct irq_domain *d, unsigned int irq,
2726a8e96aSMax Filippov irq_hw_number_t hw)
2826a8e96aSMax Filippov {
2926a8e96aSMax Filippov if (hw < HW_IRQ_IPI_COUNT) {
3026a8e96aSMax Filippov struct irq_chip *irq_chip = d->host_data;
3126a8e96aSMax Filippov irq_set_chip_and_handler_name(irq, irq_chip,
3226a8e96aSMax Filippov handle_percpu_irq, "ipi");
3326a8e96aSMax Filippov irq_set_status_flags(irq, IRQ_LEVEL);
3426a8e96aSMax Filippov return 0;
3526a8e96aSMax Filippov }
3650091212SMarc Zyngier irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(irq)));
3726a8e96aSMax Filippov return xtensa_irq_map(d, irq, hw);
3826a8e96aSMax Filippov }
3926a8e96aSMax Filippov
4026a8e96aSMax Filippov /*
4126a8e96aSMax Filippov * Device Tree IRQ specifier translation function which works with one or
4226a8e96aSMax Filippov * two cell bindings. First cell value maps directly to the hwirq number.
4326a8e96aSMax Filippov * Second cell if present specifies whether hwirq number is external (1) or
4426a8e96aSMax Filippov * internal (0).
4526a8e96aSMax Filippov */
xtensa_mx_irq_domain_xlate(struct irq_domain * d,struct device_node * ctrlr,const u32 * intspec,unsigned int intsize,unsigned long * out_hwirq,unsigned int * out_type)4626a8e96aSMax Filippov static int xtensa_mx_irq_domain_xlate(struct irq_domain *d,
4726a8e96aSMax Filippov struct device_node *ctrlr,
4826a8e96aSMax Filippov const u32 *intspec, unsigned int intsize,
4926a8e96aSMax Filippov unsigned long *out_hwirq, unsigned int *out_type)
5026a8e96aSMax Filippov {
5126a8e96aSMax Filippov return xtensa_irq_domain_xlate(intspec, intsize,
5226a8e96aSMax Filippov intspec[0], intspec[0] + HW_IRQ_EXTERN_BASE,
5326a8e96aSMax Filippov out_hwirq, out_type);
5426a8e96aSMax Filippov }
5526a8e96aSMax Filippov
5626a8e96aSMax Filippov static const struct irq_domain_ops xtensa_mx_irq_domain_ops = {
5726a8e96aSMax Filippov .xlate = xtensa_mx_irq_domain_xlate,
5826a8e96aSMax Filippov .map = xtensa_mx_irq_map,
5926a8e96aSMax Filippov };
6026a8e96aSMax Filippov
secondary_init_irq(void)6126a8e96aSMax Filippov void secondary_init_irq(void)
6226a8e96aSMax Filippov {
6326a8e96aSMax Filippov __this_cpu_write(cached_irq_mask,
6426a8e96aSMax Filippov XCHAL_INTTYPE_MASK_EXTERN_EDGE |
6526a8e96aSMax Filippov XCHAL_INTTYPE_MASK_EXTERN_LEVEL);
66cad6fadeSMax Filippov xtensa_set_sr(XCHAL_INTTYPE_MASK_EXTERN_EDGE |
6726a8e96aSMax Filippov XCHAL_INTTYPE_MASK_EXTERN_LEVEL, intenable);
6826a8e96aSMax Filippov }
6926a8e96aSMax Filippov
xtensa_mx_irq_mask(struct irq_data * d)7026a8e96aSMax Filippov static void xtensa_mx_irq_mask(struct irq_data *d)
7126a8e96aSMax Filippov {
7226a8e96aSMax Filippov unsigned int mask = 1u << d->hwirq;
7326a8e96aSMax Filippov
7426a8e96aSMax Filippov if (mask & (XCHAL_INTTYPE_MASK_EXTERN_EDGE |
7526a8e96aSMax Filippov XCHAL_INTTYPE_MASK_EXTERN_LEVEL)) {
76eb271710SMax Filippov unsigned int ext_irq = xtensa_get_ext_irq_no(d->hwirq);
77eb271710SMax Filippov
78eb271710SMax Filippov if (ext_irq >= HW_IRQ_MX_BASE) {
79eb271710SMax Filippov set_er(1u << (ext_irq - HW_IRQ_MX_BASE), MIENG);
80eb271710SMax Filippov return;
81eb271710SMax Filippov }
82eb271710SMax Filippov }
8326a8e96aSMax Filippov mask = __this_cpu_read(cached_irq_mask) & ~mask;
8426a8e96aSMax Filippov __this_cpu_write(cached_irq_mask, mask);
85cad6fadeSMax Filippov xtensa_set_sr(mask, intenable);
8626a8e96aSMax Filippov }
8726a8e96aSMax Filippov
xtensa_mx_irq_unmask(struct irq_data * d)8826a8e96aSMax Filippov static void xtensa_mx_irq_unmask(struct irq_data *d)
8926a8e96aSMax Filippov {
9026a8e96aSMax Filippov unsigned int mask = 1u << d->hwirq;
9126a8e96aSMax Filippov
9226a8e96aSMax Filippov if (mask & (XCHAL_INTTYPE_MASK_EXTERN_EDGE |
9326a8e96aSMax Filippov XCHAL_INTTYPE_MASK_EXTERN_LEVEL)) {
94eb271710SMax Filippov unsigned int ext_irq = xtensa_get_ext_irq_no(d->hwirq);
95eb271710SMax Filippov
96eb271710SMax Filippov if (ext_irq >= HW_IRQ_MX_BASE) {
97eb271710SMax Filippov set_er(1u << (ext_irq - HW_IRQ_MX_BASE), MIENGSET);
98eb271710SMax Filippov return;
99eb271710SMax Filippov }
100eb271710SMax Filippov }
10126a8e96aSMax Filippov mask |= __this_cpu_read(cached_irq_mask);
10226a8e96aSMax Filippov __this_cpu_write(cached_irq_mask, mask);
103cad6fadeSMax Filippov xtensa_set_sr(mask, intenable);
10426a8e96aSMax Filippov }
10526a8e96aSMax Filippov
xtensa_mx_irq_enable(struct irq_data * d)10626a8e96aSMax Filippov static void xtensa_mx_irq_enable(struct irq_data *d)
10726a8e96aSMax Filippov {
10826a8e96aSMax Filippov xtensa_mx_irq_unmask(d);
10926a8e96aSMax Filippov }
11026a8e96aSMax Filippov
xtensa_mx_irq_disable(struct irq_data * d)11126a8e96aSMax Filippov static void xtensa_mx_irq_disable(struct irq_data *d)
11226a8e96aSMax Filippov {
11326a8e96aSMax Filippov xtensa_mx_irq_mask(d);
11426a8e96aSMax Filippov }
11526a8e96aSMax Filippov
xtensa_mx_irq_ack(struct irq_data * d)11626a8e96aSMax Filippov static void xtensa_mx_irq_ack(struct irq_data *d)
11726a8e96aSMax Filippov {
118cad6fadeSMax Filippov xtensa_set_sr(1 << d->hwirq, intclear);
11926a8e96aSMax Filippov }
12026a8e96aSMax Filippov
xtensa_mx_irq_retrigger(struct irq_data * d)12126a8e96aSMax Filippov static int xtensa_mx_irq_retrigger(struct irq_data *d)
12226a8e96aSMax Filippov {
123bb665236SMax Filippov unsigned int mask = 1u << d->hwirq;
124bb665236SMax Filippov
125bb665236SMax Filippov if (WARN_ON(mask & ~XCHAL_INTTYPE_MASK_SOFTWARE))
126bb665236SMax Filippov return 0;
127bb665236SMax Filippov xtensa_set_sr(mask, intset);
12826a8e96aSMax Filippov return 1;
12926a8e96aSMax Filippov }
13026a8e96aSMax Filippov
xtensa_mx_irq_set_affinity(struct irq_data * d,const struct cpumask * dest,bool force)13126a8e96aSMax Filippov static int xtensa_mx_irq_set_affinity(struct irq_data *d,
13226a8e96aSMax Filippov const struct cpumask *dest, bool force)
13326a8e96aSMax Filippov {
13450091212SMarc Zyngier int cpu = cpumask_any_and(dest, cpu_online_mask);
13550091212SMarc Zyngier unsigned mask = 1u << cpu;
13626a8e96aSMax Filippov
13726a8e96aSMax Filippov set_er(mask, MIROUT(d->hwirq - HW_IRQ_MX_BASE));
13850091212SMarc Zyngier irq_data_update_effective_affinity(d, cpumask_of(cpu));
13950091212SMarc Zyngier
14026a8e96aSMax Filippov return 0;
14126a8e96aSMax Filippov
14226a8e96aSMax Filippov }
14326a8e96aSMax Filippov
14426a8e96aSMax Filippov static struct irq_chip xtensa_mx_irq_chip = {
14526a8e96aSMax Filippov .name = "xtensa-mx",
14626a8e96aSMax Filippov .irq_enable = xtensa_mx_irq_enable,
14726a8e96aSMax Filippov .irq_disable = xtensa_mx_irq_disable,
14826a8e96aSMax Filippov .irq_mask = xtensa_mx_irq_mask,
14926a8e96aSMax Filippov .irq_unmask = xtensa_mx_irq_unmask,
15026a8e96aSMax Filippov .irq_ack = xtensa_mx_irq_ack,
15126a8e96aSMax Filippov .irq_retrigger = xtensa_mx_irq_retrigger,
15226a8e96aSMax Filippov .irq_set_affinity = xtensa_mx_irq_set_affinity,
15326a8e96aSMax Filippov };
15426a8e96aSMax Filippov
xtensa_mx_init_common(struct irq_domain * root_domain)155168f633bSMax Filippov static void __init xtensa_mx_init_common(struct irq_domain *root_domain)
156168f633bSMax Filippov {
157168f633bSMax Filippov unsigned int i;
158168f633bSMax Filippov
159168f633bSMax Filippov irq_set_default_host(root_domain);
160168f633bSMax Filippov secondary_init_irq();
161168f633bSMax Filippov
162168f633bSMax Filippov /* Initialize default IRQ routing to CPU 0 */
163168f633bSMax Filippov for (i = 0; i < XCHAL_NUM_EXTINTERRUPTS; ++i)
164168f633bSMax Filippov set_er(1, MIROUT(i));
165168f633bSMax Filippov }
166168f633bSMax Filippov
xtensa_mx_init_legacy(struct device_node * interrupt_parent)16726a8e96aSMax Filippov int __init xtensa_mx_init_legacy(struct device_node *interrupt_parent)
16826a8e96aSMax Filippov {
16926a8e96aSMax Filippov struct irq_domain *root_domain =
170e5c86679SMax Filippov irq_domain_add_legacy(NULL, NR_IRQS - 1, 1, 0,
17126a8e96aSMax Filippov &xtensa_mx_irq_domain_ops,
17226a8e96aSMax Filippov &xtensa_mx_irq_chip);
173168f633bSMax Filippov xtensa_mx_init_common(root_domain);
17426a8e96aSMax Filippov return 0;
17526a8e96aSMax Filippov }
17626a8e96aSMax Filippov
xtensa_mx_init(struct device_node * np,struct device_node * interrupt_parent)17726a8e96aSMax Filippov static int __init xtensa_mx_init(struct device_node *np,
17826a8e96aSMax Filippov struct device_node *interrupt_parent)
17926a8e96aSMax Filippov {
18026a8e96aSMax Filippov struct irq_domain *root_domain =
18126a8e96aSMax Filippov irq_domain_add_linear(np, NR_IRQS, &xtensa_mx_irq_domain_ops,
18226a8e96aSMax Filippov &xtensa_mx_irq_chip);
183168f633bSMax Filippov xtensa_mx_init_common(root_domain);
18426a8e96aSMax Filippov return 0;
18526a8e96aSMax Filippov }
18626a8e96aSMax Filippov IRQCHIP_DECLARE(xtensa_mx_irq_chip, "cdns,xtensa-mx", xtensa_mx_init);
187