1 /* 2 * Copyright (C) 2007-2013 Michal Simek <monstr@monstr.eu> 3 * Copyright (C) 2012-2013 Xilinx, Inc. 4 * Copyright (C) 2007-2009 PetaLogix 5 * Copyright (C) 2006 Atmark Techno, Inc. 6 * 7 * This file is subject to the terms and conditions of the GNU General Public 8 * License. See the file "COPYING" in the main directory of this archive 9 * for more details. 10 */ 11 12 #include <linux/irqdomain.h> 13 #include <linux/irq.h> 14 #include <linux/irqchip.h> 15 #include <linux/irqchip/chained_irq.h> 16 #include <linux/of_address.h> 17 #include <linux/io.h> 18 #include <linux/jump_label.h> 19 #include <linux/bug.h> 20 #include <linux/of_irq.h> 21 22 /* No one else should require these constants, so define them locally here. */ 23 #define ISR 0x00 /* Interrupt Status Register */ 24 #define IPR 0x04 /* Interrupt Pending Register */ 25 #define IER 0x08 /* Interrupt Enable Register */ 26 #define IAR 0x0c /* Interrupt Acknowledge Register */ 27 #define SIE 0x10 /* Set Interrupt Enable bits */ 28 #define CIE 0x14 /* Clear Interrupt Enable bits */ 29 #define IVR 0x18 /* Interrupt Vector Register */ 30 #define MER 0x1c /* Master Enable Register */ 31 32 #define MER_ME (1<<0) 33 #define MER_HIE (1<<1) 34 35 static DEFINE_STATIC_KEY_FALSE(xintc_is_be); 36 37 struct xintc_irq_chip { 38 void __iomem *base; 39 struct irq_domain *root_domain; 40 u32 intr_mask; 41 u32 nr_irq; 42 }; 43 44 static struct xintc_irq_chip *primary_intc; 45 46 static void xintc_write(struct xintc_irq_chip *irqc, int reg, u32 data) 47 { 48 if (static_branch_unlikely(&xintc_is_be)) 49 iowrite32be(data, irqc->base + reg); 50 else 51 iowrite32(data, irqc->base + reg); 52 } 53 54 static u32 xintc_read(struct xintc_irq_chip *irqc, int reg) 55 { 56 if (static_branch_unlikely(&xintc_is_be)) 57 return ioread32be(irqc->base + reg); 58 else 59 return ioread32(irqc->base + reg); 60 } 61 62 static void intc_enable_or_unmask(struct irq_data *d) 63 { 64 struct xintc_irq_chip *irqc = irq_data_get_irq_chip_data(d); 65 unsigned long mask = BIT(d->hwirq); 66 67 pr_debug("irq-xilinx: enable_or_unmask: %ld\n", d->hwirq); 68 69 /* ack level irqs because they can't be acked during 70 * ack function since the handle_level_irq function 71 * acks the irq before calling the interrupt handler 72 */ 73 if (irqd_is_level_type(d)) 74 xintc_write(irqc, IAR, mask); 75 76 xintc_write(irqc, SIE, mask); 77 } 78 79 static void intc_disable_or_mask(struct irq_data *d) 80 { 81 struct xintc_irq_chip *irqc = irq_data_get_irq_chip_data(d); 82 83 pr_debug("irq-xilinx: disable: %ld\n", d->hwirq); 84 xintc_write(irqc, CIE, BIT(d->hwirq)); 85 } 86 87 static void intc_ack(struct irq_data *d) 88 { 89 struct xintc_irq_chip *irqc = irq_data_get_irq_chip_data(d); 90 91 pr_debug("irq-xilinx: ack: %ld\n", d->hwirq); 92 xintc_write(irqc, IAR, BIT(d->hwirq)); 93 } 94 95 static void intc_mask_ack(struct irq_data *d) 96 { 97 struct xintc_irq_chip *irqc = irq_data_get_irq_chip_data(d); 98 unsigned long mask = BIT(d->hwirq); 99 100 pr_debug("irq-xilinx: disable_and_ack: %ld\n", d->hwirq); 101 xintc_write(irqc, CIE, mask); 102 xintc_write(irqc, IAR, mask); 103 } 104 105 static struct irq_chip intc_dev = { 106 .name = "Xilinx INTC", 107 .irq_unmask = intc_enable_or_unmask, 108 .irq_mask = intc_disable_or_mask, 109 .irq_ack = intc_ack, 110 .irq_mask_ack = intc_mask_ack, 111 }; 112 113 static unsigned int xintc_get_irq_local(struct xintc_irq_chip *irqc) 114 { 115 unsigned int irq = 0; 116 u32 hwirq; 117 118 hwirq = xintc_read(irqc, IVR); 119 if (hwirq != -1U) 120 irq = irq_find_mapping(irqc->root_domain, hwirq); 121 122 pr_debug("irq-xilinx: hwirq=%d, irq=%d\n", hwirq, irq); 123 124 return irq; 125 } 126 127 static int xintc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw) 128 { 129 struct xintc_irq_chip *irqc = d->host_data; 130 131 if (irqc->intr_mask & BIT(hw)) { 132 irq_set_chip_and_handler_name(irq, &intc_dev, 133 handle_edge_irq, "edge"); 134 irq_clear_status_flags(irq, IRQ_LEVEL); 135 } else { 136 irq_set_chip_and_handler_name(irq, &intc_dev, 137 handle_level_irq, "level"); 138 irq_set_status_flags(irq, IRQ_LEVEL); 139 } 140 irq_set_chip_data(irq, irqc); 141 return 0; 142 } 143 144 static const struct irq_domain_ops xintc_irq_domain_ops = { 145 .xlate = irq_domain_xlate_onetwocell, 146 .map = xintc_map, 147 }; 148 149 static void xil_intc_irq_handler(struct irq_desc *desc) 150 { 151 struct irq_chip *chip = irq_desc_get_chip(desc); 152 struct xintc_irq_chip *irqc; 153 u32 pending; 154 155 irqc = irq_data_get_irq_handler_data(&desc->irq_data); 156 chained_irq_enter(chip, desc); 157 do { 158 pending = xintc_get_irq_local(irqc); 159 if (pending == 0) 160 break; 161 generic_handle_irq(pending); 162 } while (true); 163 chained_irq_exit(chip, desc); 164 } 165 166 static void xil_intc_handle_irq(struct pt_regs *regs) 167 { 168 u32 hwirq; 169 struct xintc_irq_chip *irqc = primary_intc; 170 171 do { 172 hwirq = xintc_read(irqc, IVR); 173 if (likely(hwirq != -1U)) { 174 int ret; 175 176 ret = handle_domain_irq(irqc->root_domain, hwirq, regs); 177 WARN_ONCE(ret, "Unhandled HWIRQ %d\n", hwirq); 178 continue; 179 } 180 181 break; 182 } while (1); 183 } 184 185 static int __init xilinx_intc_of_init(struct device_node *intc, 186 struct device_node *parent) 187 { 188 struct xintc_irq_chip *irqc; 189 int ret, irq; 190 191 irqc = kzalloc(sizeof(*irqc), GFP_KERNEL); 192 if (!irqc) 193 return -ENOMEM; 194 irqc->base = of_iomap(intc, 0); 195 BUG_ON(!irqc->base); 196 197 ret = of_property_read_u32(intc, "xlnx,num-intr-inputs", &irqc->nr_irq); 198 if (ret < 0) { 199 pr_err("irq-xilinx: unable to read xlnx,num-intr-inputs\n"); 200 goto error; 201 } 202 203 ret = of_property_read_u32(intc, "xlnx,kind-of-intr", &irqc->intr_mask); 204 if (ret < 0) { 205 pr_warn("irq-xilinx: unable to read xlnx,kind-of-intr\n"); 206 irqc->intr_mask = 0; 207 } 208 209 if (irqc->intr_mask >> irqc->nr_irq) 210 pr_warn("irq-xilinx: mismatch in kind-of-intr param\n"); 211 212 pr_info("irq-xilinx: %pOF: num_irq=%d, edge=0x%x\n", 213 intc, irqc->nr_irq, irqc->intr_mask); 214 215 216 /* 217 * Disable all external interrupts until they are 218 * explicity requested. 219 */ 220 xintc_write(irqc, IER, 0); 221 222 /* Acknowledge any pending interrupts just in case. */ 223 xintc_write(irqc, IAR, 0xffffffff); 224 225 /* Turn on the Master Enable. */ 226 xintc_write(irqc, MER, MER_HIE | MER_ME); 227 if (xintc_read(irqc, MER) != (MER_HIE | MER_ME)) { 228 static_branch_enable(&xintc_is_be); 229 xintc_write(irqc, MER, MER_HIE | MER_ME); 230 } 231 232 irqc->root_domain = irq_domain_add_linear(intc, irqc->nr_irq, 233 &xintc_irq_domain_ops, irqc); 234 if (!irqc->root_domain) { 235 pr_err("irq-xilinx: Unable to create IRQ domain\n"); 236 ret = -EINVAL; 237 goto error; 238 } 239 240 if (parent) { 241 irq = irq_of_parse_and_map(intc, 0); 242 if (irq) { 243 irq_set_chained_handler_and_data(irq, 244 xil_intc_irq_handler, 245 irqc); 246 } else { 247 pr_err("irq-xilinx: interrupts property not in DT\n"); 248 ret = -EINVAL; 249 goto error; 250 } 251 } else { 252 primary_intc = irqc; 253 set_handle_irq(xil_intc_handle_irq); 254 } 255 256 return 0; 257 258 error: 259 iounmap(irqc->base); 260 kfree(irqc); 261 return ret; 262 263 } 264 265 IRQCHIP_DECLARE(xilinx_intc_xps, "xlnx,xps-intc-1.00.a", xilinx_intc_of_init); 266 IRQCHIP_DECLARE(xilinx_intc_opb, "xlnx,opb-intc-1.00.c", xilinx_intc_of_init); 267