xref: /openbmc/linux/drivers/irqchip/irq-vic.c (revision 4f3db074)
1 /*
2  *  linux/arch/arm/common/vic.c
3  *
4  *  Copyright (C) 1999 - 2003 ARM Limited
5  *  Copyright (C) 2000 Deep Blue Solutions Ltd
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License as published by
9  * the Free Software Foundation; either version 2 of the License, or
10  * (at your option) any later version.
11  *
12  * This program is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15  * GNU General Public License for more details.
16  *
17  * You should have received a copy of the GNU General Public License
18  * along with this program; if not, write to the Free Software
19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
20  */
21 
22 #include <linux/export.h>
23 #include <linux/init.h>
24 #include <linux/list.h>
25 #include <linux/io.h>
26 #include <linux/irq.h>
27 #include <linux/irqchip/chained_irq.h>
28 #include <linux/irqdomain.h>
29 #include <linux/of.h>
30 #include <linux/of_address.h>
31 #include <linux/of_irq.h>
32 #include <linux/syscore_ops.h>
33 #include <linux/device.h>
34 #include <linux/amba/bus.h>
35 #include <linux/irqchip/arm-vic.h>
36 
37 #include <asm/exception.h>
38 #include <asm/irq.h>
39 
40 #include "irqchip.h"
41 
42 #define VIC_IRQ_STATUS			0x00
43 #define VIC_FIQ_STATUS			0x04
44 #define VIC_INT_SELECT			0x0c	/* 1 = FIQ, 0 = IRQ */
45 #define VIC_INT_SOFT			0x18
46 #define VIC_INT_SOFT_CLEAR		0x1c
47 #define VIC_PROTECT			0x20
48 #define VIC_PL190_VECT_ADDR		0x30	/* PL190 only */
49 #define VIC_PL190_DEF_VECT_ADDR		0x34	/* PL190 only */
50 
51 #define VIC_VECT_ADDR0			0x100	/* 0 to 15 (0..31 PL192) */
52 #define VIC_VECT_CNTL0			0x200	/* 0 to 15 (0..31 PL192) */
53 #define VIC_ITCR			0x300	/* VIC test control register */
54 
55 #define VIC_VECT_CNTL_ENABLE		(1 << 5)
56 
57 #define VIC_PL192_VECT_ADDR		0xF00
58 
59 /**
60  * struct vic_device - VIC PM device
61  * @parent_irq: The parent IRQ number of the VIC if cascaded, or 0.
62  * @irq: The IRQ number for the base of the VIC.
63  * @base: The register base for the VIC.
64  * @valid_sources: A bitmask of valid interrupts
65  * @resume_sources: A bitmask of interrupts for resume.
66  * @resume_irqs: The IRQs enabled for resume.
67  * @int_select: Save for VIC_INT_SELECT.
68  * @int_enable: Save for VIC_INT_ENABLE.
69  * @soft_int: Save for VIC_INT_SOFT.
70  * @protect: Save for VIC_PROTECT.
71  * @domain: The IRQ domain for the VIC.
72  */
73 struct vic_device {
74 	void __iomem	*base;
75 	int		irq;
76 	u32		valid_sources;
77 	u32		resume_sources;
78 	u32		resume_irqs;
79 	u32		int_select;
80 	u32		int_enable;
81 	u32		soft_int;
82 	u32		protect;
83 	struct irq_domain *domain;
84 };
85 
86 /* we cannot allocate memory when VICs are initially registered */
87 static struct vic_device vic_devices[CONFIG_ARM_VIC_NR];
88 
89 static int vic_id;
90 
91 static void vic_handle_irq(struct pt_regs *regs);
92 
93 /**
94  * vic_init2 - common initialisation code
95  * @base: Base of the VIC.
96  *
97  * Common initialisation code for registration
98  * and resume.
99 */
100 static void vic_init2(void __iomem *base)
101 {
102 	int i;
103 
104 	for (i = 0; i < 16; i++) {
105 		void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4);
106 		writel(VIC_VECT_CNTL_ENABLE | i, reg);
107 	}
108 
109 	writel(32, base + VIC_PL190_DEF_VECT_ADDR);
110 }
111 
112 #ifdef CONFIG_PM
113 static void resume_one_vic(struct vic_device *vic)
114 {
115 	void __iomem *base = vic->base;
116 
117 	printk(KERN_DEBUG "%s: resuming vic at %p\n", __func__, base);
118 
119 	/* re-initialise static settings */
120 	vic_init2(base);
121 
122 	writel(vic->int_select, base + VIC_INT_SELECT);
123 	writel(vic->protect, base + VIC_PROTECT);
124 
125 	/* set the enabled ints and then clear the non-enabled */
126 	writel(vic->int_enable, base + VIC_INT_ENABLE);
127 	writel(~vic->int_enable, base + VIC_INT_ENABLE_CLEAR);
128 
129 	/* and the same for the soft-int register */
130 
131 	writel(vic->soft_int, base + VIC_INT_SOFT);
132 	writel(~vic->soft_int, base + VIC_INT_SOFT_CLEAR);
133 }
134 
135 static void vic_resume(void)
136 {
137 	int id;
138 
139 	for (id = vic_id - 1; id >= 0; id--)
140 		resume_one_vic(vic_devices + id);
141 }
142 
143 static void suspend_one_vic(struct vic_device *vic)
144 {
145 	void __iomem *base = vic->base;
146 
147 	printk(KERN_DEBUG "%s: suspending vic at %p\n", __func__, base);
148 
149 	vic->int_select = readl(base + VIC_INT_SELECT);
150 	vic->int_enable = readl(base + VIC_INT_ENABLE);
151 	vic->soft_int = readl(base + VIC_INT_SOFT);
152 	vic->protect = readl(base + VIC_PROTECT);
153 
154 	/* set the interrupts (if any) that are used for
155 	 * resuming the system */
156 
157 	writel(vic->resume_irqs, base + VIC_INT_ENABLE);
158 	writel(~vic->resume_irqs, base + VIC_INT_ENABLE_CLEAR);
159 }
160 
161 static int vic_suspend(void)
162 {
163 	int id;
164 
165 	for (id = 0; id < vic_id; id++)
166 		suspend_one_vic(vic_devices + id);
167 
168 	return 0;
169 }
170 
171 struct syscore_ops vic_syscore_ops = {
172 	.suspend	= vic_suspend,
173 	.resume		= vic_resume,
174 };
175 
176 /**
177  * vic_pm_init - initicall to register VIC pm
178  *
179  * This is called via late_initcall() to register
180  * the resources for the VICs due to the early
181  * nature of the VIC's registration.
182 */
183 static int __init vic_pm_init(void)
184 {
185 	if (vic_id > 0)
186 		register_syscore_ops(&vic_syscore_ops);
187 
188 	return 0;
189 }
190 late_initcall(vic_pm_init);
191 #endif /* CONFIG_PM */
192 
193 static struct irq_chip vic_chip;
194 
195 static int vic_irqdomain_map(struct irq_domain *d, unsigned int irq,
196 			     irq_hw_number_t hwirq)
197 {
198 	struct vic_device *v = d->host_data;
199 
200 	/* Skip invalid IRQs, only register handlers for the real ones */
201 	if (!(v->valid_sources & (1 << hwirq)))
202 		return -EPERM;
203 	irq_set_chip_and_handler(irq, &vic_chip, handle_level_irq);
204 	irq_set_chip_data(irq, v->base);
205 	set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
206 	return 0;
207 }
208 
209 /*
210  * Handle each interrupt in a single VIC.  Returns non-zero if we've
211  * handled at least one interrupt.  This reads the status register
212  * before handling each interrupt, which is necessary given that
213  * handle_IRQ may briefly re-enable interrupts for soft IRQ handling.
214  */
215 static int handle_one_vic(struct vic_device *vic, struct pt_regs *regs)
216 {
217 	u32 stat, irq;
218 	int handled = 0;
219 
220 	while ((stat = readl_relaxed(vic->base + VIC_IRQ_STATUS))) {
221 		irq = ffs(stat) - 1;
222 		handle_domain_irq(vic->domain, irq, regs);
223 		handled = 1;
224 	}
225 
226 	return handled;
227 }
228 
229 static void vic_handle_irq_cascaded(unsigned int irq, struct irq_desc *desc)
230 {
231 	u32 stat, hwirq;
232 	struct irq_chip *host_chip = irq_desc_get_chip(desc);
233 	struct vic_device *vic = irq_desc_get_handler_data(desc);
234 
235 	chained_irq_enter(host_chip, desc);
236 
237 	while ((stat = readl_relaxed(vic->base + VIC_IRQ_STATUS))) {
238 		hwirq = ffs(stat) - 1;
239 		generic_handle_irq(irq_find_mapping(vic->domain, hwirq));
240 	}
241 
242 	chained_irq_exit(host_chip, desc);
243 }
244 
245 /*
246  * Keep iterating over all registered VIC's until there are no pending
247  * interrupts.
248  */
249 static void __exception_irq_entry vic_handle_irq(struct pt_regs *regs)
250 {
251 	int i, handled;
252 
253 	do {
254 		for (i = 0, handled = 0; i < vic_id; ++i)
255 			handled |= handle_one_vic(&vic_devices[i], regs);
256 	} while (handled);
257 }
258 
259 static struct irq_domain_ops vic_irqdomain_ops = {
260 	.map = vic_irqdomain_map,
261 	.xlate = irq_domain_xlate_onetwocell,
262 };
263 
264 /**
265  * vic_register() - Register a VIC.
266  * @base: The base address of the VIC.
267  * @parent_irq: The parent IRQ if cascaded, else 0.
268  * @irq: The base IRQ for the VIC.
269  * @valid_sources: bitmask of valid interrupts
270  * @resume_sources: bitmask of interrupts allowed for resume sources.
271  * @node: The device tree node associated with the VIC.
272  *
273  * Register the VIC with the system device tree so that it can be notified
274  * of suspend and resume requests and ensure that the correct actions are
275  * taken to re-instate the settings on resume.
276  *
277  * This also configures the IRQ domain for the VIC.
278  */
279 static void __init vic_register(void __iomem *base, unsigned int parent_irq,
280 				unsigned int irq,
281 				u32 valid_sources, u32 resume_sources,
282 				struct device_node *node)
283 {
284 	struct vic_device *v;
285 	int i;
286 
287 	if (vic_id >= ARRAY_SIZE(vic_devices)) {
288 		printk(KERN_ERR "%s: too few VICs, increase CONFIG_ARM_VIC_NR\n", __func__);
289 		return;
290 	}
291 
292 	v = &vic_devices[vic_id];
293 	v->base = base;
294 	v->valid_sources = valid_sources;
295 	v->resume_sources = resume_sources;
296 	set_handle_irq(vic_handle_irq);
297 	vic_id++;
298 
299 	if (parent_irq) {
300 		irq_set_handler_data(parent_irq, v);
301 		irq_set_chained_handler(parent_irq, vic_handle_irq_cascaded);
302 	}
303 
304 	v->domain = irq_domain_add_simple(node, fls(valid_sources), irq,
305 					  &vic_irqdomain_ops, v);
306 	/* create an IRQ mapping for each valid IRQ */
307 	for (i = 0; i < fls(valid_sources); i++)
308 		if (valid_sources & (1 << i))
309 			irq_create_mapping(v->domain, i);
310 	/* If no base IRQ was passed, figure out our allocated base */
311 	if (irq)
312 		v->irq = irq;
313 	else
314 		v->irq = irq_find_mapping(v->domain, 0);
315 }
316 
317 static void vic_ack_irq(struct irq_data *d)
318 {
319 	void __iomem *base = irq_data_get_irq_chip_data(d);
320 	unsigned int irq = d->hwirq;
321 	writel(1 << irq, base + VIC_INT_ENABLE_CLEAR);
322 	/* moreover, clear the soft-triggered, in case it was the reason */
323 	writel(1 << irq, base + VIC_INT_SOFT_CLEAR);
324 }
325 
326 static void vic_mask_irq(struct irq_data *d)
327 {
328 	void __iomem *base = irq_data_get_irq_chip_data(d);
329 	unsigned int irq = d->hwirq;
330 	writel(1 << irq, base + VIC_INT_ENABLE_CLEAR);
331 }
332 
333 static void vic_unmask_irq(struct irq_data *d)
334 {
335 	void __iomem *base = irq_data_get_irq_chip_data(d);
336 	unsigned int irq = d->hwirq;
337 	writel(1 << irq, base + VIC_INT_ENABLE);
338 }
339 
340 #if defined(CONFIG_PM)
341 static struct vic_device *vic_from_irq(unsigned int irq)
342 {
343         struct vic_device *v = vic_devices;
344 	unsigned int base_irq = irq & ~31;
345 	int id;
346 
347 	for (id = 0; id < vic_id; id++, v++) {
348 		if (v->irq == base_irq)
349 			return v;
350 	}
351 
352 	return NULL;
353 }
354 
355 static int vic_set_wake(struct irq_data *d, unsigned int on)
356 {
357 	struct vic_device *v = vic_from_irq(d->irq);
358 	unsigned int off = d->hwirq;
359 	u32 bit = 1 << off;
360 
361 	if (!v)
362 		return -EINVAL;
363 
364 	if (!(bit & v->resume_sources))
365 		return -EINVAL;
366 
367 	if (on)
368 		v->resume_irqs |= bit;
369 	else
370 		v->resume_irqs &= ~bit;
371 
372 	return 0;
373 }
374 #else
375 #define vic_set_wake NULL
376 #endif /* CONFIG_PM */
377 
378 static struct irq_chip vic_chip = {
379 	.name		= "VIC",
380 	.irq_ack	= vic_ack_irq,
381 	.irq_mask	= vic_mask_irq,
382 	.irq_unmask	= vic_unmask_irq,
383 	.irq_set_wake	= vic_set_wake,
384 };
385 
386 static void __init vic_disable(void __iomem *base)
387 {
388 	writel(0, base + VIC_INT_SELECT);
389 	writel(0, base + VIC_INT_ENABLE);
390 	writel(~0, base + VIC_INT_ENABLE_CLEAR);
391 	writel(0, base + VIC_ITCR);
392 	writel(~0, base + VIC_INT_SOFT_CLEAR);
393 }
394 
395 static void __init vic_clear_interrupts(void __iomem *base)
396 {
397 	unsigned int i;
398 
399 	writel(0, base + VIC_PL190_VECT_ADDR);
400 	for (i = 0; i < 19; i++) {
401 		unsigned int value;
402 
403 		value = readl(base + VIC_PL190_VECT_ADDR);
404 		writel(value, base + VIC_PL190_VECT_ADDR);
405 	}
406 }
407 
408 /*
409  * The PL190 cell from ARM has been modified by ST to handle 64 interrupts.
410  * The original cell has 32 interrupts, while the modified one has 64,
411  * replocating two blocks 0x00..0x1f in 0x20..0x3f. In that case
412  * the probe function is called twice, with base set to offset 000
413  *  and 020 within the page. We call this "second block".
414  */
415 static void __init vic_init_st(void __iomem *base, unsigned int irq_start,
416 			       u32 vic_sources, struct device_node *node)
417 {
418 	unsigned int i;
419 	int vic_2nd_block = ((unsigned long)base & ~PAGE_MASK) != 0;
420 
421 	/* Disable all interrupts initially. */
422 	vic_disable(base);
423 
424 	/*
425 	 * Make sure we clear all existing interrupts. The vector registers
426 	 * in this cell are after the second block of general registers,
427 	 * so we can address them using standard offsets, but only from
428 	 * the second base address, which is 0x20 in the page
429 	 */
430 	if (vic_2nd_block) {
431 		vic_clear_interrupts(base);
432 
433 		/* ST has 16 vectors as well, but we don't enable them by now */
434 		for (i = 0; i < 16; i++) {
435 			void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4);
436 			writel(0, reg);
437 		}
438 
439 		writel(32, base + VIC_PL190_DEF_VECT_ADDR);
440 	}
441 
442 	vic_register(base, 0, irq_start, vic_sources, 0, node);
443 }
444 
445 void __init __vic_init(void __iomem *base, int parent_irq, int irq_start,
446 			      u32 vic_sources, u32 resume_sources,
447 			      struct device_node *node)
448 {
449 	unsigned int i;
450 	u32 cellid = 0;
451 	enum amba_vendor vendor;
452 
453 	/* Identify which VIC cell this one is, by reading the ID */
454 	for (i = 0; i < 4; i++) {
455 		void __iomem *addr;
456 		addr = (void __iomem *)((u32)base & PAGE_MASK) + 0xfe0 + (i * 4);
457 		cellid |= (readl(addr) & 0xff) << (8 * i);
458 	}
459 	vendor = (cellid >> 12) & 0xff;
460 	printk(KERN_INFO "VIC @%p: id 0x%08x, vendor 0x%02x\n",
461 	       base, cellid, vendor);
462 
463 	switch(vendor) {
464 	case AMBA_VENDOR_ST:
465 		vic_init_st(base, irq_start, vic_sources, node);
466 		return;
467 	default:
468 		printk(KERN_WARNING "VIC: unknown vendor, continuing anyways\n");
469 		/* fall through */
470 	case AMBA_VENDOR_ARM:
471 		break;
472 	}
473 
474 	/* Disable all interrupts initially. */
475 	vic_disable(base);
476 
477 	/* Make sure we clear all existing interrupts */
478 	vic_clear_interrupts(base);
479 
480 	vic_init2(base);
481 
482 	vic_register(base, parent_irq, irq_start, vic_sources, resume_sources, node);
483 }
484 
485 /**
486  * vic_init() - initialise a vectored interrupt controller
487  * @base: iomem base address
488  * @irq_start: starting interrupt number, must be muliple of 32
489  * @vic_sources: bitmask of interrupt sources to allow
490  * @resume_sources: bitmask of interrupt sources to allow for resume
491  */
492 void __init vic_init(void __iomem *base, unsigned int irq_start,
493 		     u32 vic_sources, u32 resume_sources)
494 {
495 	__vic_init(base, 0, irq_start, vic_sources, resume_sources, NULL);
496 }
497 
498 /**
499  * vic_init_cascaded() - initialise a cascaded vectored interrupt controller
500  * @base: iomem base address
501  * @parent_irq: the parent IRQ we're cascaded off
502  * @irq_start: starting interrupt number, must be muliple of 32
503  * @vic_sources: bitmask of interrupt sources to allow
504  * @resume_sources: bitmask of interrupt sources to allow for resume
505  *
506  * This returns the base for the new interrupts or negative on error.
507  */
508 int __init vic_init_cascaded(void __iomem *base, unsigned int parent_irq,
509 			      u32 vic_sources, u32 resume_sources)
510 {
511 	struct vic_device *v;
512 
513 	v = &vic_devices[vic_id];
514 	__vic_init(base, parent_irq, 0, vic_sources, resume_sources, NULL);
515 	/* Return out acquired base */
516 	return v->irq;
517 }
518 EXPORT_SYMBOL_GPL(vic_init_cascaded);
519 
520 #ifdef CONFIG_OF
521 int __init vic_of_init(struct device_node *node, struct device_node *parent)
522 {
523 	void __iomem *regs;
524 	u32 interrupt_mask = ~0;
525 	u32 wakeup_mask = ~0;
526 
527 	if (WARN(parent, "non-root VICs are not supported"))
528 		return -EINVAL;
529 
530 	regs = of_iomap(node, 0);
531 	if (WARN_ON(!regs))
532 		return -EIO;
533 
534 	of_property_read_u32(node, "valid-mask", &interrupt_mask);
535 	of_property_read_u32(node, "valid-wakeup-mask", &wakeup_mask);
536 
537 	/*
538 	 * Passing 0 as first IRQ makes the simple domain allocate descriptors
539 	 */
540 	__vic_init(regs, 0, 0, interrupt_mask, wakeup_mask, node);
541 
542 	return 0;
543 }
544 IRQCHIP_DECLARE(arm_pl190_vic, "arm,pl190-vic", vic_of_init);
545 IRQCHIP_DECLARE(arm_pl192_vic, "arm,pl192-vic", vic_of_init);
546 IRQCHIP_DECLARE(arm_versatile_vic, "arm,versatile-vic", vic_of_init);
547 #endif /* CONFIG OF */
548