1 /* 2 * linux/arch/arm/common/vic.c 3 * 4 * Copyright (C) 1999 - 2003 ARM Limited 5 * Copyright (C) 2000 Deep Blue Solutions Ltd 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 20 */ 21 22 #include <linux/export.h> 23 #include <linux/init.h> 24 #include <linux/list.h> 25 #include <linux/io.h> 26 #include <linux/irq.h> 27 #include <linux/irqdomain.h> 28 #include <linux/of.h> 29 #include <linux/of_address.h> 30 #include <linux/of_irq.h> 31 #include <linux/syscore_ops.h> 32 #include <linux/device.h> 33 #include <linux/amba/bus.h> 34 #include <linux/irqchip/arm-vic.h> 35 36 #include <asm/exception.h> 37 #include <asm/irq.h> 38 39 #include "irqchip.h" 40 41 #define VIC_IRQ_STATUS 0x00 42 #define VIC_FIQ_STATUS 0x04 43 #define VIC_INT_SELECT 0x0c /* 1 = FIQ, 0 = IRQ */ 44 #define VIC_INT_SOFT 0x18 45 #define VIC_INT_SOFT_CLEAR 0x1c 46 #define VIC_PROTECT 0x20 47 #define VIC_PL190_VECT_ADDR 0x30 /* PL190 only */ 48 #define VIC_PL190_DEF_VECT_ADDR 0x34 /* PL190 only */ 49 50 #define VIC_VECT_ADDR0 0x100 /* 0 to 15 (0..31 PL192) */ 51 #define VIC_VECT_CNTL0 0x200 /* 0 to 15 (0..31 PL192) */ 52 #define VIC_ITCR 0x300 /* VIC test control register */ 53 54 #define VIC_VECT_CNTL_ENABLE (1 << 5) 55 56 #define VIC_PL192_VECT_ADDR 0xF00 57 58 /** 59 * struct vic_device - VIC PM device 60 * @parent_irq: The parent IRQ number of the VIC if cascaded, or 0. 61 * @irq: The IRQ number for the base of the VIC. 62 * @base: The register base for the VIC. 63 * @valid_sources: A bitmask of valid interrupts 64 * @resume_sources: A bitmask of interrupts for resume. 65 * @resume_irqs: The IRQs enabled for resume. 66 * @int_select: Save for VIC_INT_SELECT. 67 * @int_enable: Save for VIC_INT_ENABLE. 68 * @soft_int: Save for VIC_INT_SOFT. 69 * @protect: Save for VIC_PROTECT. 70 * @domain: The IRQ domain for the VIC. 71 */ 72 struct vic_device { 73 void __iomem *base; 74 int irq; 75 u32 valid_sources; 76 u32 resume_sources; 77 u32 resume_irqs; 78 u32 int_select; 79 u32 int_enable; 80 u32 soft_int; 81 u32 protect; 82 struct irq_domain *domain; 83 }; 84 85 /* we cannot allocate memory when VICs are initially registered */ 86 static struct vic_device vic_devices[CONFIG_ARM_VIC_NR]; 87 88 static int vic_id; 89 90 static void vic_handle_irq(struct pt_regs *regs); 91 92 /** 93 * vic_init2 - common initialisation code 94 * @base: Base of the VIC. 95 * 96 * Common initialisation code for registration 97 * and resume. 98 */ 99 static void vic_init2(void __iomem *base) 100 { 101 int i; 102 103 for (i = 0; i < 16; i++) { 104 void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4); 105 writel(VIC_VECT_CNTL_ENABLE | i, reg); 106 } 107 108 writel(32, base + VIC_PL190_DEF_VECT_ADDR); 109 } 110 111 #ifdef CONFIG_PM 112 static void resume_one_vic(struct vic_device *vic) 113 { 114 void __iomem *base = vic->base; 115 116 printk(KERN_DEBUG "%s: resuming vic at %p\n", __func__, base); 117 118 /* re-initialise static settings */ 119 vic_init2(base); 120 121 writel(vic->int_select, base + VIC_INT_SELECT); 122 writel(vic->protect, base + VIC_PROTECT); 123 124 /* set the enabled ints and then clear the non-enabled */ 125 writel(vic->int_enable, base + VIC_INT_ENABLE); 126 writel(~vic->int_enable, base + VIC_INT_ENABLE_CLEAR); 127 128 /* and the same for the soft-int register */ 129 130 writel(vic->soft_int, base + VIC_INT_SOFT); 131 writel(~vic->soft_int, base + VIC_INT_SOFT_CLEAR); 132 } 133 134 static void vic_resume(void) 135 { 136 int id; 137 138 for (id = vic_id - 1; id >= 0; id--) 139 resume_one_vic(vic_devices + id); 140 } 141 142 static void suspend_one_vic(struct vic_device *vic) 143 { 144 void __iomem *base = vic->base; 145 146 printk(KERN_DEBUG "%s: suspending vic at %p\n", __func__, base); 147 148 vic->int_select = readl(base + VIC_INT_SELECT); 149 vic->int_enable = readl(base + VIC_INT_ENABLE); 150 vic->soft_int = readl(base + VIC_INT_SOFT); 151 vic->protect = readl(base + VIC_PROTECT); 152 153 /* set the interrupts (if any) that are used for 154 * resuming the system */ 155 156 writel(vic->resume_irqs, base + VIC_INT_ENABLE); 157 writel(~vic->resume_irqs, base + VIC_INT_ENABLE_CLEAR); 158 } 159 160 static int vic_suspend(void) 161 { 162 int id; 163 164 for (id = 0; id < vic_id; id++) 165 suspend_one_vic(vic_devices + id); 166 167 return 0; 168 } 169 170 struct syscore_ops vic_syscore_ops = { 171 .suspend = vic_suspend, 172 .resume = vic_resume, 173 }; 174 175 /** 176 * vic_pm_init - initicall to register VIC pm 177 * 178 * This is called via late_initcall() to register 179 * the resources for the VICs due to the early 180 * nature of the VIC's registration. 181 */ 182 static int __init vic_pm_init(void) 183 { 184 if (vic_id > 0) 185 register_syscore_ops(&vic_syscore_ops); 186 187 return 0; 188 } 189 late_initcall(vic_pm_init); 190 #endif /* CONFIG_PM */ 191 192 static struct irq_chip vic_chip; 193 194 static int vic_irqdomain_map(struct irq_domain *d, unsigned int irq, 195 irq_hw_number_t hwirq) 196 { 197 struct vic_device *v = d->host_data; 198 199 /* Skip invalid IRQs, only register handlers for the real ones */ 200 if (!(v->valid_sources & (1 << hwirq))) 201 return -EPERM; 202 irq_set_chip_and_handler(irq, &vic_chip, handle_level_irq); 203 irq_set_chip_data(irq, v->base); 204 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 205 return 0; 206 } 207 208 /* 209 * Handle each interrupt in a single VIC. Returns non-zero if we've 210 * handled at least one interrupt. This reads the status register 211 * before handling each interrupt, which is necessary given that 212 * handle_IRQ may briefly re-enable interrupts for soft IRQ handling. 213 */ 214 static int handle_one_vic(struct vic_device *vic, struct pt_regs *regs) 215 { 216 u32 stat, irq; 217 int handled = 0; 218 219 while ((stat = readl_relaxed(vic->base + VIC_IRQ_STATUS))) { 220 irq = ffs(stat) - 1; 221 handle_IRQ(irq_find_mapping(vic->domain, irq), regs); 222 handled = 1; 223 } 224 225 return handled; 226 } 227 228 static void vic_handle_irq_cascaded(unsigned int irq, struct irq_desc *desc) 229 { 230 u32 stat, hwirq; 231 struct vic_device *vic = irq_desc_get_handler_data(desc); 232 233 while ((stat = readl_relaxed(vic->base + VIC_IRQ_STATUS))) { 234 hwirq = ffs(stat) - 1; 235 generic_handle_irq(irq_find_mapping(vic->domain, hwirq)); 236 } 237 } 238 239 /* 240 * Keep iterating over all registered VIC's until there are no pending 241 * interrupts. 242 */ 243 static void __exception_irq_entry vic_handle_irq(struct pt_regs *regs) 244 { 245 int i, handled; 246 247 do { 248 for (i = 0, handled = 0; i < vic_id; ++i) 249 handled |= handle_one_vic(&vic_devices[i], regs); 250 } while (handled); 251 } 252 253 static struct irq_domain_ops vic_irqdomain_ops = { 254 .map = vic_irqdomain_map, 255 .xlate = irq_domain_xlate_onetwocell, 256 }; 257 258 /** 259 * vic_register() - Register a VIC. 260 * @base: The base address of the VIC. 261 * @parent_irq: The parent IRQ if cascaded, else 0. 262 * @irq: The base IRQ for the VIC. 263 * @valid_sources: bitmask of valid interrupts 264 * @resume_sources: bitmask of interrupts allowed for resume sources. 265 * @node: The device tree node associated with the VIC. 266 * 267 * Register the VIC with the system device tree so that it can be notified 268 * of suspend and resume requests and ensure that the correct actions are 269 * taken to re-instate the settings on resume. 270 * 271 * This also configures the IRQ domain for the VIC. 272 */ 273 static void __init vic_register(void __iomem *base, unsigned int parent_irq, 274 unsigned int irq, 275 u32 valid_sources, u32 resume_sources, 276 struct device_node *node) 277 { 278 struct vic_device *v; 279 int i; 280 281 if (vic_id >= ARRAY_SIZE(vic_devices)) { 282 printk(KERN_ERR "%s: too few VICs, increase CONFIG_ARM_VIC_NR\n", __func__); 283 return; 284 } 285 286 v = &vic_devices[vic_id]; 287 v->base = base; 288 v->valid_sources = valid_sources; 289 v->resume_sources = resume_sources; 290 set_handle_irq(vic_handle_irq); 291 vic_id++; 292 293 if (parent_irq) { 294 irq_set_handler_data(parent_irq, v); 295 irq_set_chained_handler(parent_irq, vic_handle_irq_cascaded); 296 } 297 298 v->domain = irq_domain_add_simple(node, fls(valid_sources), irq, 299 &vic_irqdomain_ops, v); 300 /* create an IRQ mapping for each valid IRQ */ 301 for (i = 0; i < fls(valid_sources); i++) 302 if (valid_sources & (1 << i)) 303 irq_create_mapping(v->domain, i); 304 /* If no base IRQ was passed, figure out our allocated base */ 305 if (irq) 306 v->irq = irq; 307 else 308 v->irq = irq_find_mapping(v->domain, 0); 309 } 310 311 static void vic_ack_irq(struct irq_data *d) 312 { 313 void __iomem *base = irq_data_get_irq_chip_data(d); 314 unsigned int irq = d->hwirq; 315 writel(1 << irq, base + VIC_INT_ENABLE_CLEAR); 316 /* moreover, clear the soft-triggered, in case it was the reason */ 317 writel(1 << irq, base + VIC_INT_SOFT_CLEAR); 318 } 319 320 static void vic_mask_irq(struct irq_data *d) 321 { 322 void __iomem *base = irq_data_get_irq_chip_data(d); 323 unsigned int irq = d->hwirq; 324 writel(1 << irq, base + VIC_INT_ENABLE_CLEAR); 325 } 326 327 static void vic_unmask_irq(struct irq_data *d) 328 { 329 void __iomem *base = irq_data_get_irq_chip_data(d); 330 unsigned int irq = d->hwirq; 331 writel(1 << irq, base + VIC_INT_ENABLE); 332 } 333 334 #if defined(CONFIG_PM) 335 static struct vic_device *vic_from_irq(unsigned int irq) 336 { 337 struct vic_device *v = vic_devices; 338 unsigned int base_irq = irq & ~31; 339 int id; 340 341 for (id = 0; id < vic_id; id++, v++) { 342 if (v->irq == base_irq) 343 return v; 344 } 345 346 return NULL; 347 } 348 349 static int vic_set_wake(struct irq_data *d, unsigned int on) 350 { 351 struct vic_device *v = vic_from_irq(d->irq); 352 unsigned int off = d->hwirq; 353 u32 bit = 1 << off; 354 355 if (!v) 356 return -EINVAL; 357 358 if (!(bit & v->resume_sources)) 359 return -EINVAL; 360 361 if (on) 362 v->resume_irqs |= bit; 363 else 364 v->resume_irqs &= ~bit; 365 366 return 0; 367 } 368 #else 369 #define vic_set_wake NULL 370 #endif /* CONFIG_PM */ 371 372 static struct irq_chip vic_chip = { 373 .name = "VIC", 374 .irq_ack = vic_ack_irq, 375 .irq_mask = vic_mask_irq, 376 .irq_unmask = vic_unmask_irq, 377 .irq_set_wake = vic_set_wake, 378 }; 379 380 static void __init vic_disable(void __iomem *base) 381 { 382 writel(0, base + VIC_INT_SELECT); 383 writel(0, base + VIC_INT_ENABLE); 384 writel(~0, base + VIC_INT_ENABLE_CLEAR); 385 writel(0, base + VIC_ITCR); 386 writel(~0, base + VIC_INT_SOFT_CLEAR); 387 } 388 389 static void __init vic_clear_interrupts(void __iomem *base) 390 { 391 unsigned int i; 392 393 writel(0, base + VIC_PL190_VECT_ADDR); 394 for (i = 0; i < 19; i++) { 395 unsigned int value; 396 397 value = readl(base + VIC_PL190_VECT_ADDR); 398 writel(value, base + VIC_PL190_VECT_ADDR); 399 } 400 } 401 402 /* 403 * The PL190 cell from ARM has been modified by ST to handle 64 interrupts. 404 * The original cell has 32 interrupts, while the modified one has 64, 405 * replocating two blocks 0x00..0x1f in 0x20..0x3f. In that case 406 * the probe function is called twice, with base set to offset 000 407 * and 020 within the page. We call this "second block". 408 */ 409 static void __init vic_init_st(void __iomem *base, unsigned int irq_start, 410 u32 vic_sources, struct device_node *node) 411 { 412 unsigned int i; 413 int vic_2nd_block = ((unsigned long)base & ~PAGE_MASK) != 0; 414 415 /* Disable all interrupts initially. */ 416 vic_disable(base); 417 418 /* 419 * Make sure we clear all existing interrupts. The vector registers 420 * in this cell are after the second block of general registers, 421 * so we can address them using standard offsets, but only from 422 * the second base address, which is 0x20 in the page 423 */ 424 if (vic_2nd_block) { 425 vic_clear_interrupts(base); 426 427 /* ST has 16 vectors as well, but we don't enable them by now */ 428 for (i = 0; i < 16; i++) { 429 void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4); 430 writel(0, reg); 431 } 432 433 writel(32, base + VIC_PL190_DEF_VECT_ADDR); 434 } 435 436 vic_register(base, 0, irq_start, vic_sources, 0, node); 437 } 438 439 void __init __vic_init(void __iomem *base, int parent_irq, int irq_start, 440 u32 vic_sources, u32 resume_sources, 441 struct device_node *node) 442 { 443 unsigned int i; 444 u32 cellid = 0; 445 enum amba_vendor vendor; 446 447 /* Identify which VIC cell this one is, by reading the ID */ 448 for (i = 0; i < 4; i++) { 449 void __iomem *addr; 450 addr = (void __iomem *)((u32)base & PAGE_MASK) + 0xfe0 + (i * 4); 451 cellid |= (readl(addr) & 0xff) << (8 * i); 452 } 453 vendor = (cellid >> 12) & 0xff; 454 printk(KERN_INFO "VIC @%p: id 0x%08x, vendor 0x%02x\n", 455 base, cellid, vendor); 456 457 switch(vendor) { 458 case AMBA_VENDOR_ST: 459 vic_init_st(base, irq_start, vic_sources, node); 460 return; 461 default: 462 printk(KERN_WARNING "VIC: unknown vendor, continuing anyways\n"); 463 /* fall through */ 464 case AMBA_VENDOR_ARM: 465 break; 466 } 467 468 /* Disable all interrupts initially. */ 469 vic_disable(base); 470 471 /* Make sure we clear all existing interrupts */ 472 vic_clear_interrupts(base); 473 474 vic_init2(base); 475 476 vic_register(base, parent_irq, irq_start, vic_sources, resume_sources, node); 477 } 478 479 /** 480 * vic_init() - initialise a vectored interrupt controller 481 * @base: iomem base address 482 * @irq_start: starting interrupt number, must be muliple of 32 483 * @vic_sources: bitmask of interrupt sources to allow 484 * @resume_sources: bitmask of interrupt sources to allow for resume 485 */ 486 void __init vic_init(void __iomem *base, unsigned int irq_start, 487 u32 vic_sources, u32 resume_sources) 488 { 489 __vic_init(base, 0, irq_start, vic_sources, resume_sources, NULL); 490 } 491 492 /** 493 * vic_init_cascaded() - initialise a cascaded vectored interrupt controller 494 * @base: iomem base address 495 * @parent_irq: the parent IRQ we're cascaded off 496 * @irq_start: starting interrupt number, must be muliple of 32 497 * @vic_sources: bitmask of interrupt sources to allow 498 * @resume_sources: bitmask of interrupt sources to allow for resume 499 * 500 * This returns the base for the new interrupts or negative on error. 501 */ 502 int __init vic_init_cascaded(void __iomem *base, unsigned int parent_irq, 503 u32 vic_sources, u32 resume_sources) 504 { 505 struct vic_device *v; 506 507 v = &vic_devices[vic_id]; 508 __vic_init(base, parent_irq, 0, vic_sources, resume_sources, NULL); 509 /* Return out acquired base */ 510 return v->irq; 511 } 512 EXPORT_SYMBOL_GPL(vic_init_cascaded); 513 514 #ifdef CONFIG_OF 515 int __init vic_of_init(struct device_node *node, struct device_node *parent) 516 { 517 void __iomem *regs; 518 u32 interrupt_mask = ~0; 519 u32 wakeup_mask = ~0; 520 521 if (WARN(parent, "non-root VICs are not supported")) 522 return -EINVAL; 523 524 regs = of_iomap(node, 0); 525 if (WARN_ON(!regs)) 526 return -EIO; 527 528 of_property_read_u32(node, "valid-mask", &interrupt_mask); 529 of_property_read_u32(node, "valid-wakeup-mask", &wakeup_mask); 530 531 /* 532 * Passing 0 as first IRQ makes the simple domain allocate descriptors 533 */ 534 __vic_init(regs, 0, 0, interrupt_mask, wakeup_mask, node); 535 536 return 0; 537 } 538 IRQCHIP_DECLARE(arm_pl190_vic, "arm,pl190-vic", vic_of_init); 539 IRQCHIP_DECLARE(arm_pl192_vic, "arm,pl192-vic", vic_of_init); 540 IRQCHIP_DECLARE(arm_versatile_vic, "arm,versatile-vic", vic_of_init); 541 #endif /* CONFIG OF */ 542