11a59d1b8SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later
244430ec0SRob Herring /*
344430ec0SRob Herring * linux/arch/arm/common/vic.c
444430ec0SRob Herring *
544430ec0SRob Herring * Copyright (C) 1999 - 2003 ARM Limited
644430ec0SRob Herring * Copyright (C) 2000 Deep Blue Solutions Ltd
744430ec0SRob Herring */
844430ec0SRob Herring
944430ec0SRob Herring #include <linux/export.h>
1044430ec0SRob Herring #include <linux/init.h>
1144430ec0SRob Herring #include <linux/list.h>
1244430ec0SRob Herring #include <linux/io.h>
13bc895b59SOlof Johansson #include <linux/irq.h>
1441a83e06SJoel Porquet #include <linux/irqchip.h>
15f6da9fe4SLinus Walleij #include <linux/irqchip/chained_irq.h>
1644430ec0SRob Herring #include <linux/irqdomain.h>
1744430ec0SRob Herring #include <linux/of.h>
1844430ec0SRob Herring #include <linux/of_address.h>
1944430ec0SRob Herring #include <linux/of_irq.h>
2044430ec0SRob Herring #include <linux/syscore_ops.h>
2144430ec0SRob Herring #include <linux/device.h>
2244430ec0SRob Herring #include <linux/amba/bus.h>
239e47b8bfSRob Herring #include <linux/irqchip/arm-vic.h>
2444430ec0SRob Herring
2544430ec0SRob Herring #include <asm/exception.h>
26f36a3bb1SCatalin Marinas #include <asm/irq.h>
2744430ec0SRob Herring
2844430ec0SRob Herring #define VIC_IRQ_STATUS 0x00
2944430ec0SRob Herring #define VIC_FIQ_STATUS 0x04
30b0b92ab6SLinus Walleij #define VIC_RAW_STATUS 0x08
3144430ec0SRob Herring #define VIC_INT_SELECT 0x0c /* 1 = FIQ, 0 = IRQ */
32b0b92ab6SLinus Walleij #define VIC_INT_ENABLE 0x10 /* 1 = enable, 0 = disable */
33b0b92ab6SLinus Walleij #define VIC_INT_ENABLE_CLEAR 0x14
3444430ec0SRob Herring #define VIC_INT_SOFT 0x18
3544430ec0SRob Herring #define VIC_INT_SOFT_CLEAR 0x1c
3644430ec0SRob Herring #define VIC_PROTECT 0x20
3744430ec0SRob Herring #define VIC_PL190_VECT_ADDR 0x30 /* PL190 only */
3844430ec0SRob Herring #define VIC_PL190_DEF_VECT_ADDR 0x34 /* PL190 only */
3944430ec0SRob Herring
4044430ec0SRob Herring #define VIC_VECT_ADDR0 0x100 /* 0 to 15 (0..31 PL192) */
4144430ec0SRob Herring #define VIC_VECT_CNTL0 0x200 /* 0 to 15 (0..31 PL192) */
4244430ec0SRob Herring #define VIC_ITCR 0x300 /* VIC test control register */
4344430ec0SRob Herring
4444430ec0SRob Herring #define VIC_VECT_CNTL_ENABLE (1 << 5)
4544430ec0SRob Herring
4644430ec0SRob Herring #define VIC_PL192_VECT_ADDR 0xF00
4744430ec0SRob Herring
4844430ec0SRob Herring /**
4944430ec0SRob Herring * struct vic_device - VIC PM device
50e641b987SLinus Walleij * @parent_irq: The parent IRQ number of the VIC if cascaded, or 0.
5144430ec0SRob Herring * @irq: The IRQ number for the base of the VIC.
5244430ec0SRob Herring * @base: The register base for the VIC.
5344430ec0SRob Herring * @valid_sources: A bitmask of valid interrupts
5444430ec0SRob Herring * @resume_sources: A bitmask of interrupts for resume.
5544430ec0SRob Herring * @resume_irqs: The IRQs enabled for resume.
5644430ec0SRob Herring * @int_select: Save for VIC_INT_SELECT.
5744430ec0SRob Herring * @int_enable: Save for VIC_INT_ENABLE.
5844430ec0SRob Herring * @soft_int: Save for VIC_INT_SOFT.
5944430ec0SRob Herring * @protect: Save for VIC_PROTECT.
6044430ec0SRob Herring * @domain: The IRQ domain for the VIC.
6144430ec0SRob Herring */
6244430ec0SRob Herring struct vic_device {
6344430ec0SRob Herring void __iomem *base;
6444430ec0SRob Herring int irq;
6544430ec0SRob Herring u32 valid_sources;
6644430ec0SRob Herring u32 resume_sources;
6744430ec0SRob Herring u32 resume_irqs;
6844430ec0SRob Herring u32 int_select;
6944430ec0SRob Herring u32 int_enable;
7044430ec0SRob Herring u32 soft_int;
7144430ec0SRob Herring u32 protect;
7244430ec0SRob Herring struct irq_domain *domain;
7344430ec0SRob Herring };
7444430ec0SRob Herring
7544430ec0SRob Herring /* we cannot allocate memory when VICs are initially registered */
7644430ec0SRob Herring static struct vic_device vic_devices[CONFIG_ARM_VIC_NR];
7744430ec0SRob Herring
7844430ec0SRob Herring static int vic_id;
7944430ec0SRob Herring
8044430ec0SRob Herring static void vic_handle_irq(struct pt_regs *regs);
8144430ec0SRob Herring
8244430ec0SRob Herring /**
8344430ec0SRob Herring * vic_init2 - common initialisation code
8444430ec0SRob Herring * @base: Base of the VIC.
8544430ec0SRob Herring *
8644430ec0SRob Herring * Common initialisation code for registration
8744430ec0SRob Herring * and resume.
8844430ec0SRob Herring */
vic_init2(void __iomem * base)8944430ec0SRob Herring static void vic_init2(void __iomem *base)
9044430ec0SRob Herring {
9144430ec0SRob Herring int i;
9244430ec0SRob Herring
9344430ec0SRob Herring for (i = 0; i < 16; i++) {
9444430ec0SRob Herring void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4);
9544430ec0SRob Herring writel(VIC_VECT_CNTL_ENABLE | i, reg);
9644430ec0SRob Herring }
9744430ec0SRob Herring
9844430ec0SRob Herring writel(32, base + VIC_PL190_DEF_VECT_ADDR);
9944430ec0SRob Herring }
10044430ec0SRob Herring
10144430ec0SRob Herring #ifdef CONFIG_PM
resume_one_vic(struct vic_device * vic)10244430ec0SRob Herring static void resume_one_vic(struct vic_device *vic)
10344430ec0SRob Herring {
10444430ec0SRob Herring void __iomem *base = vic->base;
10544430ec0SRob Herring
10644430ec0SRob Herring printk(KERN_DEBUG "%s: resuming vic at %p\n", __func__, base);
10744430ec0SRob Herring
10844430ec0SRob Herring /* re-initialise static settings */
10944430ec0SRob Herring vic_init2(base);
11044430ec0SRob Herring
11144430ec0SRob Herring writel(vic->int_select, base + VIC_INT_SELECT);
11244430ec0SRob Herring writel(vic->protect, base + VIC_PROTECT);
11344430ec0SRob Herring
11444430ec0SRob Herring /* set the enabled ints and then clear the non-enabled */
11544430ec0SRob Herring writel(vic->int_enable, base + VIC_INT_ENABLE);
11644430ec0SRob Herring writel(~vic->int_enable, base + VIC_INT_ENABLE_CLEAR);
11744430ec0SRob Herring
11844430ec0SRob Herring /* and the same for the soft-int register */
11944430ec0SRob Herring
12044430ec0SRob Herring writel(vic->soft_int, base + VIC_INT_SOFT);
12144430ec0SRob Herring writel(~vic->soft_int, base + VIC_INT_SOFT_CLEAR);
12244430ec0SRob Herring }
12344430ec0SRob Herring
vic_resume(void)12444430ec0SRob Herring static void vic_resume(void)
12544430ec0SRob Herring {
12644430ec0SRob Herring int id;
12744430ec0SRob Herring
12844430ec0SRob Herring for (id = vic_id - 1; id >= 0; id--)
12944430ec0SRob Herring resume_one_vic(vic_devices + id);
13044430ec0SRob Herring }
13144430ec0SRob Herring
suspend_one_vic(struct vic_device * vic)13244430ec0SRob Herring static void suspend_one_vic(struct vic_device *vic)
13344430ec0SRob Herring {
13444430ec0SRob Herring void __iomem *base = vic->base;
13544430ec0SRob Herring
13644430ec0SRob Herring printk(KERN_DEBUG "%s: suspending vic at %p\n", __func__, base);
13744430ec0SRob Herring
13844430ec0SRob Herring vic->int_select = readl(base + VIC_INT_SELECT);
13944430ec0SRob Herring vic->int_enable = readl(base + VIC_INT_ENABLE);
14044430ec0SRob Herring vic->soft_int = readl(base + VIC_INT_SOFT);
14144430ec0SRob Herring vic->protect = readl(base + VIC_PROTECT);
14244430ec0SRob Herring
14344430ec0SRob Herring /* set the interrupts (if any) that are used for
14444430ec0SRob Herring * resuming the system */
14544430ec0SRob Herring
14644430ec0SRob Herring writel(vic->resume_irqs, base + VIC_INT_ENABLE);
14744430ec0SRob Herring writel(~vic->resume_irqs, base + VIC_INT_ENABLE_CLEAR);
14844430ec0SRob Herring }
14944430ec0SRob Herring
vic_suspend(void)15044430ec0SRob Herring static int vic_suspend(void)
15144430ec0SRob Herring {
15244430ec0SRob Herring int id;
15344430ec0SRob Herring
15444430ec0SRob Herring for (id = 0; id < vic_id; id++)
15544430ec0SRob Herring suspend_one_vic(vic_devices + id);
15644430ec0SRob Herring
15744430ec0SRob Herring return 0;
15844430ec0SRob Herring }
15944430ec0SRob Herring
160df042a5fSBen Dooks static struct syscore_ops vic_syscore_ops = {
16144430ec0SRob Herring .suspend = vic_suspend,
16244430ec0SRob Herring .resume = vic_resume,
16344430ec0SRob Herring };
16444430ec0SRob Herring
16544430ec0SRob Herring /**
166a359f757SIngo Molnar * vic_pm_init - initcall to register VIC pm
16744430ec0SRob Herring *
16844430ec0SRob Herring * This is called via late_initcall() to register
16944430ec0SRob Herring * the resources for the VICs due to the early
17044430ec0SRob Herring * nature of the VIC's registration.
17144430ec0SRob Herring */
vic_pm_init(void)17244430ec0SRob Herring static int __init vic_pm_init(void)
17344430ec0SRob Herring {
17444430ec0SRob Herring if (vic_id > 0)
17544430ec0SRob Herring register_syscore_ops(&vic_syscore_ops);
17644430ec0SRob Herring
17744430ec0SRob Herring return 0;
17844430ec0SRob Herring }
17944430ec0SRob Herring late_initcall(vic_pm_init);
18044430ec0SRob Herring #endif /* CONFIG_PM */
18144430ec0SRob Herring
18244430ec0SRob Herring static struct irq_chip vic_chip;
18344430ec0SRob Herring
vic_irqdomain_map(struct irq_domain * d,unsigned int irq,irq_hw_number_t hwirq)18444430ec0SRob Herring static int vic_irqdomain_map(struct irq_domain *d, unsigned int irq,
18544430ec0SRob Herring irq_hw_number_t hwirq)
18644430ec0SRob Herring {
18744430ec0SRob Herring struct vic_device *v = d->host_data;
18844430ec0SRob Herring
18944430ec0SRob Herring /* Skip invalid IRQs, only register handlers for the real ones */
19044430ec0SRob Herring if (!(v->valid_sources & (1 << hwirq)))
191d94ea3f6SGrant Likely return -EPERM;
19244430ec0SRob Herring irq_set_chip_and_handler(irq, &vic_chip, handle_level_irq);
19344430ec0SRob Herring irq_set_chip_data(irq, v->base);
194d17cab44SRob Herring irq_set_probe(irq);
19544430ec0SRob Herring return 0;
19644430ec0SRob Herring }
19744430ec0SRob Herring
19844430ec0SRob Herring /*
19944430ec0SRob Herring * Handle each interrupt in a single VIC. Returns non-zero if we've
20044430ec0SRob Herring * handled at least one interrupt. This reads the status register
20144430ec0SRob Herring * before handling each interrupt, which is necessary given that
20244430ec0SRob Herring * handle_IRQ may briefly re-enable interrupts for soft IRQ handling.
20344430ec0SRob Herring */
handle_one_vic(struct vic_device * vic,struct pt_regs * regs)20444430ec0SRob Herring static int handle_one_vic(struct vic_device *vic, struct pt_regs *regs)
20544430ec0SRob Herring {
20644430ec0SRob Herring u32 stat, irq;
20744430ec0SRob Herring int handled = 0;
20844430ec0SRob Herring
20944430ec0SRob Herring while ((stat = readl_relaxed(vic->base + VIC_IRQ_STATUS))) {
21044430ec0SRob Herring irq = ffs(stat) - 1;
211*0953fb26SMark Rutland generic_handle_domain_irq(vic->domain, irq);
21244430ec0SRob Herring handled = 1;
21344430ec0SRob Herring }
21444430ec0SRob Herring
21544430ec0SRob Herring return handled;
21644430ec0SRob Herring }
21744430ec0SRob Herring
vic_handle_irq_cascaded(struct irq_desc * desc)218bd0b9ac4SThomas Gleixner static void vic_handle_irq_cascaded(struct irq_desc *desc)
219e641b987SLinus Walleij {
220e641b987SLinus Walleij u32 stat, hwirq;
221f6da9fe4SLinus Walleij struct irq_chip *host_chip = irq_desc_get_chip(desc);
222e641b987SLinus Walleij struct vic_device *vic = irq_desc_get_handler_data(desc);
223e641b987SLinus Walleij
224f6da9fe4SLinus Walleij chained_irq_enter(host_chip, desc);
225f6da9fe4SLinus Walleij
226e641b987SLinus Walleij while ((stat = readl_relaxed(vic->base + VIC_IRQ_STATUS))) {
227e641b987SLinus Walleij hwirq = ffs(stat) - 1;
228046a6ee2SMarc Zyngier generic_handle_domain_irq(vic->domain, hwirq);
229e641b987SLinus Walleij }
230f6da9fe4SLinus Walleij
231f6da9fe4SLinus Walleij chained_irq_exit(host_chip, desc);
232e641b987SLinus Walleij }
233e641b987SLinus Walleij
23444430ec0SRob Herring /*
23544430ec0SRob Herring * Keep iterating over all registered VIC's until there are no pending
23644430ec0SRob Herring * interrupts.
23744430ec0SRob Herring */
vic_handle_irq(struct pt_regs * regs)2388783dd3aSStephen Boyd static void __exception_irq_entry vic_handle_irq(struct pt_regs *regs)
23944430ec0SRob Herring {
24044430ec0SRob Herring int i, handled;
24144430ec0SRob Herring
24244430ec0SRob Herring do {
24344430ec0SRob Herring for (i = 0, handled = 0; i < vic_id; ++i)
24444430ec0SRob Herring handled |= handle_one_vic(&vic_devices[i], regs);
24544430ec0SRob Herring } while (handled);
24644430ec0SRob Herring }
24744430ec0SRob Herring
24896009736SKrzysztof Kozlowski static const struct irq_domain_ops vic_irqdomain_ops = {
24944430ec0SRob Herring .map = vic_irqdomain_map,
25044430ec0SRob Herring .xlate = irq_domain_xlate_onetwocell,
25144430ec0SRob Herring };
25244430ec0SRob Herring
25344430ec0SRob Herring /**
25444430ec0SRob Herring * vic_register() - Register a VIC.
25544430ec0SRob Herring * @base: The base address of the VIC.
256e641b987SLinus Walleij * @parent_irq: The parent IRQ if cascaded, else 0.
25744430ec0SRob Herring * @irq: The base IRQ for the VIC.
25844430ec0SRob Herring * @valid_sources: bitmask of valid interrupts
25944430ec0SRob Herring * @resume_sources: bitmask of interrupts allowed for resume sources.
26044430ec0SRob Herring * @node: The device tree node associated with the VIC.
26144430ec0SRob Herring *
26244430ec0SRob Herring * Register the VIC with the system device tree so that it can be notified
26344430ec0SRob Herring * of suspend and resume requests and ensure that the correct actions are
26444430ec0SRob Herring * taken to re-instate the settings on resume.
26544430ec0SRob Herring *
26644430ec0SRob Herring * This also configures the IRQ domain for the VIC.
26744430ec0SRob Herring */
vic_register(void __iomem * base,unsigned int parent_irq,unsigned int irq,u32 valid_sources,u32 resume_sources,struct device_node * node)268e641b987SLinus Walleij static void __init vic_register(void __iomem *base, unsigned int parent_irq,
269e641b987SLinus Walleij unsigned int irq,
27044430ec0SRob Herring u32 valid_sources, u32 resume_sources,
27144430ec0SRob Herring struct device_node *node)
27244430ec0SRob Herring {
27344430ec0SRob Herring struct vic_device *v;
27444430ec0SRob Herring int i;
27544430ec0SRob Herring
27644430ec0SRob Herring if (vic_id >= ARRAY_SIZE(vic_devices)) {
27744430ec0SRob Herring printk(KERN_ERR "%s: too few VICs, increase CONFIG_ARM_VIC_NR\n", __func__);
27844430ec0SRob Herring return;
27944430ec0SRob Herring }
28044430ec0SRob Herring
28144430ec0SRob Herring v = &vic_devices[vic_id];
28244430ec0SRob Herring v->base = base;
28344430ec0SRob Herring v->valid_sources = valid_sources;
28444430ec0SRob Herring v->resume_sources = resume_sources;
28544430ec0SRob Herring set_handle_irq(vic_handle_irq);
28644430ec0SRob Herring vic_id++;
287e641b987SLinus Walleij
288e641b987SLinus Walleij if (parent_irq) {
2899f213541SThomas Gleixner irq_set_chained_handler_and_data(parent_irq,
2909f213541SThomas Gleixner vic_handle_irq_cascaded, v);
291e641b987SLinus Walleij }
292e641b987SLinus Walleij
29344430ec0SRob Herring v->domain = irq_domain_add_simple(node, fls(valid_sources), irq,
29444430ec0SRob Herring &vic_irqdomain_ops, v);
29544430ec0SRob Herring /* create an IRQ mapping for each valid IRQ */
29644430ec0SRob Herring for (i = 0; i < fls(valid_sources); i++)
29744430ec0SRob Herring if (valid_sources & (1 << i))
29844430ec0SRob Herring irq_create_mapping(v->domain, i);
2993b4df9dbSLinus Walleij /* If no base IRQ was passed, figure out our allocated base */
3003b4df9dbSLinus Walleij if (irq)
3013b4df9dbSLinus Walleij v->irq = irq;
3023b4df9dbSLinus Walleij else
3033b4df9dbSLinus Walleij v->irq = irq_find_mapping(v->domain, 0);
30444430ec0SRob Herring }
30544430ec0SRob Herring
vic_ack_irq(struct irq_data * d)30644430ec0SRob Herring static void vic_ack_irq(struct irq_data *d)
30744430ec0SRob Herring {
30844430ec0SRob Herring void __iomem *base = irq_data_get_irq_chip_data(d);
30944430ec0SRob Herring unsigned int irq = d->hwirq;
31044430ec0SRob Herring writel(1 << irq, base + VIC_INT_ENABLE_CLEAR);
31144430ec0SRob Herring /* moreover, clear the soft-triggered, in case it was the reason */
31244430ec0SRob Herring writel(1 << irq, base + VIC_INT_SOFT_CLEAR);
31344430ec0SRob Herring }
31444430ec0SRob Herring
vic_mask_irq(struct irq_data * d)31544430ec0SRob Herring static void vic_mask_irq(struct irq_data *d)
31644430ec0SRob Herring {
31744430ec0SRob Herring void __iomem *base = irq_data_get_irq_chip_data(d);
31844430ec0SRob Herring unsigned int irq = d->hwirq;
31944430ec0SRob Herring writel(1 << irq, base + VIC_INT_ENABLE_CLEAR);
32044430ec0SRob Herring }
32144430ec0SRob Herring
vic_unmask_irq(struct irq_data * d)32244430ec0SRob Herring static void vic_unmask_irq(struct irq_data *d)
32344430ec0SRob Herring {
32444430ec0SRob Herring void __iomem *base = irq_data_get_irq_chip_data(d);
32544430ec0SRob Herring unsigned int irq = d->hwirq;
32644430ec0SRob Herring writel(1 << irq, base + VIC_INT_ENABLE);
32744430ec0SRob Herring }
32844430ec0SRob Herring
32944430ec0SRob Herring #if defined(CONFIG_PM)
vic_from_irq(unsigned int irq)33044430ec0SRob Herring static struct vic_device *vic_from_irq(unsigned int irq)
33144430ec0SRob Herring {
33244430ec0SRob Herring struct vic_device *v = vic_devices;
33344430ec0SRob Herring unsigned int base_irq = irq & ~31;
33444430ec0SRob Herring int id;
33544430ec0SRob Herring
33644430ec0SRob Herring for (id = 0; id < vic_id; id++, v++) {
33744430ec0SRob Herring if (v->irq == base_irq)
33844430ec0SRob Herring return v;
33944430ec0SRob Herring }
34044430ec0SRob Herring
34144430ec0SRob Herring return NULL;
34244430ec0SRob Herring }
34344430ec0SRob Herring
vic_set_wake(struct irq_data * d,unsigned int on)34444430ec0SRob Herring static int vic_set_wake(struct irq_data *d, unsigned int on)
34544430ec0SRob Herring {
34644430ec0SRob Herring struct vic_device *v = vic_from_irq(d->irq);
34744430ec0SRob Herring unsigned int off = d->hwirq;
34844430ec0SRob Herring u32 bit = 1 << off;
34944430ec0SRob Herring
35044430ec0SRob Herring if (!v)
35144430ec0SRob Herring return -EINVAL;
35244430ec0SRob Herring
35344430ec0SRob Herring if (!(bit & v->resume_sources))
35444430ec0SRob Herring return -EINVAL;
35544430ec0SRob Herring
35644430ec0SRob Herring if (on)
35744430ec0SRob Herring v->resume_irqs |= bit;
35844430ec0SRob Herring else
35944430ec0SRob Herring v->resume_irqs &= ~bit;
36044430ec0SRob Herring
36144430ec0SRob Herring return 0;
36244430ec0SRob Herring }
36344430ec0SRob Herring #else
36444430ec0SRob Herring #define vic_set_wake NULL
36544430ec0SRob Herring #endif /* CONFIG_PM */
36644430ec0SRob Herring
36744430ec0SRob Herring static struct irq_chip vic_chip = {
36844430ec0SRob Herring .name = "VIC",
36944430ec0SRob Herring .irq_ack = vic_ack_irq,
37044430ec0SRob Herring .irq_mask = vic_mask_irq,
37144430ec0SRob Herring .irq_unmask = vic_unmask_irq,
37244430ec0SRob Herring .irq_set_wake = vic_set_wake,
37344430ec0SRob Herring };
37444430ec0SRob Herring
vic_disable(void __iomem * base)37544430ec0SRob Herring static void __init vic_disable(void __iomem *base)
37644430ec0SRob Herring {
37744430ec0SRob Herring writel(0, base + VIC_INT_SELECT);
37844430ec0SRob Herring writel(0, base + VIC_INT_ENABLE);
37944430ec0SRob Herring writel(~0, base + VIC_INT_ENABLE_CLEAR);
38044430ec0SRob Herring writel(0, base + VIC_ITCR);
38144430ec0SRob Herring writel(~0, base + VIC_INT_SOFT_CLEAR);
38244430ec0SRob Herring }
38344430ec0SRob Herring
vic_clear_interrupts(void __iomem * base)38444430ec0SRob Herring static void __init vic_clear_interrupts(void __iomem *base)
38544430ec0SRob Herring {
38644430ec0SRob Herring unsigned int i;
38744430ec0SRob Herring
38844430ec0SRob Herring writel(0, base + VIC_PL190_VECT_ADDR);
38944430ec0SRob Herring for (i = 0; i < 19; i++) {
39044430ec0SRob Herring unsigned int value;
39144430ec0SRob Herring
39244430ec0SRob Herring value = readl(base + VIC_PL190_VECT_ADDR);
39344430ec0SRob Herring writel(value, base + VIC_PL190_VECT_ADDR);
39444430ec0SRob Herring }
39544430ec0SRob Herring }
39644430ec0SRob Herring
39744430ec0SRob Herring /*
39844430ec0SRob Herring * The PL190 cell from ARM has been modified by ST to handle 64 interrupts.
39944430ec0SRob Herring * The original cell has 32 interrupts, while the modified one has 64,
400a359f757SIngo Molnar * replicating two blocks 0x00..0x1f in 0x20..0x3f. In that case
40144430ec0SRob Herring * the probe function is called twice, with base set to offset 000
40244430ec0SRob Herring * and 020 within the page. We call this "second block".
40344430ec0SRob Herring */
vic_init_st(void __iomem * base,unsigned int irq_start,u32 vic_sources,struct device_node * node)40444430ec0SRob Herring static void __init vic_init_st(void __iomem *base, unsigned int irq_start,
40544430ec0SRob Herring u32 vic_sources, struct device_node *node)
40644430ec0SRob Herring {
40744430ec0SRob Herring unsigned int i;
40844430ec0SRob Herring int vic_2nd_block = ((unsigned long)base & ~PAGE_MASK) != 0;
40944430ec0SRob Herring
41044430ec0SRob Herring /* Disable all interrupts initially. */
41144430ec0SRob Herring vic_disable(base);
41244430ec0SRob Herring
41344430ec0SRob Herring /*
41444430ec0SRob Herring * Make sure we clear all existing interrupts. The vector registers
41544430ec0SRob Herring * in this cell are after the second block of general registers,
41644430ec0SRob Herring * so we can address them using standard offsets, but only from
41744430ec0SRob Herring * the second base address, which is 0x20 in the page
41844430ec0SRob Herring */
41944430ec0SRob Herring if (vic_2nd_block) {
42044430ec0SRob Herring vic_clear_interrupts(base);
42144430ec0SRob Herring
42244430ec0SRob Herring /* ST has 16 vectors as well, but we don't enable them by now */
42344430ec0SRob Herring for (i = 0; i < 16; i++) {
42444430ec0SRob Herring void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4);
42544430ec0SRob Herring writel(0, reg);
42644430ec0SRob Herring }
42744430ec0SRob Herring
42844430ec0SRob Herring writel(32, base + VIC_PL190_DEF_VECT_ADDR);
42944430ec0SRob Herring }
43044430ec0SRob Herring
431e641b987SLinus Walleij vic_register(base, 0, irq_start, vic_sources, 0, node);
43244430ec0SRob Herring }
43344430ec0SRob Herring
__vic_init(void __iomem * base,int parent_irq,int irq_start,u32 vic_sources,u32 resume_sources,struct device_node * node)434b0b92ab6SLinus Walleij static void __init __vic_init(void __iomem *base, int parent_irq, int irq_start,
43544430ec0SRob Herring u32 vic_sources, u32 resume_sources,
43644430ec0SRob Herring struct device_node *node)
43744430ec0SRob Herring {
43844430ec0SRob Herring unsigned int i;
43944430ec0SRob Herring u32 cellid = 0;
44044430ec0SRob Herring enum amba_vendor vendor;
44144430ec0SRob Herring
44244430ec0SRob Herring /* Identify which VIC cell this one is, by reading the ID */
44344430ec0SRob Herring for (i = 0; i < 4; i++) {
44444430ec0SRob Herring void __iomem *addr;
44544430ec0SRob Herring addr = (void __iomem *)((u32)base & PAGE_MASK) + 0xfe0 + (i * 4);
44644430ec0SRob Herring cellid |= (readl(addr) & 0xff) << (8 * i);
44744430ec0SRob Herring }
44844430ec0SRob Herring vendor = (cellid >> 12) & 0xff;
44944430ec0SRob Herring printk(KERN_INFO "VIC @%p: id 0x%08x, vendor 0x%02x\n",
45044430ec0SRob Herring base, cellid, vendor);
45144430ec0SRob Herring
45244430ec0SRob Herring switch(vendor) {
45344430ec0SRob Herring case AMBA_VENDOR_ST:
45444430ec0SRob Herring vic_init_st(base, irq_start, vic_sources, node);
45544430ec0SRob Herring return;
45644430ec0SRob Herring default:
45744430ec0SRob Herring printk(KERN_WARNING "VIC: unknown vendor, continuing anyways\n");
458df561f66SGustavo A. R. Silva fallthrough;
45944430ec0SRob Herring case AMBA_VENDOR_ARM:
46044430ec0SRob Herring break;
46144430ec0SRob Herring }
46244430ec0SRob Herring
46344430ec0SRob Herring /* Disable all interrupts initially. */
46444430ec0SRob Herring vic_disable(base);
46544430ec0SRob Herring
46644430ec0SRob Herring /* Make sure we clear all existing interrupts */
46744430ec0SRob Herring vic_clear_interrupts(base);
46844430ec0SRob Herring
46944430ec0SRob Herring vic_init2(base);
47044430ec0SRob Herring
471e641b987SLinus Walleij vic_register(base, parent_irq, irq_start, vic_sources, resume_sources, node);
47244430ec0SRob Herring }
47344430ec0SRob Herring
47444430ec0SRob Herring /**
47544430ec0SRob Herring * vic_init() - initialise a vectored interrupt controller
47644430ec0SRob Herring * @base: iomem base address
47744430ec0SRob Herring * @irq_start: starting interrupt number, must be muliple of 32
47844430ec0SRob Herring * @vic_sources: bitmask of interrupt sources to allow
47944430ec0SRob Herring * @resume_sources: bitmask of interrupt sources to allow for resume
48044430ec0SRob Herring */
vic_init(void __iomem * base,unsigned int irq_start,u32 vic_sources,u32 resume_sources)48144430ec0SRob Herring void __init vic_init(void __iomem *base, unsigned int irq_start,
48244430ec0SRob Herring u32 vic_sources, u32 resume_sources)
48344430ec0SRob Herring {
484e641b987SLinus Walleij __vic_init(base, 0, irq_start, vic_sources, resume_sources, NULL);
48544430ec0SRob Herring }
48644430ec0SRob Herring
48744430ec0SRob Herring #ifdef CONFIG_OF
vic_of_init(struct device_node * node,struct device_node * parent)488df042a5fSBen Dooks static int __init vic_of_init(struct device_node *node,
489df042a5fSBen Dooks struct device_node *parent)
49044430ec0SRob Herring {
49144430ec0SRob Herring void __iomem *regs;
49281e9c179STomasz Figa u32 interrupt_mask = ~0;
49381e9c179STomasz Figa u32 wakeup_mask = ~0;
494a1511107SLinus Walleij int parent_irq;
49544430ec0SRob Herring
49644430ec0SRob Herring regs = of_iomap(node, 0);
49744430ec0SRob Herring if (WARN_ON(!regs))
49844430ec0SRob Herring return -EIO;
49944430ec0SRob Herring
50081e9c179STomasz Figa of_property_read_u32(node, "valid-mask", &interrupt_mask);
50181e9c179STomasz Figa of_property_read_u32(node, "valid-wakeup-mask", &wakeup_mask);
502a1511107SLinus Walleij parent_irq = of_irq_get(node, 0);
503a1511107SLinus Walleij if (parent_irq < 0)
504a1511107SLinus Walleij parent_irq = 0;
50581e9c179STomasz Figa
50644430ec0SRob Herring /*
50744430ec0SRob Herring * Passing 0 as first IRQ makes the simple domain allocate descriptors
50844430ec0SRob Herring */
509a1511107SLinus Walleij __vic_init(regs, parent_irq, 0, interrupt_mask, wakeup_mask, node);
51044430ec0SRob Herring
51144430ec0SRob Herring return 0;
51244430ec0SRob Herring }
51344430ec0SRob Herring IRQCHIP_DECLARE(arm_pl190_vic, "arm,pl190-vic", vic_of_init);
51444430ec0SRob Herring IRQCHIP_DECLARE(arm_pl192_vic, "arm,pl192-vic", vic_of_init);
51544430ec0SRob Herring IRQCHIP_DECLARE(arm_versatile_vic, "arm,versatile-vic", vic_of_init);
51644430ec0SRob Herring #endif /* CONFIG OF */
517