1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) Maxime Coquelin 2015 4 * Copyright (C) STMicroelectronics 2017 5 * Author: Maxime Coquelin <mcoquelin.stm32@gmail.com> 6 */ 7 8 #include <linux/bitops.h> 9 #include <linux/delay.h> 10 #include <linux/hwspinlock.h> 11 #include <linux/interrupt.h> 12 #include <linux/io.h> 13 #include <linux/irq.h> 14 #include <linux/irqchip.h> 15 #include <linux/irqchip/chained_irq.h> 16 #include <linux/irqdomain.h> 17 #include <linux/module.h> 18 #include <linux/of_address.h> 19 #include <linux/of_irq.h> 20 #include <linux/of_platform.h> 21 #include <linux/syscore_ops.h> 22 23 #include <dt-bindings/interrupt-controller/arm-gic.h> 24 25 #define IRQS_PER_BANK 32 26 27 #define HWSPNLCK_TIMEOUT 1000 /* usec */ 28 #define HWSPNLCK_RETRY_DELAY 100 /* usec */ 29 30 struct stm32_exti_bank { 31 u32 imr_ofst; 32 u32 emr_ofst; 33 u32 rtsr_ofst; 34 u32 ftsr_ofst; 35 u32 swier_ofst; 36 u32 rpr_ofst; 37 u32 fpr_ofst; 38 }; 39 40 #define UNDEF_REG ~0 41 42 struct stm32_desc_irq { 43 u32 exti; 44 u32 irq_parent; 45 }; 46 47 struct stm32_exti_drv_data { 48 const struct stm32_exti_bank **exti_banks; 49 const struct stm32_desc_irq *desc_irqs; 50 u32 bank_nr; 51 u32 irq_nr; 52 }; 53 54 struct stm32_exti_chip_data { 55 struct stm32_exti_host_data *host_data; 56 const struct stm32_exti_bank *reg_bank; 57 struct raw_spinlock rlock; 58 u32 wake_active; 59 u32 mask_cache; 60 u32 rtsr_cache; 61 u32 ftsr_cache; 62 }; 63 64 struct stm32_exti_host_data { 65 void __iomem *base; 66 struct stm32_exti_chip_data *chips_data; 67 const struct stm32_exti_drv_data *drv_data; 68 struct hwspinlock *hwlock; 69 }; 70 71 static struct stm32_exti_host_data *stm32_host_data; 72 73 static const struct stm32_exti_bank stm32f4xx_exti_b1 = { 74 .imr_ofst = 0x00, 75 .emr_ofst = 0x04, 76 .rtsr_ofst = 0x08, 77 .ftsr_ofst = 0x0C, 78 .swier_ofst = 0x10, 79 .rpr_ofst = 0x14, 80 .fpr_ofst = UNDEF_REG, 81 }; 82 83 static const struct stm32_exti_bank *stm32f4xx_exti_banks[] = { 84 &stm32f4xx_exti_b1, 85 }; 86 87 static const struct stm32_exti_drv_data stm32f4xx_drv_data = { 88 .exti_banks = stm32f4xx_exti_banks, 89 .bank_nr = ARRAY_SIZE(stm32f4xx_exti_banks), 90 }; 91 92 static const struct stm32_exti_bank stm32h7xx_exti_b1 = { 93 .imr_ofst = 0x80, 94 .emr_ofst = 0x84, 95 .rtsr_ofst = 0x00, 96 .ftsr_ofst = 0x04, 97 .swier_ofst = 0x08, 98 .rpr_ofst = 0x88, 99 .fpr_ofst = UNDEF_REG, 100 }; 101 102 static const struct stm32_exti_bank stm32h7xx_exti_b2 = { 103 .imr_ofst = 0x90, 104 .emr_ofst = 0x94, 105 .rtsr_ofst = 0x20, 106 .ftsr_ofst = 0x24, 107 .swier_ofst = 0x28, 108 .rpr_ofst = 0x98, 109 .fpr_ofst = UNDEF_REG, 110 }; 111 112 static const struct stm32_exti_bank stm32h7xx_exti_b3 = { 113 .imr_ofst = 0xA0, 114 .emr_ofst = 0xA4, 115 .rtsr_ofst = 0x40, 116 .ftsr_ofst = 0x44, 117 .swier_ofst = 0x48, 118 .rpr_ofst = 0xA8, 119 .fpr_ofst = UNDEF_REG, 120 }; 121 122 static const struct stm32_exti_bank *stm32h7xx_exti_banks[] = { 123 &stm32h7xx_exti_b1, 124 &stm32h7xx_exti_b2, 125 &stm32h7xx_exti_b3, 126 }; 127 128 static const struct stm32_exti_drv_data stm32h7xx_drv_data = { 129 .exti_banks = stm32h7xx_exti_banks, 130 .bank_nr = ARRAY_SIZE(stm32h7xx_exti_banks), 131 }; 132 133 static const struct stm32_exti_bank stm32mp1_exti_b1 = { 134 .imr_ofst = 0x80, 135 .emr_ofst = 0x84, 136 .rtsr_ofst = 0x00, 137 .ftsr_ofst = 0x04, 138 .swier_ofst = 0x08, 139 .rpr_ofst = 0x0C, 140 .fpr_ofst = 0x10, 141 }; 142 143 static const struct stm32_exti_bank stm32mp1_exti_b2 = { 144 .imr_ofst = 0x90, 145 .emr_ofst = 0x94, 146 .rtsr_ofst = 0x20, 147 .ftsr_ofst = 0x24, 148 .swier_ofst = 0x28, 149 .rpr_ofst = 0x2C, 150 .fpr_ofst = 0x30, 151 }; 152 153 static const struct stm32_exti_bank stm32mp1_exti_b3 = { 154 .imr_ofst = 0xA0, 155 .emr_ofst = 0xA4, 156 .rtsr_ofst = 0x40, 157 .ftsr_ofst = 0x44, 158 .swier_ofst = 0x48, 159 .rpr_ofst = 0x4C, 160 .fpr_ofst = 0x50, 161 }; 162 163 static const struct stm32_exti_bank *stm32mp1_exti_banks[] = { 164 &stm32mp1_exti_b1, 165 &stm32mp1_exti_b2, 166 &stm32mp1_exti_b3, 167 }; 168 169 static const struct stm32_desc_irq stm32mp1_desc_irq[] = { 170 { .exti = 0, .irq_parent = 6 }, 171 { .exti = 1, .irq_parent = 7 }, 172 { .exti = 2, .irq_parent = 8 }, 173 { .exti = 3, .irq_parent = 9 }, 174 { .exti = 4, .irq_parent = 10 }, 175 { .exti = 5, .irq_parent = 23 }, 176 { .exti = 6, .irq_parent = 64 }, 177 { .exti = 7, .irq_parent = 65 }, 178 { .exti = 8, .irq_parent = 66 }, 179 { .exti = 9, .irq_parent = 67 }, 180 { .exti = 10, .irq_parent = 40 }, 181 { .exti = 11, .irq_parent = 42 }, 182 { .exti = 12, .irq_parent = 76 }, 183 { .exti = 13, .irq_parent = 77 }, 184 { .exti = 14, .irq_parent = 121 }, 185 { .exti = 15, .irq_parent = 127 }, 186 { .exti = 16, .irq_parent = 1 }, 187 { .exti = 65, .irq_parent = 144 }, 188 { .exti = 68, .irq_parent = 143 }, 189 { .exti = 73, .irq_parent = 129 }, 190 }; 191 192 static const struct stm32_exti_drv_data stm32mp1_drv_data = { 193 .exti_banks = stm32mp1_exti_banks, 194 .bank_nr = ARRAY_SIZE(stm32mp1_exti_banks), 195 .desc_irqs = stm32mp1_desc_irq, 196 .irq_nr = ARRAY_SIZE(stm32mp1_desc_irq), 197 }; 198 199 static int stm32_exti_to_irq(const struct stm32_exti_drv_data *drv_data, 200 irq_hw_number_t hwirq) 201 { 202 const struct stm32_desc_irq *desc_irq; 203 int i; 204 205 if (!drv_data->desc_irqs) 206 return -EINVAL; 207 208 for (i = 0; i < drv_data->irq_nr; i++) { 209 desc_irq = &drv_data->desc_irqs[i]; 210 if (desc_irq->exti == hwirq) 211 return desc_irq->irq_parent; 212 } 213 214 return -EINVAL; 215 } 216 217 static unsigned long stm32_exti_pending(struct irq_chip_generic *gc) 218 { 219 struct stm32_exti_chip_data *chip_data = gc->private; 220 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank; 221 unsigned long pending; 222 223 pending = irq_reg_readl(gc, stm32_bank->rpr_ofst); 224 if (stm32_bank->fpr_ofst != UNDEF_REG) 225 pending |= irq_reg_readl(gc, stm32_bank->fpr_ofst); 226 227 return pending; 228 } 229 230 static void stm32_irq_handler(struct irq_desc *desc) 231 { 232 struct irq_domain *domain = irq_desc_get_handler_data(desc); 233 struct irq_chip *chip = irq_desc_get_chip(desc); 234 unsigned int virq, nbanks = domain->gc->num_chips; 235 struct irq_chip_generic *gc; 236 unsigned long pending; 237 int n, i, irq_base = 0; 238 239 chained_irq_enter(chip, desc); 240 241 for (i = 0; i < nbanks; i++, irq_base += IRQS_PER_BANK) { 242 gc = irq_get_domain_generic_chip(domain, irq_base); 243 244 while ((pending = stm32_exti_pending(gc))) { 245 for_each_set_bit(n, &pending, IRQS_PER_BANK) { 246 virq = irq_find_mapping(domain, irq_base + n); 247 generic_handle_irq(virq); 248 } 249 } 250 } 251 252 chained_irq_exit(chip, desc); 253 } 254 255 static int stm32_exti_set_type(struct irq_data *d, 256 unsigned int type, u32 *rtsr, u32 *ftsr) 257 { 258 u32 mask = BIT(d->hwirq % IRQS_PER_BANK); 259 260 switch (type) { 261 case IRQ_TYPE_EDGE_RISING: 262 *rtsr |= mask; 263 *ftsr &= ~mask; 264 break; 265 case IRQ_TYPE_EDGE_FALLING: 266 *rtsr &= ~mask; 267 *ftsr |= mask; 268 break; 269 case IRQ_TYPE_EDGE_BOTH: 270 *rtsr |= mask; 271 *ftsr |= mask; 272 break; 273 default: 274 return -EINVAL; 275 } 276 277 return 0; 278 } 279 280 static int stm32_exti_hwspin_lock(struct stm32_exti_chip_data *chip_data) 281 { 282 int ret, timeout = 0; 283 284 if (!chip_data->host_data->hwlock) 285 return 0; 286 287 /* 288 * Use the x_raw API since we are under spin_lock protection. 289 * Do not use the x_timeout API because we are under irq_disable 290 * mode (see __setup_irq()) 291 */ 292 do { 293 ret = hwspin_trylock_raw(chip_data->host_data->hwlock); 294 if (!ret) 295 return 0; 296 297 udelay(HWSPNLCK_RETRY_DELAY); 298 timeout += HWSPNLCK_RETRY_DELAY; 299 } while (timeout < HWSPNLCK_TIMEOUT); 300 301 if (ret == -EBUSY) 302 ret = -ETIMEDOUT; 303 304 if (ret) 305 pr_err("%s can't get hwspinlock (%d)\n", __func__, ret); 306 307 return ret; 308 } 309 310 static void stm32_exti_hwspin_unlock(struct stm32_exti_chip_data *chip_data) 311 { 312 if (chip_data->host_data->hwlock) 313 hwspin_unlock_raw(chip_data->host_data->hwlock); 314 } 315 316 static int stm32_irq_set_type(struct irq_data *d, unsigned int type) 317 { 318 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 319 struct stm32_exti_chip_data *chip_data = gc->private; 320 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank; 321 u32 rtsr, ftsr; 322 int err; 323 324 irq_gc_lock(gc); 325 326 err = stm32_exti_hwspin_lock(chip_data); 327 if (err) 328 goto unlock; 329 330 rtsr = irq_reg_readl(gc, stm32_bank->rtsr_ofst); 331 ftsr = irq_reg_readl(gc, stm32_bank->ftsr_ofst); 332 333 err = stm32_exti_set_type(d, type, &rtsr, &ftsr); 334 if (err) 335 goto unspinlock; 336 337 irq_reg_writel(gc, rtsr, stm32_bank->rtsr_ofst); 338 irq_reg_writel(gc, ftsr, stm32_bank->ftsr_ofst); 339 340 unspinlock: 341 stm32_exti_hwspin_unlock(chip_data); 342 unlock: 343 irq_gc_unlock(gc); 344 345 return err; 346 } 347 348 static void stm32_chip_suspend(struct stm32_exti_chip_data *chip_data, 349 u32 wake_active) 350 { 351 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank; 352 void __iomem *base = chip_data->host_data->base; 353 354 /* save rtsr, ftsr registers */ 355 chip_data->rtsr_cache = readl_relaxed(base + stm32_bank->rtsr_ofst); 356 chip_data->ftsr_cache = readl_relaxed(base + stm32_bank->ftsr_ofst); 357 358 writel_relaxed(wake_active, base + stm32_bank->imr_ofst); 359 } 360 361 static void stm32_chip_resume(struct stm32_exti_chip_data *chip_data, 362 u32 mask_cache) 363 { 364 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank; 365 void __iomem *base = chip_data->host_data->base; 366 367 /* restore rtsr, ftsr, registers */ 368 writel_relaxed(chip_data->rtsr_cache, base + stm32_bank->rtsr_ofst); 369 writel_relaxed(chip_data->ftsr_cache, base + stm32_bank->ftsr_ofst); 370 371 writel_relaxed(mask_cache, base + stm32_bank->imr_ofst); 372 } 373 374 static void stm32_irq_suspend(struct irq_chip_generic *gc) 375 { 376 struct stm32_exti_chip_data *chip_data = gc->private; 377 378 irq_gc_lock(gc); 379 stm32_chip_suspend(chip_data, gc->wake_active); 380 irq_gc_unlock(gc); 381 } 382 383 static void stm32_irq_resume(struct irq_chip_generic *gc) 384 { 385 struct stm32_exti_chip_data *chip_data = gc->private; 386 387 irq_gc_lock(gc); 388 stm32_chip_resume(chip_data, gc->mask_cache); 389 irq_gc_unlock(gc); 390 } 391 392 static int stm32_exti_alloc(struct irq_domain *d, unsigned int virq, 393 unsigned int nr_irqs, void *data) 394 { 395 struct irq_fwspec *fwspec = data; 396 irq_hw_number_t hwirq; 397 398 hwirq = fwspec->param[0]; 399 400 irq_map_generic_chip(d, virq, hwirq); 401 402 return 0; 403 } 404 405 static void stm32_exti_free(struct irq_domain *d, unsigned int virq, 406 unsigned int nr_irqs) 407 { 408 struct irq_data *data = irq_domain_get_irq_data(d, virq); 409 410 irq_domain_reset_irq_data(data); 411 } 412 413 static const struct irq_domain_ops irq_exti_domain_ops = { 414 .map = irq_map_generic_chip, 415 .alloc = stm32_exti_alloc, 416 .free = stm32_exti_free, 417 }; 418 419 static void stm32_irq_ack(struct irq_data *d) 420 { 421 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 422 struct stm32_exti_chip_data *chip_data = gc->private; 423 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank; 424 425 irq_gc_lock(gc); 426 427 irq_reg_writel(gc, d->mask, stm32_bank->rpr_ofst); 428 if (stm32_bank->fpr_ofst != UNDEF_REG) 429 irq_reg_writel(gc, d->mask, stm32_bank->fpr_ofst); 430 431 irq_gc_unlock(gc); 432 } 433 434 static inline u32 stm32_exti_set_bit(struct irq_data *d, u32 reg) 435 { 436 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d); 437 void __iomem *base = chip_data->host_data->base; 438 u32 val; 439 440 val = readl_relaxed(base + reg); 441 val |= BIT(d->hwirq % IRQS_PER_BANK); 442 writel_relaxed(val, base + reg); 443 444 return val; 445 } 446 447 static inline u32 stm32_exti_clr_bit(struct irq_data *d, u32 reg) 448 { 449 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d); 450 void __iomem *base = chip_data->host_data->base; 451 u32 val; 452 453 val = readl_relaxed(base + reg); 454 val &= ~BIT(d->hwirq % IRQS_PER_BANK); 455 writel_relaxed(val, base + reg); 456 457 return val; 458 } 459 460 static void stm32_exti_h_eoi(struct irq_data *d) 461 { 462 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d); 463 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank; 464 465 raw_spin_lock(&chip_data->rlock); 466 467 stm32_exti_set_bit(d, stm32_bank->rpr_ofst); 468 if (stm32_bank->fpr_ofst != UNDEF_REG) 469 stm32_exti_set_bit(d, stm32_bank->fpr_ofst); 470 471 raw_spin_unlock(&chip_data->rlock); 472 473 if (d->parent_data->chip) 474 irq_chip_eoi_parent(d); 475 } 476 477 static void stm32_exti_h_mask(struct irq_data *d) 478 { 479 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d); 480 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank; 481 482 raw_spin_lock(&chip_data->rlock); 483 chip_data->mask_cache = stm32_exti_clr_bit(d, stm32_bank->imr_ofst); 484 raw_spin_unlock(&chip_data->rlock); 485 486 if (d->parent_data->chip) 487 irq_chip_mask_parent(d); 488 } 489 490 static void stm32_exti_h_unmask(struct irq_data *d) 491 { 492 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d); 493 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank; 494 495 raw_spin_lock(&chip_data->rlock); 496 chip_data->mask_cache = stm32_exti_set_bit(d, stm32_bank->imr_ofst); 497 raw_spin_unlock(&chip_data->rlock); 498 499 if (d->parent_data->chip) 500 irq_chip_unmask_parent(d); 501 } 502 503 static int stm32_exti_h_set_type(struct irq_data *d, unsigned int type) 504 { 505 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d); 506 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank; 507 void __iomem *base = chip_data->host_data->base; 508 u32 rtsr, ftsr; 509 int err; 510 511 raw_spin_lock(&chip_data->rlock); 512 513 err = stm32_exti_hwspin_lock(chip_data); 514 if (err) 515 goto unlock; 516 517 rtsr = readl_relaxed(base + stm32_bank->rtsr_ofst); 518 ftsr = readl_relaxed(base + stm32_bank->ftsr_ofst); 519 520 err = stm32_exti_set_type(d, type, &rtsr, &ftsr); 521 if (err) 522 goto unspinlock; 523 524 writel_relaxed(rtsr, base + stm32_bank->rtsr_ofst); 525 writel_relaxed(ftsr, base + stm32_bank->ftsr_ofst); 526 527 unspinlock: 528 stm32_exti_hwspin_unlock(chip_data); 529 unlock: 530 raw_spin_unlock(&chip_data->rlock); 531 532 return err; 533 } 534 535 static int stm32_exti_h_set_wake(struct irq_data *d, unsigned int on) 536 { 537 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d); 538 u32 mask = BIT(d->hwirq % IRQS_PER_BANK); 539 540 raw_spin_lock(&chip_data->rlock); 541 542 if (on) 543 chip_data->wake_active |= mask; 544 else 545 chip_data->wake_active &= ~mask; 546 547 raw_spin_unlock(&chip_data->rlock); 548 549 return 0; 550 } 551 552 static int stm32_exti_h_set_affinity(struct irq_data *d, 553 const struct cpumask *dest, bool force) 554 { 555 if (d->parent_data->chip) 556 return irq_chip_set_affinity_parent(d, dest, force); 557 558 return -EINVAL; 559 } 560 561 static int __maybe_unused stm32_exti_h_suspend(void) 562 { 563 struct stm32_exti_chip_data *chip_data; 564 int i; 565 566 for (i = 0; i < stm32_host_data->drv_data->bank_nr; i++) { 567 chip_data = &stm32_host_data->chips_data[i]; 568 raw_spin_lock(&chip_data->rlock); 569 stm32_chip_suspend(chip_data, chip_data->wake_active); 570 raw_spin_unlock(&chip_data->rlock); 571 } 572 573 return 0; 574 } 575 576 static void __maybe_unused stm32_exti_h_resume(void) 577 { 578 struct stm32_exti_chip_data *chip_data; 579 int i; 580 581 for (i = 0; i < stm32_host_data->drv_data->bank_nr; i++) { 582 chip_data = &stm32_host_data->chips_data[i]; 583 raw_spin_lock(&chip_data->rlock); 584 stm32_chip_resume(chip_data, chip_data->mask_cache); 585 raw_spin_unlock(&chip_data->rlock); 586 } 587 } 588 589 static struct syscore_ops stm32_exti_h_syscore_ops = { 590 #ifdef CONFIG_PM_SLEEP 591 .suspend = stm32_exti_h_suspend, 592 .resume = stm32_exti_h_resume, 593 #endif 594 }; 595 596 static void stm32_exti_h_syscore_init(struct stm32_exti_host_data *host_data) 597 { 598 stm32_host_data = host_data; 599 register_syscore_ops(&stm32_exti_h_syscore_ops); 600 } 601 602 static void stm32_exti_h_syscore_deinit(void) 603 { 604 unregister_syscore_ops(&stm32_exti_h_syscore_ops); 605 } 606 607 static struct irq_chip stm32_exti_h_chip = { 608 .name = "stm32-exti-h", 609 .irq_eoi = stm32_exti_h_eoi, 610 .irq_mask = stm32_exti_h_mask, 611 .irq_unmask = stm32_exti_h_unmask, 612 .irq_retrigger = irq_chip_retrigger_hierarchy, 613 .irq_set_type = stm32_exti_h_set_type, 614 .irq_set_wake = stm32_exti_h_set_wake, 615 .flags = IRQCHIP_MASK_ON_SUSPEND, 616 .irq_set_affinity = IS_ENABLED(CONFIG_SMP) ? stm32_exti_h_set_affinity : NULL, 617 }; 618 619 static int stm32_exti_h_domain_alloc(struct irq_domain *dm, 620 unsigned int virq, 621 unsigned int nr_irqs, void *data) 622 { 623 struct stm32_exti_host_data *host_data = dm->host_data; 624 struct stm32_exti_chip_data *chip_data; 625 struct irq_fwspec *fwspec = data; 626 struct irq_fwspec p_fwspec; 627 irq_hw_number_t hwirq; 628 int p_irq, bank; 629 630 hwirq = fwspec->param[0]; 631 bank = hwirq / IRQS_PER_BANK; 632 chip_data = &host_data->chips_data[bank]; 633 634 irq_domain_set_hwirq_and_chip(dm, virq, hwirq, 635 &stm32_exti_h_chip, chip_data); 636 637 p_irq = stm32_exti_to_irq(host_data->drv_data, hwirq); 638 if (p_irq >= 0) { 639 p_fwspec.fwnode = dm->parent->fwnode; 640 p_fwspec.param_count = 3; 641 p_fwspec.param[0] = GIC_SPI; 642 p_fwspec.param[1] = p_irq; 643 p_fwspec.param[2] = IRQ_TYPE_LEVEL_HIGH; 644 645 return irq_domain_alloc_irqs_parent(dm, virq, 1, &p_fwspec); 646 } 647 648 return 0; 649 } 650 651 static struct 652 stm32_exti_host_data *stm32_exti_host_init(const struct stm32_exti_drv_data *dd, 653 struct device_node *node) 654 { 655 struct stm32_exti_host_data *host_data; 656 657 host_data = kzalloc(sizeof(*host_data), GFP_KERNEL); 658 if (!host_data) 659 return NULL; 660 661 host_data->drv_data = dd; 662 host_data->chips_data = kcalloc(dd->bank_nr, 663 sizeof(struct stm32_exti_chip_data), 664 GFP_KERNEL); 665 if (!host_data->chips_data) 666 goto free_host_data; 667 668 host_data->base = of_iomap(node, 0); 669 if (!host_data->base) { 670 pr_err("%pOF: Unable to map registers\n", node); 671 goto free_chips_data; 672 } 673 674 stm32_host_data = host_data; 675 676 return host_data; 677 678 free_chips_data: 679 kfree(host_data->chips_data); 680 free_host_data: 681 kfree(host_data); 682 683 return NULL; 684 } 685 686 static struct 687 stm32_exti_chip_data *stm32_exti_chip_init(struct stm32_exti_host_data *h_data, 688 u32 bank_idx, 689 struct device_node *node) 690 { 691 const struct stm32_exti_bank *stm32_bank; 692 struct stm32_exti_chip_data *chip_data; 693 void __iomem *base = h_data->base; 694 695 stm32_bank = h_data->drv_data->exti_banks[bank_idx]; 696 chip_data = &h_data->chips_data[bank_idx]; 697 chip_data->host_data = h_data; 698 chip_data->reg_bank = stm32_bank; 699 700 raw_spin_lock_init(&chip_data->rlock); 701 702 /* 703 * This IP has no reset, so after hot reboot we should 704 * clear registers to avoid residue 705 */ 706 writel_relaxed(0, base + stm32_bank->imr_ofst); 707 writel_relaxed(0, base + stm32_bank->emr_ofst); 708 709 pr_info("%pOF: bank%d\n", node, bank_idx); 710 711 return chip_data; 712 } 713 714 static int __init stm32_exti_init(const struct stm32_exti_drv_data *drv_data, 715 struct device_node *node) 716 { 717 struct stm32_exti_host_data *host_data; 718 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; 719 int nr_irqs, ret, i; 720 struct irq_chip_generic *gc; 721 struct irq_domain *domain; 722 723 host_data = stm32_exti_host_init(drv_data, node); 724 if (!host_data) 725 return -ENOMEM; 726 727 domain = irq_domain_add_linear(node, drv_data->bank_nr * IRQS_PER_BANK, 728 &irq_exti_domain_ops, NULL); 729 if (!domain) { 730 pr_err("%pOFn: Could not register interrupt domain.\n", 731 node); 732 ret = -ENOMEM; 733 goto out_unmap; 734 } 735 736 ret = irq_alloc_domain_generic_chips(domain, IRQS_PER_BANK, 1, "exti", 737 handle_edge_irq, clr, 0, 0); 738 if (ret) { 739 pr_err("%pOF: Could not allocate generic interrupt chip.\n", 740 node); 741 goto out_free_domain; 742 } 743 744 for (i = 0; i < drv_data->bank_nr; i++) { 745 const struct stm32_exti_bank *stm32_bank; 746 struct stm32_exti_chip_data *chip_data; 747 748 stm32_bank = drv_data->exti_banks[i]; 749 chip_data = stm32_exti_chip_init(host_data, i, node); 750 751 gc = irq_get_domain_generic_chip(domain, i * IRQS_PER_BANK); 752 753 gc->reg_base = host_data->base; 754 gc->chip_types->type = IRQ_TYPE_EDGE_BOTH; 755 gc->chip_types->chip.irq_ack = stm32_irq_ack; 756 gc->chip_types->chip.irq_mask = irq_gc_mask_clr_bit; 757 gc->chip_types->chip.irq_unmask = irq_gc_mask_set_bit; 758 gc->chip_types->chip.irq_set_type = stm32_irq_set_type; 759 gc->chip_types->chip.irq_set_wake = irq_gc_set_wake; 760 gc->suspend = stm32_irq_suspend; 761 gc->resume = stm32_irq_resume; 762 gc->wake_enabled = IRQ_MSK(IRQS_PER_BANK); 763 764 gc->chip_types->regs.mask = stm32_bank->imr_ofst; 765 gc->private = (void *)chip_data; 766 } 767 768 nr_irqs = of_irq_count(node); 769 for (i = 0; i < nr_irqs; i++) { 770 unsigned int irq = irq_of_parse_and_map(node, i); 771 772 irq_set_handler_data(irq, domain); 773 irq_set_chained_handler(irq, stm32_irq_handler); 774 } 775 776 return 0; 777 778 out_free_domain: 779 irq_domain_remove(domain); 780 out_unmap: 781 iounmap(host_data->base); 782 kfree(host_data->chips_data); 783 kfree(host_data); 784 return ret; 785 } 786 787 static const struct irq_domain_ops stm32_exti_h_domain_ops = { 788 .alloc = stm32_exti_h_domain_alloc, 789 .free = irq_domain_free_irqs_common, 790 .xlate = irq_domain_xlate_twocell, 791 }; 792 793 static void stm32_exti_remove_irq(void *data) 794 { 795 struct irq_domain *domain = data; 796 797 irq_domain_remove(domain); 798 } 799 800 static int stm32_exti_remove(struct platform_device *pdev) 801 { 802 stm32_exti_h_syscore_deinit(); 803 return 0; 804 } 805 806 static int stm32_exti_probe(struct platform_device *pdev) 807 { 808 int ret, i; 809 struct device *dev = &pdev->dev; 810 struct device_node *np = dev->of_node; 811 struct irq_domain *parent_domain, *domain; 812 struct stm32_exti_host_data *host_data; 813 const struct stm32_exti_drv_data *drv_data; 814 struct resource *res; 815 816 host_data = devm_kzalloc(dev, sizeof(*host_data), GFP_KERNEL); 817 if (!host_data) 818 return -ENOMEM; 819 820 /* check for optional hwspinlock which may be not available yet */ 821 ret = of_hwspin_lock_get_id(np, 0); 822 if (ret == -EPROBE_DEFER) 823 /* hwspinlock framework not yet ready */ 824 return ret; 825 826 if (ret >= 0) { 827 host_data->hwlock = devm_hwspin_lock_request_specific(dev, ret); 828 if (!host_data->hwlock) { 829 dev_err(dev, "Failed to request hwspinlock\n"); 830 return -EINVAL; 831 } 832 } else if (ret != -ENOENT) { 833 /* note: ENOENT is a valid case (means 'no hwspinlock') */ 834 dev_err(dev, "Failed to get hwspinlock\n"); 835 return ret; 836 } 837 838 /* initialize host_data */ 839 drv_data = of_device_get_match_data(dev); 840 if (!drv_data) { 841 dev_err(dev, "no of match data\n"); 842 return -ENODEV; 843 } 844 host_data->drv_data = drv_data; 845 846 host_data->chips_data = devm_kcalloc(dev, drv_data->bank_nr, 847 sizeof(*host_data->chips_data), 848 GFP_KERNEL); 849 if (!host_data->chips_data) 850 return -ENOMEM; 851 852 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 853 host_data->base = devm_ioremap_resource(dev, res); 854 if (IS_ERR(host_data->base)) { 855 dev_err(dev, "Unable to map registers\n"); 856 return PTR_ERR(host_data->base); 857 } 858 859 for (i = 0; i < drv_data->bank_nr; i++) 860 stm32_exti_chip_init(host_data, i, np); 861 862 parent_domain = irq_find_host(of_irq_find_parent(np)); 863 if (!parent_domain) { 864 dev_err(dev, "GIC interrupt-parent not found\n"); 865 return -EINVAL; 866 } 867 868 domain = irq_domain_add_hierarchy(parent_domain, 0, 869 drv_data->bank_nr * IRQS_PER_BANK, 870 np, &stm32_exti_h_domain_ops, 871 host_data); 872 873 if (!domain) { 874 dev_err(dev, "Could not register exti domain\n"); 875 return -ENOMEM; 876 } 877 878 ret = devm_add_action_or_reset(dev, stm32_exti_remove_irq, domain); 879 if (ret) 880 return ret; 881 882 stm32_exti_h_syscore_init(host_data); 883 884 return 0; 885 } 886 887 /* platform driver only for MP1 */ 888 static const struct of_device_id stm32_exti_ids[] = { 889 { .compatible = "st,stm32mp1-exti", .data = &stm32mp1_drv_data}, 890 {}, 891 }; 892 MODULE_DEVICE_TABLE(of, stm32_exti_ids); 893 894 static struct platform_driver stm32_exti_driver = { 895 .probe = stm32_exti_probe, 896 .remove = stm32_exti_remove, 897 .driver = { 898 .name = "stm32_exti", 899 .of_match_table = stm32_exti_ids, 900 }, 901 }; 902 903 static int __init stm32_exti_arch_init(void) 904 { 905 return platform_driver_register(&stm32_exti_driver); 906 } 907 908 static void __exit stm32_exti_arch_exit(void) 909 { 910 return platform_driver_unregister(&stm32_exti_driver); 911 } 912 913 arch_initcall(stm32_exti_arch_init); 914 module_exit(stm32_exti_arch_exit); 915 916 /* no platform driver for F4 and H7 */ 917 static int __init stm32f4_exti_of_init(struct device_node *np, 918 struct device_node *parent) 919 { 920 return stm32_exti_init(&stm32f4xx_drv_data, np); 921 } 922 923 IRQCHIP_DECLARE(stm32f4_exti, "st,stm32-exti", stm32f4_exti_of_init); 924 925 static int __init stm32h7_exti_of_init(struct device_node *np, 926 struct device_node *parent) 927 { 928 return stm32_exti_init(&stm32h7xx_drv_data, np); 929 } 930 931 IRQCHIP_DECLARE(stm32h7_exti, "st,stm32h7-exti", stm32h7_exti_of_init); 932