1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) Maxime Coquelin 2015 4 * Copyright (C) STMicroelectronics 2017 5 * Author: Maxime Coquelin <mcoquelin.stm32@gmail.com> 6 */ 7 8 #include <linux/bitops.h> 9 #include <linux/delay.h> 10 #include <linux/hwspinlock.h> 11 #include <linux/interrupt.h> 12 #include <linux/io.h> 13 #include <linux/irq.h> 14 #include <linux/irqchip.h> 15 #include <linux/irqchip/chained_irq.h> 16 #include <linux/irqdomain.h> 17 #include <linux/module.h> 18 #include <linux/of_address.h> 19 #include <linux/of_irq.h> 20 #include <linux/of_platform.h> 21 #include <linux/syscore_ops.h> 22 23 #include <dt-bindings/interrupt-controller/arm-gic.h> 24 25 #define IRQS_PER_BANK 32 26 27 #define HWSPNLCK_TIMEOUT 1000 /* usec */ 28 29 struct stm32_exti_bank { 30 u32 imr_ofst; 31 u32 emr_ofst; 32 u32 rtsr_ofst; 33 u32 ftsr_ofst; 34 u32 swier_ofst; 35 u32 rpr_ofst; 36 u32 fpr_ofst; 37 u32 trg_ofst; 38 }; 39 40 #define UNDEF_REG ~0 41 42 struct stm32_desc_irq { 43 u32 exti; 44 u32 irq_parent; 45 }; 46 47 struct stm32_exti_drv_data { 48 const struct stm32_exti_bank **exti_banks; 49 const struct stm32_desc_irq *desc_irqs; 50 u32 bank_nr; 51 u32 irq_nr; 52 }; 53 54 struct stm32_exti_chip_data { 55 struct stm32_exti_host_data *host_data; 56 const struct stm32_exti_bank *reg_bank; 57 struct raw_spinlock rlock; 58 u32 wake_active; 59 u32 mask_cache; 60 u32 rtsr_cache; 61 u32 ftsr_cache; 62 }; 63 64 struct stm32_exti_host_data { 65 void __iomem *base; 66 struct stm32_exti_chip_data *chips_data; 67 const struct stm32_exti_drv_data *drv_data; 68 struct hwspinlock *hwlock; 69 }; 70 71 static struct stm32_exti_host_data *stm32_host_data; 72 73 static const struct stm32_exti_bank stm32f4xx_exti_b1 = { 74 .imr_ofst = 0x00, 75 .emr_ofst = 0x04, 76 .rtsr_ofst = 0x08, 77 .ftsr_ofst = 0x0C, 78 .swier_ofst = 0x10, 79 .rpr_ofst = 0x14, 80 .fpr_ofst = UNDEF_REG, 81 .trg_ofst = UNDEF_REG, 82 }; 83 84 static const struct stm32_exti_bank *stm32f4xx_exti_banks[] = { 85 &stm32f4xx_exti_b1, 86 }; 87 88 static const struct stm32_exti_drv_data stm32f4xx_drv_data = { 89 .exti_banks = stm32f4xx_exti_banks, 90 .bank_nr = ARRAY_SIZE(stm32f4xx_exti_banks), 91 }; 92 93 static const struct stm32_exti_bank stm32h7xx_exti_b1 = { 94 .imr_ofst = 0x80, 95 .emr_ofst = 0x84, 96 .rtsr_ofst = 0x00, 97 .ftsr_ofst = 0x04, 98 .swier_ofst = 0x08, 99 .rpr_ofst = 0x88, 100 .fpr_ofst = UNDEF_REG, 101 .trg_ofst = UNDEF_REG, 102 }; 103 104 static const struct stm32_exti_bank stm32h7xx_exti_b2 = { 105 .imr_ofst = 0x90, 106 .emr_ofst = 0x94, 107 .rtsr_ofst = 0x20, 108 .ftsr_ofst = 0x24, 109 .swier_ofst = 0x28, 110 .rpr_ofst = 0x98, 111 .fpr_ofst = UNDEF_REG, 112 .trg_ofst = UNDEF_REG, 113 }; 114 115 static const struct stm32_exti_bank stm32h7xx_exti_b3 = { 116 .imr_ofst = 0xA0, 117 .emr_ofst = 0xA4, 118 .rtsr_ofst = 0x40, 119 .ftsr_ofst = 0x44, 120 .swier_ofst = 0x48, 121 .rpr_ofst = 0xA8, 122 .fpr_ofst = UNDEF_REG, 123 .trg_ofst = UNDEF_REG, 124 }; 125 126 static const struct stm32_exti_bank *stm32h7xx_exti_banks[] = { 127 &stm32h7xx_exti_b1, 128 &stm32h7xx_exti_b2, 129 &stm32h7xx_exti_b3, 130 }; 131 132 static const struct stm32_exti_drv_data stm32h7xx_drv_data = { 133 .exti_banks = stm32h7xx_exti_banks, 134 .bank_nr = ARRAY_SIZE(stm32h7xx_exti_banks), 135 }; 136 137 static const struct stm32_exti_bank stm32mp1_exti_b1 = { 138 .imr_ofst = 0x80, 139 .emr_ofst = UNDEF_REG, 140 .rtsr_ofst = 0x00, 141 .ftsr_ofst = 0x04, 142 .swier_ofst = 0x08, 143 .rpr_ofst = 0x0C, 144 .fpr_ofst = 0x10, 145 .trg_ofst = 0x3EC, 146 }; 147 148 static const struct stm32_exti_bank stm32mp1_exti_b2 = { 149 .imr_ofst = 0x90, 150 .emr_ofst = UNDEF_REG, 151 .rtsr_ofst = 0x20, 152 .ftsr_ofst = 0x24, 153 .swier_ofst = 0x28, 154 .rpr_ofst = 0x2C, 155 .fpr_ofst = 0x30, 156 .trg_ofst = 0x3E8, 157 }; 158 159 static const struct stm32_exti_bank stm32mp1_exti_b3 = { 160 .imr_ofst = 0xA0, 161 .emr_ofst = UNDEF_REG, 162 .rtsr_ofst = 0x40, 163 .ftsr_ofst = 0x44, 164 .swier_ofst = 0x48, 165 .rpr_ofst = 0x4C, 166 .fpr_ofst = 0x50, 167 .trg_ofst = 0x3E4, 168 }; 169 170 static const struct stm32_exti_bank *stm32mp1_exti_banks[] = { 171 &stm32mp1_exti_b1, 172 &stm32mp1_exti_b2, 173 &stm32mp1_exti_b3, 174 }; 175 176 static struct irq_chip stm32_exti_h_chip; 177 static struct irq_chip stm32_exti_h_chip_direct; 178 179 static const struct stm32_desc_irq stm32mp1_desc_irq[] = { 180 { .exti = 0, .irq_parent = 6 }, 181 { .exti = 1, .irq_parent = 7 }, 182 { .exti = 2, .irq_parent = 8 }, 183 { .exti = 3, .irq_parent = 9 }, 184 { .exti = 4, .irq_parent = 10 }, 185 { .exti = 5, .irq_parent = 23 }, 186 { .exti = 6, .irq_parent = 64 }, 187 { .exti = 7, .irq_parent = 65 }, 188 { .exti = 8, .irq_parent = 66 }, 189 { .exti = 9, .irq_parent = 67 }, 190 { .exti = 10, .irq_parent = 40 }, 191 { .exti = 11, .irq_parent = 42 }, 192 { .exti = 12, .irq_parent = 76 }, 193 { .exti = 13, .irq_parent = 77 }, 194 { .exti = 14, .irq_parent = 121 }, 195 { .exti = 15, .irq_parent = 127 }, 196 { .exti = 16, .irq_parent = 1 }, 197 { .exti = 19, .irq_parent = 3 }, 198 { .exti = 21, .irq_parent = 31 }, 199 { .exti = 22, .irq_parent = 33 }, 200 { .exti = 23, .irq_parent = 72 }, 201 { .exti = 24, .irq_parent = 95 }, 202 { .exti = 25, .irq_parent = 107 }, 203 { .exti = 26, .irq_parent = 37 }, 204 { .exti = 27, .irq_parent = 38 }, 205 { .exti = 28, .irq_parent = 39 }, 206 { .exti = 29, .irq_parent = 71 }, 207 { .exti = 30, .irq_parent = 52 }, 208 { .exti = 31, .irq_parent = 53 }, 209 { .exti = 32, .irq_parent = 82 }, 210 { .exti = 33, .irq_parent = 83 }, 211 { .exti = 47, .irq_parent = 93 }, 212 { .exti = 48, .irq_parent = 138 }, 213 { .exti = 50, .irq_parent = 139 }, 214 { .exti = 52, .irq_parent = 140 }, 215 { .exti = 53, .irq_parent = 141 }, 216 { .exti = 54, .irq_parent = 135 }, 217 { .exti = 61, .irq_parent = 100 }, 218 { .exti = 65, .irq_parent = 144 }, 219 { .exti = 68, .irq_parent = 143 }, 220 { .exti = 70, .irq_parent = 62 }, 221 { .exti = 73, .irq_parent = 129 }, 222 }; 223 224 static const struct stm32_desc_irq stm32mp13_desc_irq[] = { 225 { .exti = 0, .irq_parent = 6 }, 226 { .exti = 1, .irq_parent = 7 }, 227 { .exti = 2, .irq_parent = 8 }, 228 { .exti = 3, .irq_parent = 9 }, 229 { .exti = 4, .irq_parent = 10 }, 230 { .exti = 5, .irq_parent = 24 }, 231 { .exti = 6, .irq_parent = 65 }, 232 { .exti = 7, .irq_parent = 66 }, 233 { .exti = 8, .irq_parent = 67 }, 234 { .exti = 9, .irq_parent = 68 }, 235 { .exti = 10, .irq_parent = 41 }, 236 { .exti = 11, .irq_parent = 43 }, 237 { .exti = 12, .irq_parent = 77 }, 238 { .exti = 13, .irq_parent = 78 }, 239 { .exti = 14, .irq_parent = 106 }, 240 { .exti = 15, .irq_parent = 109 }, 241 { .exti = 16, .irq_parent = 1 }, 242 { .exti = 19, .irq_parent = 3 }, 243 { .exti = 21, .irq_parent = 32 }, 244 { .exti = 22, .irq_parent = 34 }, 245 { .exti = 23, .irq_parent = 73 }, 246 { .exti = 24, .irq_parent = 93 }, 247 { .exti = 25, .irq_parent = 114 }, 248 { .exti = 26, .irq_parent = 38 }, 249 { .exti = 27, .irq_parent = 39 }, 250 { .exti = 28, .irq_parent = 40 }, 251 { .exti = 29, .irq_parent = 72 }, 252 { .exti = 30, .irq_parent = 53 }, 253 { .exti = 31, .irq_parent = 54 }, 254 { .exti = 32, .irq_parent = 83 }, 255 { .exti = 33, .irq_parent = 84 }, 256 { .exti = 44, .irq_parent = 96 }, 257 { .exti = 47, .irq_parent = 92 }, 258 { .exti = 48, .irq_parent = 116 }, 259 { .exti = 50, .irq_parent = 117 }, 260 { .exti = 52, .irq_parent = 118 }, 261 { .exti = 53, .irq_parent = 119 }, 262 { .exti = 68, .irq_parent = 63 }, 263 { .exti = 70, .irq_parent = 98 }, 264 }; 265 266 static const struct stm32_exti_drv_data stm32mp1_drv_data = { 267 .exti_banks = stm32mp1_exti_banks, 268 .bank_nr = ARRAY_SIZE(stm32mp1_exti_banks), 269 .desc_irqs = stm32mp1_desc_irq, 270 .irq_nr = ARRAY_SIZE(stm32mp1_desc_irq), 271 }; 272 273 static const struct stm32_exti_drv_data stm32mp13_drv_data = { 274 .exti_banks = stm32mp1_exti_banks, 275 .bank_nr = ARRAY_SIZE(stm32mp1_exti_banks), 276 .desc_irqs = stm32mp13_desc_irq, 277 .irq_nr = ARRAY_SIZE(stm32mp13_desc_irq), 278 }; 279 280 static const struct 281 stm32_desc_irq *stm32_exti_get_desc(const struct stm32_exti_drv_data *drv_data, 282 irq_hw_number_t hwirq) 283 { 284 const struct stm32_desc_irq *desc = NULL; 285 int i; 286 287 if (!drv_data->desc_irqs) 288 return NULL; 289 290 for (i = 0; i < drv_data->irq_nr; i++) { 291 desc = &drv_data->desc_irqs[i]; 292 if (desc->exti == hwirq) 293 break; 294 } 295 296 return desc; 297 } 298 299 static unsigned long stm32_exti_pending(struct irq_chip_generic *gc) 300 { 301 struct stm32_exti_chip_data *chip_data = gc->private; 302 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank; 303 unsigned long pending; 304 305 pending = irq_reg_readl(gc, stm32_bank->rpr_ofst); 306 if (stm32_bank->fpr_ofst != UNDEF_REG) 307 pending |= irq_reg_readl(gc, stm32_bank->fpr_ofst); 308 309 return pending; 310 } 311 312 static void stm32_irq_handler(struct irq_desc *desc) 313 { 314 struct irq_domain *domain = irq_desc_get_handler_data(desc); 315 struct irq_chip *chip = irq_desc_get_chip(desc); 316 unsigned int nbanks = domain->gc->num_chips; 317 struct irq_chip_generic *gc; 318 unsigned long pending; 319 int n, i, irq_base = 0; 320 321 chained_irq_enter(chip, desc); 322 323 for (i = 0; i < nbanks; i++, irq_base += IRQS_PER_BANK) { 324 gc = irq_get_domain_generic_chip(domain, irq_base); 325 326 while ((pending = stm32_exti_pending(gc))) { 327 for_each_set_bit(n, &pending, IRQS_PER_BANK) 328 generic_handle_domain_irq(domain, irq_base + n); 329 } 330 } 331 332 chained_irq_exit(chip, desc); 333 } 334 335 static int stm32_exti_set_type(struct irq_data *d, 336 unsigned int type, u32 *rtsr, u32 *ftsr) 337 { 338 u32 mask = BIT(d->hwirq % IRQS_PER_BANK); 339 340 switch (type) { 341 case IRQ_TYPE_EDGE_RISING: 342 *rtsr |= mask; 343 *ftsr &= ~mask; 344 break; 345 case IRQ_TYPE_EDGE_FALLING: 346 *rtsr &= ~mask; 347 *ftsr |= mask; 348 break; 349 case IRQ_TYPE_EDGE_BOTH: 350 *rtsr |= mask; 351 *ftsr |= mask; 352 break; 353 default: 354 return -EINVAL; 355 } 356 357 return 0; 358 } 359 360 static int stm32_irq_set_type(struct irq_data *d, unsigned int type) 361 { 362 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 363 struct stm32_exti_chip_data *chip_data = gc->private; 364 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank; 365 struct hwspinlock *hwlock = chip_data->host_data->hwlock; 366 u32 rtsr, ftsr; 367 int err; 368 369 irq_gc_lock(gc); 370 371 if (hwlock) { 372 err = hwspin_lock_timeout_in_atomic(hwlock, HWSPNLCK_TIMEOUT); 373 if (err) { 374 pr_err("%s can't get hwspinlock (%d)\n", __func__, err); 375 goto unlock; 376 } 377 } 378 379 rtsr = irq_reg_readl(gc, stm32_bank->rtsr_ofst); 380 ftsr = irq_reg_readl(gc, stm32_bank->ftsr_ofst); 381 382 err = stm32_exti_set_type(d, type, &rtsr, &ftsr); 383 if (err) 384 goto unspinlock; 385 386 irq_reg_writel(gc, rtsr, stm32_bank->rtsr_ofst); 387 irq_reg_writel(gc, ftsr, stm32_bank->ftsr_ofst); 388 389 unspinlock: 390 if (hwlock) 391 hwspin_unlock_in_atomic(hwlock); 392 unlock: 393 irq_gc_unlock(gc); 394 395 return err; 396 } 397 398 static void stm32_chip_suspend(struct stm32_exti_chip_data *chip_data, 399 u32 wake_active) 400 { 401 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank; 402 void __iomem *base = chip_data->host_data->base; 403 404 /* save rtsr, ftsr registers */ 405 chip_data->rtsr_cache = readl_relaxed(base + stm32_bank->rtsr_ofst); 406 chip_data->ftsr_cache = readl_relaxed(base + stm32_bank->ftsr_ofst); 407 408 writel_relaxed(wake_active, base + stm32_bank->imr_ofst); 409 } 410 411 static void stm32_chip_resume(struct stm32_exti_chip_data *chip_data, 412 u32 mask_cache) 413 { 414 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank; 415 void __iomem *base = chip_data->host_data->base; 416 417 /* restore rtsr, ftsr, registers */ 418 writel_relaxed(chip_data->rtsr_cache, base + stm32_bank->rtsr_ofst); 419 writel_relaxed(chip_data->ftsr_cache, base + stm32_bank->ftsr_ofst); 420 421 writel_relaxed(mask_cache, base + stm32_bank->imr_ofst); 422 } 423 424 static void stm32_irq_suspend(struct irq_chip_generic *gc) 425 { 426 struct stm32_exti_chip_data *chip_data = gc->private; 427 428 irq_gc_lock(gc); 429 stm32_chip_suspend(chip_data, gc->wake_active); 430 irq_gc_unlock(gc); 431 } 432 433 static void stm32_irq_resume(struct irq_chip_generic *gc) 434 { 435 struct stm32_exti_chip_data *chip_data = gc->private; 436 437 irq_gc_lock(gc); 438 stm32_chip_resume(chip_data, gc->mask_cache); 439 irq_gc_unlock(gc); 440 } 441 442 static int stm32_exti_alloc(struct irq_domain *d, unsigned int virq, 443 unsigned int nr_irqs, void *data) 444 { 445 struct irq_fwspec *fwspec = data; 446 irq_hw_number_t hwirq; 447 448 hwirq = fwspec->param[0]; 449 450 irq_map_generic_chip(d, virq, hwirq); 451 452 return 0; 453 } 454 455 static void stm32_exti_free(struct irq_domain *d, unsigned int virq, 456 unsigned int nr_irqs) 457 { 458 struct irq_data *data = irq_domain_get_irq_data(d, virq); 459 460 irq_domain_reset_irq_data(data); 461 } 462 463 static const struct irq_domain_ops irq_exti_domain_ops = { 464 .map = irq_map_generic_chip, 465 .alloc = stm32_exti_alloc, 466 .free = stm32_exti_free, 467 }; 468 469 static void stm32_irq_ack(struct irq_data *d) 470 { 471 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 472 struct stm32_exti_chip_data *chip_data = gc->private; 473 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank; 474 475 irq_gc_lock(gc); 476 477 irq_reg_writel(gc, d->mask, stm32_bank->rpr_ofst); 478 if (stm32_bank->fpr_ofst != UNDEF_REG) 479 irq_reg_writel(gc, d->mask, stm32_bank->fpr_ofst); 480 481 irq_gc_unlock(gc); 482 } 483 484 /* directly set the target bit without reading first. */ 485 static inline void stm32_exti_write_bit(struct irq_data *d, u32 reg) 486 { 487 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d); 488 void __iomem *base = chip_data->host_data->base; 489 u32 val = BIT(d->hwirq % IRQS_PER_BANK); 490 491 writel_relaxed(val, base + reg); 492 } 493 494 static inline u32 stm32_exti_set_bit(struct irq_data *d, u32 reg) 495 { 496 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d); 497 void __iomem *base = chip_data->host_data->base; 498 u32 val; 499 500 val = readl_relaxed(base + reg); 501 val |= BIT(d->hwirq % IRQS_PER_BANK); 502 writel_relaxed(val, base + reg); 503 504 return val; 505 } 506 507 static inline u32 stm32_exti_clr_bit(struct irq_data *d, u32 reg) 508 { 509 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d); 510 void __iomem *base = chip_data->host_data->base; 511 u32 val; 512 513 val = readl_relaxed(base + reg); 514 val &= ~BIT(d->hwirq % IRQS_PER_BANK); 515 writel_relaxed(val, base + reg); 516 517 return val; 518 } 519 520 static void stm32_exti_h_eoi(struct irq_data *d) 521 { 522 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d); 523 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank; 524 525 raw_spin_lock(&chip_data->rlock); 526 527 stm32_exti_write_bit(d, stm32_bank->rpr_ofst); 528 if (stm32_bank->fpr_ofst != UNDEF_REG) 529 stm32_exti_write_bit(d, stm32_bank->fpr_ofst); 530 531 raw_spin_unlock(&chip_data->rlock); 532 533 if (d->parent_data->chip) 534 irq_chip_eoi_parent(d); 535 } 536 537 static void stm32_exti_h_mask(struct irq_data *d) 538 { 539 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d); 540 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank; 541 542 raw_spin_lock(&chip_data->rlock); 543 chip_data->mask_cache = stm32_exti_clr_bit(d, stm32_bank->imr_ofst); 544 raw_spin_unlock(&chip_data->rlock); 545 546 if (d->parent_data->chip) 547 irq_chip_mask_parent(d); 548 } 549 550 static void stm32_exti_h_unmask(struct irq_data *d) 551 { 552 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d); 553 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank; 554 555 raw_spin_lock(&chip_data->rlock); 556 chip_data->mask_cache = stm32_exti_set_bit(d, stm32_bank->imr_ofst); 557 raw_spin_unlock(&chip_data->rlock); 558 559 if (d->parent_data->chip) 560 irq_chip_unmask_parent(d); 561 } 562 563 static int stm32_exti_h_set_type(struct irq_data *d, unsigned int type) 564 { 565 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d); 566 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank; 567 struct hwspinlock *hwlock = chip_data->host_data->hwlock; 568 void __iomem *base = chip_data->host_data->base; 569 u32 rtsr, ftsr; 570 int err; 571 572 raw_spin_lock(&chip_data->rlock); 573 574 if (hwlock) { 575 err = hwspin_lock_timeout_in_atomic(hwlock, HWSPNLCK_TIMEOUT); 576 if (err) { 577 pr_err("%s can't get hwspinlock (%d)\n", __func__, err); 578 goto unlock; 579 } 580 } 581 582 rtsr = readl_relaxed(base + stm32_bank->rtsr_ofst); 583 ftsr = readl_relaxed(base + stm32_bank->ftsr_ofst); 584 585 err = stm32_exti_set_type(d, type, &rtsr, &ftsr); 586 if (err) 587 goto unspinlock; 588 589 writel_relaxed(rtsr, base + stm32_bank->rtsr_ofst); 590 writel_relaxed(ftsr, base + stm32_bank->ftsr_ofst); 591 592 unspinlock: 593 if (hwlock) 594 hwspin_unlock_in_atomic(hwlock); 595 unlock: 596 raw_spin_unlock(&chip_data->rlock); 597 598 return err; 599 } 600 601 static int stm32_exti_h_set_wake(struct irq_data *d, unsigned int on) 602 { 603 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d); 604 u32 mask = BIT(d->hwirq % IRQS_PER_BANK); 605 606 raw_spin_lock(&chip_data->rlock); 607 608 if (on) 609 chip_data->wake_active |= mask; 610 else 611 chip_data->wake_active &= ~mask; 612 613 raw_spin_unlock(&chip_data->rlock); 614 615 return 0; 616 } 617 618 static int stm32_exti_h_set_affinity(struct irq_data *d, 619 const struct cpumask *dest, bool force) 620 { 621 if (d->parent_data->chip) 622 return irq_chip_set_affinity_parent(d, dest, force); 623 624 return IRQ_SET_MASK_OK_DONE; 625 } 626 627 static int __maybe_unused stm32_exti_h_suspend(void) 628 { 629 struct stm32_exti_chip_data *chip_data; 630 int i; 631 632 for (i = 0; i < stm32_host_data->drv_data->bank_nr; i++) { 633 chip_data = &stm32_host_data->chips_data[i]; 634 raw_spin_lock(&chip_data->rlock); 635 stm32_chip_suspend(chip_data, chip_data->wake_active); 636 raw_spin_unlock(&chip_data->rlock); 637 } 638 639 return 0; 640 } 641 642 static void __maybe_unused stm32_exti_h_resume(void) 643 { 644 struct stm32_exti_chip_data *chip_data; 645 int i; 646 647 for (i = 0; i < stm32_host_data->drv_data->bank_nr; i++) { 648 chip_data = &stm32_host_data->chips_data[i]; 649 raw_spin_lock(&chip_data->rlock); 650 stm32_chip_resume(chip_data, chip_data->mask_cache); 651 raw_spin_unlock(&chip_data->rlock); 652 } 653 } 654 655 static struct syscore_ops stm32_exti_h_syscore_ops = { 656 #ifdef CONFIG_PM_SLEEP 657 .suspend = stm32_exti_h_suspend, 658 .resume = stm32_exti_h_resume, 659 #endif 660 }; 661 662 static void stm32_exti_h_syscore_init(struct stm32_exti_host_data *host_data) 663 { 664 stm32_host_data = host_data; 665 register_syscore_ops(&stm32_exti_h_syscore_ops); 666 } 667 668 static void stm32_exti_h_syscore_deinit(void) 669 { 670 unregister_syscore_ops(&stm32_exti_h_syscore_ops); 671 } 672 673 static int stm32_exti_h_retrigger(struct irq_data *d) 674 { 675 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d); 676 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank; 677 void __iomem *base = chip_data->host_data->base; 678 u32 mask = BIT(d->hwirq % IRQS_PER_BANK); 679 680 writel_relaxed(mask, base + stm32_bank->swier_ofst); 681 682 return 0; 683 } 684 685 static struct irq_chip stm32_exti_h_chip = { 686 .name = "stm32-exti-h", 687 .irq_eoi = stm32_exti_h_eoi, 688 .irq_mask = stm32_exti_h_mask, 689 .irq_unmask = stm32_exti_h_unmask, 690 .irq_retrigger = stm32_exti_h_retrigger, 691 .irq_set_type = stm32_exti_h_set_type, 692 .irq_set_wake = stm32_exti_h_set_wake, 693 .flags = IRQCHIP_MASK_ON_SUSPEND, 694 .irq_set_affinity = IS_ENABLED(CONFIG_SMP) ? stm32_exti_h_set_affinity : NULL, 695 }; 696 697 static struct irq_chip stm32_exti_h_chip_direct = { 698 .name = "stm32-exti-h-direct", 699 .irq_eoi = irq_chip_eoi_parent, 700 .irq_ack = irq_chip_ack_parent, 701 .irq_mask = stm32_exti_h_mask, 702 .irq_unmask = stm32_exti_h_unmask, 703 .irq_retrigger = irq_chip_retrigger_hierarchy, 704 .irq_set_type = irq_chip_set_type_parent, 705 .irq_set_wake = stm32_exti_h_set_wake, 706 .flags = IRQCHIP_MASK_ON_SUSPEND, 707 .irq_set_affinity = IS_ENABLED(CONFIG_SMP) ? irq_chip_set_affinity_parent : NULL, 708 }; 709 710 static int stm32_exti_h_domain_alloc(struct irq_domain *dm, 711 unsigned int virq, 712 unsigned int nr_irqs, void *data) 713 { 714 struct stm32_exti_host_data *host_data = dm->host_data; 715 struct stm32_exti_chip_data *chip_data; 716 const struct stm32_desc_irq *desc; 717 struct irq_fwspec *fwspec = data; 718 struct irq_fwspec p_fwspec; 719 irq_hw_number_t hwirq; 720 int bank; 721 u32 event_trg; 722 struct irq_chip *chip; 723 724 hwirq = fwspec->param[0]; 725 if (hwirq >= host_data->drv_data->bank_nr * IRQS_PER_BANK) 726 return -EINVAL; 727 728 bank = hwirq / IRQS_PER_BANK; 729 chip_data = &host_data->chips_data[bank]; 730 731 732 desc = stm32_exti_get_desc(host_data->drv_data, hwirq); 733 if (!desc) 734 return -EINVAL; 735 736 event_trg = readl_relaxed(host_data->base + chip_data->reg_bank->trg_ofst); 737 chip = (event_trg & BIT(hwirq % IRQS_PER_BANK)) ? 738 &stm32_exti_h_chip : &stm32_exti_h_chip_direct; 739 740 irq_domain_set_hwirq_and_chip(dm, virq, hwirq, chip, chip_data); 741 if (desc->irq_parent) { 742 p_fwspec.fwnode = dm->parent->fwnode; 743 p_fwspec.param_count = 3; 744 p_fwspec.param[0] = GIC_SPI; 745 p_fwspec.param[1] = desc->irq_parent; 746 p_fwspec.param[2] = IRQ_TYPE_LEVEL_HIGH; 747 748 return irq_domain_alloc_irqs_parent(dm, virq, 1, &p_fwspec); 749 } 750 751 return 0; 752 } 753 754 static struct 755 stm32_exti_host_data *stm32_exti_host_init(const struct stm32_exti_drv_data *dd, 756 struct device_node *node) 757 { 758 struct stm32_exti_host_data *host_data; 759 760 host_data = kzalloc(sizeof(*host_data), GFP_KERNEL); 761 if (!host_data) 762 return NULL; 763 764 host_data->drv_data = dd; 765 host_data->chips_data = kcalloc(dd->bank_nr, 766 sizeof(struct stm32_exti_chip_data), 767 GFP_KERNEL); 768 if (!host_data->chips_data) 769 goto free_host_data; 770 771 host_data->base = of_iomap(node, 0); 772 if (!host_data->base) { 773 pr_err("%pOF: Unable to map registers\n", node); 774 goto free_chips_data; 775 } 776 777 stm32_host_data = host_data; 778 779 return host_data; 780 781 free_chips_data: 782 kfree(host_data->chips_data); 783 free_host_data: 784 kfree(host_data); 785 786 return NULL; 787 } 788 789 static struct 790 stm32_exti_chip_data *stm32_exti_chip_init(struct stm32_exti_host_data *h_data, 791 u32 bank_idx, 792 struct device_node *node) 793 { 794 const struct stm32_exti_bank *stm32_bank; 795 struct stm32_exti_chip_data *chip_data; 796 void __iomem *base = h_data->base; 797 798 stm32_bank = h_data->drv_data->exti_banks[bank_idx]; 799 chip_data = &h_data->chips_data[bank_idx]; 800 chip_data->host_data = h_data; 801 chip_data->reg_bank = stm32_bank; 802 803 raw_spin_lock_init(&chip_data->rlock); 804 805 /* 806 * This IP has no reset, so after hot reboot we should 807 * clear registers to avoid residue 808 */ 809 writel_relaxed(0, base + stm32_bank->imr_ofst); 810 if (stm32_bank->emr_ofst != UNDEF_REG) 811 writel_relaxed(0, base + stm32_bank->emr_ofst); 812 813 pr_info("%pOF: bank%d\n", node, bank_idx); 814 815 return chip_data; 816 } 817 818 static int __init stm32_exti_init(const struct stm32_exti_drv_data *drv_data, 819 struct device_node *node) 820 { 821 struct stm32_exti_host_data *host_data; 822 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; 823 int nr_irqs, ret, i; 824 struct irq_chip_generic *gc; 825 struct irq_domain *domain; 826 827 host_data = stm32_exti_host_init(drv_data, node); 828 if (!host_data) 829 return -ENOMEM; 830 831 domain = irq_domain_add_linear(node, drv_data->bank_nr * IRQS_PER_BANK, 832 &irq_exti_domain_ops, NULL); 833 if (!domain) { 834 pr_err("%pOFn: Could not register interrupt domain.\n", 835 node); 836 ret = -ENOMEM; 837 goto out_unmap; 838 } 839 840 ret = irq_alloc_domain_generic_chips(domain, IRQS_PER_BANK, 1, "exti", 841 handle_edge_irq, clr, 0, 0); 842 if (ret) { 843 pr_err("%pOF: Could not allocate generic interrupt chip.\n", 844 node); 845 goto out_free_domain; 846 } 847 848 for (i = 0; i < drv_data->bank_nr; i++) { 849 const struct stm32_exti_bank *stm32_bank; 850 struct stm32_exti_chip_data *chip_data; 851 852 stm32_bank = drv_data->exti_banks[i]; 853 chip_data = stm32_exti_chip_init(host_data, i, node); 854 855 gc = irq_get_domain_generic_chip(domain, i * IRQS_PER_BANK); 856 857 gc->reg_base = host_data->base; 858 gc->chip_types->type = IRQ_TYPE_EDGE_BOTH; 859 gc->chip_types->chip.irq_ack = stm32_irq_ack; 860 gc->chip_types->chip.irq_mask = irq_gc_mask_clr_bit; 861 gc->chip_types->chip.irq_unmask = irq_gc_mask_set_bit; 862 gc->chip_types->chip.irq_set_type = stm32_irq_set_type; 863 gc->chip_types->chip.irq_set_wake = irq_gc_set_wake; 864 gc->suspend = stm32_irq_suspend; 865 gc->resume = stm32_irq_resume; 866 gc->wake_enabled = IRQ_MSK(IRQS_PER_BANK); 867 868 gc->chip_types->regs.mask = stm32_bank->imr_ofst; 869 gc->private = (void *)chip_data; 870 } 871 872 nr_irqs = of_irq_count(node); 873 for (i = 0; i < nr_irqs; i++) { 874 unsigned int irq = irq_of_parse_and_map(node, i); 875 876 irq_set_handler_data(irq, domain); 877 irq_set_chained_handler(irq, stm32_irq_handler); 878 } 879 880 return 0; 881 882 out_free_domain: 883 irq_domain_remove(domain); 884 out_unmap: 885 iounmap(host_data->base); 886 kfree(host_data->chips_data); 887 kfree(host_data); 888 return ret; 889 } 890 891 static const struct irq_domain_ops stm32_exti_h_domain_ops = { 892 .alloc = stm32_exti_h_domain_alloc, 893 .free = irq_domain_free_irqs_common, 894 .xlate = irq_domain_xlate_twocell, 895 }; 896 897 static void stm32_exti_remove_irq(void *data) 898 { 899 struct irq_domain *domain = data; 900 901 irq_domain_remove(domain); 902 } 903 904 static int stm32_exti_remove(struct platform_device *pdev) 905 { 906 stm32_exti_h_syscore_deinit(); 907 return 0; 908 } 909 910 static int stm32_exti_probe(struct platform_device *pdev) 911 { 912 int ret, i; 913 struct device *dev = &pdev->dev; 914 struct device_node *np = dev->of_node; 915 struct irq_domain *parent_domain, *domain; 916 struct stm32_exti_host_data *host_data; 917 const struct stm32_exti_drv_data *drv_data; 918 919 host_data = devm_kzalloc(dev, sizeof(*host_data), GFP_KERNEL); 920 if (!host_data) 921 return -ENOMEM; 922 923 /* check for optional hwspinlock which may be not available yet */ 924 ret = of_hwspin_lock_get_id(np, 0); 925 if (ret == -EPROBE_DEFER) 926 /* hwspinlock framework not yet ready */ 927 return ret; 928 929 if (ret >= 0) { 930 host_data->hwlock = devm_hwspin_lock_request_specific(dev, ret); 931 if (!host_data->hwlock) { 932 dev_err(dev, "Failed to request hwspinlock\n"); 933 return -EINVAL; 934 } 935 } else if (ret != -ENOENT) { 936 /* note: ENOENT is a valid case (means 'no hwspinlock') */ 937 dev_err(dev, "Failed to get hwspinlock\n"); 938 return ret; 939 } 940 941 /* initialize host_data */ 942 drv_data = of_device_get_match_data(dev); 943 if (!drv_data) { 944 dev_err(dev, "no of match data\n"); 945 return -ENODEV; 946 } 947 host_data->drv_data = drv_data; 948 949 host_data->chips_data = devm_kcalloc(dev, drv_data->bank_nr, 950 sizeof(*host_data->chips_data), 951 GFP_KERNEL); 952 if (!host_data->chips_data) 953 return -ENOMEM; 954 955 host_data->base = devm_platform_ioremap_resource(pdev, 0); 956 if (IS_ERR(host_data->base)) 957 return PTR_ERR(host_data->base); 958 959 for (i = 0; i < drv_data->bank_nr; i++) 960 stm32_exti_chip_init(host_data, i, np); 961 962 parent_domain = irq_find_host(of_irq_find_parent(np)); 963 if (!parent_domain) { 964 dev_err(dev, "GIC interrupt-parent not found\n"); 965 return -EINVAL; 966 } 967 968 domain = irq_domain_add_hierarchy(parent_domain, 0, 969 drv_data->bank_nr * IRQS_PER_BANK, 970 np, &stm32_exti_h_domain_ops, 971 host_data); 972 973 if (!domain) { 974 dev_err(dev, "Could not register exti domain\n"); 975 return -ENOMEM; 976 } 977 978 ret = devm_add_action_or_reset(dev, stm32_exti_remove_irq, domain); 979 if (ret) 980 return ret; 981 982 stm32_exti_h_syscore_init(host_data); 983 984 return 0; 985 } 986 987 /* platform driver only for MP1 */ 988 static const struct of_device_id stm32_exti_ids[] = { 989 { .compatible = "st,stm32mp1-exti", .data = &stm32mp1_drv_data}, 990 { .compatible = "st,stm32mp13-exti", .data = &stm32mp13_drv_data}, 991 {}, 992 }; 993 MODULE_DEVICE_TABLE(of, stm32_exti_ids); 994 995 static struct platform_driver stm32_exti_driver = { 996 .probe = stm32_exti_probe, 997 .remove = stm32_exti_remove, 998 .driver = { 999 .name = "stm32_exti", 1000 .of_match_table = stm32_exti_ids, 1001 }, 1002 }; 1003 1004 static int __init stm32_exti_arch_init(void) 1005 { 1006 return platform_driver_register(&stm32_exti_driver); 1007 } 1008 1009 static void __exit stm32_exti_arch_exit(void) 1010 { 1011 return platform_driver_unregister(&stm32_exti_driver); 1012 } 1013 1014 arch_initcall(stm32_exti_arch_init); 1015 module_exit(stm32_exti_arch_exit); 1016 1017 /* no platform driver for F4 and H7 */ 1018 static int __init stm32f4_exti_of_init(struct device_node *np, 1019 struct device_node *parent) 1020 { 1021 return stm32_exti_init(&stm32f4xx_drv_data, np); 1022 } 1023 1024 IRQCHIP_DECLARE(stm32f4_exti, "st,stm32-exti", stm32f4_exti_of_init); 1025 1026 static int __init stm32h7_exti_of_init(struct device_node *np, 1027 struct device_node *parent) 1028 { 1029 return stm32_exti_init(&stm32h7xx_drv_data, np); 1030 } 1031 1032 IRQCHIP_DECLARE(stm32h7_exti, "st,stm32h7-exti", stm32h7_exti_of_init); 1033