1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) Maxime Coquelin 2015 4 * Copyright (C) STMicroelectronics 2017 5 * Author: Maxime Coquelin <mcoquelin.stm32@gmail.com> 6 */ 7 8 #include <linux/bitops.h> 9 #include <linux/delay.h> 10 #include <linux/hwspinlock.h> 11 #include <linux/interrupt.h> 12 #include <linux/io.h> 13 #include <linux/irq.h> 14 #include <linux/irqchip.h> 15 #include <linux/irqchip/chained_irq.h> 16 #include <linux/irqdomain.h> 17 #include <linux/module.h> 18 #include <linux/of_address.h> 19 #include <linux/of_irq.h> 20 #include <linux/of_platform.h> 21 #include <linux/syscore_ops.h> 22 23 #include <dt-bindings/interrupt-controller/arm-gic.h> 24 25 #define IRQS_PER_BANK 32 26 27 #define HWSPNLCK_TIMEOUT 1000 /* usec */ 28 29 struct stm32_exti_bank { 30 u32 imr_ofst; 31 u32 emr_ofst; 32 u32 rtsr_ofst; 33 u32 ftsr_ofst; 34 u32 swier_ofst; 35 u32 rpr_ofst; 36 u32 fpr_ofst; 37 }; 38 39 #define UNDEF_REG ~0 40 41 struct stm32_desc_irq { 42 u32 exti; 43 u32 irq_parent; 44 struct irq_chip *chip; 45 }; 46 47 struct stm32_exti_drv_data { 48 const struct stm32_exti_bank **exti_banks; 49 const struct stm32_desc_irq *desc_irqs; 50 u32 bank_nr; 51 u32 irq_nr; 52 }; 53 54 struct stm32_exti_chip_data { 55 struct stm32_exti_host_data *host_data; 56 const struct stm32_exti_bank *reg_bank; 57 struct raw_spinlock rlock; 58 u32 wake_active; 59 u32 mask_cache; 60 u32 rtsr_cache; 61 u32 ftsr_cache; 62 }; 63 64 struct stm32_exti_host_data { 65 void __iomem *base; 66 struct stm32_exti_chip_data *chips_data; 67 const struct stm32_exti_drv_data *drv_data; 68 struct hwspinlock *hwlock; 69 }; 70 71 static struct stm32_exti_host_data *stm32_host_data; 72 73 static const struct stm32_exti_bank stm32f4xx_exti_b1 = { 74 .imr_ofst = 0x00, 75 .emr_ofst = 0x04, 76 .rtsr_ofst = 0x08, 77 .ftsr_ofst = 0x0C, 78 .swier_ofst = 0x10, 79 .rpr_ofst = 0x14, 80 .fpr_ofst = UNDEF_REG, 81 }; 82 83 static const struct stm32_exti_bank *stm32f4xx_exti_banks[] = { 84 &stm32f4xx_exti_b1, 85 }; 86 87 static const struct stm32_exti_drv_data stm32f4xx_drv_data = { 88 .exti_banks = stm32f4xx_exti_banks, 89 .bank_nr = ARRAY_SIZE(stm32f4xx_exti_banks), 90 }; 91 92 static const struct stm32_exti_bank stm32h7xx_exti_b1 = { 93 .imr_ofst = 0x80, 94 .emr_ofst = 0x84, 95 .rtsr_ofst = 0x00, 96 .ftsr_ofst = 0x04, 97 .swier_ofst = 0x08, 98 .rpr_ofst = 0x88, 99 .fpr_ofst = UNDEF_REG, 100 }; 101 102 static const struct stm32_exti_bank stm32h7xx_exti_b2 = { 103 .imr_ofst = 0x90, 104 .emr_ofst = 0x94, 105 .rtsr_ofst = 0x20, 106 .ftsr_ofst = 0x24, 107 .swier_ofst = 0x28, 108 .rpr_ofst = 0x98, 109 .fpr_ofst = UNDEF_REG, 110 }; 111 112 static const struct stm32_exti_bank stm32h7xx_exti_b3 = { 113 .imr_ofst = 0xA0, 114 .emr_ofst = 0xA4, 115 .rtsr_ofst = 0x40, 116 .ftsr_ofst = 0x44, 117 .swier_ofst = 0x48, 118 .rpr_ofst = 0xA8, 119 .fpr_ofst = UNDEF_REG, 120 }; 121 122 static const struct stm32_exti_bank *stm32h7xx_exti_banks[] = { 123 &stm32h7xx_exti_b1, 124 &stm32h7xx_exti_b2, 125 &stm32h7xx_exti_b3, 126 }; 127 128 static const struct stm32_exti_drv_data stm32h7xx_drv_data = { 129 .exti_banks = stm32h7xx_exti_banks, 130 .bank_nr = ARRAY_SIZE(stm32h7xx_exti_banks), 131 }; 132 133 static const struct stm32_exti_bank stm32mp1_exti_b1 = { 134 .imr_ofst = 0x80, 135 .emr_ofst = 0x84, 136 .rtsr_ofst = 0x00, 137 .ftsr_ofst = 0x04, 138 .swier_ofst = 0x08, 139 .rpr_ofst = 0x0C, 140 .fpr_ofst = 0x10, 141 }; 142 143 static const struct stm32_exti_bank stm32mp1_exti_b2 = { 144 .imr_ofst = 0x90, 145 .emr_ofst = 0x94, 146 .rtsr_ofst = 0x20, 147 .ftsr_ofst = 0x24, 148 .swier_ofst = 0x28, 149 .rpr_ofst = 0x2C, 150 .fpr_ofst = 0x30, 151 }; 152 153 static const struct stm32_exti_bank stm32mp1_exti_b3 = { 154 .imr_ofst = 0xA0, 155 .emr_ofst = 0xA4, 156 .rtsr_ofst = 0x40, 157 .ftsr_ofst = 0x44, 158 .swier_ofst = 0x48, 159 .rpr_ofst = 0x4C, 160 .fpr_ofst = 0x50, 161 }; 162 163 static const struct stm32_exti_bank *stm32mp1_exti_banks[] = { 164 &stm32mp1_exti_b1, 165 &stm32mp1_exti_b2, 166 &stm32mp1_exti_b3, 167 }; 168 169 static struct irq_chip stm32_exti_h_chip; 170 static struct irq_chip stm32_exti_h_chip_direct; 171 172 static const struct stm32_desc_irq stm32mp1_desc_irq[] = { 173 { .exti = 0, .irq_parent = 6, .chip = &stm32_exti_h_chip }, 174 { .exti = 1, .irq_parent = 7, .chip = &stm32_exti_h_chip }, 175 { .exti = 2, .irq_parent = 8, .chip = &stm32_exti_h_chip }, 176 { .exti = 3, .irq_parent = 9, .chip = &stm32_exti_h_chip }, 177 { .exti = 4, .irq_parent = 10, .chip = &stm32_exti_h_chip }, 178 { .exti = 5, .irq_parent = 23, .chip = &stm32_exti_h_chip }, 179 { .exti = 6, .irq_parent = 64, .chip = &stm32_exti_h_chip }, 180 { .exti = 7, .irq_parent = 65, .chip = &stm32_exti_h_chip }, 181 { .exti = 8, .irq_parent = 66, .chip = &stm32_exti_h_chip }, 182 { .exti = 9, .irq_parent = 67, .chip = &stm32_exti_h_chip }, 183 { .exti = 10, .irq_parent = 40, .chip = &stm32_exti_h_chip }, 184 { .exti = 11, .irq_parent = 42, .chip = &stm32_exti_h_chip }, 185 { .exti = 12, .irq_parent = 76, .chip = &stm32_exti_h_chip }, 186 { .exti = 13, .irq_parent = 77, .chip = &stm32_exti_h_chip }, 187 { .exti = 14, .irq_parent = 121, .chip = &stm32_exti_h_chip }, 188 { .exti = 15, .irq_parent = 127, .chip = &stm32_exti_h_chip }, 189 { .exti = 16, .irq_parent = 1, .chip = &stm32_exti_h_chip }, 190 { .exti = 19, .irq_parent = 3, .chip = &stm32_exti_h_chip_direct }, 191 { .exti = 21, .irq_parent = 31, .chip = &stm32_exti_h_chip_direct }, 192 { .exti = 22, .irq_parent = 33, .chip = &stm32_exti_h_chip_direct }, 193 { .exti = 23, .irq_parent = 72, .chip = &stm32_exti_h_chip_direct }, 194 { .exti = 24, .irq_parent = 95, .chip = &stm32_exti_h_chip_direct }, 195 { .exti = 25, .irq_parent = 107, .chip = &stm32_exti_h_chip_direct }, 196 { .exti = 26, .irq_parent = 37, .chip = &stm32_exti_h_chip_direct }, 197 { .exti = 27, .irq_parent = 38, .chip = &stm32_exti_h_chip_direct }, 198 { .exti = 28, .irq_parent = 39, .chip = &stm32_exti_h_chip_direct }, 199 { .exti = 29, .irq_parent = 71, .chip = &stm32_exti_h_chip_direct }, 200 { .exti = 30, .irq_parent = 52, .chip = &stm32_exti_h_chip_direct }, 201 { .exti = 31, .irq_parent = 53, .chip = &stm32_exti_h_chip_direct }, 202 { .exti = 32, .irq_parent = 82, .chip = &stm32_exti_h_chip_direct }, 203 { .exti = 33, .irq_parent = 83, .chip = &stm32_exti_h_chip_direct }, 204 { .exti = 47, .irq_parent = 93, .chip = &stm32_exti_h_chip_direct }, 205 { .exti = 48, .irq_parent = 138, .chip = &stm32_exti_h_chip_direct }, 206 { .exti = 50, .irq_parent = 139, .chip = &stm32_exti_h_chip_direct }, 207 { .exti = 52, .irq_parent = 140, .chip = &stm32_exti_h_chip_direct }, 208 { .exti = 53, .irq_parent = 141, .chip = &stm32_exti_h_chip_direct }, 209 { .exti = 54, .irq_parent = 135, .chip = &stm32_exti_h_chip_direct }, 210 { .exti = 61, .irq_parent = 100, .chip = &stm32_exti_h_chip_direct }, 211 { .exti = 65, .irq_parent = 144, .chip = &stm32_exti_h_chip }, 212 { .exti = 68, .irq_parent = 143, .chip = &stm32_exti_h_chip }, 213 { .exti = 70, .irq_parent = 62, .chip = &stm32_exti_h_chip_direct }, 214 { .exti = 73, .irq_parent = 129, .chip = &stm32_exti_h_chip }, 215 }; 216 217 static const struct stm32_exti_drv_data stm32mp1_drv_data = { 218 .exti_banks = stm32mp1_exti_banks, 219 .bank_nr = ARRAY_SIZE(stm32mp1_exti_banks), 220 .desc_irqs = stm32mp1_desc_irq, 221 .irq_nr = ARRAY_SIZE(stm32mp1_desc_irq), 222 }; 223 224 static const struct 225 stm32_desc_irq *stm32_exti_get_desc(const struct stm32_exti_drv_data *drv_data, 226 irq_hw_number_t hwirq) 227 { 228 const struct stm32_desc_irq *desc = NULL; 229 int i; 230 231 if (!drv_data->desc_irqs) 232 return NULL; 233 234 for (i = 0; i < drv_data->irq_nr; i++) { 235 desc = &drv_data->desc_irqs[i]; 236 if (desc->exti == hwirq) 237 break; 238 } 239 240 return desc; 241 } 242 243 static unsigned long stm32_exti_pending(struct irq_chip_generic *gc) 244 { 245 struct stm32_exti_chip_data *chip_data = gc->private; 246 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank; 247 unsigned long pending; 248 249 pending = irq_reg_readl(gc, stm32_bank->rpr_ofst); 250 if (stm32_bank->fpr_ofst != UNDEF_REG) 251 pending |= irq_reg_readl(gc, stm32_bank->fpr_ofst); 252 253 return pending; 254 } 255 256 static void stm32_irq_handler(struct irq_desc *desc) 257 { 258 struct irq_domain *domain = irq_desc_get_handler_data(desc); 259 struct irq_chip *chip = irq_desc_get_chip(desc); 260 unsigned int nbanks = domain->gc->num_chips; 261 struct irq_chip_generic *gc; 262 unsigned long pending; 263 int n, i, irq_base = 0; 264 265 chained_irq_enter(chip, desc); 266 267 for (i = 0; i < nbanks; i++, irq_base += IRQS_PER_BANK) { 268 gc = irq_get_domain_generic_chip(domain, irq_base); 269 270 while ((pending = stm32_exti_pending(gc))) { 271 for_each_set_bit(n, &pending, IRQS_PER_BANK) 272 generic_handle_domain_irq(domain, irq_base + n); 273 } 274 } 275 276 chained_irq_exit(chip, desc); 277 } 278 279 static int stm32_exti_set_type(struct irq_data *d, 280 unsigned int type, u32 *rtsr, u32 *ftsr) 281 { 282 u32 mask = BIT(d->hwirq % IRQS_PER_BANK); 283 284 switch (type) { 285 case IRQ_TYPE_EDGE_RISING: 286 *rtsr |= mask; 287 *ftsr &= ~mask; 288 break; 289 case IRQ_TYPE_EDGE_FALLING: 290 *rtsr &= ~mask; 291 *ftsr |= mask; 292 break; 293 case IRQ_TYPE_EDGE_BOTH: 294 *rtsr |= mask; 295 *ftsr |= mask; 296 break; 297 default: 298 return -EINVAL; 299 } 300 301 return 0; 302 } 303 304 static int stm32_irq_set_type(struct irq_data *d, unsigned int type) 305 { 306 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 307 struct stm32_exti_chip_data *chip_data = gc->private; 308 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank; 309 struct hwspinlock *hwlock = chip_data->host_data->hwlock; 310 u32 rtsr, ftsr; 311 int err; 312 313 irq_gc_lock(gc); 314 315 if (hwlock) { 316 err = hwspin_lock_timeout_in_atomic(hwlock, HWSPNLCK_TIMEOUT); 317 if (err) { 318 pr_err("%s can't get hwspinlock (%d)\n", __func__, err); 319 goto unlock; 320 } 321 } 322 323 rtsr = irq_reg_readl(gc, stm32_bank->rtsr_ofst); 324 ftsr = irq_reg_readl(gc, stm32_bank->ftsr_ofst); 325 326 err = stm32_exti_set_type(d, type, &rtsr, &ftsr); 327 if (err) 328 goto unspinlock; 329 330 irq_reg_writel(gc, rtsr, stm32_bank->rtsr_ofst); 331 irq_reg_writel(gc, ftsr, stm32_bank->ftsr_ofst); 332 333 unspinlock: 334 if (hwlock) 335 hwspin_unlock_in_atomic(hwlock); 336 unlock: 337 irq_gc_unlock(gc); 338 339 return err; 340 } 341 342 static void stm32_chip_suspend(struct stm32_exti_chip_data *chip_data, 343 u32 wake_active) 344 { 345 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank; 346 void __iomem *base = chip_data->host_data->base; 347 348 /* save rtsr, ftsr registers */ 349 chip_data->rtsr_cache = readl_relaxed(base + stm32_bank->rtsr_ofst); 350 chip_data->ftsr_cache = readl_relaxed(base + stm32_bank->ftsr_ofst); 351 352 writel_relaxed(wake_active, base + stm32_bank->imr_ofst); 353 } 354 355 static void stm32_chip_resume(struct stm32_exti_chip_data *chip_data, 356 u32 mask_cache) 357 { 358 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank; 359 void __iomem *base = chip_data->host_data->base; 360 361 /* restore rtsr, ftsr, registers */ 362 writel_relaxed(chip_data->rtsr_cache, base + stm32_bank->rtsr_ofst); 363 writel_relaxed(chip_data->ftsr_cache, base + stm32_bank->ftsr_ofst); 364 365 writel_relaxed(mask_cache, base + stm32_bank->imr_ofst); 366 } 367 368 static void stm32_irq_suspend(struct irq_chip_generic *gc) 369 { 370 struct stm32_exti_chip_data *chip_data = gc->private; 371 372 irq_gc_lock(gc); 373 stm32_chip_suspend(chip_data, gc->wake_active); 374 irq_gc_unlock(gc); 375 } 376 377 static void stm32_irq_resume(struct irq_chip_generic *gc) 378 { 379 struct stm32_exti_chip_data *chip_data = gc->private; 380 381 irq_gc_lock(gc); 382 stm32_chip_resume(chip_data, gc->mask_cache); 383 irq_gc_unlock(gc); 384 } 385 386 static int stm32_exti_alloc(struct irq_domain *d, unsigned int virq, 387 unsigned int nr_irqs, void *data) 388 { 389 struct irq_fwspec *fwspec = data; 390 irq_hw_number_t hwirq; 391 392 hwirq = fwspec->param[0]; 393 394 irq_map_generic_chip(d, virq, hwirq); 395 396 return 0; 397 } 398 399 static void stm32_exti_free(struct irq_domain *d, unsigned int virq, 400 unsigned int nr_irqs) 401 { 402 struct irq_data *data = irq_domain_get_irq_data(d, virq); 403 404 irq_domain_reset_irq_data(data); 405 } 406 407 static const struct irq_domain_ops irq_exti_domain_ops = { 408 .map = irq_map_generic_chip, 409 .alloc = stm32_exti_alloc, 410 .free = stm32_exti_free, 411 }; 412 413 static void stm32_irq_ack(struct irq_data *d) 414 { 415 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 416 struct stm32_exti_chip_data *chip_data = gc->private; 417 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank; 418 419 irq_gc_lock(gc); 420 421 irq_reg_writel(gc, d->mask, stm32_bank->rpr_ofst); 422 if (stm32_bank->fpr_ofst != UNDEF_REG) 423 irq_reg_writel(gc, d->mask, stm32_bank->fpr_ofst); 424 425 irq_gc_unlock(gc); 426 } 427 428 /* directly set the target bit without reading first. */ 429 static inline void stm32_exti_write_bit(struct irq_data *d, u32 reg) 430 { 431 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d); 432 void __iomem *base = chip_data->host_data->base; 433 u32 val = BIT(d->hwirq % IRQS_PER_BANK); 434 435 writel_relaxed(val, base + reg); 436 } 437 438 static inline u32 stm32_exti_set_bit(struct irq_data *d, u32 reg) 439 { 440 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d); 441 void __iomem *base = chip_data->host_data->base; 442 u32 val; 443 444 val = readl_relaxed(base + reg); 445 val |= BIT(d->hwirq % IRQS_PER_BANK); 446 writel_relaxed(val, base + reg); 447 448 return val; 449 } 450 451 static inline u32 stm32_exti_clr_bit(struct irq_data *d, u32 reg) 452 { 453 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d); 454 void __iomem *base = chip_data->host_data->base; 455 u32 val; 456 457 val = readl_relaxed(base + reg); 458 val &= ~BIT(d->hwirq % IRQS_PER_BANK); 459 writel_relaxed(val, base + reg); 460 461 return val; 462 } 463 464 static void stm32_exti_h_eoi(struct irq_data *d) 465 { 466 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d); 467 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank; 468 469 raw_spin_lock(&chip_data->rlock); 470 471 stm32_exti_write_bit(d, stm32_bank->rpr_ofst); 472 if (stm32_bank->fpr_ofst != UNDEF_REG) 473 stm32_exti_write_bit(d, stm32_bank->fpr_ofst); 474 475 raw_spin_unlock(&chip_data->rlock); 476 477 if (d->parent_data->chip) 478 irq_chip_eoi_parent(d); 479 } 480 481 static void stm32_exti_h_mask(struct irq_data *d) 482 { 483 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d); 484 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank; 485 486 raw_spin_lock(&chip_data->rlock); 487 chip_data->mask_cache = stm32_exti_clr_bit(d, stm32_bank->imr_ofst); 488 raw_spin_unlock(&chip_data->rlock); 489 490 if (d->parent_data->chip) 491 irq_chip_mask_parent(d); 492 } 493 494 static void stm32_exti_h_unmask(struct irq_data *d) 495 { 496 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d); 497 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank; 498 499 raw_spin_lock(&chip_data->rlock); 500 chip_data->mask_cache = stm32_exti_set_bit(d, stm32_bank->imr_ofst); 501 raw_spin_unlock(&chip_data->rlock); 502 503 if (d->parent_data->chip) 504 irq_chip_unmask_parent(d); 505 } 506 507 static int stm32_exti_h_set_type(struct irq_data *d, unsigned int type) 508 { 509 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d); 510 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank; 511 struct hwspinlock *hwlock = chip_data->host_data->hwlock; 512 void __iomem *base = chip_data->host_data->base; 513 u32 rtsr, ftsr; 514 int err; 515 516 raw_spin_lock(&chip_data->rlock); 517 518 if (hwlock) { 519 err = hwspin_lock_timeout_in_atomic(hwlock, HWSPNLCK_TIMEOUT); 520 if (err) { 521 pr_err("%s can't get hwspinlock (%d)\n", __func__, err); 522 goto unlock; 523 } 524 } 525 526 rtsr = readl_relaxed(base + stm32_bank->rtsr_ofst); 527 ftsr = readl_relaxed(base + stm32_bank->ftsr_ofst); 528 529 err = stm32_exti_set_type(d, type, &rtsr, &ftsr); 530 if (err) 531 goto unspinlock; 532 533 writel_relaxed(rtsr, base + stm32_bank->rtsr_ofst); 534 writel_relaxed(ftsr, base + stm32_bank->ftsr_ofst); 535 536 unspinlock: 537 if (hwlock) 538 hwspin_unlock_in_atomic(hwlock); 539 unlock: 540 raw_spin_unlock(&chip_data->rlock); 541 542 return err; 543 } 544 545 static int stm32_exti_h_set_wake(struct irq_data *d, unsigned int on) 546 { 547 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d); 548 u32 mask = BIT(d->hwirq % IRQS_PER_BANK); 549 550 raw_spin_lock(&chip_data->rlock); 551 552 if (on) 553 chip_data->wake_active |= mask; 554 else 555 chip_data->wake_active &= ~mask; 556 557 raw_spin_unlock(&chip_data->rlock); 558 559 return 0; 560 } 561 562 static int stm32_exti_h_set_affinity(struct irq_data *d, 563 const struct cpumask *dest, bool force) 564 { 565 if (d->parent_data->chip) 566 return irq_chip_set_affinity_parent(d, dest, force); 567 568 return -EINVAL; 569 } 570 571 static int __maybe_unused stm32_exti_h_suspend(void) 572 { 573 struct stm32_exti_chip_data *chip_data; 574 int i; 575 576 for (i = 0; i < stm32_host_data->drv_data->bank_nr; i++) { 577 chip_data = &stm32_host_data->chips_data[i]; 578 raw_spin_lock(&chip_data->rlock); 579 stm32_chip_suspend(chip_data, chip_data->wake_active); 580 raw_spin_unlock(&chip_data->rlock); 581 } 582 583 return 0; 584 } 585 586 static void __maybe_unused stm32_exti_h_resume(void) 587 { 588 struct stm32_exti_chip_data *chip_data; 589 int i; 590 591 for (i = 0; i < stm32_host_data->drv_data->bank_nr; i++) { 592 chip_data = &stm32_host_data->chips_data[i]; 593 raw_spin_lock(&chip_data->rlock); 594 stm32_chip_resume(chip_data, chip_data->mask_cache); 595 raw_spin_unlock(&chip_data->rlock); 596 } 597 } 598 599 static struct syscore_ops stm32_exti_h_syscore_ops = { 600 #ifdef CONFIG_PM_SLEEP 601 .suspend = stm32_exti_h_suspend, 602 .resume = stm32_exti_h_resume, 603 #endif 604 }; 605 606 static void stm32_exti_h_syscore_init(struct stm32_exti_host_data *host_data) 607 { 608 stm32_host_data = host_data; 609 register_syscore_ops(&stm32_exti_h_syscore_ops); 610 } 611 612 static void stm32_exti_h_syscore_deinit(void) 613 { 614 unregister_syscore_ops(&stm32_exti_h_syscore_ops); 615 } 616 617 static int stm32_exti_h_retrigger(struct irq_data *d) 618 { 619 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d); 620 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank; 621 void __iomem *base = chip_data->host_data->base; 622 u32 mask = BIT(d->hwirq % IRQS_PER_BANK); 623 624 writel_relaxed(mask, base + stm32_bank->swier_ofst); 625 626 return 0; 627 } 628 629 static struct irq_chip stm32_exti_h_chip = { 630 .name = "stm32-exti-h", 631 .irq_eoi = stm32_exti_h_eoi, 632 .irq_mask = stm32_exti_h_mask, 633 .irq_unmask = stm32_exti_h_unmask, 634 .irq_retrigger = stm32_exti_h_retrigger, 635 .irq_set_type = stm32_exti_h_set_type, 636 .irq_set_wake = stm32_exti_h_set_wake, 637 .flags = IRQCHIP_MASK_ON_SUSPEND, 638 .irq_set_affinity = IS_ENABLED(CONFIG_SMP) ? stm32_exti_h_set_affinity : NULL, 639 }; 640 641 static struct irq_chip stm32_exti_h_chip_direct = { 642 .name = "stm32-exti-h-direct", 643 .irq_eoi = irq_chip_eoi_parent, 644 .irq_ack = irq_chip_ack_parent, 645 .irq_mask = irq_chip_mask_parent, 646 .irq_unmask = irq_chip_unmask_parent, 647 .irq_retrigger = irq_chip_retrigger_hierarchy, 648 .irq_set_type = irq_chip_set_type_parent, 649 .irq_set_wake = stm32_exti_h_set_wake, 650 .flags = IRQCHIP_MASK_ON_SUSPEND, 651 .irq_set_affinity = IS_ENABLED(CONFIG_SMP) ? irq_chip_set_affinity_parent : NULL, 652 }; 653 654 static int stm32_exti_h_domain_alloc(struct irq_domain *dm, 655 unsigned int virq, 656 unsigned int nr_irqs, void *data) 657 { 658 struct stm32_exti_host_data *host_data = dm->host_data; 659 struct stm32_exti_chip_data *chip_data; 660 const struct stm32_desc_irq *desc; 661 struct irq_fwspec *fwspec = data; 662 struct irq_fwspec p_fwspec; 663 irq_hw_number_t hwirq; 664 int bank; 665 666 hwirq = fwspec->param[0]; 667 bank = hwirq / IRQS_PER_BANK; 668 chip_data = &host_data->chips_data[bank]; 669 670 671 desc = stm32_exti_get_desc(host_data->drv_data, hwirq); 672 if (!desc) 673 return -EINVAL; 674 675 irq_domain_set_hwirq_and_chip(dm, virq, hwirq, desc->chip, 676 chip_data); 677 if (desc->irq_parent) { 678 p_fwspec.fwnode = dm->parent->fwnode; 679 p_fwspec.param_count = 3; 680 p_fwspec.param[0] = GIC_SPI; 681 p_fwspec.param[1] = desc->irq_parent; 682 p_fwspec.param[2] = IRQ_TYPE_LEVEL_HIGH; 683 684 return irq_domain_alloc_irqs_parent(dm, virq, 1, &p_fwspec); 685 } 686 687 return 0; 688 } 689 690 static struct 691 stm32_exti_host_data *stm32_exti_host_init(const struct stm32_exti_drv_data *dd, 692 struct device_node *node) 693 { 694 struct stm32_exti_host_data *host_data; 695 696 host_data = kzalloc(sizeof(*host_data), GFP_KERNEL); 697 if (!host_data) 698 return NULL; 699 700 host_data->drv_data = dd; 701 host_data->chips_data = kcalloc(dd->bank_nr, 702 sizeof(struct stm32_exti_chip_data), 703 GFP_KERNEL); 704 if (!host_data->chips_data) 705 goto free_host_data; 706 707 host_data->base = of_iomap(node, 0); 708 if (!host_data->base) { 709 pr_err("%pOF: Unable to map registers\n", node); 710 goto free_chips_data; 711 } 712 713 stm32_host_data = host_data; 714 715 return host_data; 716 717 free_chips_data: 718 kfree(host_data->chips_data); 719 free_host_data: 720 kfree(host_data); 721 722 return NULL; 723 } 724 725 static struct 726 stm32_exti_chip_data *stm32_exti_chip_init(struct stm32_exti_host_data *h_data, 727 u32 bank_idx, 728 struct device_node *node) 729 { 730 const struct stm32_exti_bank *stm32_bank; 731 struct stm32_exti_chip_data *chip_data; 732 void __iomem *base = h_data->base; 733 734 stm32_bank = h_data->drv_data->exti_banks[bank_idx]; 735 chip_data = &h_data->chips_data[bank_idx]; 736 chip_data->host_data = h_data; 737 chip_data->reg_bank = stm32_bank; 738 739 raw_spin_lock_init(&chip_data->rlock); 740 741 /* 742 * This IP has no reset, so after hot reboot we should 743 * clear registers to avoid residue 744 */ 745 writel_relaxed(0, base + stm32_bank->imr_ofst); 746 writel_relaxed(0, base + stm32_bank->emr_ofst); 747 748 pr_info("%pOF: bank%d\n", node, bank_idx); 749 750 return chip_data; 751 } 752 753 static int __init stm32_exti_init(const struct stm32_exti_drv_data *drv_data, 754 struct device_node *node) 755 { 756 struct stm32_exti_host_data *host_data; 757 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; 758 int nr_irqs, ret, i; 759 struct irq_chip_generic *gc; 760 struct irq_domain *domain; 761 762 host_data = stm32_exti_host_init(drv_data, node); 763 if (!host_data) 764 return -ENOMEM; 765 766 domain = irq_domain_add_linear(node, drv_data->bank_nr * IRQS_PER_BANK, 767 &irq_exti_domain_ops, NULL); 768 if (!domain) { 769 pr_err("%pOFn: Could not register interrupt domain.\n", 770 node); 771 ret = -ENOMEM; 772 goto out_unmap; 773 } 774 775 ret = irq_alloc_domain_generic_chips(domain, IRQS_PER_BANK, 1, "exti", 776 handle_edge_irq, clr, 0, 0); 777 if (ret) { 778 pr_err("%pOF: Could not allocate generic interrupt chip.\n", 779 node); 780 goto out_free_domain; 781 } 782 783 for (i = 0; i < drv_data->bank_nr; i++) { 784 const struct stm32_exti_bank *stm32_bank; 785 struct stm32_exti_chip_data *chip_data; 786 787 stm32_bank = drv_data->exti_banks[i]; 788 chip_data = stm32_exti_chip_init(host_data, i, node); 789 790 gc = irq_get_domain_generic_chip(domain, i * IRQS_PER_BANK); 791 792 gc->reg_base = host_data->base; 793 gc->chip_types->type = IRQ_TYPE_EDGE_BOTH; 794 gc->chip_types->chip.irq_ack = stm32_irq_ack; 795 gc->chip_types->chip.irq_mask = irq_gc_mask_clr_bit; 796 gc->chip_types->chip.irq_unmask = irq_gc_mask_set_bit; 797 gc->chip_types->chip.irq_set_type = stm32_irq_set_type; 798 gc->chip_types->chip.irq_set_wake = irq_gc_set_wake; 799 gc->suspend = stm32_irq_suspend; 800 gc->resume = stm32_irq_resume; 801 gc->wake_enabled = IRQ_MSK(IRQS_PER_BANK); 802 803 gc->chip_types->regs.mask = stm32_bank->imr_ofst; 804 gc->private = (void *)chip_data; 805 } 806 807 nr_irqs = of_irq_count(node); 808 for (i = 0; i < nr_irqs; i++) { 809 unsigned int irq = irq_of_parse_and_map(node, i); 810 811 irq_set_handler_data(irq, domain); 812 irq_set_chained_handler(irq, stm32_irq_handler); 813 } 814 815 return 0; 816 817 out_free_domain: 818 irq_domain_remove(domain); 819 out_unmap: 820 iounmap(host_data->base); 821 kfree(host_data->chips_data); 822 kfree(host_data); 823 return ret; 824 } 825 826 static const struct irq_domain_ops stm32_exti_h_domain_ops = { 827 .alloc = stm32_exti_h_domain_alloc, 828 .free = irq_domain_free_irqs_common, 829 .xlate = irq_domain_xlate_twocell, 830 }; 831 832 static void stm32_exti_remove_irq(void *data) 833 { 834 struct irq_domain *domain = data; 835 836 irq_domain_remove(domain); 837 } 838 839 static int stm32_exti_remove(struct platform_device *pdev) 840 { 841 stm32_exti_h_syscore_deinit(); 842 return 0; 843 } 844 845 static int stm32_exti_probe(struct platform_device *pdev) 846 { 847 int ret, i; 848 struct device *dev = &pdev->dev; 849 struct device_node *np = dev->of_node; 850 struct irq_domain *parent_domain, *domain; 851 struct stm32_exti_host_data *host_data; 852 const struct stm32_exti_drv_data *drv_data; 853 struct resource *res; 854 855 host_data = devm_kzalloc(dev, sizeof(*host_data), GFP_KERNEL); 856 if (!host_data) 857 return -ENOMEM; 858 859 /* check for optional hwspinlock which may be not available yet */ 860 ret = of_hwspin_lock_get_id(np, 0); 861 if (ret == -EPROBE_DEFER) 862 /* hwspinlock framework not yet ready */ 863 return ret; 864 865 if (ret >= 0) { 866 host_data->hwlock = devm_hwspin_lock_request_specific(dev, ret); 867 if (!host_data->hwlock) { 868 dev_err(dev, "Failed to request hwspinlock\n"); 869 return -EINVAL; 870 } 871 } else if (ret != -ENOENT) { 872 /* note: ENOENT is a valid case (means 'no hwspinlock') */ 873 dev_err(dev, "Failed to get hwspinlock\n"); 874 return ret; 875 } 876 877 /* initialize host_data */ 878 drv_data = of_device_get_match_data(dev); 879 if (!drv_data) { 880 dev_err(dev, "no of match data\n"); 881 return -ENODEV; 882 } 883 host_data->drv_data = drv_data; 884 885 host_data->chips_data = devm_kcalloc(dev, drv_data->bank_nr, 886 sizeof(*host_data->chips_data), 887 GFP_KERNEL); 888 if (!host_data->chips_data) 889 return -ENOMEM; 890 891 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 892 host_data->base = devm_ioremap_resource(dev, res); 893 if (IS_ERR(host_data->base)) 894 return PTR_ERR(host_data->base); 895 896 for (i = 0; i < drv_data->bank_nr; i++) 897 stm32_exti_chip_init(host_data, i, np); 898 899 parent_domain = irq_find_host(of_irq_find_parent(np)); 900 if (!parent_domain) { 901 dev_err(dev, "GIC interrupt-parent not found\n"); 902 return -EINVAL; 903 } 904 905 domain = irq_domain_add_hierarchy(parent_domain, 0, 906 drv_data->bank_nr * IRQS_PER_BANK, 907 np, &stm32_exti_h_domain_ops, 908 host_data); 909 910 if (!domain) { 911 dev_err(dev, "Could not register exti domain\n"); 912 return -ENOMEM; 913 } 914 915 ret = devm_add_action_or_reset(dev, stm32_exti_remove_irq, domain); 916 if (ret) 917 return ret; 918 919 stm32_exti_h_syscore_init(host_data); 920 921 return 0; 922 } 923 924 /* platform driver only for MP1 */ 925 static const struct of_device_id stm32_exti_ids[] = { 926 { .compatible = "st,stm32mp1-exti", .data = &stm32mp1_drv_data}, 927 {}, 928 }; 929 MODULE_DEVICE_TABLE(of, stm32_exti_ids); 930 931 static struct platform_driver stm32_exti_driver = { 932 .probe = stm32_exti_probe, 933 .remove = stm32_exti_remove, 934 .driver = { 935 .name = "stm32_exti", 936 .of_match_table = stm32_exti_ids, 937 }, 938 }; 939 940 static int __init stm32_exti_arch_init(void) 941 { 942 return platform_driver_register(&stm32_exti_driver); 943 } 944 945 static void __exit stm32_exti_arch_exit(void) 946 { 947 return platform_driver_unregister(&stm32_exti_driver); 948 } 949 950 arch_initcall(stm32_exti_arch_init); 951 module_exit(stm32_exti_arch_exit); 952 953 /* no platform driver for F4 and H7 */ 954 static int __init stm32f4_exti_of_init(struct device_node *np, 955 struct device_node *parent) 956 { 957 return stm32_exti_init(&stm32f4xx_drv_data, np); 958 } 959 960 IRQCHIP_DECLARE(stm32f4_exti, "st,stm32-exti", stm32f4_exti_of_init); 961 962 static int __init stm32h7_exti_of_init(struct device_node *np, 963 struct device_node *parent) 964 { 965 return stm32_exti_init(&stm32h7xx_drv_data, np); 966 } 967 968 IRQCHIP_DECLARE(stm32h7_exti, "st,stm32h7-exti", stm32h7_exti_of_init); 969