1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) Maxime Coquelin 2015 4 * Copyright (C) STMicroelectronics 2017 5 * Author: Maxime Coquelin <mcoquelin.stm32@gmail.com> 6 */ 7 8 #include <linux/bitops.h> 9 #include <linux/delay.h> 10 #include <linux/hwspinlock.h> 11 #include <linux/interrupt.h> 12 #include <linux/io.h> 13 #include <linux/irq.h> 14 #include <linux/irqchip.h> 15 #include <linux/irqchip/chained_irq.h> 16 #include <linux/irqdomain.h> 17 #include <linux/module.h> 18 #include <linux/of_address.h> 19 #include <linux/of_irq.h> 20 #include <linux/of_platform.h> 21 #include <linux/syscore_ops.h> 22 23 #include <dt-bindings/interrupt-controller/arm-gic.h> 24 25 #define IRQS_PER_BANK 32 26 27 #define HWSPNLCK_TIMEOUT 1000 /* usec */ 28 29 struct stm32_exti_bank { 30 u32 imr_ofst; 31 u32 emr_ofst; 32 u32 rtsr_ofst; 33 u32 ftsr_ofst; 34 u32 swier_ofst; 35 u32 rpr_ofst; 36 u32 fpr_ofst; 37 u32 trg_ofst; 38 }; 39 40 #define UNDEF_REG ~0 41 42 struct stm32_exti_drv_data { 43 const struct stm32_exti_bank **exti_banks; 44 const u8 *desc_irqs; 45 u32 bank_nr; 46 }; 47 48 struct stm32_exti_chip_data { 49 struct stm32_exti_host_data *host_data; 50 const struct stm32_exti_bank *reg_bank; 51 struct raw_spinlock rlock; 52 u32 wake_active; 53 u32 mask_cache; 54 u32 rtsr_cache; 55 u32 ftsr_cache; 56 }; 57 58 struct stm32_exti_host_data { 59 void __iomem *base; 60 struct stm32_exti_chip_data *chips_data; 61 const struct stm32_exti_drv_data *drv_data; 62 struct hwspinlock *hwlock; 63 }; 64 65 static struct stm32_exti_host_data *stm32_host_data; 66 67 static const struct stm32_exti_bank stm32f4xx_exti_b1 = { 68 .imr_ofst = 0x00, 69 .emr_ofst = 0x04, 70 .rtsr_ofst = 0x08, 71 .ftsr_ofst = 0x0C, 72 .swier_ofst = 0x10, 73 .rpr_ofst = 0x14, 74 .fpr_ofst = UNDEF_REG, 75 .trg_ofst = UNDEF_REG, 76 }; 77 78 static const struct stm32_exti_bank *stm32f4xx_exti_banks[] = { 79 &stm32f4xx_exti_b1, 80 }; 81 82 static const struct stm32_exti_drv_data stm32f4xx_drv_data = { 83 .exti_banks = stm32f4xx_exti_banks, 84 .bank_nr = ARRAY_SIZE(stm32f4xx_exti_banks), 85 }; 86 87 static const struct stm32_exti_bank stm32h7xx_exti_b1 = { 88 .imr_ofst = 0x80, 89 .emr_ofst = 0x84, 90 .rtsr_ofst = 0x00, 91 .ftsr_ofst = 0x04, 92 .swier_ofst = 0x08, 93 .rpr_ofst = 0x88, 94 .fpr_ofst = UNDEF_REG, 95 .trg_ofst = UNDEF_REG, 96 }; 97 98 static const struct stm32_exti_bank stm32h7xx_exti_b2 = { 99 .imr_ofst = 0x90, 100 .emr_ofst = 0x94, 101 .rtsr_ofst = 0x20, 102 .ftsr_ofst = 0x24, 103 .swier_ofst = 0x28, 104 .rpr_ofst = 0x98, 105 .fpr_ofst = UNDEF_REG, 106 .trg_ofst = UNDEF_REG, 107 }; 108 109 static const struct stm32_exti_bank stm32h7xx_exti_b3 = { 110 .imr_ofst = 0xA0, 111 .emr_ofst = 0xA4, 112 .rtsr_ofst = 0x40, 113 .ftsr_ofst = 0x44, 114 .swier_ofst = 0x48, 115 .rpr_ofst = 0xA8, 116 .fpr_ofst = UNDEF_REG, 117 .trg_ofst = UNDEF_REG, 118 }; 119 120 static const struct stm32_exti_bank *stm32h7xx_exti_banks[] = { 121 &stm32h7xx_exti_b1, 122 &stm32h7xx_exti_b2, 123 &stm32h7xx_exti_b3, 124 }; 125 126 static const struct stm32_exti_drv_data stm32h7xx_drv_data = { 127 .exti_banks = stm32h7xx_exti_banks, 128 .bank_nr = ARRAY_SIZE(stm32h7xx_exti_banks), 129 }; 130 131 static const struct stm32_exti_bank stm32mp1_exti_b1 = { 132 .imr_ofst = 0x80, 133 .emr_ofst = UNDEF_REG, 134 .rtsr_ofst = 0x00, 135 .ftsr_ofst = 0x04, 136 .swier_ofst = 0x08, 137 .rpr_ofst = 0x0C, 138 .fpr_ofst = 0x10, 139 .trg_ofst = 0x3EC, 140 }; 141 142 static const struct stm32_exti_bank stm32mp1_exti_b2 = { 143 .imr_ofst = 0x90, 144 .emr_ofst = UNDEF_REG, 145 .rtsr_ofst = 0x20, 146 .ftsr_ofst = 0x24, 147 .swier_ofst = 0x28, 148 .rpr_ofst = 0x2C, 149 .fpr_ofst = 0x30, 150 .trg_ofst = 0x3E8, 151 }; 152 153 static const struct stm32_exti_bank stm32mp1_exti_b3 = { 154 .imr_ofst = 0xA0, 155 .emr_ofst = UNDEF_REG, 156 .rtsr_ofst = 0x40, 157 .ftsr_ofst = 0x44, 158 .swier_ofst = 0x48, 159 .rpr_ofst = 0x4C, 160 .fpr_ofst = 0x50, 161 .trg_ofst = 0x3E4, 162 }; 163 164 static const struct stm32_exti_bank *stm32mp1_exti_banks[] = { 165 &stm32mp1_exti_b1, 166 &stm32mp1_exti_b2, 167 &stm32mp1_exti_b3, 168 }; 169 170 static struct irq_chip stm32_exti_h_chip; 171 static struct irq_chip stm32_exti_h_chip_direct; 172 173 #define EXTI_INVALID_IRQ U8_MAX 174 #define STM32MP1_DESC_IRQ_SIZE (ARRAY_SIZE(stm32mp1_exti_banks) * IRQS_PER_BANK) 175 176 /* 177 * Use some intentionally tricky logic here to initialize the whole array to 178 * EXTI_INVALID_IRQ, but then override certain fields, requiring us to indicate 179 * that we "know" that there are overrides in this structure, and we'll need to 180 * disable that warning from W=1 builds. 181 */ 182 __diag_push(); 183 __diag_ignore_all("-Woverride-init", 184 "logic to initialize all and then override some is OK"); 185 186 static const u8 stm32mp1_desc_irq[] = { 187 /* default value */ 188 [0 ... (STM32MP1_DESC_IRQ_SIZE - 1)] = EXTI_INVALID_IRQ, 189 190 [0] = 6, 191 [1] = 7, 192 [2] = 8, 193 [3] = 9, 194 [4] = 10, 195 [5] = 23, 196 [6] = 64, 197 [7] = 65, 198 [8] = 66, 199 [9] = 67, 200 [10] = 40, 201 [11] = 42, 202 [12] = 76, 203 [13] = 77, 204 [14] = 121, 205 [15] = 127, 206 [16] = 1, 207 [19] = 3, 208 [21] = 31, 209 [22] = 33, 210 [23] = 72, 211 [24] = 95, 212 [25] = 107, 213 [26] = 37, 214 [27] = 38, 215 [28] = 39, 216 [29] = 71, 217 [30] = 52, 218 [31] = 53, 219 [32] = 82, 220 [33] = 83, 221 [46] = 151, 222 [47] = 93, 223 [48] = 138, 224 [50] = 139, 225 [52] = 140, 226 [53] = 141, 227 [54] = 135, 228 [61] = 100, 229 [65] = 144, 230 [68] = 143, 231 [70] = 62, 232 [73] = 129, 233 }; 234 235 static const u8 stm32mp13_desc_irq[] = { 236 /* default value */ 237 [0 ... (STM32MP1_DESC_IRQ_SIZE - 1)] = EXTI_INVALID_IRQ, 238 239 [0] = 6, 240 [1] = 7, 241 [2] = 8, 242 [3] = 9, 243 [4] = 10, 244 [5] = 24, 245 [6] = 65, 246 [7] = 66, 247 [8] = 67, 248 [9] = 68, 249 [10] = 41, 250 [11] = 43, 251 [12] = 77, 252 [13] = 78, 253 [14] = 106, 254 [15] = 109, 255 [16] = 1, 256 [19] = 3, 257 [21] = 32, 258 [22] = 34, 259 [23] = 73, 260 [24] = 93, 261 [25] = 114, 262 [26] = 38, 263 [27] = 39, 264 [28] = 40, 265 [29] = 72, 266 [30] = 53, 267 [31] = 54, 268 [32] = 83, 269 [33] = 84, 270 [44] = 96, 271 [47] = 92, 272 [48] = 116, 273 [50] = 117, 274 [52] = 118, 275 [53] = 119, 276 [68] = 63, 277 [70] = 98, 278 }; 279 280 __diag_pop(); 281 282 static const struct stm32_exti_drv_data stm32mp1_drv_data = { 283 .exti_banks = stm32mp1_exti_banks, 284 .bank_nr = ARRAY_SIZE(stm32mp1_exti_banks), 285 .desc_irqs = stm32mp1_desc_irq, 286 }; 287 288 static const struct stm32_exti_drv_data stm32mp13_drv_data = { 289 .exti_banks = stm32mp1_exti_banks, 290 .bank_nr = ARRAY_SIZE(stm32mp1_exti_banks), 291 .desc_irqs = stm32mp13_desc_irq, 292 }; 293 294 static unsigned long stm32_exti_pending(struct irq_chip_generic *gc) 295 { 296 struct stm32_exti_chip_data *chip_data = gc->private; 297 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank; 298 unsigned long pending; 299 300 pending = irq_reg_readl(gc, stm32_bank->rpr_ofst); 301 if (stm32_bank->fpr_ofst != UNDEF_REG) 302 pending |= irq_reg_readl(gc, stm32_bank->fpr_ofst); 303 304 return pending; 305 } 306 307 static void stm32_irq_handler(struct irq_desc *desc) 308 { 309 struct irq_domain *domain = irq_desc_get_handler_data(desc); 310 struct irq_chip *chip = irq_desc_get_chip(desc); 311 unsigned int nbanks = domain->gc->num_chips; 312 struct irq_chip_generic *gc; 313 unsigned long pending; 314 int n, i, irq_base = 0; 315 316 chained_irq_enter(chip, desc); 317 318 for (i = 0; i < nbanks; i++, irq_base += IRQS_PER_BANK) { 319 gc = irq_get_domain_generic_chip(domain, irq_base); 320 321 while ((pending = stm32_exti_pending(gc))) { 322 for_each_set_bit(n, &pending, IRQS_PER_BANK) 323 generic_handle_domain_irq(domain, irq_base + n); 324 } 325 } 326 327 chained_irq_exit(chip, desc); 328 } 329 330 static int stm32_exti_set_type(struct irq_data *d, 331 unsigned int type, u32 *rtsr, u32 *ftsr) 332 { 333 u32 mask = BIT(d->hwirq % IRQS_PER_BANK); 334 335 switch (type) { 336 case IRQ_TYPE_EDGE_RISING: 337 *rtsr |= mask; 338 *ftsr &= ~mask; 339 break; 340 case IRQ_TYPE_EDGE_FALLING: 341 *rtsr &= ~mask; 342 *ftsr |= mask; 343 break; 344 case IRQ_TYPE_EDGE_BOTH: 345 *rtsr |= mask; 346 *ftsr |= mask; 347 break; 348 default: 349 return -EINVAL; 350 } 351 352 return 0; 353 } 354 355 static int stm32_irq_set_type(struct irq_data *d, unsigned int type) 356 { 357 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 358 struct stm32_exti_chip_data *chip_data = gc->private; 359 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank; 360 struct hwspinlock *hwlock = chip_data->host_data->hwlock; 361 u32 rtsr, ftsr; 362 int err; 363 364 irq_gc_lock(gc); 365 366 if (hwlock) { 367 err = hwspin_lock_timeout_in_atomic(hwlock, HWSPNLCK_TIMEOUT); 368 if (err) { 369 pr_err("%s can't get hwspinlock (%d)\n", __func__, err); 370 goto unlock; 371 } 372 } 373 374 rtsr = irq_reg_readl(gc, stm32_bank->rtsr_ofst); 375 ftsr = irq_reg_readl(gc, stm32_bank->ftsr_ofst); 376 377 err = stm32_exti_set_type(d, type, &rtsr, &ftsr); 378 if (err) 379 goto unspinlock; 380 381 irq_reg_writel(gc, rtsr, stm32_bank->rtsr_ofst); 382 irq_reg_writel(gc, ftsr, stm32_bank->ftsr_ofst); 383 384 unspinlock: 385 if (hwlock) 386 hwspin_unlock_in_atomic(hwlock); 387 unlock: 388 irq_gc_unlock(gc); 389 390 return err; 391 } 392 393 static void stm32_chip_suspend(struct stm32_exti_chip_data *chip_data, 394 u32 wake_active) 395 { 396 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank; 397 void __iomem *base = chip_data->host_data->base; 398 399 /* save rtsr, ftsr registers */ 400 chip_data->rtsr_cache = readl_relaxed(base + stm32_bank->rtsr_ofst); 401 chip_data->ftsr_cache = readl_relaxed(base + stm32_bank->ftsr_ofst); 402 403 writel_relaxed(wake_active, base + stm32_bank->imr_ofst); 404 } 405 406 static void stm32_chip_resume(struct stm32_exti_chip_data *chip_data, 407 u32 mask_cache) 408 { 409 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank; 410 void __iomem *base = chip_data->host_data->base; 411 412 /* restore rtsr, ftsr, registers */ 413 writel_relaxed(chip_data->rtsr_cache, base + stm32_bank->rtsr_ofst); 414 writel_relaxed(chip_data->ftsr_cache, base + stm32_bank->ftsr_ofst); 415 416 writel_relaxed(mask_cache, base + stm32_bank->imr_ofst); 417 } 418 419 static void stm32_irq_suspend(struct irq_chip_generic *gc) 420 { 421 struct stm32_exti_chip_data *chip_data = gc->private; 422 423 irq_gc_lock(gc); 424 stm32_chip_suspend(chip_data, gc->wake_active); 425 irq_gc_unlock(gc); 426 } 427 428 static void stm32_irq_resume(struct irq_chip_generic *gc) 429 { 430 struct stm32_exti_chip_data *chip_data = gc->private; 431 432 irq_gc_lock(gc); 433 stm32_chip_resume(chip_data, gc->mask_cache); 434 irq_gc_unlock(gc); 435 } 436 437 static int stm32_exti_alloc(struct irq_domain *d, unsigned int virq, 438 unsigned int nr_irqs, void *data) 439 { 440 struct irq_fwspec *fwspec = data; 441 irq_hw_number_t hwirq; 442 443 hwirq = fwspec->param[0]; 444 445 irq_map_generic_chip(d, virq, hwirq); 446 447 return 0; 448 } 449 450 static void stm32_exti_free(struct irq_domain *d, unsigned int virq, 451 unsigned int nr_irqs) 452 { 453 struct irq_data *data = irq_domain_get_irq_data(d, virq); 454 455 irq_domain_reset_irq_data(data); 456 } 457 458 static const struct irq_domain_ops irq_exti_domain_ops = { 459 .map = irq_map_generic_chip, 460 .alloc = stm32_exti_alloc, 461 .free = stm32_exti_free, 462 }; 463 464 static void stm32_irq_ack(struct irq_data *d) 465 { 466 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 467 struct stm32_exti_chip_data *chip_data = gc->private; 468 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank; 469 470 irq_gc_lock(gc); 471 472 irq_reg_writel(gc, d->mask, stm32_bank->rpr_ofst); 473 if (stm32_bank->fpr_ofst != UNDEF_REG) 474 irq_reg_writel(gc, d->mask, stm32_bank->fpr_ofst); 475 476 irq_gc_unlock(gc); 477 } 478 479 /* directly set the target bit without reading first. */ 480 static inline void stm32_exti_write_bit(struct irq_data *d, u32 reg) 481 { 482 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d); 483 void __iomem *base = chip_data->host_data->base; 484 u32 val = BIT(d->hwirq % IRQS_PER_BANK); 485 486 writel_relaxed(val, base + reg); 487 } 488 489 static inline u32 stm32_exti_set_bit(struct irq_data *d, u32 reg) 490 { 491 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d); 492 void __iomem *base = chip_data->host_data->base; 493 u32 val; 494 495 val = readl_relaxed(base + reg); 496 val |= BIT(d->hwirq % IRQS_PER_BANK); 497 writel_relaxed(val, base + reg); 498 499 return val; 500 } 501 502 static inline u32 stm32_exti_clr_bit(struct irq_data *d, u32 reg) 503 { 504 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d); 505 void __iomem *base = chip_data->host_data->base; 506 u32 val; 507 508 val = readl_relaxed(base + reg); 509 val &= ~BIT(d->hwirq % IRQS_PER_BANK); 510 writel_relaxed(val, base + reg); 511 512 return val; 513 } 514 515 static void stm32_exti_h_eoi(struct irq_data *d) 516 { 517 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d); 518 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank; 519 520 raw_spin_lock(&chip_data->rlock); 521 522 stm32_exti_write_bit(d, stm32_bank->rpr_ofst); 523 if (stm32_bank->fpr_ofst != UNDEF_REG) 524 stm32_exti_write_bit(d, stm32_bank->fpr_ofst); 525 526 raw_spin_unlock(&chip_data->rlock); 527 528 if (d->parent_data->chip) 529 irq_chip_eoi_parent(d); 530 } 531 532 static void stm32_exti_h_mask(struct irq_data *d) 533 { 534 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d); 535 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank; 536 537 raw_spin_lock(&chip_data->rlock); 538 chip_data->mask_cache = stm32_exti_clr_bit(d, stm32_bank->imr_ofst); 539 raw_spin_unlock(&chip_data->rlock); 540 541 if (d->parent_data->chip) 542 irq_chip_mask_parent(d); 543 } 544 545 static void stm32_exti_h_unmask(struct irq_data *d) 546 { 547 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d); 548 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank; 549 550 raw_spin_lock(&chip_data->rlock); 551 chip_data->mask_cache = stm32_exti_set_bit(d, stm32_bank->imr_ofst); 552 raw_spin_unlock(&chip_data->rlock); 553 554 if (d->parent_data->chip) 555 irq_chip_unmask_parent(d); 556 } 557 558 static int stm32_exti_h_set_type(struct irq_data *d, unsigned int type) 559 { 560 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d); 561 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank; 562 struct hwspinlock *hwlock = chip_data->host_data->hwlock; 563 void __iomem *base = chip_data->host_data->base; 564 u32 rtsr, ftsr; 565 int err; 566 567 raw_spin_lock(&chip_data->rlock); 568 569 if (hwlock) { 570 err = hwspin_lock_timeout_in_atomic(hwlock, HWSPNLCK_TIMEOUT); 571 if (err) { 572 pr_err("%s can't get hwspinlock (%d)\n", __func__, err); 573 goto unlock; 574 } 575 } 576 577 rtsr = readl_relaxed(base + stm32_bank->rtsr_ofst); 578 ftsr = readl_relaxed(base + stm32_bank->ftsr_ofst); 579 580 err = stm32_exti_set_type(d, type, &rtsr, &ftsr); 581 if (err) 582 goto unspinlock; 583 584 writel_relaxed(rtsr, base + stm32_bank->rtsr_ofst); 585 writel_relaxed(ftsr, base + stm32_bank->ftsr_ofst); 586 587 unspinlock: 588 if (hwlock) 589 hwspin_unlock_in_atomic(hwlock); 590 unlock: 591 raw_spin_unlock(&chip_data->rlock); 592 593 return err; 594 } 595 596 static int stm32_exti_h_set_wake(struct irq_data *d, unsigned int on) 597 { 598 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d); 599 u32 mask = BIT(d->hwirq % IRQS_PER_BANK); 600 601 raw_spin_lock(&chip_data->rlock); 602 603 if (on) 604 chip_data->wake_active |= mask; 605 else 606 chip_data->wake_active &= ~mask; 607 608 raw_spin_unlock(&chip_data->rlock); 609 610 return 0; 611 } 612 613 static int stm32_exti_h_set_affinity(struct irq_data *d, 614 const struct cpumask *dest, bool force) 615 { 616 if (d->parent_data->chip) 617 return irq_chip_set_affinity_parent(d, dest, force); 618 619 return IRQ_SET_MASK_OK_DONE; 620 } 621 622 static int __maybe_unused stm32_exti_h_suspend(void) 623 { 624 struct stm32_exti_chip_data *chip_data; 625 int i; 626 627 for (i = 0; i < stm32_host_data->drv_data->bank_nr; i++) { 628 chip_data = &stm32_host_data->chips_data[i]; 629 raw_spin_lock(&chip_data->rlock); 630 stm32_chip_suspend(chip_data, chip_data->wake_active); 631 raw_spin_unlock(&chip_data->rlock); 632 } 633 634 return 0; 635 } 636 637 static void __maybe_unused stm32_exti_h_resume(void) 638 { 639 struct stm32_exti_chip_data *chip_data; 640 int i; 641 642 for (i = 0; i < stm32_host_data->drv_data->bank_nr; i++) { 643 chip_data = &stm32_host_data->chips_data[i]; 644 raw_spin_lock(&chip_data->rlock); 645 stm32_chip_resume(chip_data, chip_data->mask_cache); 646 raw_spin_unlock(&chip_data->rlock); 647 } 648 } 649 650 static struct syscore_ops stm32_exti_h_syscore_ops = { 651 #ifdef CONFIG_PM_SLEEP 652 .suspend = stm32_exti_h_suspend, 653 .resume = stm32_exti_h_resume, 654 #endif 655 }; 656 657 static void stm32_exti_h_syscore_init(struct stm32_exti_host_data *host_data) 658 { 659 stm32_host_data = host_data; 660 register_syscore_ops(&stm32_exti_h_syscore_ops); 661 } 662 663 static void stm32_exti_h_syscore_deinit(void) 664 { 665 unregister_syscore_ops(&stm32_exti_h_syscore_ops); 666 } 667 668 static int stm32_exti_h_retrigger(struct irq_data *d) 669 { 670 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d); 671 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank; 672 void __iomem *base = chip_data->host_data->base; 673 u32 mask = BIT(d->hwirq % IRQS_PER_BANK); 674 675 writel_relaxed(mask, base + stm32_bank->swier_ofst); 676 677 return 0; 678 } 679 680 static struct irq_chip stm32_exti_h_chip = { 681 .name = "stm32-exti-h", 682 .irq_eoi = stm32_exti_h_eoi, 683 .irq_mask = stm32_exti_h_mask, 684 .irq_unmask = stm32_exti_h_unmask, 685 .irq_retrigger = stm32_exti_h_retrigger, 686 .irq_set_type = stm32_exti_h_set_type, 687 .irq_set_wake = stm32_exti_h_set_wake, 688 .flags = IRQCHIP_MASK_ON_SUSPEND, 689 .irq_set_affinity = IS_ENABLED(CONFIG_SMP) ? stm32_exti_h_set_affinity : NULL, 690 }; 691 692 static struct irq_chip stm32_exti_h_chip_direct = { 693 .name = "stm32-exti-h-direct", 694 .irq_eoi = irq_chip_eoi_parent, 695 .irq_ack = irq_chip_ack_parent, 696 .irq_mask = stm32_exti_h_mask, 697 .irq_unmask = stm32_exti_h_unmask, 698 .irq_retrigger = irq_chip_retrigger_hierarchy, 699 .irq_set_type = irq_chip_set_type_parent, 700 .irq_set_wake = stm32_exti_h_set_wake, 701 .flags = IRQCHIP_MASK_ON_SUSPEND, 702 .irq_set_affinity = IS_ENABLED(CONFIG_SMP) ? irq_chip_set_affinity_parent : NULL, 703 }; 704 705 static int stm32_exti_h_domain_alloc(struct irq_domain *dm, 706 unsigned int virq, 707 unsigned int nr_irqs, void *data) 708 { 709 struct stm32_exti_host_data *host_data = dm->host_data; 710 struct stm32_exti_chip_data *chip_data; 711 u8 desc_irq; 712 struct irq_fwspec *fwspec = data; 713 struct irq_fwspec p_fwspec; 714 irq_hw_number_t hwirq; 715 int bank; 716 u32 event_trg; 717 struct irq_chip *chip; 718 719 hwirq = fwspec->param[0]; 720 if (hwirq >= host_data->drv_data->bank_nr * IRQS_PER_BANK) 721 return -EINVAL; 722 723 bank = hwirq / IRQS_PER_BANK; 724 chip_data = &host_data->chips_data[bank]; 725 726 event_trg = readl_relaxed(host_data->base + chip_data->reg_bank->trg_ofst); 727 chip = (event_trg & BIT(hwirq % IRQS_PER_BANK)) ? 728 &stm32_exti_h_chip : &stm32_exti_h_chip_direct; 729 730 irq_domain_set_hwirq_and_chip(dm, virq, hwirq, chip, chip_data); 731 732 if (!host_data->drv_data->desc_irqs) 733 return -EINVAL; 734 735 desc_irq = host_data->drv_data->desc_irqs[hwirq]; 736 if (desc_irq != EXTI_INVALID_IRQ) { 737 p_fwspec.fwnode = dm->parent->fwnode; 738 p_fwspec.param_count = 3; 739 p_fwspec.param[0] = GIC_SPI; 740 p_fwspec.param[1] = desc_irq; 741 p_fwspec.param[2] = IRQ_TYPE_LEVEL_HIGH; 742 743 return irq_domain_alloc_irqs_parent(dm, virq, 1, &p_fwspec); 744 } 745 746 return 0; 747 } 748 749 static struct 750 stm32_exti_host_data *stm32_exti_host_init(const struct stm32_exti_drv_data *dd, 751 struct device_node *node) 752 { 753 struct stm32_exti_host_data *host_data; 754 755 host_data = kzalloc(sizeof(*host_data), GFP_KERNEL); 756 if (!host_data) 757 return NULL; 758 759 host_data->drv_data = dd; 760 host_data->chips_data = kcalloc(dd->bank_nr, 761 sizeof(struct stm32_exti_chip_data), 762 GFP_KERNEL); 763 if (!host_data->chips_data) 764 goto free_host_data; 765 766 host_data->base = of_iomap(node, 0); 767 if (!host_data->base) { 768 pr_err("%pOF: Unable to map registers\n", node); 769 goto free_chips_data; 770 } 771 772 stm32_host_data = host_data; 773 774 return host_data; 775 776 free_chips_data: 777 kfree(host_data->chips_data); 778 free_host_data: 779 kfree(host_data); 780 781 return NULL; 782 } 783 784 static struct 785 stm32_exti_chip_data *stm32_exti_chip_init(struct stm32_exti_host_data *h_data, 786 u32 bank_idx, 787 struct device_node *node) 788 { 789 const struct stm32_exti_bank *stm32_bank; 790 struct stm32_exti_chip_data *chip_data; 791 void __iomem *base = h_data->base; 792 793 stm32_bank = h_data->drv_data->exti_banks[bank_idx]; 794 chip_data = &h_data->chips_data[bank_idx]; 795 chip_data->host_data = h_data; 796 chip_data->reg_bank = stm32_bank; 797 798 raw_spin_lock_init(&chip_data->rlock); 799 800 /* 801 * This IP has no reset, so after hot reboot we should 802 * clear registers to avoid residue 803 */ 804 writel_relaxed(0, base + stm32_bank->imr_ofst); 805 if (stm32_bank->emr_ofst != UNDEF_REG) 806 writel_relaxed(0, base + stm32_bank->emr_ofst); 807 808 pr_info("%pOF: bank%d\n", node, bank_idx); 809 810 return chip_data; 811 } 812 813 static int __init stm32_exti_init(const struct stm32_exti_drv_data *drv_data, 814 struct device_node *node) 815 { 816 struct stm32_exti_host_data *host_data; 817 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; 818 int nr_irqs, ret, i; 819 struct irq_chip_generic *gc; 820 struct irq_domain *domain; 821 822 host_data = stm32_exti_host_init(drv_data, node); 823 if (!host_data) 824 return -ENOMEM; 825 826 domain = irq_domain_add_linear(node, drv_data->bank_nr * IRQS_PER_BANK, 827 &irq_exti_domain_ops, NULL); 828 if (!domain) { 829 pr_err("%pOFn: Could not register interrupt domain.\n", 830 node); 831 ret = -ENOMEM; 832 goto out_unmap; 833 } 834 835 ret = irq_alloc_domain_generic_chips(domain, IRQS_PER_BANK, 1, "exti", 836 handle_edge_irq, clr, 0, 0); 837 if (ret) { 838 pr_err("%pOF: Could not allocate generic interrupt chip.\n", 839 node); 840 goto out_free_domain; 841 } 842 843 for (i = 0; i < drv_data->bank_nr; i++) { 844 const struct stm32_exti_bank *stm32_bank; 845 struct stm32_exti_chip_data *chip_data; 846 847 stm32_bank = drv_data->exti_banks[i]; 848 chip_data = stm32_exti_chip_init(host_data, i, node); 849 850 gc = irq_get_domain_generic_chip(domain, i * IRQS_PER_BANK); 851 852 gc->reg_base = host_data->base; 853 gc->chip_types->type = IRQ_TYPE_EDGE_BOTH; 854 gc->chip_types->chip.irq_ack = stm32_irq_ack; 855 gc->chip_types->chip.irq_mask = irq_gc_mask_clr_bit; 856 gc->chip_types->chip.irq_unmask = irq_gc_mask_set_bit; 857 gc->chip_types->chip.irq_set_type = stm32_irq_set_type; 858 gc->chip_types->chip.irq_set_wake = irq_gc_set_wake; 859 gc->suspend = stm32_irq_suspend; 860 gc->resume = stm32_irq_resume; 861 gc->wake_enabled = IRQ_MSK(IRQS_PER_BANK); 862 863 gc->chip_types->regs.mask = stm32_bank->imr_ofst; 864 gc->private = (void *)chip_data; 865 } 866 867 nr_irqs = of_irq_count(node); 868 for (i = 0; i < nr_irqs; i++) { 869 unsigned int irq = irq_of_parse_and_map(node, i); 870 871 irq_set_handler_data(irq, domain); 872 irq_set_chained_handler(irq, stm32_irq_handler); 873 } 874 875 return 0; 876 877 out_free_domain: 878 irq_domain_remove(domain); 879 out_unmap: 880 iounmap(host_data->base); 881 kfree(host_data->chips_data); 882 kfree(host_data); 883 return ret; 884 } 885 886 static const struct irq_domain_ops stm32_exti_h_domain_ops = { 887 .alloc = stm32_exti_h_domain_alloc, 888 .free = irq_domain_free_irqs_common, 889 .xlate = irq_domain_xlate_twocell, 890 }; 891 892 static void stm32_exti_remove_irq(void *data) 893 { 894 struct irq_domain *domain = data; 895 896 irq_domain_remove(domain); 897 } 898 899 static int stm32_exti_remove(struct platform_device *pdev) 900 { 901 stm32_exti_h_syscore_deinit(); 902 return 0; 903 } 904 905 static int stm32_exti_probe(struct platform_device *pdev) 906 { 907 int ret, i; 908 struct device *dev = &pdev->dev; 909 struct device_node *np = dev->of_node; 910 struct irq_domain *parent_domain, *domain; 911 struct stm32_exti_host_data *host_data; 912 const struct stm32_exti_drv_data *drv_data; 913 914 host_data = devm_kzalloc(dev, sizeof(*host_data), GFP_KERNEL); 915 if (!host_data) 916 return -ENOMEM; 917 918 /* check for optional hwspinlock which may be not available yet */ 919 ret = of_hwspin_lock_get_id(np, 0); 920 if (ret == -EPROBE_DEFER) 921 /* hwspinlock framework not yet ready */ 922 return ret; 923 924 if (ret >= 0) { 925 host_data->hwlock = devm_hwspin_lock_request_specific(dev, ret); 926 if (!host_data->hwlock) { 927 dev_err(dev, "Failed to request hwspinlock\n"); 928 return -EINVAL; 929 } 930 } else if (ret != -ENOENT) { 931 /* note: ENOENT is a valid case (means 'no hwspinlock') */ 932 dev_err(dev, "Failed to get hwspinlock\n"); 933 return ret; 934 } 935 936 /* initialize host_data */ 937 drv_data = of_device_get_match_data(dev); 938 if (!drv_data) { 939 dev_err(dev, "no of match data\n"); 940 return -ENODEV; 941 } 942 host_data->drv_data = drv_data; 943 944 host_data->chips_data = devm_kcalloc(dev, drv_data->bank_nr, 945 sizeof(*host_data->chips_data), 946 GFP_KERNEL); 947 if (!host_data->chips_data) 948 return -ENOMEM; 949 950 host_data->base = devm_platform_ioremap_resource(pdev, 0); 951 if (IS_ERR(host_data->base)) 952 return PTR_ERR(host_data->base); 953 954 for (i = 0; i < drv_data->bank_nr; i++) 955 stm32_exti_chip_init(host_data, i, np); 956 957 parent_domain = irq_find_host(of_irq_find_parent(np)); 958 if (!parent_domain) { 959 dev_err(dev, "GIC interrupt-parent not found\n"); 960 return -EINVAL; 961 } 962 963 domain = irq_domain_add_hierarchy(parent_domain, 0, 964 drv_data->bank_nr * IRQS_PER_BANK, 965 np, &stm32_exti_h_domain_ops, 966 host_data); 967 968 if (!domain) { 969 dev_err(dev, "Could not register exti domain\n"); 970 return -ENOMEM; 971 } 972 973 ret = devm_add_action_or_reset(dev, stm32_exti_remove_irq, domain); 974 if (ret) 975 return ret; 976 977 stm32_exti_h_syscore_init(host_data); 978 979 return 0; 980 } 981 982 /* platform driver only for MP1 */ 983 static const struct of_device_id stm32_exti_ids[] = { 984 { .compatible = "st,stm32mp1-exti", .data = &stm32mp1_drv_data}, 985 { .compatible = "st,stm32mp13-exti", .data = &stm32mp13_drv_data}, 986 {}, 987 }; 988 MODULE_DEVICE_TABLE(of, stm32_exti_ids); 989 990 static struct platform_driver stm32_exti_driver = { 991 .probe = stm32_exti_probe, 992 .remove = stm32_exti_remove, 993 .driver = { 994 .name = "stm32_exti", 995 .of_match_table = stm32_exti_ids, 996 }, 997 }; 998 999 static int __init stm32_exti_arch_init(void) 1000 { 1001 return platform_driver_register(&stm32_exti_driver); 1002 } 1003 1004 static void __exit stm32_exti_arch_exit(void) 1005 { 1006 return platform_driver_unregister(&stm32_exti_driver); 1007 } 1008 1009 arch_initcall(stm32_exti_arch_init); 1010 module_exit(stm32_exti_arch_exit); 1011 1012 /* no platform driver for F4 and H7 */ 1013 static int __init stm32f4_exti_of_init(struct device_node *np, 1014 struct device_node *parent) 1015 { 1016 return stm32_exti_init(&stm32f4xx_drv_data, np); 1017 } 1018 1019 IRQCHIP_DECLARE(stm32f4_exti, "st,stm32-exti", stm32f4_exti_of_init); 1020 1021 static int __init stm32h7_exti_of_init(struct device_node *np, 1022 struct device_node *parent) 1023 { 1024 return stm32_exti_init(&stm32h7xx_drv_data, np); 1025 } 1026 1027 IRQCHIP_DECLARE(stm32h7_exti, "st,stm32h7-exti", stm32h7_exti_of_init); 1028